1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef __iop_dmc_out_defs_h
3 #define __iop_dmc_out_defs_h
6 * This file is autogenerated from
7 * file: ../../inst/io_proc/rtl/iop_dmc_out.r
8 * id: iop_dmc_out.r,v 1.30 2005/02/16 09:14:11 niklaspa Exp
9 * last modfied: Mon Apr 11 16:08:45 2005
11 * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_dmc_out_defs.h ../../inst/io_proc/rtl/iop_dmc_out.r
12 * id: $Id: iop_dmc_out_defs.h,v 1.5 2005/04/24 18:31:05 starvik Exp $
13 * Any changes here will be lost.
15 * -*- buffer-read-only: t -*-
17 /* Main access macros */
19 #define REG_RD( scope, inst, reg ) \
20 REG_READ( reg_##scope##_##reg, \
21 (inst) + REG_RD_ADDR_##scope##_##reg )
25 #define REG_WR( scope, inst, reg, val ) \
26 REG_WRITE( reg_##scope##_##reg, \
27 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
31 #define REG_RD_VECT( scope, inst, reg, index ) \
32 REG_READ( reg_##scope##_##reg, \
33 (inst) + REG_RD_ADDR_##scope##_##reg + \
34 (index) * STRIDE_##scope##_##reg )
38 #define REG_WR_VECT( scope, inst, reg, index, val ) \
39 REG_WRITE( reg_##scope##_##reg, \
40 (inst) + REG_WR_ADDR_##scope##_##reg + \
41 (index) * STRIDE_##scope##_##reg, (val) )
45 #define REG_RD_INT( scope, inst, reg ) \
46 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
50 #define REG_WR_INT( scope, inst, reg, val ) \
51 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
54 #ifndef REG_RD_INT_VECT
55 #define REG_RD_INT_VECT( scope, inst, reg, index ) \
56 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
57 (index) * STRIDE_##scope##_##reg )
60 #ifndef REG_WR_INT_VECT
61 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
62 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
63 (index) * STRIDE_##scope##_##reg, (val) )
67 #define REG_TYPE_CONV( type, orgtype, val ) \
68 ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
72 #define reg_page_size 8192
76 #define REG_ADDR( scope, inst, reg ) \
77 ( (inst) + REG_RD_ADDR_##scope##_##reg )
81 #define REG_ADDR_VECT( scope, inst, reg, index ) \
82 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
83 (index) * STRIDE_##scope##_##reg )
86 /* C-code for register scope iop_dmc_out */
88 /* Register rw_cfg, scope iop_dmc_out, type rw */
90 unsigned int trf_lim : 16;
91 unsigned int last_at_trf_lim : 1;
92 unsigned int dth_intr : 3;
93 unsigned int dummy1 : 12;
94 } reg_iop_dmc_out_rw_cfg;
95 #define REG_RD_ADDR_iop_dmc_out_rw_cfg 0
96 #define REG_WR_ADDR_iop_dmc_out_rw_cfg 0
98 /* Register rw_ctrl, scope iop_dmc_out, type rw */
100 unsigned int dif_en : 1;
101 unsigned int dif_dis : 1;
102 unsigned int dummy1 : 30;
103 } reg_iop_dmc_out_rw_ctrl;
104 #define REG_RD_ADDR_iop_dmc_out_rw_ctrl 4
105 #define REG_WR_ADDR_iop_dmc_out_rw_ctrl 4
107 /* Register r_stat, scope iop_dmc_out, type r */
109 unsigned int dif_en : 1;
110 unsigned int dummy1 : 31;
111 } reg_iop_dmc_out_r_stat;
112 #define REG_RD_ADDR_iop_dmc_out_r_stat 8
114 /* Register rw_stream_cmd, scope iop_dmc_out, type rw */
116 unsigned int cmd : 10;
117 unsigned int dummy1 : 6;
119 unsigned int dummy2 : 8;
120 } reg_iop_dmc_out_rw_stream_cmd;
121 #define REG_RD_ADDR_iop_dmc_out_rw_stream_cmd 12
122 #define REG_WR_ADDR_iop_dmc_out_rw_stream_cmd 12
124 /* Register rs_stream_data, scope iop_dmc_out, type rs */
125 typedef unsigned int reg_iop_dmc_out_rs_stream_data;
126 #define REG_RD_ADDR_iop_dmc_out_rs_stream_data 16
128 /* Register r_stream_data, scope iop_dmc_out, type r */
129 typedef unsigned int reg_iop_dmc_out_r_stream_data;
130 #define REG_RD_ADDR_iop_dmc_out_r_stream_data 20
132 /* Register r_stream_stat, scope iop_dmc_out, type r */
134 unsigned int dth : 7;
135 unsigned int dummy1 : 9;
137 unsigned int all_avail : 1;
138 unsigned int last : 1;
139 unsigned int size : 3;
140 unsigned int data_md_valid : 1;
141 unsigned int ctxt_md_valid : 1;
142 unsigned int group_md_valid : 1;
143 unsigned int stream_busy : 1;
144 unsigned int cmd_rdy : 1;
145 unsigned int cmd_rq : 1;
146 unsigned int dummy2 : 4;
147 } reg_iop_dmc_out_r_stream_stat;
148 #define REG_RD_ADDR_iop_dmc_out_r_stream_stat 24
150 /* Register r_data_descr, scope iop_dmc_out, type r */
152 unsigned int ctrl : 8;
153 unsigned int stat : 8;
154 unsigned int md : 16;
155 } reg_iop_dmc_out_r_data_descr;
156 #define REG_RD_ADDR_iop_dmc_out_r_data_descr 28
158 /* Register r_ctxt_descr, scope iop_dmc_out, type r */
160 unsigned int ctrl : 8;
161 unsigned int stat : 8;
162 unsigned int md0 : 16;
163 } reg_iop_dmc_out_r_ctxt_descr;
164 #define REG_RD_ADDR_iop_dmc_out_r_ctxt_descr 32
166 /* Register r_ctxt_descr_md1, scope iop_dmc_out, type r */
167 typedef unsigned int reg_iop_dmc_out_r_ctxt_descr_md1;
168 #define REG_RD_ADDR_iop_dmc_out_r_ctxt_descr_md1 36
170 /* Register r_ctxt_descr_md2, scope iop_dmc_out, type r */
171 typedef unsigned int reg_iop_dmc_out_r_ctxt_descr_md2;
172 #define REG_RD_ADDR_iop_dmc_out_r_ctxt_descr_md2 40
174 /* Register r_group_descr, scope iop_dmc_out, type r */
176 unsigned int ctrl : 8;
177 unsigned int stat : 8;
178 unsigned int md : 16;
179 } reg_iop_dmc_out_r_group_descr;
180 #define REG_RD_ADDR_iop_dmc_out_r_group_descr 52
182 /* Register rw_data_descr, scope iop_dmc_out, type rw */
184 unsigned int dummy1 : 16;
185 unsigned int md : 16;
186 } reg_iop_dmc_out_rw_data_descr;
187 #define REG_RD_ADDR_iop_dmc_out_rw_data_descr 56
188 #define REG_WR_ADDR_iop_dmc_out_rw_data_descr 56
190 /* Register rw_ctxt_descr, scope iop_dmc_out, type rw */
192 unsigned int dummy1 : 16;
193 unsigned int md0 : 16;
194 } reg_iop_dmc_out_rw_ctxt_descr;
195 #define REG_RD_ADDR_iop_dmc_out_rw_ctxt_descr 60
196 #define REG_WR_ADDR_iop_dmc_out_rw_ctxt_descr 60
198 /* Register rw_ctxt_descr_md1, scope iop_dmc_out, type rw */
199 typedef unsigned int reg_iop_dmc_out_rw_ctxt_descr_md1;
200 #define REG_RD_ADDR_iop_dmc_out_rw_ctxt_descr_md1 64
201 #define REG_WR_ADDR_iop_dmc_out_rw_ctxt_descr_md1 64
203 /* Register rw_ctxt_descr_md2, scope iop_dmc_out, type rw */
204 typedef unsigned int reg_iop_dmc_out_rw_ctxt_descr_md2;
205 #define REG_RD_ADDR_iop_dmc_out_rw_ctxt_descr_md2 68
206 #define REG_WR_ADDR_iop_dmc_out_rw_ctxt_descr_md2 68
208 /* Register rw_group_descr, scope iop_dmc_out, type rw */
210 unsigned int dummy1 : 16;
211 unsigned int md : 16;
212 } reg_iop_dmc_out_rw_group_descr;
213 #define REG_RD_ADDR_iop_dmc_out_rw_group_descr 80
214 #define REG_WR_ADDR_iop_dmc_out_rw_group_descr 80
216 /* Register rw_intr_mask, scope iop_dmc_out, type rw */
218 unsigned int data_md : 1;
219 unsigned int ctxt_md : 1;
220 unsigned int group_md : 1;
221 unsigned int cmd_rdy : 1;
222 unsigned int dth : 1;
224 unsigned int last_data : 1;
225 unsigned int trf_lim : 1;
226 unsigned int cmd_rq : 1;
227 unsigned int dummy1 : 23;
228 } reg_iop_dmc_out_rw_intr_mask;
229 #define REG_RD_ADDR_iop_dmc_out_rw_intr_mask 84
230 #define REG_WR_ADDR_iop_dmc_out_rw_intr_mask 84
232 /* Register rw_ack_intr, scope iop_dmc_out, type rw */
234 unsigned int data_md : 1;
235 unsigned int ctxt_md : 1;
236 unsigned int group_md : 1;
237 unsigned int cmd_rdy : 1;
238 unsigned int dth : 1;
240 unsigned int last_data : 1;
241 unsigned int trf_lim : 1;
242 unsigned int cmd_rq : 1;
243 unsigned int dummy1 : 23;
244 } reg_iop_dmc_out_rw_ack_intr;
245 #define REG_RD_ADDR_iop_dmc_out_rw_ack_intr 88
246 #define REG_WR_ADDR_iop_dmc_out_rw_ack_intr 88
248 /* Register r_intr, scope iop_dmc_out, type r */
250 unsigned int data_md : 1;
251 unsigned int ctxt_md : 1;
252 unsigned int group_md : 1;
253 unsigned int cmd_rdy : 1;
254 unsigned int dth : 1;
256 unsigned int last_data : 1;
257 unsigned int trf_lim : 1;
258 unsigned int cmd_rq : 1;
259 unsigned int dummy1 : 23;
260 } reg_iop_dmc_out_r_intr;
261 #define REG_RD_ADDR_iop_dmc_out_r_intr 92
263 /* Register r_masked_intr, scope iop_dmc_out, type r */
265 unsigned int data_md : 1;
266 unsigned int ctxt_md : 1;
267 unsigned int group_md : 1;
268 unsigned int cmd_rdy : 1;
269 unsigned int dth : 1;
271 unsigned int last_data : 1;
272 unsigned int trf_lim : 1;
273 unsigned int cmd_rq : 1;
274 unsigned int dummy1 : 23;
275 } reg_iop_dmc_out_r_masked_intr;
276 #define REG_RD_ADDR_iop_dmc_out_r_masked_intr 96
281 regk_iop_dmc_out_ack_pkt = 0x00000100,
282 regk_iop_dmc_out_array = 0x00000008,
283 regk_iop_dmc_out_burst = 0x00000020,
284 regk_iop_dmc_out_copy_next = 0x00000010,
285 regk_iop_dmc_out_copy_up = 0x00000020,
286 regk_iop_dmc_out_dis_c = 0x00000010,
287 regk_iop_dmc_out_dis_g = 0x00000020,
288 regk_iop_dmc_out_lim1 = 0x00000000,
289 regk_iop_dmc_out_lim16 = 0x00000004,
290 regk_iop_dmc_out_lim2 = 0x00000001,
291 regk_iop_dmc_out_lim32 = 0x00000005,
292 regk_iop_dmc_out_lim4 = 0x00000002,
293 regk_iop_dmc_out_lim64 = 0x00000006,
294 regk_iop_dmc_out_lim8 = 0x00000003,
295 regk_iop_dmc_out_load_c = 0x00000200,
296 regk_iop_dmc_out_load_c_n = 0x00000280,
297 regk_iop_dmc_out_load_c_next = 0x00000240,
298 regk_iop_dmc_out_load_d = 0x00000140,
299 regk_iop_dmc_out_load_g = 0x00000300,
300 regk_iop_dmc_out_load_g_down = 0x000003c0,
301 regk_iop_dmc_out_load_g_next = 0x00000340,
302 regk_iop_dmc_out_load_g_up = 0x00000380,
303 regk_iop_dmc_out_next_en = 0x00000010,
304 regk_iop_dmc_out_next_pkt = 0x00000010,
305 regk_iop_dmc_out_no = 0x00000000,
306 regk_iop_dmc_out_restore = 0x00000020,
307 regk_iop_dmc_out_rw_cfg_default = 0x00000000,
308 regk_iop_dmc_out_rw_ctxt_descr_default = 0x00000000,
309 regk_iop_dmc_out_rw_ctxt_descr_md1_default = 0x00000000,
310 regk_iop_dmc_out_rw_ctxt_descr_md2_default = 0x00000000,
311 regk_iop_dmc_out_rw_data_descr_default = 0x00000000,
312 regk_iop_dmc_out_rw_group_descr_default = 0x00000000,
313 regk_iop_dmc_out_rw_intr_mask_default = 0x00000000,
314 regk_iop_dmc_out_save_down = 0x00000020,
315 regk_iop_dmc_out_save_up = 0x00000020,
316 regk_iop_dmc_out_set_reg = 0x00000050,
317 regk_iop_dmc_out_set_w_size1 = 0x00000190,
318 regk_iop_dmc_out_set_w_size2 = 0x000001a0,
319 regk_iop_dmc_out_set_w_size4 = 0x000001c0,
320 regk_iop_dmc_out_store_c = 0x00000002,
321 regk_iop_dmc_out_store_descr = 0x00000000,
322 regk_iop_dmc_out_store_g = 0x00000004,
323 regk_iop_dmc_out_store_md = 0x00000001,
324 regk_iop_dmc_out_update_down = 0x00000020,
325 regk_iop_dmc_out_yes = 0x00000001
327 #endif /* __iop_dmc_out_defs_h */