1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef __iop_sw_cfg_defs_asm_h
3 #define __iop_sw_cfg_defs_asm_h
6 * This file is autogenerated from
7 * file: ../../inst/io_proc/rtl/guinness/iop_sw_cfg.r
9 * last modfied: Mon Apr 11 16:10:19 2005
11 * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_sw_cfg_defs_asm.h ../../inst/io_proc/rtl/guinness/iop_sw_cfg.r
12 * id: $Id: iop_sw_cfg_defs_asm.h,v 1.5 2005/04/24 18:31:07 starvik Exp $
13 * Any changes here will be lost.
15 * -*- buffer-read-only: t -*-
19 #define REG_FIELD( scope, reg, field, value ) \
20 REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
21 #define REG_FIELD_X_( value, shift ) ((value) << shift)
25 #define REG_STATE( scope, reg, field, symbolic_value ) \
26 REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
27 #define REG_STATE_X_( k, shift ) (k << shift)
31 #define REG_MASK( scope, reg, field ) \
32 REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
33 #define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
37 #define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
41 #define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
45 #define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
46 #define REG_ADDR_X_( inst, offs ) ((inst) + offs)
50 #define REG_ADDR_VECT( scope, inst, reg, index ) \
51 REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
52 STRIDE_##scope##_##reg )
53 #define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
54 ((inst) + offs + (index) * stride)
57 /* Register rw_crc_par0_owner, scope iop_sw_cfg, type rw */
58 #define reg_iop_sw_cfg_rw_crc_par0_owner___cfg___lsb 0
59 #define reg_iop_sw_cfg_rw_crc_par0_owner___cfg___width 2
60 #define reg_iop_sw_cfg_rw_crc_par0_owner_offset 0
62 /* Register rw_crc_par1_owner, scope iop_sw_cfg, type rw */
63 #define reg_iop_sw_cfg_rw_crc_par1_owner___cfg___lsb 0
64 #define reg_iop_sw_cfg_rw_crc_par1_owner___cfg___width 2
65 #define reg_iop_sw_cfg_rw_crc_par1_owner_offset 4
67 /* Register rw_dmc_in0_owner, scope iop_sw_cfg, type rw */
68 #define reg_iop_sw_cfg_rw_dmc_in0_owner___cfg___lsb 0
69 #define reg_iop_sw_cfg_rw_dmc_in0_owner___cfg___width 2
70 #define reg_iop_sw_cfg_rw_dmc_in0_owner_offset 8
72 /* Register rw_dmc_in1_owner, scope iop_sw_cfg, type rw */
73 #define reg_iop_sw_cfg_rw_dmc_in1_owner___cfg___lsb 0
74 #define reg_iop_sw_cfg_rw_dmc_in1_owner___cfg___width 2
75 #define reg_iop_sw_cfg_rw_dmc_in1_owner_offset 12
77 /* Register rw_dmc_out0_owner, scope iop_sw_cfg, type rw */
78 #define reg_iop_sw_cfg_rw_dmc_out0_owner___cfg___lsb 0
79 #define reg_iop_sw_cfg_rw_dmc_out0_owner___cfg___width 2
80 #define reg_iop_sw_cfg_rw_dmc_out0_owner_offset 16
82 /* Register rw_dmc_out1_owner, scope iop_sw_cfg, type rw */
83 #define reg_iop_sw_cfg_rw_dmc_out1_owner___cfg___lsb 0
84 #define reg_iop_sw_cfg_rw_dmc_out1_owner___cfg___width 2
85 #define reg_iop_sw_cfg_rw_dmc_out1_owner_offset 20
87 /* Register rw_fifo_in0_owner, scope iop_sw_cfg, type rw */
88 #define reg_iop_sw_cfg_rw_fifo_in0_owner___cfg___lsb 0
89 #define reg_iop_sw_cfg_rw_fifo_in0_owner___cfg___width 2
90 #define reg_iop_sw_cfg_rw_fifo_in0_owner_offset 24
92 /* Register rw_fifo_in0_extra_owner, scope iop_sw_cfg, type rw */
93 #define reg_iop_sw_cfg_rw_fifo_in0_extra_owner___cfg___lsb 0
94 #define reg_iop_sw_cfg_rw_fifo_in0_extra_owner___cfg___width 2
95 #define reg_iop_sw_cfg_rw_fifo_in0_extra_owner_offset 28
97 /* Register rw_fifo_in1_owner, scope iop_sw_cfg, type rw */
98 #define reg_iop_sw_cfg_rw_fifo_in1_owner___cfg___lsb 0
99 #define reg_iop_sw_cfg_rw_fifo_in1_owner___cfg___width 2
100 #define reg_iop_sw_cfg_rw_fifo_in1_owner_offset 32
102 /* Register rw_fifo_in1_extra_owner, scope iop_sw_cfg, type rw */
103 #define reg_iop_sw_cfg_rw_fifo_in1_extra_owner___cfg___lsb 0
104 #define reg_iop_sw_cfg_rw_fifo_in1_extra_owner___cfg___width 2
105 #define reg_iop_sw_cfg_rw_fifo_in1_extra_owner_offset 36
107 /* Register rw_fifo_out0_owner, scope iop_sw_cfg, type rw */
108 #define reg_iop_sw_cfg_rw_fifo_out0_owner___cfg___lsb 0
109 #define reg_iop_sw_cfg_rw_fifo_out0_owner___cfg___width 2
110 #define reg_iop_sw_cfg_rw_fifo_out0_owner_offset 40
112 /* Register rw_fifo_out0_extra_owner, scope iop_sw_cfg, type rw */
113 #define reg_iop_sw_cfg_rw_fifo_out0_extra_owner___cfg___lsb 0
114 #define reg_iop_sw_cfg_rw_fifo_out0_extra_owner___cfg___width 2
115 #define reg_iop_sw_cfg_rw_fifo_out0_extra_owner_offset 44
117 /* Register rw_fifo_out1_owner, scope iop_sw_cfg, type rw */
118 #define reg_iop_sw_cfg_rw_fifo_out1_owner___cfg___lsb 0
119 #define reg_iop_sw_cfg_rw_fifo_out1_owner___cfg___width 2
120 #define reg_iop_sw_cfg_rw_fifo_out1_owner_offset 48
122 /* Register rw_fifo_out1_extra_owner, scope iop_sw_cfg, type rw */
123 #define reg_iop_sw_cfg_rw_fifo_out1_extra_owner___cfg___lsb 0
124 #define reg_iop_sw_cfg_rw_fifo_out1_extra_owner___cfg___width 2
125 #define reg_iop_sw_cfg_rw_fifo_out1_extra_owner_offset 52
127 /* Register rw_sap_in_owner, scope iop_sw_cfg, type rw */
128 #define reg_iop_sw_cfg_rw_sap_in_owner___cfg___lsb 0
129 #define reg_iop_sw_cfg_rw_sap_in_owner___cfg___width 2
130 #define reg_iop_sw_cfg_rw_sap_in_owner_offset 56
132 /* Register rw_sap_out_owner, scope iop_sw_cfg, type rw */
133 #define reg_iop_sw_cfg_rw_sap_out_owner___cfg___lsb 0
134 #define reg_iop_sw_cfg_rw_sap_out_owner___cfg___width 2
135 #define reg_iop_sw_cfg_rw_sap_out_owner_offset 60
137 /* Register rw_scrc_in0_owner, scope iop_sw_cfg, type rw */
138 #define reg_iop_sw_cfg_rw_scrc_in0_owner___cfg___lsb 0
139 #define reg_iop_sw_cfg_rw_scrc_in0_owner___cfg___width 2
140 #define reg_iop_sw_cfg_rw_scrc_in0_owner_offset 64
142 /* Register rw_scrc_in1_owner, scope iop_sw_cfg, type rw */
143 #define reg_iop_sw_cfg_rw_scrc_in1_owner___cfg___lsb 0
144 #define reg_iop_sw_cfg_rw_scrc_in1_owner___cfg___width 2
145 #define reg_iop_sw_cfg_rw_scrc_in1_owner_offset 68
147 /* Register rw_scrc_out0_owner, scope iop_sw_cfg, type rw */
148 #define reg_iop_sw_cfg_rw_scrc_out0_owner___cfg___lsb 0
149 #define reg_iop_sw_cfg_rw_scrc_out0_owner___cfg___width 2
150 #define reg_iop_sw_cfg_rw_scrc_out0_owner_offset 72
152 /* Register rw_scrc_out1_owner, scope iop_sw_cfg, type rw */
153 #define reg_iop_sw_cfg_rw_scrc_out1_owner___cfg___lsb 0
154 #define reg_iop_sw_cfg_rw_scrc_out1_owner___cfg___width 2
155 #define reg_iop_sw_cfg_rw_scrc_out1_owner_offset 76
157 /* Register rw_spu0_owner, scope iop_sw_cfg, type rw */
158 #define reg_iop_sw_cfg_rw_spu0_owner___cfg___lsb 0
159 #define reg_iop_sw_cfg_rw_spu0_owner___cfg___width 2
160 #define reg_iop_sw_cfg_rw_spu0_owner_offset 80
162 /* Register rw_spu1_owner, scope iop_sw_cfg, type rw */
163 #define reg_iop_sw_cfg_rw_spu1_owner___cfg___lsb 0
164 #define reg_iop_sw_cfg_rw_spu1_owner___cfg___width 2
165 #define reg_iop_sw_cfg_rw_spu1_owner_offset 84
167 /* Register rw_timer_grp0_owner, scope iop_sw_cfg, type rw */
168 #define reg_iop_sw_cfg_rw_timer_grp0_owner___cfg___lsb 0
169 #define reg_iop_sw_cfg_rw_timer_grp0_owner___cfg___width 2
170 #define reg_iop_sw_cfg_rw_timer_grp0_owner_offset 88
172 /* Register rw_timer_grp1_owner, scope iop_sw_cfg, type rw */
173 #define reg_iop_sw_cfg_rw_timer_grp1_owner___cfg___lsb 0
174 #define reg_iop_sw_cfg_rw_timer_grp1_owner___cfg___width 2
175 #define reg_iop_sw_cfg_rw_timer_grp1_owner_offset 92
177 /* Register rw_timer_grp2_owner, scope iop_sw_cfg, type rw */
178 #define reg_iop_sw_cfg_rw_timer_grp2_owner___cfg___lsb 0
179 #define reg_iop_sw_cfg_rw_timer_grp2_owner___cfg___width 2
180 #define reg_iop_sw_cfg_rw_timer_grp2_owner_offset 96
182 /* Register rw_timer_grp3_owner, scope iop_sw_cfg, type rw */
183 #define reg_iop_sw_cfg_rw_timer_grp3_owner___cfg___lsb 0
184 #define reg_iop_sw_cfg_rw_timer_grp3_owner___cfg___width 2
185 #define reg_iop_sw_cfg_rw_timer_grp3_owner_offset 100
187 /* Register rw_trigger_grp0_owner, scope iop_sw_cfg, type rw */
188 #define reg_iop_sw_cfg_rw_trigger_grp0_owner___cfg___lsb 0
189 #define reg_iop_sw_cfg_rw_trigger_grp0_owner___cfg___width 2
190 #define reg_iop_sw_cfg_rw_trigger_grp0_owner_offset 104
192 /* Register rw_trigger_grp1_owner, scope iop_sw_cfg, type rw */
193 #define reg_iop_sw_cfg_rw_trigger_grp1_owner___cfg___lsb 0
194 #define reg_iop_sw_cfg_rw_trigger_grp1_owner___cfg___width 2
195 #define reg_iop_sw_cfg_rw_trigger_grp1_owner_offset 108
197 /* Register rw_trigger_grp2_owner, scope iop_sw_cfg, type rw */
198 #define reg_iop_sw_cfg_rw_trigger_grp2_owner___cfg___lsb 0
199 #define reg_iop_sw_cfg_rw_trigger_grp2_owner___cfg___width 2
200 #define reg_iop_sw_cfg_rw_trigger_grp2_owner_offset 112
202 /* Register rw_trigger_grp3_owner, scope iop_sw_cfg, type rw */
203 #define reg_iop_sw_cfg_rw_trigger_grp3_owner___cfg___lsb 0
204 #define reg_iop_sw_cfg_rw_trigger_grp3_owner___cfg___width 2
205 #define reg_iop_sw_cfg_rw_trigger_grp3_owner_offset 116
207 /* Register rw_trigger_grp4_owner, scope iop_sw_cfg, type rw */
208 #define reg_iop_sw_cfg_rw_trigger_grp4_owner___cfg___lsb 0
209 #define reg_iop_sw_cfg_rw_trigger_grp4_owner___cfg___width 2
210 #define reg_iop_sw_cfg_rw_trigger_grp4_owner_offset 120
212 /* Register rw_trigger_grp5_owner, scope iop_sw_cfg, type rw */
213 #define reg_iop_sw_cfg_rw_trigger_grp5_owner___cfg___lsb 0
214 #define reg_iop_sw_cfg_rw_trigger_grp5_owner___cfg___width 2
215 #define reg_iop_sw_cfg_rw_trigger_grp5_owner_offset 124
217 /* Register rw_trigger_grp6_owner, scope iop_sw_cfg, type rw */
218 #define reg_iop_sw_cfg_rw_trigger_grp6_owner___cfg___lsb 0
219 #define reg_iop_sw_cfg_rw_trigger_grp6_owner___cfg___width 2
220 #define reg_iop_sw_cfg_rw_trigger_grp6_owner_offset 128
222 /* Register rw_trigger_grp7_owner, scope iop_sw_cfg, type rw */
223 #define reg_iop_sw_cfg_rw_trigger_grp7_owner___cfg___lsb 0
224 #define reg_iop_sw_cfg_rw_trigger_grp7_owner___cfg___width 2
225 #define reg_iop_sw_cfg_rw_trigger_grp7_owner_offset 132
227 /* Register rw_bus0_mask, scope iop_sw_cfg, type rw */
228 #define reg_iop_sw_cfg_rw_bus0_mask___byte0___lsb 0
229 #define reg_iop_sw_cfg_rw_bus0_mask___byte0___width 8
230 #define reg_iop_sw_cfg_rw_bus0_mask___byte1___lsb 8
231 #define reg_iop_sw_cfg_rw_bus0_mask___byte1___width 8
232 #define reg_iop_sw_cfg_rw_bus0_mask___byte2___lsb 16
233 #define reg_iop_sw_cfg_rw_bus0_mask___byte2___width 8
234 #define reg_iop_sw_cfg_rw_bus0_mask___byte3___lsb 24
235 #define reg_iop_sw_cfg_rw_bus0_mask___byte3___width 8
236 #define reg_iop_sw_cfg_rw_bus0_mask_offset 136
238 /* Register rw_bus0_oe_mask, scope iop_sw_cfg, type rw */
239 #define reg_iop_sw_cfg_rw_bus0_oe_mask___byte0___lsb 0
240 #define reg_iop_sw_cfg_rw_bus0_oe_mask___byte0___width 1
241 #define reg_iop_sw_cfg_rw_bus0_oe_mask___byte0___bit 0
242 #define reg_iop_sw_cfg_rw_bus0_oe_mask___byte1___lsb 1
243 #define reg_iop_sw_cfg_rw_bus0_oe_mask___byte1___width 1
244 #define reg_iop_sw_cfg_rw_bus0_oe_mask___byte1___bit 1
245 #define reg_iop_sw_cfg_rw_bus0_oe_mask___byte2___lsb 2
246 #define reg_iop_sw_cfg_rw_bus0_oe_mask___byte2___width 1
247 #define reg_iop_sw_cfg_rw_bus0_oe_mask___byte2___bit 2
248 #define reg_iop_sw_cfg_rw_bus0_oe_mask___byte3___lsb 3
249 #define reg_iop_sw_cfg_rw_bus0_oe_mask___byte3___width 1
250 #define reg_iop_sw_cfg_rw_bus0_oe_mask___byte3___bit 3
251 #define reg_iop_sw_cfg_rw_bus0_oe_mask_offset 140
253 /* Register rw_bus1_mask, scope iop_sw_cfg, type rw */
254 #define reg_iop_sw_cfg_rw_bus1_mask___byte0___lsb 0
255 #define reg_iop_sw_cfg_rw_bus1_mask___byte0___width 8
256 #define reg_iop_sw_cfg_rw_bus1_mask___byte1___lsb 8
257 #define reg_iop_sw_cfg_rw_bus1_mask___byte1___width 8
258 #define reg_iop_sw_cfg_rw_bus1_mask___byte2___lsb 16
259 #define reg_iop_sw_cfg_rw_bus1_mask___byte2___width 8
260 #define reg_iop_sw_cfg_rw_bus1_mask___byte3___lsb 24
261 #define reg_iop_sw_cfg_rw_bus1_mask___byte3___width 8
262 #define reg_iop_sw_cfg_rw_bus1_mask_offset 144
264 /* Register rw_bus1_oe_mask, scope iop_sw_cfg, type rw */
265 #define reg_iop_sw_cfg_rw_bus1_oe_mask___byte0___lsb 0
266 #define reg_iop_sw_cfg_rw_bus1_oe_mask___byte0___width 1
267 #define reg_iop_sw_cfg_rw_bus1_oe_mask___byte0___bit 0
268 #define reg_iop_sw_cfg_rw_bus1_oe_mask___byte1___lsb 1
269 #define reg_iop_sw_cfg_rw_bus1_oe_mask___byte1___width 1
270 #define reg_iop_sw_cfg_rw_bus1_oe_mask___byte1___bit 1
271 #define reg_iop_sw_cfg_rw_bus1_oe_mask___byte2___lsb 2
272 #define reg_iop_sw_cfg_rw_bus1_oe_mask___byte2___width 1
273 #define reg_iop_sw_cfg_rw_bus1_oe_mask___byte2___bit 2
274 #define reg_iop_sw_cfg_rw_bus1_oe_mask___byte3___lsb 3
275 #define reg_iop_sw_cfg_rw_bus1_oe_mask___byte3___width 1
276 #define reg_iop_sw_cfg_rw_bus1_oe_mask___byte3___bit 3
277 #define reg_iop_sw_cfg_rw_bus1_oe_mask_offset 148
279 /* Register rw_gio_mask, scope iop_sw_cfg, type rw */
280 #define reg_iop_sw_cfg_rw_gio_mask___val___lsb 0
281 #define reg_iop_sw_cfg_rw_gio_mask___val___width 32
282 #define reg_iop_sw_cfg_rw_gio_mask_offset 152
284 /* Register rw_gio_oe_mask, scope iop_sw_cfg, type rw */
285 #define reg_iop_sw_cfg_rw_gio_oe_mask___val___lsb 0
286 #define reg_iop_sw_cfg_rw_gio_oe_mask___val___width 32
287 #define reg_iop_sw_cfg_rw_gio_oe_mask_offset 156
289 /* Register rw_pinmapping, scope iop_sw_cfg, type rw */
290 #define reg_iop_sw_cfg_rw_pinmapping___bus0_byte0___lsb 0
291 #define reg_iop_sw_cfg_rw_pinmapping___bus0_byte0___width 2
292 #define reg_iop_sw_cfg_rw_pinmapping___bus0_byte1___lsb 2
293 #define reg_iop_sw_cfg_rw_pinmapping___bus0_byte1___width 2
294 #define reg_iop_sw_cfg_rw_pinmapping___bus0_byte2___lsb 4
295 #define reg_iop_sw_cfg_rw_pinmapping___bus0_byte2___width 2
296 #define reg_iop_sw_cfg_rw_pinmapping___bus0_byte3___lsb 6
297 #define reg_iop_sw_cfg_rw_pinmapping___bus0_byte3___width 2
298 #define reg_iop_sw_cfg_rw_pinmapping___bus1_byte0___lsb 8
299 #define reg_iop_sw_cfg_rw_pinmapping___bus1_byte0___width 2
300 #define reg_iop_sw_cfg_rw_pinmapping___bus1_byte1___lsb 10
301 #define reg_iop_sw_cfg_rw_pinmapping___bus1_byte1___width 2
302 #define reg_iop_sw_cfg_rw_pinmapping___bus1_byte2___lsb 12
303 #define reg_iop_sw_cfg_rw_pinmapping___bus1_byte2___width 2
304 #define reg_iop_sw_cfg_rw_pinmapping___bus1_byte3___lsb 14
305 #define reg_iop_sw_cfg_rw_pinmapping___bus1_byte3___width 2
306 #define reg_iop_sw_cfg_rw_pinmapping___gio3_0___lsb 16
307 #define reg_iop_sw_cfg_rw_pinmapping___gio3_0___width 2
308 #define reg_iop_sw_cfg_rw_pinmapping___gio7_4___lsb 18
309 #define reg_iop_sw_cfg_rw_pinmapping___gio7_4___width 2
310 #define reg_iop_sw_cfg_rw_pinmapping___gio11_8___lsb 20
311 #define reg_iop_sw_cfg_rw_pinmapping___gio11_8___width 2
312 #define reg_iop_sw_cfg_rw_pinmapping___gio15_12___lsb 22
313 #define reg_iop_sw_cfg_rw_pinmapping___gio15_12___width 2
314 #define reg_iop_sw_cfg_rw_pinmapping___gio19_16___lsb 24
315 #define reg_iop_sw_cfg_rw_pinmapping___gio19_16___width 2
316 #define reg_iop_sw_cfg_rw_pinmapping___gio23_20___lsb 26
317 #define reg_iop_sw_cfg_rw_pinmapping___gio23_20___width 2
318 #define reg_iop_sw_cfg_rw_pinmapping___gio27_24___lsb 28
319 #define reg_iop_sw_cfg_rw_pinmapping___gio27_24___width 2
320 #define reg_iop_sw_cfg_rw_pinmapping___gio31_28___lsb 30
321 #define reg_iop_sw_cfg_rw_pinmapping___gio31_28___width 2
322 #define reg_iop_sw_cfg_rw_pinmapping_offset 160
324 /* Register rw_bus_out_cfg, scope iop_sw_cfg, type rw */
325 #define reg_iop_sw_cfg_rw_bus_out_cfg___bus0_lo___lsb 0
326 #define reg_iop_sw_cfg_rw_bus_out_cfg___bus0_lo___width 3
327 #define reg_iop_sw_cfg_rw_bus_out_cfg___bus0_hi___lsb 3
328 #define reg_iop_sw_cfg_rw_bus_out_cfg___bus0_hi___width 3
329 #define reg_iop_sw_cfg_rw_bus_out_cfg___bus0_lo_oe___lsb 6
330 #define reg_iop_sw_cfg_rw_bus_out_cfg___bus0_lo_oe___width 3
331 #define reg_iop_sw_cfg_rw_bus_out_cfg___bus0_hi_oe___lsb 9
332 #define reg_iop_sw_cfg_rw_bus_out_cfg___bus0_hi_oe___width 3
333 #define reg_iop_sw_cfg_rw_bus_out_cfg___bus1_lo___lsb 12
334 #define reg_iop_sw_cfg_rw_bus_out_cfg___bus1_lo___width 3
335 #define reg_iop_sw_cfg_rw_bus_out_cfg___bus1_hi___lsb 15
336 #define reg_iop_sw_cfg_rw_bus_out_cfg___bus1_hi___width 3
337 #define reg_iop_sw_cfg_rw_bus_out_cfg___bus1_lo_oe___lsb 18
338 #define reg_iop_sw_cfg_rw_bus_out_cfg___bus1_lo_oe___width 3
339 #define reg_iop_sw_cfg_rw_bus_out_cfg___bus1_hi_oe___lsb 21
340 #define reg_iop_sw_cfg_rw_bus_out_cfg___bus1_hi_oe___width 3
341 #define reg_iop_sw_cfg_rw_bus_out_cfg_offset 164
343 /* Register rw_gio_out_grp0_cfg, scope iop_sw_cfg, type rw */
344 #define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio0___lsb 0
345 #define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio0___width 4
346 #define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio0_oe___lsb 4
347 #define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio0_oe___width 2
348 #define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio1___lsb 6
349 #define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio1___width 4
350 #define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio1_oe___lsb 10
351 #define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio1_oe___width 2
352 #define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio2___lsb 12
353 #define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio2___width 4
354 #define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio2_oe___lsb 16
355 #define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio2_oe___width 2
356 #define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio3___lsb 18
357 #define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio3___width 4
358 #define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio3_oe___lsb 22
359 #define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio3_oe___width 2
360 #define reg_iop_sw_cfg_rw_gio_out_grp0_cfg_offset 168
362 /* Register rw_gio_out_grp1_cfg, scope iop_sw_cfg, type rw */
363 #define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio4___lsb 0
364 #define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio4___width 4
365 #define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio4_oe___lsb 4
366 #define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio4_oe___width 2
367 #define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio5___lsb 6
368 #define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio5___width 4
369 #define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio5_oe___lsb 10
370 #define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio5_oe___width 2
371 #define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio6___lsb 12
372 #define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio6___width 4
373 #define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio6_oe___lsb 16
374 #define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio6_oe___width 2
375 #define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio7___lsb 18
376 #define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio7___width 4
377 #define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio7_oe___lsb 22
378 #define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio7_oe___width 2
379 #define reg_iop_sw_cfg_rw_gio_out_grp1_cfg_offset 172
381 /* Register rw_gio_out_grp2_cfg, scope iop_sw_cfg, type rw */
382 #define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio8___lsb 0
383 #define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio8___width 4
384 #define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio8_oe___lsb 4
385 #define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio8_oe___width 2
386 #define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio9___lsb 6
387 #define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio9___width 4
388 #define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio9_oe___lsb 10
389 #define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio9_oe___width 2
390 #define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio10___lsb 12
391 #define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio10___width 4
392 #define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio10_oe___lsb 16
393 #define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio10_oe___width 2
394 #define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio11___lsb 18
395 #define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio11___width 4
396 #define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio11_oe___lsb 22
397 #define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio11_oe___width 2
398 #define reg_iop_sw_cfg_rw_gio_out_grp2_cfg_offset 176
400 /* Register rw_gio_out_grp3_cfg, scope iop_sw_cfg, type rw */
401 #define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio12___lsb 0
402 #define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio12___width 4
403 #define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio12_oe___lsb 4
404 #define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio12_oe___width 2
405 #define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio13___lsb 6
406 #define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio13___width 4
407 #define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio13_oe___lsb 10
408 #define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio13_oe___width 2
409 #define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio14___lsb 12
410 #define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio14___width 4
411 #define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio14_oe___lsb 16
412 #define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio14_oe___width 2
413 #define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio15___lsb 18
414 #define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio15___width 4
415 #define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio15_oe___lsb 22
416 #define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio15_oe___width 2
417 #define reg_iop_sw_cfg_rw_gio_out_grp3_cfg_offset 180
419 /* Register rw_gio_out_grp4_cfg, scope iop_sw_cfg, type rw */
420 #define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio16___lsb 0
421 #define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio16___width 4
422 #define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio16_oe___lsb 4
423 #define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio16_oe___width 2
424 #define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio17___lsb 6
425 #define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio17___width 4
426 #define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio17_oe___lsb 10
427 #define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio17_oe___width 2
428 #define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio18___lsb 12
429 #define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio18___width 4
430 #define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio18_oe___lsb 16
431 #define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio18_oe___width 2
432 #define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio19___lsb 18
433 #define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio19___width 4
434 #define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio19_oe___lsb 22
435 #define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio19_oe___width 2
436 #define reg_iop_sw_cfg_rw_gio_out_grp4_cfg_offset 184
438 /* Register rw_gio_out_grp5_cfg, scope iop_sw_cfg, type rw */
439 #define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio20___lsb 0
440 #define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio20___width 4
441 #define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio20_oe___lsb 4
442 #define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio20_oe___width 2
443 #define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio21___lsb 6
444 #define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio21___width 4
445 #define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio21_oe___lsb 10
446 #define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio21_oe___width 2
447 #define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio22___lsb 12
448 #define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio22___width 4
449 #define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio22_oe___lsb 16
450 #define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio22_oe___width 2
451 #define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio23___lsb 18
452 #define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio23___width 4
453 #define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio23_oe___lsb 22
454 #define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio23_oe___width 2
455 #define reg_iop_sw_cfg_rw_gio_out_grp5_cfg_offset 188
457 /* Register rw_gio_out_grp6_cfg, scope iop_sw_cfg, type rw */
458 #define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio24___lsb 0
459 #define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio24___width 4
460 #define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio24_oe___lsb 4
461 #define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio24_oe___width 2
462 #define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio25___lsb 6
463 #define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio25___width 4
464 #define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio25_oe___lsb 10
465 #define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio25_oe___width 2
466 #define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio26___lsb 12
467 #define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio26___width 4
468 #define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio26_oe___lsb 16
469 #define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio26_oe___width 2
470 #define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio27___lsb 18
471 #define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio27___width 4
472 #define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio27_oe___lsb 22
473 #define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio27_oe___width 2
474 #define reg_iop_sw_cfg_rw_gio_out_grp6_cfg_offset 192
476 /* Register rw_gio_out_grp7_cfg, scope iop_sw_cfg, type rw */
477 #define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio28___lsb 0
478 #define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio28___width 4
479 #define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio28_oe___lsb 4
480 #define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio28_oe___width 2
481 #define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio29___lsb 6
482 #define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio29___width 4
483 #define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio29_oe___lsb 10
484 #define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio29_oe___width 2
485 #define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio30___lsb 12
486 #define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio30___width 4
487 #define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio30_oe___lsb 16
488 #define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio30_oe___width 2
489 #define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio31___lsb 18
490 #define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio31___width 4
491 #define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio31_oe___lsb 22
492 #define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio31_oe___width 2
493 #define reg_iop_sw_cfg_rw_gio_out_grp7_cfg_offset 196
495 /* Register rw_spu0_cfg, scope iop_sw_cfg, type rw */
496 #define reg_iop_sw_cfg_rw_spu0_cfg___bus0_in___lsb 0
497 #define reg_iop_sw_cfg_rw_spu0_cfg___bus0_in___width 2
498 #define reg_iop_sw_cfg_rw_spu0_cfg___bus1_in___lsb 2
499 #define reg_iop_sw_cfg_rw_spu0_cfg___bus1_in___width 2
500 #define reg_iop_sw_cfg_rw_spu0_cfg_offset 200
502 /* Register rw_spu1_cfg, scope iop_sw_cfg, type rw */
503 #define reg_iop_sw_cfg_rw_spu1_cfg___bus0_in___lsb 0
504 #define reg_iop_sw_cfg_rw_spu1_cfg___bus0_in___width 2
505 #define reg_iop_sw_cfg_rw_spu1_cfg___bus1_in___lsb 2
506 #define reg_iop_sw_cfg_rw_spu1_cfg___bus1_in___width 2
507 #define reg_iop_sw_cfg_rw_spu1_cfg_offset 204
509 /* Register rw_timer_grp0_cfg, scope iop_sw_cfg, type rw */
510 #define reg_iop_sw_cfg_rw_timer_grp0_cfg___ext_clk___lsb 0
511 #define reg_iop_sw_cfg_rw_timer_grp0_cfg___ext_clk___width 3
512 #define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr0_en___lsb 3
513 #define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr0_en___width 1
514 #define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr0_en___bit 3
515 #define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr1_en___lsb 4
516 #define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr1_en___width 1
517 #define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr1_en___bit 4
518 #define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr2_en___lsb 5
519 #define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr2_en___width 1
520 #define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr2_en___bit 5
521 #define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr3_en___lsb 6
522 #define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr3_en___width 1
523 #define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr3_en___bit 6
524 #define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr0_dis___lsb 7
525 #define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr0_dis___width 1
526 #define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr0_dis___bit 7
527 #define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr1_dis___lsb 8
528 #define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr1_dis___width 1
529 #define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr1_dis___bit 8
530 #define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr2_dis___lsb 9
531 #define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr2_dis___width 1
532 #define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr2_dis___bit 9
533 #define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr3_dis___lsb 10
534 #define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr3_dis___width 1
535 #define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr3_dis___bit 10
536 #define reg_iop_sw_cfg_rw_timer_grp0_cfg_offset 208
538 /* Register rw_timer_grp1_cfg, scope iop_sw_cfg, type rw */
539 #define reg_iop_sw_cfg_rw_timer_grp1_cfg___ext_clk___lsb 0
540 #define reg_iop_sw_cfg_rw_timer_grp1_cfg___ext_clk___width 3
541 #define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr0_en___lsb 3
542 #define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr0_en___width 1
543 #define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr0_en___bit 3
544 #define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr1_en___lsb 4
545 #define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr1_en___width 1
546 #define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr1_en___bit 4
547 #define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr2_en___lsb 5
548 #define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr2_en___width 1
549 #define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr2_en___bit 5
550 #define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr3_en___lsb 6
551 #define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr3_en___width 1
552 #define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr3_en___bit 6
553 #define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr0_dis___lsb 7
554 #define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr0_dis___width 1
555 #define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr0_dis___bit 7
556 #define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr1_dis___lsb 8
557 #define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr1_dis___width 1
558 #define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr1_dis___bit 8
559 #define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr2_dis___lsb 9
560 #define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr2_dis___width 1
561 #define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr2_dis___bit 9
562 #define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr3_dis___lsb 10
563 #define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr3_dis___width 1
564 #define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr3_dis___bit 10
565 #define reg_iop_sw_cfg_rw_timer_grp1_cfg_offset 212
567 /* Register rw_timer_grp2_cfg, scope iop_sw_cfg, type rw */
568 #define reg_iop_sw_cfg_rw_timer_grp2_cfg___ext_clk___lsb 0
569 #define reg_iop_sw_cfg_rw_timer_grp2_cfg___ext_clk___width 3
570 #define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr0_en___lsb 3
571 #define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr0_en___width 1
572 #define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr0_en___bit 3
573 #define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr1_en___lsb 4
574 #define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr1_en___width 1
575 #define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr1_en___bit 4
576 #define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr2_en___lsb 5
577 #define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr2_en___width 1
578 #define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr2_en___bit 5
579 #define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr3_en___lsb 6
580 #define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr3_en___width 1
581 #define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr3_en___bit 6
582 #define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr0_dis___lsb 7
583 #define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr0_dis___width 1
584 #define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr0_dis___bit 7
585 #define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr1_dis___lsb 8
586 #define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr1_dis___width 1
587 #define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr1_dis___bit 8
588 #define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr2_dis___lsb 9
589 #define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr2_dis___width 1
590 #define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr2_dis___bit 9
591 #define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr3_dis___lsb 10
592 #define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr3_dis___width 1
593 #define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr3_dis___bit 10
594 #define reg_iop_sw_cfg_rw_timer_grp2_cfg_offset 216
596 /* Register rw_timer_grp3_cfg, scope iop_sw_cfg, type rw */
597 #define reg_iop_sw_cfg_rw_timer_grp3_cfg___ext_clk___lsb 0
598 #define reg_iop_sw_cfg_rw_timer_grp3_cfg___ext_clk___width 3
599 #define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr0_en___lsb 3
600 #define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr0_en___width 1
601 #define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr0_en___bit 3
602 #define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr1_en___lsb 4
603 #define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr1_en___width 1
604 #define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr1_en___bit 4
605 #define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr2_en___lsb 5
606 #define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr2_en___width 1
607 #define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr2_en___bit 5
608 #define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr3_en___lsb 6
609 #define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr3_en___width 1
610 #define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr3_en___bit 6
611 #define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr0_dis___lsb 7
612 #define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr0_dis___width 1
613 #define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr0_dis___bit 7
614 #define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr1_dis___lsb 8
615 #define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr1_dis___width 1
616 #define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr1_dis___bit 8
617 #define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr2_dis___lsb 9
618 #define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr2_dis___width 1
619 #define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr2_dis___bit 9
620 #define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr3_dis___lsb 10
621 #define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr3_dis___width 1
622 #define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr3_dis___bit 10
623 #define reg_iop_sw_cfg_rw_timer_grp3_cfg_offset 220
625 /* Register rw_trigger_grps_cfg, scope iop_sw_cfg, type rw */
626 #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_dis___lsb 0
627 #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_dis___width 1
628 #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_dis___bit 0
629 #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_en___lsb 1
630 #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_en___width 1
631 #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_en___bit 1
632 #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_dis___lsb 2
633 #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_dis___width 1
634 #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_dis___bit 2
635 #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_en___lsb 3
636 #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_en___width 1
637 #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_en___bit 3
638 #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_dis___lsb 4
639 #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_dis___width 1
640 #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_dis___bit 4
641 #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_en___lsb 5
642 #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_en___width 1
643 #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_en___bit 5
644 #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_dis___lsb 6
645 #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_dis___width 1
646 #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_dis___bit 6
647 #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_en___lsb 7
648 #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_en___width 1
649 #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_en___bit 7
650 #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_dis___lsb 8
651 #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_dis___width 1
652 #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_dis___bit 8
653 #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_en___lsb 9
654 #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_en___width 1
655 #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_en___bit 9
656 #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_dis___lsb 10
657 #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_dis___width 1
658 #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_dis___bit 10
659 #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_en___lsb 11
660 #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_en___width 1
661 #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_en___bit 11
662 #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_dis___lsb 12
663 #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_dis___width 1
664 #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_dis___bit 12
665 #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_en___lsb 13
666 #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_en___width 1
667 #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_en___bit 13
668 #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_dis___lsb 14
669 #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_dis___width 1
670 #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_dis___bit 14
671 #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_en___lsb 15
672 #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_en___width 1
673 #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_en___bit 15
674 #define reg_iop_sw_cfg_rw_trigger_grps_cfg_offset 224
676 /* Register rw_pdp0_cfg, scope iop_sw_cfg, type rw */
677 #define reg_iop_sw_cfg_rw_pdp0_cfg___dmc0_usr___lsb 0
678 #define reg_iop_sw_cfg_rw_pdp0_cfg___dmc0_usr___width 1
679 #define reg_iop_sw_cfg_rw_pdp0_cfg___dmc0_usr___bit 0
680 #define reg_iop_sw_cfg_rw_pdp0_cfg___out_strb___lsb 1
681 #define reg_iop_sw_cfg_rw_pdp0_cfg___out_strb___width 5
682 #define reg_iop_sw_cfg_rw_pdp0_cfg___in_src___lsb 6
683 #define reg_iop_sw_cfg_rw_pdp0_cfg___in_src___width 3
684 #define reg_iop_sw_cfg_rw_pdp0_cfg___in_size___lsb 9
685 #define reg_iop_sw_cfg_rw_pdp0_cfg___in_size___width 3
686 #define reg_iop_sw_cfg_rw_pdp0_cfg___in_last___lsb 12
687 #define reg_iop_sw_cfg_rw_pdp0_cfg___in_last___width 2
688 #define reg_iop_sw_cfg_rw_pdp0_cfg___in_strb___lsb 14
689 #define reg_iop_sw_cfg_rw_pdp0_cfg___in_strb___width 4
690 #define reg_iop_sw_cfg_rw_pdp0_cfg___out_src___lsb 18
691 #define reg_iop_sw_cfg_rw_pdp0_cfg___out_src___width 1
692 #define reg_iop_sw_cfg_rw_pdp0_cfg___out_src___bit 18
693 #define reg_iop_sw_cfg_rw_pdp0_cfg_offset 228
695 /* Register rw_pdp1_cfg, scope iop_sw_cfg, type rw */
696 #define reg_iop_sw_cfg_rw_pdp1_cfg___dmc1_usr___lsb 0
697 #define reg_iop_sw_cfg_rw_pdp1_cfg___dmc1_usr___width 1
698 #define reg_iop_sw_cfg_rw_pdp1_cfg___dmc1_usr___bit 0
699 #define reg_iop_sw_cfg_rw_pdp1_cfg___out_strb___lsb 1
700 #define reg_iop_sw_cfg_rw_pdp1_cfg___out_strb___width 5
701 #define reg_iop_sw_cfg_rw_pdp1_cfg___in_src___lsb 6
702 #define reg_iop_sw_cfg_rw_pdp1_cfg___in_src___width 3
703 #define reg_iop_sw_cfg_rw_pdp1_cfg___in_size___lsb 9
704 #define reg_iop_sw_cfg_rw_pdp1_cfg___in_size___width 3
705 #define reg_iop_sw_cfg_rw_pdp1_cfg___in_last___lsb 12
706 #define reg_iop_sw_cfg_rw_pdp1_cfg___in_last___width 2
707 #define reg_iop_sw_cfg_rw_pdp1_cfg___in_strb___lsb 14
708 #define reg_iop_sw_cfg_rw_pdp1_cfg___in_strb___width 4
709 #define reg_iop_sw_cfg_rw_pdp1_cfg___out_src___lsb 18
710 #define reg_iop_sw_cfg_rw_pdp1_cfg___out_src___width 1
711 #define reg_iop_sw_cfg_rw_pdp1_cfg___out_src___bit 18
712 #define reg_iop_sw_cfg_rw_pdp1_cfg_offset 232
714 /* Register rw_sdp_cfg, scope iop_sw_cfg, type rw */
715 #define reg_iop_sw_cfg_rw_sdp_cfg___sdp_out0_strb___lsb 0
716 #define reg_iop_sw_cfg_rw_sdp_cfg___sdp_out0_strb___width 3
717 #define reg_iop_sw_cfg_rw_sdp_cfg___sdp_out1_strb___lsb 3
718 #define reg_iop_sw_cfg_rw_sdp_cfg___sdp_out1_strb___width 3
719 #define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in0_data___lsb 6
720 #define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in0_data___width 3
721 #define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in0_last___lsb 9
722 #define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in0_last___width 2
723 #define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in0_strb___lsb 11
724 #define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in0_strb___width 3
725 #define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in1_data___lsb 14
726 #define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in1_data___width 3
727 #define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in1_last___lsb 17
728 #define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in1_last___width 2
729 #define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in1_strb___lsb 19
730 #define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in1_strb___width 3
731 #define reg_iop_sw_cfg_rw_sdp_cfg_offset 236
735 #define regk_iop_sw_cfg_a 0x00000001
736 #define regk_iop_sw_cfg_b 0x00000002
737 #define regk_iop_sw_cfg_bus0 0x00000000
738 #define regk_iop_sw_cfg_bus0_rot16 0x00000004
739 #define regk_iop_sw_cfg_bus0_rot24 0x00000006
740 #define regk_iop_sw_cfg_bus0_rot8 0x00000002
741 #define regk_iop_sw_cfg_bus1 0x00000001
742 #define regk_iop_sw_cfg_bus1_rot16 0x00000005
743 #define regk_iop_sw_cfg_bus1_rot24 0x00000007
744 #define regk_iop_sw_cfg_bus1_rot8 0x00000003
745 #define regk_iop_sw_cfg_clk12 0x00000000
746 #define regk_iop_sw_cfg_cpu 0x00000000
747 #define regk_iop_sw_cfg_dmc0 0x00000000
748 #define regk_iop_sw_cfg_dmc1 0x00000001
749 #define regk_iop_sw_cfg_gated_clk0 0x00000010
750 #define regk_iop_sw_cfg_gated_clk1 0x00000011
751 #define regk_iop_sw_cfg_gated_clk2 0x00000012
752 #define regk_iop_sw_cfg_gated_clk3 0x00000013
753 #define regk_iop_sw_cfg_gio0 0x00000004
754 #define regk_iop_sw_cfg_gio1 0x00000001
755 #define regk_iop_sw_cfg_gio2 0x00000005
756 #define regk_iop_sw_cfg_gio3 0x00000002
757 #define regk_iop_sw_cfg_gio4 0x00000006
758 #define regk_iop_sw_cfg_gio5 0x00000003
759 #define regk_iop_sw_cfg_gio6 0x00000007
760 #define regk_iop_sw_cfg_gio7 0x00000004
761 #define regk_iop_sw_cfg_gio_in0 0x00000000
762 #define regk_iop_sw_cfg_gio_in1 0x00000001
763 #define regk_iop_sw_cfg_gio_in10 0x00000002
764 #define regk_iop_sw_cfg_gio_in11 0x00000003
765 #define regk_iop_sw_cfg_gio_in14 0x00000004
766 #define regk_iop_sw_cfg_gio_in15 0x00000005
767 #define regk_iop_sw_cfg_gio_in18 0x00000002
768 #define regk_iop_sw_cfg_gio_in19 0x00000003
769 #define regk_iop_sw_cfg_gio_in20 0x00000004
770 #define regk_iop_sw_cfg_gio_in21 0x00000005
771 #define regk_iop_sw_cfg_gio_in26 0x00000006
772 #define regk_iop_sw_cfg_gio_in27 0x00000007
773 #define regk_iop_sw_cfg_gio_in28 0x00000006
774 #define regk_iop_sw_cfg_gio_in29 0x00000007
775 #define regk_iop_sw_cfg_gio_in4 0x00000000
776 #define regk_iop_sw_cfg_gio_in5 0x00000001
777 #define regk_iop_sw_cfg_last_timer_grp0_tmr2 0x00000001
778 #define regk_iop_sw_cfg_last_timer_grp1_tmr2 0x00000001
779 #define regk_iop_sw_cfg_last_timer_grp2_tmr2 0x00000002
780 #define regk_iop_sw_cfg_last_timer_grp2_tmr3 0x00000003
781 #define regk_iop_sw_cfg_last_timer_grp3_tmr2 0x00000002
782 #define regk_iop_sw_cfg_last_timer_grp3_tmr3 0x00000003
783 #define regk_iop_sw_cfg_mpu 0x00000001
784 #define regk_iop_sw_cfg_none 0x00000000
785 #define regk_iop_sw_cfg_par0 0x00000000
786 #define regk_iop_sw_cfg_par1 0x00000001
787 #define regk_iop_sw_cfg_pdp_out0 0x00000002
788 #define regk_iop_sw_cfg_pdp_out0_hi 0x00000001
789 #define regk_iop_sw_cfg_pdp_out0_hi_rot8 0x00000005
790 #define regk_iop_sw_cfg_pdp_out0_lo 0x00000000
791 #define regk_iop_sw_cfg_pdp_out0_lo_rot8 0x00000004
792 #define regk_iop_sw_cfg_pdp_out1 0x00000003
793 #define regk_iop_sw_cfg_pdp_out1_hi 0x00000003
794 #define regk_iop_sw_cfg_pdp_out1_hi_rot8 0x00000005
795 #define regk_iop_sw_cfg_pdp_out1_lo 0x00000002
796 #define regk_iop_sw_cfg_pdp_out1_lo_rot8 0x00000004
797 #define regk_iop_sw_cfg_rw_bus0_mask_default 0x00000000
798 #define regk_iop_sw_cfg_rw_bus0_oe_mask_default 0x00000000
799 #define regk_iop_sw_cfg_rw_bus1_mask_default 0x00000000
800 #define regk_iop_sw_cfg_rw_bus1_oe_mask_default 0x00000000
801 #define regk_iop_sw_cfg_rw_bus_out_cfg_default 0x00000000
802 #define regk_iop_sw_cfg_rw_crc_par0_owner_default 0x00000000
803 #define regk_iop_sw_cfg_rw_crc_par1_owner_default 0x00000000
804 #define regk_iop_sw_cfg_rw_dmc_in0_owner_default 0x00000000
805 #define regk_iop_sw_cfg_rw_dmc_in1_owner_default 0x00000000
806 #define regk_iop_sw_cfg_rw_dmc_out0_owner_default 0x00000000
807 #define regk_iop_sw_cfg_rw_dmc_out1_owner_default 0x00000000
808 #define regk_iop_sw_cfg_rw_fifo_in0_extra_owner_default 0x00000000
809 #define regk_iop_sw_cfg_rw_fifo_in0_owner_default 0x00000000
810 #define regk_iop_sw_cfg_rw_fifo_in1_extra_owner_default 0x00000000
811 #define regk_iop_sw_cfg_rw_fifo_in1_owner_default 0x00000000
812 #define regk_iop_sw_cfg_rw_fifo_out0_extra_owner_default 0x00000000
813 #define regk_iop_sw_cfg_rw_fifo_out0_owner_default 0x00000000
814 #define regk_iop_sw_cfg_rw_fifo_out1_extra_owner_default 0x00000000
815 #define regk_iop_sw_cfg_rw_fifo_out1_owner_default 0x00000000
816 #define regk_iop_sw_cfg_rw_gio_mask_default 0x00000000
817 #define regk_iop_sw_cfg_rw_gio_oe_mask_default 0x00000000
818 #define regk_iop_sw_cfg_rw_gio_out_grp0_cfg_default 0x00000000
819 #define regk_iop_sw_cfg_rw_gio_out_grp1_cfg_default 0x00000000
820 #define regk_iop_sw_cfg_rw_gio_out_grp2_cfg_default 0x00000000
821 #define regk_iop_sw_cfg_rw_gio_out_grp3_cfg_default 0x00000000
822 #define regk_iop_sw_cfg_rw_gio_out_grp4_cfg_default 0x00000000
823 #define regk_iop_sw_cfg_rw_gio_out_grp5_cfg_default 0x00000000
824 #define regk_iop_sw_cfg_rw_gio_out_grp6_cfg_default 0x00000000
825 #define regk_iop_sw_cfg_rw_gio_out_grp7_cfg_default 0x00000000
826 #define regk_iop_sw_cfg_rw_pdp0_cfg_default 0x00000000
827 #define regk_iop_sw_cfg_rw_pdp1_cfg_default 0x00000000
828 #define regk_iop_sw_cfg_rw_pinmapping_default 0x55555555
829 #define regk_iop_sw_cfg_rw_sap_in_owner_default 0x00000000
830 #define regk_iop_sw_cfg_rw_sap_out_owner_default 0x00000000
831 #define regk_iop_sw_cfg_rw_scrc_in0_owner_default 0x00000000
832 #define regk_iop_sw_cfg_rw_scrc_in1_owner_default 0x00000000
833 #define regk_iop_sw_cfg_rw_scrc_out0_owner_default 0x00000000
834 #define regk_iop_sw_cfg_rw_scrc_out1_owner_default 0x00000000
835 #define regk_iop_sw_cfg_rw_sdp_cfg_default 0x00000000
836 #define regk_iop_sw_cfg_rw_spu0_cfg_default 0x00000000
837 #define regk_iop_sw_cfg_rw_spu0_owner_default 0x00000000
838 #define regk_iop_sw_cfg_rw_spu1_cfg_default 0x00000000
839 #define regk_iop_sw_cfg_rw_spu1_owner_default 0x00000000
840 #define regk_iop_sw_cfg_rw_timer_grp0_cfg_default 0x00000000
841 #define regk_iop_sw_cfg_rw_timer_grp0_owner_default 0x00000000
842 #define regk_iop_sw_cfg_rw_timer_grp1_cfg_default 0x00000000
843 #define regk_iop_sw_cfg_rw_timer_grp1_owner_default 0x00000000
844 #define regk_iop_sw_cfg_rw_timer_grp2_cfg_default 0x00000000
845 #define regk_iop_sw_cfg_rw_timer_grp2_owner_default 0x00000000
846 #define regk_iop_sw_cfg_rw_timer_grp3_cfg_default 0x00000000
847 #define regk_iop_sw_cfg_rw_timer_grp3_owner_default 0x00000000
848 #define regk_iop_sw_cfg_rw_trigger_grp0_owner_default 0x00000000
849 #define regk_iop_sw_cfg_rw_trigger_grp1_owner_default 0x00000000
850 #define regk_iop_sw_cfg_rw_trigger_grp2_owner_default 0x00000000
851 #define regk_iop_sw_cfg_rw_trigger_grp3_owner_default 0x00000000
852 #define regk_iop_sw_cfg_rw_trigger_grp4_owner_default 0x00000000
853 #define regk_iop_sw_cfg_rw_trigger_grp5_owner_default 0x00000000
854 #define regk_iop_sw_cfg_rw_trigger_grp6_owner_default 0x00000000
855 #define regk_iop_sw_cfg_rw_trigger_grp7_owner_default 0x00000000
856 #define regk_iop_sw_cfg_rw_trigger_grps_cfg_default 0x00000000
857 #define regk_iop_sw_cfg_sdp_out0 0x00000008
858 #define regk_iop_sw_cfg_sdp_out1 0x00000009
859 #define regk_iop_sw_cfg_size16 0x00000002
860 #define regk_iop_sw_cfg_size24 0x00000003
861 #define regk_iop_sw_cfg_size32 0x00000004
862 #define regk_iop_sw_cfg_size8 0x00000001
863 #define regk_iop_sw_cfg_spu0 0x00000002
864 #define regk_iop_sw_cfg_spu0_bus_out0_hi 0x00000006
865 #define regk_iop_sw_cfg_spu0_bus_out0_lo 0x00000006
866 #define regk_iop_sw_cfg_spu0_bus_out1_hi 0x00000007
867 #define regk_iop_sw_cfg_spu0_bus_out1_lo 0x00000007
868 #define regk_iop_sw_cfg_spu0_g0 0x0000000e
869 #define regk_iop_sw_cfg_spu0_g1 0x0000000e
870 #define regk_iop_sw_cfg_spu0_g2 0x0000000e
871 #define regk_iop_sw_cfg_spu0_g3 0x0000000e
872 #define regk_iop_sw_cfg_spu0_g4 0x0000000e
873 #define regk_iop_sw_cfg_spu0_g5 0x0000000e
874 #define regk_iop_sw_cfg_spu0_g6 0x0000000e
875 #define regk_iop_sw_cfg_spu0_g7 0x0000000e
876 #define regk_iop_sw_cfg_spu0_gio0 0x00000000
877 #define regk_iop_sw_cfg_spu0_gio1 0x00000001
878 #define regk_iop_sw_cfg_spu0_gio2 0x00000000
879 #define regk_iop_sw_cfg_spu0_gio5 0x00000005
880 #define regk_iop_sw_cfg_spu0_gio6 0x00000006
881 #define regk_iop_sw_cfg_spu0_gio7 0x00000007
882 #define regk_iop_sw_cfg_spu0_gio_out0 0x00000008
883 #define regk_iop_sw_cfg_spu0_gio_out1 0x00000009
884 #define regk_iop_sw_cfg_spu0_gio_out2 0x0000000a
885 #define regk_iop_sw_cfg_spu0_gio_out3 0x0000000b
886 #define regk_iop_sw_cfg_spu0_gio_out4 0x0000000c
887 #define regk_iop_sw_cfg_spu0_gio_out5 0x0000000d
888 #define regk_iop_sw_cfg_spu0_gio_out6 0x0000000e
889 #define regk_iop_sw_cfg_spu0_gio_out7 0x0000000f
890 #define regk_iop_sw_cfg_spu0_gioout0 0x00000000
891 #define regk_iop_sw_cfg_spu0_gioout1 0x00000000
892 #define regk_iop_sw_cfg_spu0_gioout10 0x0000000e
893 #define regk_iop_sw_cfg_spu0_gioout11 0x0000000e
894 #define regk_iop_sw_cfg_spu0_gioout12 0x0000000e
895 #define regk_iop_sw_cfg_spu0_gioout13 0x0000000e
896 #define regk_iop_sw_cfg_spu0_gioout14 0x0000000e
897 #define regk_iop_sw_cfg_spu0_gioout15 0x0000000e
898 #define regk_iop_sw_cfg_spu0_gioout16 0x0000000e
899 #define regk_iop_sw_cfg_spu0_gioout17 0x0000000e
900 #define regk_iop_sw_cfg_spu0_gioout18 0x0000000e
901 #define regk_iop_sw_cfg_spu0_gioout19 0x0000000e
902 #define regk_iop_sw_cfg_spu0_gioout2 0x00000002
903 #define regk_iop_sw_cfg_spu0_gioout20 0x0000000e
904 #define regk_iop_sw_cfg_spu0_gioout21 0x0000000e
905 #define regk_iop_sw_cfg_spu0_gioout22 0x0000000e
906 #define regk_iop_sw_cfg_spu0_gioout23 0x0000000e
907 #define regk_iop_sw_cfg_spu0_gioout24 0x0000000e
908 #define regk_iop_sw_cfg_spu0_gioout25 0x0000000e
909 #define regk_iop_sw_cfg_spu0_gioout26 0x0000000e
910 #define regk_iop_sw_cfg_spu0_gioout27 0x0000000e
911 #define regk_iop_sw_cfg_spu0_gioout28 0x0000000e
912 #define regk_iop_sw_cfg_spu0_gioout29 0x0000000e
913 #define regk_iop_sw_cfg_spu0_gioout3 0x00000002
914 #define regk_iop_sw_cfg_spu0_gioout30 0x0000000e
915 #define regk_iop_sw_cfg_spu0_gioout31 0x0000000e
916 #define regk_iop_sw_cfg_spu0_gioout4 0x00000004
917 #define regk_iop_sw_cfg_spu0_gioout5 0x00000004
918 #define regk_iop_sw_cfg_spu0_gioout6 0x00000006
919 #define regk_iop_sw_cfg_spu0_gioout7 0x00000006
920 #define regk_iop_sw_cfg_spu0_gioout8 0x0000000e
921 #define regk_iop_sw_cfg_spu0_gioout9 0x0000000e
922 #define regk_iop_sw_cfg_spu1 0x00000003
923 #define regk_iop_sw_cfg_spu1_bus_out0_hi 0x00000006
924 #define regk_iop_sw_cfg_spu1_bus_out0_lo 0x00000006
925 #define regk_iop_sw_cfg_spu1_bus_out1_hi 0x00000007
926 #define regk_iop_sw_cfg_spu1_bus_out1_lo 0x00000007
927 #define regk_iop_sw_cfg_spu1_g0 0x0000000f
928 #define regk_iop_sw_cfg_spu1_g1 0x0000000f
929 #define regk_iop_sw_cfg_spu1_g2 0x0000000f
930 #define regk_iop_sw_cfg_spu1_g3 0x0000000f
931 #define regk_iop_sw_cfg_spu1_g4 0x0000000f
932 #define regk_iop_sw_cfg_spu1_g5 0x0000000f
933 #define regk_iop_sw_cfg_spu1_g6 0x0000000f
934 #define regk_iop_sw_cfg_spu1_g7 0x0000000f
935 #define regk_iop_sw_cfg_spu1_gio0 0x00000002
936 #define regk_iop_sw_cfg_spu1_gio1 0x00000003
937 #define regk_iop_sw_cfg_spu1_gio2 0x00000002
938 #define regk_iop_sw_cfg_spu1_gio5 0x00000005
939 #define regk_iop_sw_cfg_spu1_gio6 0x00000006
940 #define regk_iop_sw_cfg_spu1_gio7 0x00000007
941 #define regk_iop_sw_cfg_spu1_gio_out0 0x00000008
942 #define regk_iop_sw_cfg_spu1_gio_out1 0x00000009
943 #define regk_iop_sw_cfg_spu1_gio_out2 0x0000000a
944 #define regk_iop_sw_cfg_spu1_gio_out3 0x0000000b
945 #define regk_iop_sw_cfg_spu1_gio_out4 0x0000000c
946 #define regk_iop_sw_cfg_spu1_gio_out5 0x0000000d
947 #define regk_iop_sw_cfg_spu1_gio_out6 0x0000000e
948 #define regk_iop_sw_cfg_spu1_gio_out7 0x0000000f
949 #define regk_iop_sw_cfg_spu1_gioout0 0x00000001
950 #define regk_iop_sw_cfg_spu1_gioout1 0x00000001
951 #define regk_iop_sw_cfg_spu1_gioout10 0x0000000f
952 #define regk_iop_sw_cfg_spu1_gioout11 0x0000000f
953 #define regk_iop_sw_cfg_spu1_gioout12 0x0000000f
954 #define regk_iop_sw_cfg_spu1_gioout13 0x0000000f
955 #define regk_iop_sw_cfg_spu1_gioout14 0x0000000f
956 #define regk_iop_sw_cfg_spu1_gioout15 0x0000000f
957 #define regk_iop_sw_cfg_spu1_gioout16 0x0000000f
958 #define regk_iop_sw_cfg_spu1_gioout17 0x0000000f
959 #define regk_iop_sw_cfg_spu1_gioout18 0x0000000f
960 #define regk_iop_sw_cfg_spu1_gioout19 0x0000000f
961 #define regk_iop_sw_cfg_spu1_gioout2 0x00000003
962 #define regk_iop_sw_cfg_spu1_gioout20 0x0000000f
963 #define regk_iop_sw_cfg_spu1_gioout21 0x0000000f
964 #define regk_iop_sw_cfg_spu1_gioout22 0x0000000f
965 #define regk_iop_sw_cfg_spu1_gioout23 0x0000000f
966 #define regk_iop_sw_cfg_spu1_gioout24 0x0000000f
967 #define regk_iop_sw_cfg_spu1_gioout25 0x0000000f
968 #define regk_iop_sw_cfg_spu1_gioout26 0x0000000f
969 #define regk_iop_sw_cfg_spu1_gioout27 0x0000000f
970 #define regk_iop_sw_cfg_spu1_gioout28 0x0000000f
971 #define regk_iop_sw_cfg_spu1_gioout29 0x0000000f
972 #define regk_iop_sw_cfg_spu1_gioout3 0x00000003
973 #define regk_iop_sw_cfg_spu1_gioout30 0x0000000f
974 #define regk_iop_sw_cfg_spu1_gioout31 0x0000000f
975 #define regk_iop_sw_cfg_spu1_gioout4 0x00000005
976 #define regk_iop_sw_cfg_spu1_gioout5 0x00000005
977 #define regk_iop_sw_cfg_spu1_gioout6 0x00000007
978 #define regk_iop_sw_cfg_spu1_gioout7 0x00000007
979 #define regk_iop_sw_cfg_spu1_gioout8 0x0000000f
980 #define regk_iop_sw_cfg_spu1_gioout9 0x0000000f
981 #define regk_iop_sw_cfg_strb_timer_grp0_tmr0 0x00000001
982 #define regk_iop_sw_cfg_strb_timer_grp0_tmr1 0x00000002
983 #define regk_iop_sw_cfg_strb_timer_grp1_tmr0 0x00000001
984 #define regk_iop_sw_cfg_strb_timer_grp1_tmr1 0x00000002
985 #define regk_iop_sw_cfg_strb_timer_grp2_tmr0 0x00000003
986 #define regk_iop_sw_cfg_strb_timer_grp2_tmr1 0x00000002
987 #define regk_iop_sw_cfg_strb_timer_grp3_tmr0 0x00000003
988 #define regk_iop_sw_cfg_strb_timer_grp3_tmr1 0x00000002
989 #define regk_iop_sw_cfg_timer_grp0 0x00000000
990 #define regk_iop_sw_cfg_timer_grp0_rot 0x00000001
991 #define regk_iop_sw_cfg_timer_grp0_strb0 0x0000000a
992 #define regk_iop_sw_cfg_timer_grp0_strb1 0x0000000a
993 #define regk_iop_sw_cfg_timer_grp0_strb2 0x0000000a
994 #define regk_iop_sw_cfg_timer_grp0_strb3 0x0000000a
995 #define regk_iop_sw_cfg_timer_grp0_tmr0 0x00000004
996 #define regk_iop_sw_cfg_timer_grp0_tmr1 0x00000004
997 #define regk_iop_sw_cfg_timer_grp1 0x00000000
998 #define regk_iop_sw_cfg_timer_grp1_rot 0x00000001
999 #define regk_iop_sw_cfg_timer_grp1_strb0 0x0000000b
1000 #define regk_iop_sw_cfg_timer_grp1_strb1 0x0000000b
1001 #define regk_iop_sw_cfg_timer_grp1_strb2 0x0000000b
1002 #define regk_iop_sw_cfg_timer_grp1_strb3 0x0000000b
1003 #define regk_iop_sw_cfg_timer_grp1_tmr0 0x00000005
1004 #define regk_iop_sw_cfg_timer_grp1_tmr1 0x00000005
1005 #define regk_iop_sw_cfg_timer_grp2 0x00000000
1006 #define regk_iop_sw_cfg_timer_grp2_rot 0x00000001
1007 #define regk_iop_sw_cfg_timer_grp2_strb0 0x0000000c
1008 #define regk_iop_sw_cfg_timer_grp2_strb1 0x0000000c
1009 #define regk_iop_sw_cfg_timer_grp2_strb2 0x0000000c
1010 #define regk_iop_sw_cfg_timer_grp2_strb3 0x0000000c
1011 #define regk_iop_sw_cfg_timer_grp2_tmr0 0x00000006
1012 #define regk_iop_sw_cfg_timer_grp2_tmr1 0x00000006
1013 #define regk_iop_sw_cfg_timer_grp3 0x00000000
1014 #define regk_iop_sw_cfg_timer_grp3_rot 0x00000001
1015 #define regk_iop_sw_cfg_timer_grp3_strb0 0x0000000d
1016 #define regk_iop_sw_cfg_timer_grp3_strb1 0x0000000d
1017 #define regk_iop_sw_cfg_timer_grp3_strb2 0x0000000d
1018 #define regk_iop_sw_cfg_timer_grp3_strb3 0x0000000d
1019 #define regk_iop_sw_cfg_timer_grp3_tmr0 0x00000007
1020 #define regk_iop_sw_cfg_timer_grp3_tmr1 0x00000007
1021 #define regk_iop_sw_cfg_trig0_0 0x00000000
1022 #define regk_iop_sw_cfg_trig0_1 0x00000000
1023 #define regk_iop_sw_cfg_trig0_2 0x00000000
1024 #define regk_iop_sw_cfg_trig0_3 0x00000000
1025 #define regk_iop_sw_cfg_trig1_0 0x00000000
1026 #define regk_iop_sw_cfg_trig1_1 0x00000000
1027 #define regk_iop_sw_cfg_trig1_2 0x00000000
1028 #define regk_iop_sw_cfg_trig1_3 0x00000000
1029 #define regk_iop_sw_cfg_trig2_0 0x00000000
1030 #define regk_iop_sw_cfg_trig2_1 0x00000000
1031 #define regk_iop_sw_cfg_trig2_2 0x00000000
1032 #define regk_iop_sw_cfg_trig2_3 0x00000000
1033 #define regk_iop_sw_cfg_trig3_0 0x00000000
1034 #define regk_iop_sw_cfg_trig3_1 0x00000000
1035 #define regk_iop_sw_cfg_trig3_2 0x00000000
1036 #define regk_iop_sw_cfg_trig3_3 0x00000000
1037 #define regk_iop_sw_cfg_trig4_0 0x00000001
1038 #define regk_iop_sw_cfg_trig4_1 0x00000001
1039 #define regk_iop_sw_cfg_trig4_2 0x00000001
1040 #define regk_iop_sw_cfg_trig4_3 0x00000001
1041 #define regk_iop_sw_cfg_trig5_0 0x00000001
1042 #define regk_iop_sw_cfg_trig5_1 0x00000001
1043 #define regk_iop_sw_cfg_trig5_2 0x00000001
1044 #define regk_iop_sw_cfg_trig5_3 0x00000001
1045 #define regk_iop_sw_cfg_trig6_0 0x00000001
1046 #define regk_iop_sw_cfg_trig6_1 0x00000001
1047 #define regk_iop_sw_cfg_trig6_2 0x00000001
1048 #define regk_iop_sw_cfg_trig6_3 0x00000001
1049 #define regk_iop_sw_cfg_trig7_0 0x00000001
1050 #define regk_iop_sw_cfg_trig7_1 0x00000001
1051 #define regk_iop_sw_cfg_trig7_2 0x00000001
1052 #define regk_iop_sw_cfg_trig7_3 0x00000001
1053 #endif /* __iop_sw_cfg_defs_asm_h */