1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef __iop_crc_par_defs_asm_h
3 #define __iop_crc_par_defs_asm_h
6 * This file is autogenerated from
7 * file: ../../inst/io_proc/rtl/iop_crc_par.r
9 * last modfied: Mon Apr 11 16:08:45 2005
11 * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_crc_par_defs_asm.h ../../inst/io_proc/rtl/iop_crc_par.r
12 * id: $Id: iop_crc_par_defs_asm.h,v 1.5 2005/04/24 18:31:06 starvik Exp $
13 * Any changes here will be lost.
15 * -*- buffer-read-only: t -*-
19 #define REG_FIELD( scope, reg, field, value ) \
20 REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
21 #define REG_FIELD_X_( value, shift ) ((value) << shift)
25 #define REG_STATE( scope, reg, field, symbolic_value ) \
26 REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
27 #define REG_STATE_X_( k, shift ) (k << shift)
31 #define REG_MASK( scope, reg, field ) \
32 REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
33 #define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
37 #define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
41 #define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
45 #define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
46 #define REG_ADDR_X_( inst, offs ) ((inst) + offs)
50 #define REG_ADDR_VECT( scope, inst, reg, index ) \
51 REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
52 STRIDE_##scope##_##reg )
53 #define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
54 ((inst) + offs + (index) * stride)
57 /* Register rw_cfg, scope iop_crc_par, type rw */
58 #define reg_iop_crc_par_rw_cfg___mode___lsb 0
59 #define reg_iop_crc_par_rw_cfg___mode___width 1
60 #define reg_iop_crc_par_rw_cfg___mode___bit 0
61 #define reg_iop_crc_par_rw_cfg___crc_out___lsb 1
62 #define reg_iop_crc_par_rw_cfg___crc_out___width 1
63 #define reg_iop_crc_par_rw_cfg___crc_out___bit 1
64 #define reg_iop_crc_par_rw_cfg___rev_out___lsb 2
65 #define reg_iop_crc_par_rw_cfg___rev_out___width 1
66 #define reg_iop_crc_par_rw_cfg___rev_out___bit 2
67 #define reg_iop_crc_par_rw_cfg___inv_out___lsb 3
68 #define reg_iop_crc_par_rw_cfg___inv_out___width 1
69 #define reg_iop_crc_par_rw_cfg___inv_out___bit 3
70 #define reg_iop_crc_par_rw_cfg___trig___lsb 4
71 #define reg_iop_crc_par_rw_cfg___trig___width 2
72 #define reg_iop_crc_par_rw_cfg___poly___lsb 6
73 #define reg_iop_crc_par_rw_cfg___poly___width 3
74 #define reg_iop_crc_par_rw_cfg_offset 0
76 /* Register rw_init_crc, scope iop_crc_par, type rw */
77 #define reg_iop_crc_par_rw_init_crc_offset 4
79 /* Register rw_correct_crc, scope iop_crc_par, type rw */
80 #define reg_iop_crc_par_rw_correct_crc_offset 8
82 /* Register rw_ctrl, scope iop_crc_par, type rw */
83 #define reg_iop_crc_par_rw_ctrl___en___lsb 0
84 #define reg_iop_crc_par_rw_ctrl___en___width 1
85 #define reg_iop_crc_par_rw_ctrl___en___bit 0
86 #define reg_iop_crc_par_rw_ctrl_offset 12
88 /* Register rw_set_last, scope iop_crc_par, type rw */
89 #define reg_iop_crc_par_rw_set_last___tr_dif___lsb 0
90 #define reg_iop_crc_par_rw_set_last___tr_dif___width 1
91 #define reg_iop_crc_par_rw_set_last___tr_dif___bit 0
92 #define reg_iop_crc_par_rw_set_last_offset 16
94 /* Register rw_wr1byte, scope iop_crc_par, type rw */
95 #define reg_iop_crc_par_rw_wr1byte___data___lsb 0
96 #define reg_iop_crc_par_rw_wr1byte___data___width 8
97 #define reg_iop_crc_par_rw_wr1byte_offset 20
99 /* Register rw_wr2byte, scope iop_crc_par, type rw */
100 #define reg_iop_crc_par_rw_wr2byte___data___lsb 0
101 #define reg_iop_crc_par_rw_wr2byte___data___width 16
102 #define reg_iop_crc_par_rw_wr2byte_offset 24
104 /* Register rw_wr3byte, scope iop_crc_par, type rw */
105 #define reg_iop_crc_par_rw_wr3byte___data___lsb 0
106 #define reg_iop_crc_par_rw_wr3byte___data___width 24
107 #define reg_iop_crc_par_rw_wr3byte_offset 28
109 /* Register rw_wr4byte, scope iop_crc_par, type rw */
110 #define reg_iop_crc_par_rw_wr4byte___data___lsb 0
111 #define reg_iop_crc_par_rw_wr4byte___data___width 32
112 #define reg_iop_crc_par_rw_wr4byte_offset 32
114 /* Register rw_wr1byte_last, scope iop_crc_par, type rw */
115 #define reg_iop_crc_par_rw_wr1byte_last___data___lsb 0
116 #define reg_iop_crc_par_rw_wr1byte_last___data___width 8
117 #define reg_iop_crc_par_rw_wr1byte_last_offset 36
119 /* Register rw_wr2byte_last, scope iop_crc_par, type rw */
120 #define reg_iop_crc_par_rw_wr2byte_last___data___lsb 0
121 #define reg_iop_crc_par_rw_wr2byte_last___data___width 16
122 #define reg_iop_crc_par_rw_wr2byte_last_offset 40
124 /* Register rw_wr3byte_last, scope iop_crc_par, type rw */
125 #define reg_iop_crc_par_rw_wr3byte_last___data___lsb 0
126 #define reg_iop_crc_par_rw_wr3byte_last___data___width 24
127 #define reg_iop_crc_par_rw_wr3byte_last_offset 44
129 /* Register rw_wr4byte_last, scope iop_crc_par, type rw */
130 #define reg_iop_crc_par_rw_wr4byte_last___data___lsb 0
131 #define reg_iop_crc_par_rw_wr4byte_last___data___width 32
132 #define reg_iop_crc_par_rw_wr4byte_last_offset 48
134 /* Register r_stat, scope iop_crc_par, type r */
135 #define reg_iop_crc_par_r_stat___err___lsb 0
136 #define reg_iop_crc_par_r_stat___err___width 1
137 #define reg_iop_crc_par_r_stat___err___bit 0
138 #define reg_iop_crc_par_r_stat___busy___lsb 1
139 #define reg_iop_crc_par_r_stat___busy___width 1
140 #define reg_iop_crc_par_r_stat___busy___bit 1
141 #define reg_iop_crc_par_r_stat_offset 52
143 /* Register r_sh_reg, scope iop_crc_par, type r */
144 #define reg_iop_crc_par_r_sh_reg_offset 56
146 /* Register r_crc, scope iop_crc_par, type r */
147 #define reg_iop_crc_par_r_crc_offset 60
149 /* Register rw_strb_rec_dif_in, scope iop_crc_par, type rw */
150 #define reg_iop_crc_par_rw_strb_rec_dif_in___last___lsb 0
151 #define reg_iop_crc_par_rw_strb_rec_dif_in___last___width 2
152 #define reg_iop_crc_par_rw_strb_rec_dif_in_offset 64
156 #define regk_iop_crc_par_calc 0x00000001
157 #define regk_iop_crc_par_ccitt 0x00000002
158 #define regk_iop_crc_par_check 0x00000000
159 #define regk_iop_crc_par_crc16 0x00000001
160 #define regk_iop_crc_par_crc32 0x00000000
161 #define regk_iop_crc_par_crc5 0x00000003
162 #define regk_iop_crc_par_crc5_11 0x00000004
163 #define regk_iop_crc_par_dif_in 0x00000002
164 #define regk_iop_crc_par_hi 0x00000000
165 #define regk_iop_crc_par_neg 0x00000002
166 #define regk_iop_crc_par_no 0x00000000
167 #define regk_iop_crc_par_pos 0x00000001
168 #define regk_iop_crc_par_pos_neg 0x00000003
169 #define regk_iop_crc_par_rw_cfg_default 0x00000000
170 #define regk_iop_crc_par_rw_ctrl_default 0x00000000
171 #define regk_iop_crc_par_yes 0x00000001
172 #endif /* __iop_crc_par_defs_asm_h */