1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef __extmem_defs_h
3 #define __extmem_defs_h
6 * This file is autogenerated from
7 * file: ../../inst/ext_mem/mod/extmem_regs.r
8 * id: extmem_regs.r,v 1.1 2004/02/16 13:29:30 np Exp
9 * last modfied: Tue Mar 30 22:26:21 2004
11 * by /n/asic/design/tools/rdesc/src/rdes2c --outfile extmem_defs.h ../../inst/ext_mem/mod/extmem_regs.r
12 * id: $Id: extmem_defs.h,v 1.5 2004/06/04 07:15:33 starvik Exp $
13 * Any changes here will be lost.
15 * -*- buffer-read-only: t -*-
17 /* Main access macros */
19 #define REG_RD( scope, inst, reg ) \
20 REG_READ( reg_##scope##_##reg, \
21 (inst) + REG_RD_ADDR_##scope##_##reg )
25 #define REG_WR( scope, inst, reg, val ) \
26 REG_WRITE( reg_##scope##_##reg, \
27 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
31 #define REG_RD_VECT( scope, inst, reg, index ) \
32 REG_READ( reg_##scope##_##reg, \
33 (inst) + REG_RD_ADDR_##scope##_##reg + \
34 (index) * STRIDE_##scope##_##reg )
38 #define REG_WR_VECT( scope, inst, reg, index, val ) \
39 REG_WRITE( reg_##scope##_##reg, \
40 (inst) + REG_WR_ADDR_##scope##_##reg + \
41 (index) * STRIDE_##scope##_##reg, (val) )
45 #define REG_RD_INT( scope, inst, reg ) \
46 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
50 #define REG_WR_INT( scope, inst, reg, val ) \
51 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
54 #ifndef REG_RD_INT_VECT
55 #define REG_RD_INT_VECT( scope, inst, reg, index ) \
56 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
57 (index) * STRIDE_##scope##_##reg )
60 #ifndef REG_WR_INT_VECT
61 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
62 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
63 (index) * STRIDE_##scope##_##reg, (val) )
67 #define REG_TYPE_CONV( type, orgtype, val ) \
68 ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
72 #define reg_page_size 8192
76 #define REG_ADDR( scope, inst, reg ) \
77 ( (inst) + REG_RD_ADDR_##scope##_##reg )
81 #define REG_ADDR_VECT( scope, inst, reg, index ) \
82 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
83 (index) * STRIDE_##scope##_##reg )
86 /* C-code for register scope extmem */
88 /* Register rw_cse0_cfg, scope extmem, type rw */
97 unsigned int mode : 1;
98 unsigned int erc_en : 1;
99 unsigned int dummy1 : 6;
100 unsigned int size : 3;
101 unsigned int log : 1;
103 } reg_extmem_rw_cse0_cfg;
104 #define REG_RD_ADDR_extmem_rw_cse0_cfg 0
105 #define REG_WR_ADDR_extmem_rw_cse0_cfg 0
107 /* Register rw_cse1_cfg, scope extmem, type rw */
114 unsigned int ewb : 2;
116 unsigned int mode : 1;
117 unsigned int erc_en : 1;
118 unsigned int dummy1 : 6;
119 unsigned int size : 3;
120 unsigned int log : 1;
122 } reg_extmem_rw_cse1_cfg;
123 #define REG_RD_ADDR_extmem_rw_cse1_cfg 4
124 #define REG_WR_ADDR_extmem_rw_cse1_cfg 4
126 /* Register rw_csr0_cfg, scope extmem, type rw */
133 unsigned int ewb : 2;
135 unsigned int mode : 1;
136 unsigned int erc_en : 1;
137 unsigned int dummy1 : 6;
138 unsigned int size : 3;
139 unsigned int log : 1;
141 } reg_extmem_rw_csr0_cfg;
142 #define REG_RD_ADDR_extmem_rw_csr0_cfg 8
143 #define REG_WR_ADDR_extmem_rw_csr0_cfg 8
145 /* Register rw_csr1_cfg, scope extmem, type rw */
152 unsigned int ewb : 2;
154 unsigned int mode : 1;
155 unsigned int erc_en : 1;
156 unsigned int dummy1 : 6;
157 unsigned int size : 3;
158 unsigned int log : 1;
160 } reg_extmem_rw_csr1_cfg;
161 #define REG_RD_ADDR_extmem_rw_csr1_cfg 12
162 #define REG_WR_ADDR_extmem_rw_csr1_cfg 12
164 /* Register rw_csp0_cfg, scope extmem, type rw */
171 unsigned int ewb : 2;
173 unsigned int mode : 1;
174 unsigned int erc_en : 1;
175 unsigned int dummy1 : 6;
176 unsigned int size : 3;
177 unsigned int log : 1;
179 } reg_extmem_rw_csp0_cfg;
180 #define REG_RD_ADDR_extmem_rw_csp0_cfg 16
181 #define REG_WR_ADDR_extmem_rw_csp0_cfg 16
183 /* Register rw_csp1_cfg, scope extmem, type rw */
190 unsigned int ewb : 2;
192 unsigned int mode : 1;
193 unsigned int erc_en : 1;
194 unsigned int dummy1 : 6;
195 unsigned int size : 3;
196 unsigned int log : 1;
198 } reg_extmem_rw_csp1_cfg;
199 #define REG_RD_ADDR_extmem_rw_csp1_cfg 20
200 #define REG_WR_ADDR_extmem_rw_csp1_cfg 20
202 /* Register rw_csp2_cfg, scope extmem, type rw */
209 unsigned int ewb : 2;
211 unsigned int mode : 1;
212 unsigned int erc_en : 1;
213 unsigned int dummy1 : 6;
214 unsigned int size : 3;
215 unsigned int log : 1;
217 } reg_extmem_rw_csp2_cfg;
218 #define REG_RD_ADDR_extmem_rw_csp2_cfg 24
219 #define REG_WR_ADDR_extmem_rw_csp2_cfg 24
221 /* Register rw_csp3_cfg, scope extmem, type rw */
228 unsigned int ewb : 2;
230 unsigned int mode : 1;
231 unsigned int erc_en : 1;
232 unsigned int dummy1 : 6;
233 unsigned int size : 3;
234 unsigned int log : 1;
236 } reg_extmem_rw_csp3_cfg;
237 #define REG_RD_ADDR_extmem_rw_csp3_cfg 28
238 #define REG_WR_ADDR_extmem_rw_csp3_cfg 28
240 /* Register rw_csp4_cfg, scope extmem, type rw */
247 unsigned int ewb : 2;
249 unsigned int mode : 1;
250 unsigned int erc_en : 1;
251 unsigned int dummy1 : 6;
252 unsigned int size : 3;
253 unsigned int log : 1;
255 } reg_extmem_rw_csp4_cfg;
256 #define REG_RD_ADDR_extmem_rw_csp4_cfg 32
257 #define REG_WR_ADDR_extmem_rw_csp4_cfg 32
259 /* Register rw_csp5_cfg, scope extmem, type rw */
266 unsigned int ewb : 2;
268 unsigned int mode : 1;
269 unsigned int erc_en : 1;
270 unsigned int dummy1 : 6;
271 unsigned int size : 3;
272 unsigned int log : 1;
274 } reg_extmem_rw_csp5_cfg;
275 #define REG_RD_ADDR_extmem_rw_csp5_cfg 36
276 #define REG_WR_ADDR_extmem_rw_csp5_cfg 36
278 /* Register rw_csp6_cfg, scope extmem, type rw */
285 unsigned int ewb : 2;
287 unsigned int mode : 1;
288 unsigned int erc_en : 1;
289 unsigned int dummy1 : 6;
290 unsigned int size : 3;
291 unsigned int log : 1;
293 } reg_extmem_rw_csp6_cfg;
294 #define REG_RD_ADDR_extmem_rw_csp6_cfg 40
295 #define REG_WR_ADDR_extmem_rw_csp6_cfg 40
297 /* Register rw_css_cfg, scope extmem, type rw */
304 unsigned int ewb : 2;
306 unsigned int mode : 1;
307 unsigned int erc_en : 1;
308 unsigned int dummy1 : 6;
309 unsigned int size : 3;
310 unsigned int log : 1;
312 } reg_extmem_rw_css_cfg;
313 #define REG_RD_ADDR_extmem_rw_css_cfg 44
314 #define REG_WR_ADDR_extmem_rw_css_cfg 44
316 /* Register rw_status_handle, scope extmem, type rw */
319 } reg_extmem_rw_status_handle;
320 #define REG_RD_ADDR_extmem_rw_status_handle 48
321 #define REG_WR_ADDR_extmem_rw_status_handle 48
323 /* Register rw_wait_pin, scope extmem, type rw */
325 unsigned int val : 16;
326 unsigned int dummy1 : 15;
327 unsigned int start : 1;
328 } reg_extmem_rw_wait_pin;
329 #define REG_RD_ADDR_extmem_rw_wait_pin 52
330 #define REG_WR_ADDR_extmem_rw_wait_pin 52
332 /* Register rw_gated_csp, scope extmem, type rw */
334 unsigned int dummy1 : 31;
336 } reg_extmem_rw_gated_csp;
337 #define REG_RD_ADDR_extmem_rw_gated_csp 56
338 #define REG_WR_ADDR_extmem_rw_gated_csp 56
343 regk_extmem_b16 = 0x00000001,
344 regk_extmem_b32 = 0x00000000,
345 regk_extmem_bwe = 0x00000000,
346 regk_extmem_cwe = 0x00000001,
347 regk_extmem_no = 0x00000000,
348 regk_extmem_rw_cse0_cfg_default = 0x000006cf,
349 regk_extmem_rw_cse1_cfg_default = 0x000006cf,
350 regk_extmem_rw_csp0_cfg_default = 0x000006cf,
351 regk_extmem_rw_csp1_cfg_default = 0x000006cf,
352 regk_extmem_rw_csp2_cfg_default = 0x000006cf,
353 regk_extmem_rw_csp3_cfg_default = 0x000006cf,
354 regk_extmem_rw_csp4_cfg_default = 0x000006cf,
355 regk_extmem_rw_csp5_cfg_default = 0x000006cf,
356 regk_extmem_rw_csp6_cfg_default = 0x000006cf,
357 regk_extmem_rw_csr0_cfg_default = 0x000006cf,
358 regk_extmem_rw_csr1_cfg_default = 0x000006cf,
359 regk_extmem_rw_css_cfg_default = 0x000006cf,
360 regk_extmem_s128KB = 0x00000000,
361 regk_extmem_s16MB = 0x00000005,
362 regk_extmem_s1MB = 0x00000001,
363 regk_extmem_s2MB = 0x00000002,
364 regk_extmem_s32MB = 0x00000006,
365 regk_extmem_s4MB = 0x00000003,
366 regk_extmem_s64MB = 0x00000007,
367 regk_extmem_s8MB = 0x00000004,
368 regk_extmem_yes = 0x00000001
370 #endif /* __extmem_defs_h */