1 /* SPDX-License-Identifier: GPL-2.0 */
6 * This file is autogenerated from
8 * id: eth_regs.r,v 1.16 2005/05/20 15:41:22 perz Exp
9 * last modfied: Mon Jan 9 06:06:41 2006
11 * by /n/asic/design/tools/rdesc/rdes2c eth.r
12 * id: $Id: eth_defs.h,v 1.7 2006/01/26 13:45:30 karljope Exp $
13 * Any changes here will be lost.
15 * -*- buffer-read-only: t -*-
17 /* Main access macros */
19 #define REG_RD( scope, inst, reg ) \
20 REG_READ( reg_##scope##_##reg, \
21 (inst) + REG_RD_ADDR_##scope##_##reg )
25 #define REG_WR( scope, inst, reg, val ) \
26 REG_WRITE( reg_##scope##_##reg, \
27 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
31 #define REG_RD_VECT( scope, inst, reg, index ) \
32 REG_READ( reg_##scope##_##reg, \
33 (inst) + REG_RD_ADDR_##scope##_##reg + \
34 (index) * STRIDE_##scope##_##reg )
38 #define REG_WR_VECT( scope, inst, reg, index, val ) \
39 REG_WRITE( reg_##scope##_##reg, \
40 (inst) + REG_WR_ADDR_##scope##_##reg + \
41 (index) * STRIDE_##scope##_##reg, (val) )
45 #define REG_RD_INT( scope, inst, reg ) \
46 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
50 #define REG_WR_INT( scope, inst, reg, val ) \
51 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
54 #ifndef REG_RD_INT_VECT
55 #define REG_RD_INT_VECT( scope, inst, reg, index ) \
56 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
57 (index) * STRIDE_##scope##_##reg )
60 #ifndef REG_WR_INT_VECT
61 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
62 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
63 (index) * STRIDE_##scope##_##reg, (val) )
67 #define REG_TYPE_CONV( type, orgtype, val ) \
68 ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
72 #define reg_page_size 8192
76 #define REG_ADDR( scope, inst, reg ) \
77 ( (inst) + REG_RD_ADDR_##scope##_##reg )
81 #define REG_ADDR_VECT( scope, inst, reg, index ) \
82 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
83 (index) * STRIDE_##scope##_##reg )
86 /* C-code for register scope eth */
88 /* Register rw_ma0_lo, scope eth, type rw */
90 unsigned int addr : 32;
92 #define REG_RD_ADDR_eth_rw_ma0_lo 0
93 #define REG_WR_ADDR_eth_rw_ma0_lo 0
95 /* Register rw_ma0_hi, scope eth, type rw */
97 unsigned int addr : 16;
98 unsigned int dummy1 : 16;
100 #define REG_RD_ADDR_eth_rw_ma0_hi 4
101 #define REG_WR_ADDR_eth_rw_ma0_hi 4
103 /* Register rw_ma1_lo, scope eth, type rw */
105 unsigned int addr : 32;
107 #define REG_RD_ADDR_eth_rw_ma1_lo 8
108 #define REG_WR_ADDR_eth_rw_ma1_lo 8
110 /* Register rw_ma1_hi, scope eth, type rw */
112 unsigned int addr : 16;
113 unsigned int dummy1 : 16;
115 #define REG_RD_ADDR_eth_rw_ma1_hi 12
116 #define REG_WR_ADDR_eth_rw_ma1_hi 12
118 /* Register rw_ga_lo, scope eth, type rw */
120 unsigned int tbl : 32;
122 #define REG_RD_ADDR_eth_rw_ga_lo 16
123 #define REG_WR_ADDR_eth_rw_ga_lo 16
125 /* Register rw_ga_hi, scope eth, type rw */
127 unsigned int tbl : 32;
129 #define REG_RD_ADDR_eth_rw_ga_hi 20
130 #define REG_WR_ADDR_eth_rw_ga_hi 20
132 /* Register rw_gen_ctrl, scope eth, type rw */
135 unsigned int phy : 2;
136 unsigned int protocol : 1;
137 unsigned int loopback : 1;
138 unsigned int flow_ctrl : 1;
139 unsigned int gtxclk_out : 1;
140 unsigned int phyrst_n : 1;
141 unsigned int dummy1 : 24;
142 } reg_eth_rw_gen_ctrl;
143 #define REG_RD_ADDR_eth_rw_gen_ctrl 24
144 #define REG_WR_ADDR_eth_rw_gen_ctrl 24
146 /* Register rw_rec_ctrl, scope eth, type rw */
148 unsigned int ma0 : 1;
149 unsigned int ma1 : 1;
150 unsigned int individual : 1;
151 unsigned int broadcast : 1;
152 unsigned int undersize : 1;
153 unsigned int oversize : 1;
154 unsigned int bad_crc : 1;
155 unsigned int duplex : 1;
156 unsigned int max_size : 16;
157 unsigned int dummy1 : 8;
158 } reg_eth_rw_rec_ctrl;
159 #define REG_RD_ADDR_eth_rw_rec_ctrl 28
160 #define REG_WR_ADDR_eth_rw_rec_ctrl 28
162 /* Register rw_tr_ctrl, scope eth, type rw */
164 unsigned int crc : 1;
165 unsigned int pad : 1;
166 unsigned int retry : 1;
167 unsigned int ignore_col : 1;
168 unsigned int cancel : 1;
169 unsigned int hsh_delay : 1;
170 unsigned int ignore_crs : 1;
171 unsigned int carrier_ext : 1;
172 unsigned int dummy1 : 24;
173 } reg_eth_rw_tr_ctrl;
174 #define REG_RD_ADDR_eth_rw_tr_ctrl 32
175 #define REG_WR_ADDR_eth_rw_tr_ctrl 32
177 /* Register rw_clr_err, scope eth, type rw */
179 unsigned int clr : 1;
180 unsigned int dummy1 : 31;
181 } reg_eth_rw_clr_err;
182 #define REG_RD_ADDR_eth_rw_clr_err 36
183 #define REG_WR_ADDR_eth_rw_clr_err 36
185 /* Register rw_mgm_ctrl, scope eth, type rw */
187 unsigned int mdio : 1;
188 unsigned int mdoe : 1;
189 unsigned int mdc : 1;
190 unsigned int dummy1 : 29;
191 } reg_eth_rw_mgm_ctrl;
192 #define REG_RD_ADDR_eth_rw_mgm_ctrl 40
193 #define REG_WR_ADDR_eth_rw_mgm_ctrl 40
195 /* Register r_stat, scope eth, type r */
197 unsigned int mdio : 1;
198 unsigned int exc_col : 1;
199 unsigned int urun : 1;
200 unsigned int clk_125 : 1;
201 unsigned int dummy1 : 28;
203 #define REG_RD_ADDR_eth_r_stat 44
205 /* Register rs_rec_cnt, scope eth, type rs */
207 unsigned int crc_err : 8;
208 unsigned int align_err : 8;
209 unsigned int oversize : 8;
210 unsigned int congestion : 8;
211 } reg_eth_rs_rec_cnt;
212 #define REG_RD_ADDR_eth_rs_rec_cnt 48
214 /* Register r_rec_cnt, scope eth, type r */
216 unsigned int crc_err : 8;
217 unsigned int align_err : 8;
218 unsigned int oversize : 8;
219 unsigned int congestion : 8;
221 #define REG_RD_ADDR_eth_r_rec_cnt 52
223 /* Register rs_tr_cnt, scope eth, type rs */
225 unsigned int single_col : 8;
226 unsigned int mult_col : 8;
227 unsigned int late_col : 8;
228 unsigned int deferred : 8;
230 #define REG_RD_ADDR_eth_rs_tr_cnt 56
232 /* Register r_tr_cnt, scope eth, type r */
234 unsigned int single_col : 8;
235 unsigned int mult_col : 8;
236 unsigned int late_col : 8;
237 unsigned int deferred : 8;
239 #define REG_RD_ADDR_eth_r_tr_cnt 60
241 /* Register rs_phy_cnt, scope eth, type rs */
243 unsigned int carrier_loss : 8;
244 unsigned int sqe_err : 8;
245 unsigned int dummy1 : 16;
246 } reg_eth_rs_phy_cnt;
247 #define REG_RD_ADDR_eth_rs_phy_cnt 64
249 /* Register r_phy_cnt, scope eth, type r */
251 unsigned int carrier_loss : 8;
252 unsigned int sqe_err : 8;
253 unsigned int dummy1 : 16;
255 #define REG_RD_ADDR_eth_r_phy_cnt 68
257 /* Register rw_test_ctrl, scope eth, type rw */
259 unsigned int snmp_inc : 1;
260 unsigned int snmp : 1;
261 unsigned int backoff : 1;
262 unsigned int dummy1 : 29;
263 } reg_eth_rw_test_ctrl;
264 #define REG_RD_ADDR_eth_rw_test_ctrl 72
265 #define REG_WR_ADDR_eth_rw_test_ctrl 72
267 /* Register rw_intr_mask, scope eth, type rw */
269 unsigned int crc : 1;
270 unsigned int align : 1;
271 unsigned int oversize : 1;
272 unsigned int congestion : 1;
273 unsigned int single_col : 1;
274 unsigned int mult_col : 1;
275 unsigned int late_col : 1;
276 unsigned int deferred : 1;
277 unsigned int carrier_loss : 1;
278 unsigned int sqe_test_err : 1;
279 unsigned int orun : 1;
280 unsigned int urun : 1;
281 unsigned int exc_col : 1;
282 unsigned int mdio : 1;
283 unsigned int dummy1 : 18;
284 } reg_eth_rw_intr_mask;
285 #define REG_RD_ADDR_eth_rw_intr_mask 76
286 #define REG_WR_ADDR_eth_rw_intr_mask 76
288 /* Register rw_ack_intr, scope eth, type rw */
290 unsigned int crc : 1;
291 unsigned int align : 1;
292 unsigned int oversize : 1;
293 unsigned int congestion : 1;
294 unsigned int single_col : 1;
295 unsigned int mult_col : 1;
296 unsigned int late_col : 1;
297 unsigned int deferred : 1;
298 unsigned int carrier_loss : 1;
299 unsigned int sqe_test_err : 1;
300 unsigned int orun : 1;
301 unsigned int urun : 1;
302 unsigned int exc_col : 1;
303 unsigned int mdio : 1;
304 unsigned int dummy1 : 18;
305 } reg_eth_rw_ack_intr;
306 #define REG_RD_ADDR_eth_rw_ack_intr 80
307 #define REG_WR_ADDR_eth_rw_ack_intr 80
309 /* Register r_intr, scope eth, type r */
311 unsigned int crc : 1;
312 unsigned int align : 1;
313 unsigned int oversize : 1;
314 unsigned int congestion : 1;
315 unsigned int single_col : 1;
316 unsigned int mult_col : 1;
317 unsigned int late_col : 1;
318 unsigned int deferred : 1;
319 unsigned int carrier_loss : 1;
320 unsigned int sqe_test_err : 1;
321 unsigned int orun : 1;
322 unsigned int urun : 1;
323 unsigned int exc_col : 1;
324 unsigned int mdio : 1;
325 unsigned int dummy1 : 18;
327 #define REG_RD_ADDR_eth_r_intr 84
329 /* Register r_masked_intr, scope eth, type r */
331 unsigned int crc : 1;
332 unsigned int align : 1;
333 unsigned int oversize : 1;
334 unsigned int congestion : 1;
335 unsigned int single_col : 1;
336 unsigned int mult_col : 1;
337 unsigned int late_col : 1;
338 unsigned int deferred : 1;
339 unsigned int carrier_loss : 1;
340 unsigned int sqe_test_err : 1;
341 unsigned int orun : 1;
342 unsigned int urun : 1;
343 unsigned int exc_col : 1;
344 unsigned int mdio : 1;
345 unsigned int dummy1 : 18;
346 } reg_eth_r_masked_intr;
347 #define REG_RD_ADDR_eth_r_masked_intr 88
352 regk_eth_discard = 0x00000000,
353 regk_eth_ether = 0x00000000,
354 regk_eth_full = 0x00000001,
355 regk_eth_gmii = 0x00000003,
356 regk_eth_gtxclk = 0x00000001,
357 regk_eth_half = 0x00000000,
358 regk_eth_hsh = 0x00000001,
359 regk_eth_mii = 0x00000001,
360 regk_eth_mii_arec = 0x00000002,
361 regk_eth_mii_clk = 0x00000000,
362 regk_eth_no = 0x00000000,
363 regk_eth_phyrst = 0x00000000,
364 regk_eth_rec = 0x00000001,
365 regk_eth_rw_ga_hi_default = 0x00000000,
366 regk_eth_rw_ga_lo_default = 0x00000000,
367 regk_eth_rw_gen_ctrl_default = 0x00000000,
368 regk_eth_rw_intr_mask_default = 0x00000000,
369 regk_eth_rw_ma0_hi_default = 0x00000000,
370 regk_eth_rw_ma0_lo_default = 0x00000000,
371 regk_eth_rw_ma1_hi_default = 0x00000000,
372 regk_eth_rw_ma1_lo_default = 0x00000000,
373 regk_eth_rw_mgm_ctrl_default = 0x00000000,
374 regk_eth_rw_test_ctrl_default = 0x00000000,
375 regk_eth_size1518 = 0x000005ee,
376 regk_eth_size1522 = 0x000005f2,
377 regk_eth_yes = 0x00000001
379 #endif /* __eth_defs_h */