1 /* SPDX-License-Identifier: GPL-2.0 */
3 * DMA C definitions and help macros
10 /* registers */ /* Really needed, since both are listed in sw.list? */
11 #include <arch/hwregs/dma_defs.h>
16 // ------------------------------------------------------------ dma_descr_group
17 typedef struct dma_descr_group {
18 struct dma_descr_group *next;
29 struct dma_descr_group *up;
31 struct dma_descr_context *context;
32 struct dma_descr_group *group;
36 // ---------------------------------------------------------- dma_descr_context
37 typedef struct dma_descr_context {
38 struct dma_descr_context *next;
43 unsigned store_mode : 1;
52 struct dma_descr_data *saved_data;
56 // ------------------------------------------------------------- dma_descr_data
57 typedef struct dma_descr_data {
58 struct dma_descr_data *next;
73 // --------------------------------------------------------------------- macros
76 #define DMA_ENABLE( inst ) \
77 do { reg_dma_rw_cfg e = REG_RD( dma, inst, rw_cfg );\
78 e.en = regk_dma_yes; \
79 REG_WR( dma, inst, rw_cfg, e); } while( 0 )
82 #define DMA_RESET( inst ) \
83 do { reg_dma_rw_cfg r = REG_RD( dma, inst, rw_cfg );\
85 REG_WR( dma, inst, rw_cfg, r); } while( 0 )
88 #define DMA_STOP( inst ) \
89 do { reg_dma_rw_cfg s = REG_RD( dma, inst, rw_cfg );\
90 s.stop = regk_dma_yes; \
91 REG_WR( dma, inst, rw_cfg, s); } while( 0 )
93 // continue DMA channel operation
94 #define DMA_CONTINUE( inst ) \
95 do { reg_dma_rw_cfg c = REG_RD( dma, inst, rw_cfg );\
96 c.stop = regk_dma_no; \
97 REG_WR( dma, inst, rw_cfg, c); } while( 0 )
99 // give stream command
100 #define DMA_WR_CMD( inst, cmd_par ) \
101 do { reg_dma_rw_stream_cmd __x = {0}; \
102 do { __x = REG_RD(dma, inst, rw_stream_cmd); } while (__x.busy); \
103 __x.cmd = (cmd_par); \
104 REG_WR(dma, inst, rw_stream_cmd, __x); \
108 #define DMA_START_GROUP( inst, group_descr ) \
109 do { REG_WR_INT( dma, inst, rw_group, (int) group_descr ); \
110 DMA_WR_CMD( inst, regk_dma_load_g ); \
111 DMA_WR_CMD( inst, regk_dma_load_c ); \
112 DMA_WR_CMD( inst, regk_dma_load_d | regk_dma_burst ); \
116 #define DMA_START_CONTEXT( inst, ctx_descr ) \
117 do { REG_WR_INT( dma, inst, rw_group_down, (int) ctx_descr ); \
118 DMA_WR_CMD( inst, regk_dma_load_c ); \
119 DMA_WR_CMD( inst, regk_dma_load_d | regk_dma_burst ); \
122 // if the DMA is at the end of the data list, the last data descr is reloaded
123 #define DMA_CONTINUE_DATA( inst ) \
124 do { reg_dma_rw_cmd c = {0}; \
125 c.cont_data = regk_dma_yes;\
126 REG_WR( dma, inst, rw_cmd, c ); } while( 0 )