1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef __cris_defs_asm_h
3 #define __cris_defs_asm_h
6 * This file is autogenerated from
7 * file: ../../inst/crisp/doc/cris.r
8 * id: cris.r,v 1.6 2004/05/05 07:41:12 perz Exp
9 * last modfied: Mon Apr 11 16:06:39 2005
11 * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/cris_defs_asm.h ../../inst/crisp/doc/cris.r
12 * id: $Id: cris_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $
13 * Any changes here will be lost.
15 * -*- buffer-read-only: t -*-
19 #define REG_FIELD( scope, reg, field, value ) \
20 REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
21 #define REG_FIELD_X_( value, shift ) ((value) << shift)
25 #define REG_STATE( scope, reg, field, symbolic_value ) \
26 REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
27 #define REG_STATE_X_( k, shift ) (k << shift)
31 #define REG_MASK( scope, reg, field ) \
32 REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
33 #define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
37 #define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
41 #define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
45 #define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
46 #define REG_ADDR_X_( inst, offs ) ((inst) + offs)
50 #define REG_ADDR_VECT( scope, inst, reg, index ) \
51 REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
52 STRIDE_##scope##_##reg )
53 #define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
54 ((inst) + offs + (index) * stride)
57 /* Register rw_gc_cfg, scope cris, type rw */
58 #define reg_cris_rw_gc_cfg___ic___lsb 0
59 #define reg_cris_rw_gc_cfg___ic___width 1
60 #define reg_cris_rw_gc_cfg___ic___bit 0
61 #define reg_cris_rw_gc_cfg___dc___lsb 1
62 #define reg_cris_rw_gc_cfg___dc___width 1
63 #define reg_cris_rw_gc_cfg___dc___bit 1
64 #define reg_cris_rw_gc_cfg___im___lsb 2
65 #define reg_cris_rw_gc_cfg___im___width 1
66 #define reg_cris_rw_gc_cfg___im___bit 2
67 #define reg_cris_rw_gc_cfg___dm___lsb 3
68 #define reg_cris_rw_gc_cfg___dm___width 1
69 #define reg_cris_rw_gc_cfg___dm___bit 3
70 #define reg_cris_rw_gc_cfg___gb___lsb 4
71 #define reg_cris_rw_gc_cfg___gb___width 1
72 #define reg_cris_rw_gc_cfg___gb___bit 4
73 #define reg_cris_rw_gc_cfg___gk___lsb 5
74 #define reg_cris_rw_gc_cfg___gk___width 1
75 #define reg_cris_rw_gc_cfg___gk___bit 5
76 #define reg_cris_rw_gc_cfg___gp___lsb 6
77 #define reg_cris_rw_gc_cfg___gp___width 1
78 #define reg_cris_rw_gc_cfg___gp___bit 6
79 #define reg_cris_rw_gc_cfg_offset 0
81 /* Register rw_gc_ccs, scope cris, type rw */
82 #define reg_cris_rw_gc_ccs_offset 4
84 /* Register rw_gc_srs, scope cris, type rw */
85 #define reg_cris_rw_gc_srs___srs___lsb 0
86 #define reg_cris_rw_gc_srs___srs___width 8
87 #define reg_cris_rw_gc_srs_offset 8
89 /* Register rw_gc_nrp, scope cris, type rw */
90 #define reg_cris_rw_gc_nrp_offset 12
92 /* Register rw_gc_exs, scope cris, type rw */
93 #define reg_cris_rw_gc_exs_offset 16
95 /* Register rw_gc_eda, scope cris, type rw */
96 #define reg_cris_rw_gc_eda_offset 20
98 /* Register rw_gc_r0, scope cris, type rw */
99 #define reg_cris_rw_gc_r0_offset 32
101 /* Register rw_gc_r1, scope cris, type rw */
102 #define reg_cris_rw_gc_r1_offset 36
104 /* Register rw_gc_r2, scope cris, type rw */
105 #define reg_cris_rw_gc_r2_offset 40
107 /* Register rw_gc_r3, scope cris, type rw */
108 #define reg_cris_rw_gc_r3_offset 44
112 #define regk_cris_no 0x00000000
113 #define regk_cris_rw_gc_cfg_default 0x00000000
114 #define regk_cris_yes 0x00000001
115 #endif /* __cris_defs_asm_h */