GNU Linux-libre 4.14.294-gnu1
[releases.git] / arch / cris / include / arch-v32 / arch / hwregs / asm / config_defs_asm.h
1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef __config_defs_asm_h
3 #define __config_defs_asm_h
4
5 /*
6  * This file is autogenerated from
7  *   file:           ../../rtl/config_regs.r
8  *     id:           config_regs.r,v 1.23 2004/03/04 11:34:42 mikaeln Exp
9  *     last modfied: Thu Mar  4 12:34:39 2004
10  *
11  *   by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/config_defs_asm.h ../../rtl/config_regs.r
12  *      id: $Id: config_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $
13  * Any changes here will be lost.
14  *
15  * -*- buffer-read-only: t -*-
16  */
17
18 #ifndef REG_FIELD
19 #define REG_FIELD( scope, reg, field, value ) \
20   REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
21 #define REG_FIELD_X_( value, shift ) ((value) << shift)
22 #endif
23
24 #ifndef REG_STATE
25 #define REG_STATE( scope, reg, field, symbolic_value ) \
26   REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
27 #define REG_STATE_X_( k, shift ) (k << shift)
28 #endif
29
30 #ifndef REG_MASK
31 #define REG_MASK( scope, reg, field ) \
32   REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
33 #define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
34 #endif
35
36 #ifndef REG_LSB
37 #define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
38 #endif
39
40 #ifndef REG_BIT
41 #define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
42 #endif
43
44 #ifndef REG_ADDR
45 #define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
46 #define REG_ADDR_X_( inst, offs ) ((inst) + offs)
47 #endif
48
49 #ifndef REG_ADDR_VECT
50 #define REG_ADDR_VECT( scope, inst, reg, index ) \
51          REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
52                          STRIDE_##scope##_##reg )
53 #define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
54                           ((inst) + offs + (index) * stride)
55 #endif
56
57 /* Register r_bootsel, scope config, type r */
58 #define reg_config_r_bootsel___boot_mode___lsb 0
59 #define reg_config_r_bootsel___boot_mode___width 3
60 #define reg_config_r_bootsel___full_duplex___lsb 3
61 #define reg_config_r_bootsel___full_duplex___width 1
62 #define reg_config_r_bootsel___full_duplex___bit 3
63 #define reg_config_r_bootsel___user___lsb 4
64 #define reg_config_r_bootsel___user___width 1
65 #define reg_config_r_bootsel___user___bit 4
66 #define reg_config_r_bootsel___pll___lsb 5
67 #define reg_config_r_bootsel___pll___width 1
68 #define reg_config_r_bootsel___pll___bit 5
69 #define reg_config_r_bootsel___flash_bw___lsb 6
70 #define reg_config_r_bootsel___flash_bw___width 1
71 #define reg_config_r_bootsel___flash_bw___bit 6
72 #define reg_config_r_bootsel_offset 0
73
74 /* Register rw_clk_ctrl, scope config, type rw */
75 #define reg_config_rw_clk_ctrl___pll___lsb 0
76 #define reg_config_rw_clk_ctrl___pll___width 1
77 #define reg_config_rw_clk_ctrl___pll___bit 0
78 #define reg_config_rw_clk_ctrl___cpu___lsb 1
79 #define reg_config_rw_clk_ctrl___cpu___width 1
80 #define reg_config_rw_clk_ctrl___cpu___bit 1
81 #define reg_config_rw_clk_ctrl___iop___lsb 2
82 #define reg_config_rw_clk_ctrl___iop___width 1
83 #define reg_config_rw_clk_ctrl___iop___bit 2
84 #define reg_config_rw_clk_ctrl___dma01_eth0___lsb 3
85 #define reg_config_rw_clk_ctrl___dma01_eth0___width 1
86 #define reg_config_rw_clk_ctrl___dma01_eth0___bit 3
87 #define reg_config_rw_clk_ctrl___dma23___lsb 4
88 #define reg_config_rw_clk_ctrl___dma23___width 1
89 #define reg_config_rw_clk_ctrl___dma23___bit 4
90 #define reg_config_rw_clk_ctrl___dma45___lsb 5
91 #define reg_config_rw_clk_ctrl___dma45___width 1
92 #define reg_config_rw_clk_ctrl___dma45___bit 5
93 #define reg_config_rw_clk_ctrl___dma67___lsb 6
94 #define reg_config_rw_clk_ctrl___dma67___width 1
95 #define reg_config_rw_clk_ctrl___dma67___bit 6
96 #define reg_config_rw_clk_ctrl___dma89_strcop___lsb 7
97 #define reg_config_rw_clk_ctrl___dma89_strcop___width 1
98 #define reg_config_rw_clk_ctrl___dma89_strcop___bit 7
99 #define reg_config_rw_clk_ctrl___bif___lsb 8
100 #define reg_config_rw_clk_ctrl___bif___width 1
101 #define reg_config_rw_clk_ctrl___bif___bit 8
102 #define reg_config_rw_clk_ctrl___fix_io___lsb 9
103 #define reg_config_rw_clk_ctrl___fix_io___width 1
104 #define reg_config_rw_clk_ctrl___fix_io___bit 9
105 #define reg_config_rw_clk_ctrl_offset 4
106
107 /* Register rw_pad_ctrl, scope config, type rw */
108 #define reg_config_rw_pad_ctrl___usb_susp___lsb 0
109 #define reg_config_rw_pad_ctrl___usb_susp___width 1
110 #define reg_config_rw_pad_ctrl___usb_susp___bit 0
111 #define reg_config_rw_pad_ctrl___phyrst_n___lsb 1
112 #define reg_config_rw_pad_ctrl___phyrst_n___width 1
113 #define reg_config_rw_pad_ctrl___phyrst_n___bit 1
114 #define reg_config_rw_pad_ctrl_offset 8
115
116
117 /* Constants */
118 #define regk_config_bw16                          0x00000000
119 #define regk_config_bw32                          0x00000001
120 #define regk_config_master                        0x00000005
121 #define regk_config_nand                          0x00000003
122 #define regk_config_net_rx                        0x00000001
123 #define regk_config_net_tx_rx                     0x00000002
124 #define regk_config_no                            0x00000000
125 #define regk_config_none                          0x00000007
126 #define regk_config_nor                           0x00000000
127 #define regk_config_rw_clk_ctrl_default           0x00000002
128 #define regk_config_rw_pad_ctrl_default           0x00000000
129 #define regk_config_ser                           0x00000004
130 #define regk_config_slave                         0x00000006
131 #define regk_config_yes                           0x00000001
132 #endif /* __config_defs_asm_h */