1 /* Wrapper for DMA channel allocator that starts clocks etc */
3 #include <linux/kernel.h>
4 #include <linux/spinlock.h>
6 #include <hwregs/reg_map.h>
7 #include <hwregs/reg_rdwr.h>
8 #include <hwregs/marb_defs.h>
9 #include <hwregs/clkgen_defs.h>
10 #include <hwregs/strmux_defs.h>
11 #include <linux/errno.h>
14 static char used_dma_channels[MAX_DMA_CHANNELS];
15 static const char *used_dma_channels_users[MAX_DMA_CHANNELS];
17 static DEFINE_SPINLOCK(dma_lock);
19 int crisv32_request_dma(unsigned int dmanr, const char *device_id,
20 unsigned options, unsigned int bandwidth, enum dma_owner owner)
23 reg_clkgen_rw_clk_ctrl clk_ctrl;
24 reg_strmux_rw_cfg strmux_cfg;
26 if (crisv32_arbiter_allocate_bandwidth(dmanr,
27 options & DMA_INT_MEM ? INT_REGION : EXT_REGION,
31 spin_lock_irqsave(&dma_lock, flags);
33 if (used_dma_channels[dmanr]) {
34 spin_unlock_irqrestore(&dma_lock, flags);
35 if (options & DMA_VERBOSE_ON_ERROR)
36 printk(KERN_ERR "Failed to request DMA %i for %s, "
37 "already allocated by %s\n",
40 used_dma_channels_users[dmanr]);
42 if (options & DMA_PANIC_ON_ERROR)
43 panic("request_dma error!");
46 clk_ctrl = REG_RD(clkgen, regi_clkgen, rw_clk_ctrl);
47 strmux_cfg = REG_RD(strmux, regi_strmux, rw_cfg);
52 clk_ctrl.dma0_1_eth = 1;
56 clk_ctrl.dma2_3_strcop = 1;
60 clk_ctrl.dma4_5_iop = 1;
64 clk_ctrl.sser_ser_dma6_7 = 1;
70 #if MAX_DMA_CHANNELS-1 != 11
74 spin_unlock_irqrestore(&dma_lock, flags);
75 if (options & DMA_VERBOSE_ON_ERROR)
76 printk(KERN_ERR "Failed to request DMA %i for %s, "
78 dmanr, device_id, MAX_DMA_CHANNELS-1);
80 if (options & DMA_PANIC_ON_ERROR)
81 panic("request_dma error!");
88 strmux_cfg.dma0 = regk_strmux_eth;
90 strmux_cfg.dma1 = regk_strmux_eth;
92 panic("Invalid DMA channel for eth\n");
96 strmux_cfg.dma0 = regk_strmux_ser0;
98 strmux_cfg.dma1 = regk_strmux_ser0;
100 panic("Invalid DMA channel for ser0\n");
104 strmux_cfg.dma2 = regk_strmux_ser3;
106 strmux_cfg.dma3 = regk_strmux_ser3;
108 panic("Invalid DMA channel for ser3\n");
112 strmux_cfg.dma2 = regk_strmux_strcop;
114 strmux_cfg.dma3 = regk_strmux_strcop;
116 panic("Invalid DMA channel for strp\n");
120 strmux_cfg.dma4 = regk_strmux_ser1;
122 strmux_cfg.dma5 = regk_strmux_ser1;
124 panic("Invalid DMA channel for ser1\n");
128 strmux_cfg.dma4 = regk_strmux_iop;
130 strmux_cfg.dma5 = regk_strmux_iop;
132 panic("Invalid DMA channel for iop\n");
136 strmux_cfg.dma6 = regk_strmux_ser2;
138 strmux_cfg.dma7 = regk_strmux_ser2;
140 panic("Invalid DMA channel for ser2\n");
144 strmux_cfg.dma6 = regk_strmux_sser;
146 strmux_cfg.dma7 = regk_strmux_sser;
148 panic("Invalid DMA channel for sser\n");
152 strmux_cfg.dma9 = regk_strmux_ser4;
154 panic("Invalid DMA channel for ser4\n");
158 strmux_cfg.dma9 = regk_strmux_jpeg;
160 panic("Invalid DMA channel for JPEG\n");
164 strmux_cfg.dma11 = regk_strmux_h264;
166 panic("Invalid DMA channel for H264\n");
170 used_dma_channels[dmanr] = 1;
171 used_dma_channels_users[dmanr] = device_id;
172 REG_WR(clkgen, regi_clkgen, rw_clk_ctrl, clk_ctrl);
173 REG_WR(strmux, regi_strmux, rw_cfg, strmux_cfg);
174 spin_unlock_irqrestore(&dma_lock, flags);
178 void crisv32_free_dma(unsigned int dmanr)
180 spin_lock(&dma_lock);
181 used_dma_channels[dmanr] = 0;
182 spin_unlock(&dma_lock);