1 // SPDX-License-Identifier: GPL-2.0
3 * Memory arbiter functions. Allocates bandwidth through the
4 * arbiter and sets up arbiter breakpoints.
6 * The algorithm first assigns slots to the clients that has specified
7 * bandwidth (e.g. ethernet) and then the remaining slots are divided
8 * on all the active clients.
10 * Copyright (c) 2004-2007 Axis Communications AB.
12 * The artpec-3 has two arbiters. The memory hierarchy looks like this:
18 * -------------- ------------------
19 * | foo arbiter|----| Internal memory|
20 * -------------- ------------------
39 #include <hwregs/reg_map.h>
40 #include <hwregs/reg_rdwr.h>
41 #include <hwregs/marb_foo_defs.h>
42 #include <hwregs/marb_bar_defs.h>
44 #include <hwregs/intr_vect.h>
45 #include <linux/interrupt.h>
46 #include <linux/irq.h>
47 #include <linux/signal.h>
48 #include <linux/errno.h>
49 #include <linux/spinlock.h>
51 #include <asm/irq_regs.h>
55 struct crisv32_watch_entry {
56 unsigned long instance;
63 #define NUMBER_OF_BP 4
64 #define SDRAM_BANDWIDTH 400000000
65 #define INTMEM_BANDWIDTH 400000000
66 #define NBR_OF_SLOTS 64
67 #define NBR_OF_REGIONS 2
68 #define NBR_OF_CLIENTS 15
70 #define UNASSIGNED 100
73 unsigned long instance;
76 int requested_slots[NBR_OF_REGIONS][NBR_OF_CLIENTS];
77 int active_clients[NBR_OF_REGIONS][NBR_OF_CLIENTS];
80 static struct crisv32_watch_entry watches[ARBITERS][NUMBER_OF_BP] =
96 struct arbiter arbiters[ARBITERS] =
98 { /* L2 cache arbiter */
99 .instance = regi_marb_foo,
104 .instance = regi_marb_bar,
110 static int max_bandwidth[NBR_OF_REGIONS] = {SDRAM_BANDWIDTH, INTMEM_BANDWIDTH};
112 DEFINE_SPINLOCK(arbiter_lock);
115 crisv32_foo_arbiter_irq(int irq, void *dev_id);
117 crisv32_bar_arbiter_irq(int irq, void *dev_id);
120 * "I'm the arbiter, I know the score.
121 * From square one I'll be watching all 64."
122 * (memory arbiter slots, that is)
125 * Program the memory arbiter slots for "region" according to what's
126 * in requested_slots[] and active_clients[], while minimizing
127 * latency. A caller may pass a non-zero positive amount for
128 * "unused_slots", which must then be the unallocated, remaining
129 * number of slots, free to hand out to any client.
132 static void crisv32_arbiter_config(int arbiter, int region, int unused_slots)
139 * This vector corresponds to the hardware arbiter slots (see
140 * the hardware documentation for semantics). We initialize
141 * each slot with a suitable sentinel value outside the valid
142 * range {0 .. NBR_OF_CLIENTS - 1} and replace them with
143 * client indexes. Then it's fed to the hardware.
145 s8 val[NBR_OF_SLOTS];
147 for (slot = 0; slot < NBR_OF_SLOTS; slot++)
150 for (client = 0; client < arbiters[arbiter].nbr_clients; client++) {
152 /* Allocate the requested non-zero number of slots, but
153 * also give clients with zero-requests one slot each
154 * while stocks last. We do the latter here, in client
155 * order. This makes sure zero-request clients are the
156 * first to get to any spare slots, else those slots
157 * could, when bandwidth is allocated close to the limit,
158 * all be allocated to low-index non-zero-request clients
159 * in the default-fill loop below. Another positive but
160 * secondary effect is a somewhat better spread of the
161 * zero-bandwidth clients in the vector, avoiding some of
162 * the latency that could otherwise be caused by the
163 * partitioning of non-zero-bandwidth clients at low
164 * indexes and zero-bandwidth clients at high
165 * indexes. (Note that this spreading can only affect the
166 * unallocated bandwidth.) All the above only matters for
167 * memory-intensive situations, of course.
169 if (!arbiters[arbiter].requested_slots[region][client]) {
171 * Skip inactive clients. Also skip zero-slot
172 * allocations in this pass when there are no known
175 if (!arbiters[arbiter].active_clients[region][client] ||
181 /* Only allocate one slot for this client. */
182 interval = NBR_OF_SLOTS;
184 interval = NBR_OF_SLOTS /
185 arbiters[arbiter].requested_slots[region][client];
188 while (pos < NBR_OF_SLOTS) {
199 for (slot = 0; slot < NBR_OF_SLOTS; slot++) {
201 * Allocate remaining slots in round-robin
202 * client-number order for active clients. For this
203 * pass, we ignore requested bandwidth and previous
208 while (!arbiters[arbiter].active_clients[region][client]) {
209 client = (client + 1) %
210 arbiters[arbiter].nbr_clients;
215 client = (client + 1) % arbiters[arbiter].nbr_clients;
218 if (region == EXT_REGION)
219 REG_WR_INT_VECT(marb_foo, regi_marb_foo,
220 rw_l2_slots, slot, val[slot]);
221 else if (region == INT_REGION)
222 REG_WR_INT_VECT(marb_foo, regi_marb_foo,
223 rw_intm_slots, slot, val[slot]);
225 REG_WR_INT_VECT(marb_bar, regi_marb_bar,
226 rw_ddr2_slots, slot, val[slot]);
231 extern char _stext[], _etext[];
233 static void crisv32_arbiter_init(void)
235 static int initialized;
243 * CPU caches are always set to active, but with zero
244 * bandwidth allocated. It should be ok to allocate zero
245 * bandwidth for the caches, because DMA for other channels
246 * will supposedly finish, once their programmed amount is
247 * done, and then the caches will get access according to the
248 * "fixed scheme" for unclaimed slots. Though, if for some
249 * use-case somewhere, there's a maximum CPU latency for
250 * e.g. some interrupt, we have to start allocating specific
251 * bandwidth for the CPU caches too.
253 arbiters[0].active_clients[EXT_REGION][11] = 1;
254 arbiters[0].active_clients[EXT_REGION][12] = 1;
255 crisv32_arbiter_config(0, EXT_REGION, 0);
256 crisv32_arbiter_config(0, INT_REGION, 0);
257 crisv32_arbiter_config(1, EXT_REGION, 0);
259 if (request_irq(MEMARB_FOO_INTR_VECT, crisv32_foo_arbiter_irq,
261 printk(KERN_ERR "Couldn't allocate arbiter IRQ\n");
263 if (request_irq(MEMARB_BAR_INTR_VECT, crisv32_bar_arbiter_irq,
265 printk(KERN_ERR "Couldn't allocate arbiter IRQ\n");
267 #ifndef CONFIG_ETRAX_KGDB
268 /* Global watch for writes to kernel text segment. */
269 crisv32_arbiter_watch(virt_to_phys(_stext), _etext - _stext,
270 MARB_CLIENTS(arbiter_all_clients, arbiter_bar_all_clients),
271 arbiter_all_write, NULL);
274 /* Set up max burst sizes by default */
275 REG_WR_INT(marb_bar, regi_marb_bar, rw_h264_rd_burst, 3);
276 REG_WR_INT(marb_bar, regi_marb_bar, rw_h264_wr_burst, 3);
277 REG_WR_INT(marb_bar, regi_marb_bar, rw_ccd_burst, 3);
278 REG_WR_INT(marb_bar, regi_marb_bar, rw_vin_wr_burst, 3);
279 REG_WR_INT(marb_bar, regi_marb_bar, rw_vin_rd_burst, 3);
280 REG_WR_INT(marb_bar, regi_marb_bar, rw_sclr_rd_burst, 3);
281 REG_WR_INT(marb_bar, regi_marb_bar, rw_vout_burst, 3);
282 REG_WR_INT(marb_bar, regi_marb_bar, rw_sclr_fifo_burst, 3);
283 REG_WR_INT(marb_bar, regi_marb_bar, rw_l2cache_burst, 3);
286 int crisv32_arbiter_allocate_bandwidth(int client, int region,
287 unsigned long bandwidth)
290 int total_assigned = 0;
291 int total_clients = 0;
295 crisv32_arbiter_init();
297 if (client & 0xffff0000) {
302 for (i = 0; i < arbiters[arbiter].nbr_clients; i++) {
303 total_assigned += arbiters[arbiter].requested_slots[region][i];
304 total_clients += arbiters[arbiter].active_clients[region][i];
307 /* Avoid division by 0 for 0-bandwidth requests. */
309 ? 0 : NBR_OF_SLOTS / (max_bandwidth[region] / bandwidth);
312 * We make sure that there are enough slots only for non-zero
313 * requests. Requesting 0 bandwidth *may* allocate slots,
314 * though if all bandwidth is allocated, such a client won't
315 * get any and will have to rely on getting memory access
316 * according to the fixed scheme that's the default when one
317 * of the slot-allocated clients doesn't claim their slot.
319 if (total_assigned + req > NBR_OF_SLOTS)
322 arbiters[arbiter].active_clients[region][client] = 1;
323 arbiters[arbiter].requested_slots[region][client] = req;
324 crisv32_arbiter_config(arbiter, region, NBR_OF_SLOTS - total_assigned);
326 /* Propagate allocation from foo to bar */
328 crisv32_arbiter_allocate_bandwidth(8 << 16,
329 EXT_REGION, bandwidth);
334 * Main entry for bandwidth deallocation.
336 * Strictly speaking, for a somewhat constant set of clients where
337 * each client gets a constant bandwidth and is just enabled or
338 * disabled (somewhat dynamically), no action is necessary here to
339 * avoid starvation for non-zero-allocation clients, as the allocated
340 * slots will just be unused. However, handing out those unused slots
341 * to active clients avoids needless latency if the "fixed scheme"
342 * would give unclaimed slots to an eager low-index client.
345 void crisv32_arbiter_deallocate_bandwidth(int client, int region)
348 int total_assigned = 0;
351 if (client & 0xffff0000)
354 arbiters[arbiter].requested_slots[region][client] = 0;
355 arbiters[arbiter].active_clients[region][client] = 0;
357 for (i = 0; i < arbiters[arbiter].nbr_clients; i++)
358 total_assigned += arbiters[arbiter].requested_slots[region][i];
360 crisv32_arbiter_config(arbiter, region, NBR_OF_SLOTS - total_assigned);
363 int crisv32_arbiter_watch(unsigned long start, unsigned long size,
364 unsigned long clients, unsigned long accesses,
372 crisv32_arbiter_init();
374 if (start > 0x80000000) {
375 printk(KERN_ERR "Arbiter: %lX doesn't look like a "
376 "physical address", start);
380 spin_lock(&arbiter_lock);
382 if (clients & 0xffff)
384 if (clients & 0xffff0000)
387 for (arbiter = 0; arbiter < ARBITERS; arbiter++) {
391 for (i = 0; i < NUMBER_OF_BP; i++) {
392 if (!watches[arbiter][i].used) {
395 intr_mask = REG_RD_INT(marb_bar,
396 regi_marb_bar, rw_intr_mask);
398 intr_mask = REG_RD_INT(marb_foo,
399 regi_marb_foo, rw_intr_mask);
401 watches[arbiter][i].used = 1;
402 watches[arbiter][i].start = start;
403 watches[arbiter][i].end = start + size;
404 watches[arbiter][i].cb = cb;
406 ret |= (i + 1) << (arbiter + 8);
408 REG_WR_INT(marb_bar_bp,
409 watches[arbiter][i].instance,
411 watches[arbiter][i].start);
412 REG_WR_INT(marb_bar_bp,
413 watches[arbiter][i].instance,
415 watches[arbiter][i].end);
416 REG_WR_INT(marb_bar_bp,
417 watches[arbiter][i].instance,
419 REG_WR_INT(marb_bar_bp,
420 watches[arbiter][i].instance,
424 REG_WR_INT(marb_foo_bp,
425 watches[arbiter][i].instance,
427 watches[arbiter][i].start);
428 REG_WR_INT(marb_foo_bp,
429 watches[arbiter][i].instance,
431 watches[arbiter][i].end);
432 REG_WR_INT(marb_foo_bp,
433 watches[arbiter][i].instance,
435 REG_WR_INT(marb_foo_bp,
436 watches[arbiter][i].instance,
437 rw_clients, clients >> 16);
450 REG_WR_INT(marb_bar, regi_marb_bar,
451 rw_intr_mask, intr_mask);
453 REG_WR_INT(marb_foo, regi_marb_foo,
454 rw_intr_mask, intr_mask);
456 spin_unlock(&arbiter_lock);
462 spin_unlock(&arbiter_lock);
469 int crisv32_arbiter_unwatch(int id)
474 crisv32_arbiter_init();
476 spin_lock(&arbiter_lock);
478 for (arbiter = 0; arbiter < ARBITERS; arbiter++) {
482 intr_mask = REG_RD_INT(marb_bar, regi_marb_bar,
485 intr_mask = REG_RD_INT(marb_foo, regi_marb_foo,
488 id2 = (id & (0xff << (arbiter + 8))) >> (arbiter + 8);
492 if ((id2 >= NUMBER_OF_BP) || (!watches[arbiter][id2].used)) {
493 spin_unlock(&arbiter_lock);
497 memset(&watches[arbiter][id2], 0,
498 sizeof(struct crisv32_watch_entry));
510 REG_WR_INT(marb_bar, regi_marb_bar, rw_intr_mask,
513 REG_WR_INT(marb_foo, regi_marb_foo, rw_intr_mask,
517 spin_unlock(&arbiter_lock);
521 extern void show_registers(struct pt_regs *regs);
525 crisv32_foo_arbiter_irq(int irq, void *dev_id)
527 reg_marb_foo_r_masked_intr masked_intr =
528 REG_RD(marb_foo, regi_marb_foo, r_masked_intr);
529 reg_marb_foo_bp_r_brk_clients r_clients;
530 reg_marb_foo_bp_r_brk_addr r_addr;
531 reg_marb_foo_bp_r_brk_op r_op;
532 reg_marb_foo_bp_r_brk_first_client r_first;
533 reg_marb_foo_bp_r_brk_size r_size;
534 reg_marb_foo_bp_rw_ack ack = {0};
535 reg_marb_foo_rw_ack_intr ack_intr = {
536 .bp0 = 1, .bp1 = 1, .bp2 = 1, .bp3 = 1
538 struct crisv32_watch_entry *watch;
539 unsigned arbiter = (unsigned)dev_id;
541 masked_intr = REG_RD(marb_foo, regi_marb_foo, r_masked_intr);
544 watch = &watches[arbiter][0];
545 else if (masked_intr.bp1)
546 watch = &watches[arbiter][1];
547 else if (masked_intr.bp2)
548 watch = &watches[arbiter][2];
549 else if (masked_intr.bp3)
550 watch = &watches[arbiter][3];
554 /* Retrieve all useful information and print it. */
555 r_clients = REG_RD(marb_foo_bp, watch->instance, r_brk_clients);
556 r_addr = REG_RD(marb_foo_bp, watch->instance, r_brk_addr);
557 r_op = REG_RD(marb_foo_bp, watch->instance, r_brk_op);
558 r_first = REG_RD(marb_foo_bp, watch->instance, r_brk_first_client);
559 r_size = REG_RD(marb_foo_bp, watch->instance, r_brk_size);
561 printk(KERN_DEBUG "Arbiter IRQ\n");
562 printk(KERN_DEBUG "Clients %X addr %X op %X first %X size %X\n",
563 REG_TYPE_CONV(int, reg_marb_foo_bp_r_brk_clients, r_clients),
564 REG_TYPE_CONV(int, reg_marb_foo_bp_r_brk_addr, r_addr),
565 REG_TYPE_CONV(int, reg_marb_foo_bp_r_brk_op, r_op),
566 REG_TYPE_CONV(int, reg_marb_foo_bp_r_brk_first_client, r_first),
567 REG_TYPE_CONV(int, reg_marb_foo_bp_r_brk_size, r_size));
569 REG_WR(marb_foo_bp, watch->instance, rw_ack, ack);
570 REG_WR(marb_foo, regi_marb_foo, rw_ack_intr, ack_intr);
572 printk(KERN_DEBUG "IRQ occurred at %X\n", (unsigned)get_irq_regs());
581 crisv32_bar_arbiter_irq(int irq, void *dev_id)
583 reg_marb_bar_r_masked_intr masked_intr =
584 REG_RD(marb_bar, regi_marb_bar, r_masked_intr);
585 reg_marb_bar_bp_r_brk_clients r_clients;
586 reg_marb_bar_bp_r_brk_addr r_addr;
587 reg_marb_bar_bp_r_brk_op r_op;
588 reg_marb_bar_bp_r_brk_first_client r_first;
589 reg_marb_bar_bp_r_brk_size r_size;
590 reg_marb_bar_bp_rw_ack ack = {0};
591 reg_marb_bar_rw_ack_intr ack_intr = {
592 .bp0 = 1, .bp1 = 1, .bp2 = 1, .bp3 = 1
594 struct crisv32_watch_entry *watch;
595 unsigned arbiter = (unsigned)dev_id;
597 masked_intr = REG_RD(marb_bar, regi_marb_bar, r_masked_intr);
600 watch = &watches[arbiter][0];
601 else if (masked_intr.bp1)
602 watch = &watches[arbiter][1];
603 else if (masked_intr.bp2)
604 watch = &watches[arbiter][2];
605 else if (masked_intr.bp3)
606 watch = &watches[arbiter][3];
610 /* Retrieve all useful information and print it. */
611 r_clients = REG_RD(marb_bar_bp, watch->instance, r_brk_clients);
612 r_addr = REG_RD(marb_bar_bp, watch->instance, r_brk_addr);
613 r_op = REG_RD(marb_bar_bp, watch->instance, r_brk_op);
614 r_first = REG_RD(marb_bar_bp, watch->instance, r_brk_first_client);
615 r_size = REG_RD(marb_bar_bp, watch->instance, r_brk_size);
617 printk(KERN_DEBUG "Arbiter IRQ\n");
618 printk(KERN_DEBUG "Clients %X addr %X op %X first %X size %X\n",
619 REG_TYPE_CONV(int, reg_marb_bar_bp_r_brk_clients, r_clients),
620 REG_TYPE_CONV(int, reg_marb_bar_bp_r_brk_addr, r_addr),
621 REG_TYPE_CONV(int, reg_marb_bar_bp_r_brk_op, r_op),
622 REG_TYPE_CONV(int, reg_marb_bar_bp_r_brk_first_client, r_first),
623 REG_TYPE_CONV(int, reg_marb_bar_bp_r_brk_size, r_size));
625 REG_WR(marb_bar_bp, watch->instance, rw_ack, ack);
626 REG_WR(marb_bar, regi_marb_bar, rw_ack_intr, ack_intr);
628 printk(KERN_DEBUG "IRQ occurred at %X\n", (unsigned)get_irq_regs()->erp);