1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Based on arch/arm/mm/proc.S
5 * Copyright (C) 2001 Deep Blue Solutions Ltd.
6 * Copyright (C) 2012 ARM Ltd.
7 * Author: Catalin Marinas <catalin.marinas@arm.com>
10 #include <linux/init.h>
11 #include <linux/linkage.h>
12 #include <linux/pgtable.h>
13 #include <asm/assembler.h>
14 #include <asm/asm-offsets.h>
15 #include <asm/asm_pointer_auth.h>
16 #include <asm/hwcap.h>
17 #include <asm/pgtable-hwdef.h>
18 #include <asm/cpufeature.h>
19 #include <asm/alternative.h>
21 #include <asm/sysreg.h>
23 #ifdef CONFIG_ARM64_64K_PAGES
24 #define TCR_TG_FLAGS TCR_TG0_64K | TCR_TG1_64K
25 #elif defined(CONFIG_ARM64_16K_PAGES)
26 #define TCR_TG_FLAGS TCR_TG0_16K | TCR_TG1_16K
27 #else /* CONFIG_ARM64_4K_PAGES */
28 #define TCR_TG_FLAGS TCR_TG0_4K | TCR_TG1_4K
31 #ifdef CONFIG_RANDOMIZE_BASE
32 #define TCR_KASLR_FLAGS TCR_NFD1
34 #define TCR_KASLR_FLAGS 0
37 #define TCR_SMP_FLAGS TCR_SHARED
39 /* PTWs cacheable, inner/outer WBWA */
40 #define TCR_CACHE_FLAGS TCR_IRGN_WBWA | TCR_ORGN_WBWA
42 #ifdef CONFIG_KASAN_SW_TAGS
43 #define TCR_KASAN_SW_FLAGS TCR_TBI1 | TCR_TBID1
45 #define TCR_KASAN_SW_FLAGS 0
48 #ifdef CONFIG_KASAN_HW_TAGS
49 #define TCR_MTE_FLAGS TCR_TCMA1 | TCR_TBI1 | TCR_TBID1
50 #elif defined(CONFIG_ARM64_MTE)
52 * The mte_zero_clear_page_tags() implementation uses DC GZVA, which relies on
53 * TBI being enabled at EL1.
55 #define TCR_MTE_FLAGS TCR_TBI1 | TCR_TBID1
57 #define TCR_MTE_FLAGS 0
61 * Default MAIR_EL1. MT_NORMAL_TAGGED is initially mapped as Normal memory and
62 * changed during mte_cpu_setup to Normal Tagged if the system supports MTE.
64 #define MAIR_EL1_SET \
65 (MAIR_ATTRIDX(MAIR_ATTR_DEVICE_nGnRnE, MT_DEVICE_nGnRnE) | \
66 MAIR_ATTRIDX(MAIR_ATTR_DEVICE_nGnRE, MT_DEVICE_nGnRE) | \
67 MAIR_ATTRIDX(MAIR_ATTR_NORMAL_NC, MT_NORMAL_NC) | \
68 MAIR_ATTRIDX(MAIR_ATTR_NORMAL, MT_NORMAL) | \
69 MAIR_ATTRIDX(MAIR_ATTR_NORMAL, MT_NORMAL_TAGGED))
73 * cpu_do_suspend - save CPU registers context
75 * x0: virtual address of context pointer
77 * This must be kept in sync with struct cpu_suspend_ctx in <asm/suspend.h>.
79 SYM_FUNC_START(cpu_do_suspend)
82 mrs x4, contextidr_el1
90 get_this_cpu_offset x12
96 stp x10, x11, [x0, #64]
97 stp x12, x13, [x0, #80]
99 * Save x18 as it may be used as a platform register, e.g. by shadow
104 SYM_FUNC_END(cpu_do_suspend)
107 * cpu_do_resume - restore CPU register context
109 * x0: Address of context pointer
111 .pushsection ".idmap.text", "awx"
112 SYM_FUNC_START(cpu_do_resume)
114 ldp x4, x5, [x0, #16]
115 ldp x6, x8, [x0, #32]
116 ldp x9, x10, [x0, #48]
117 ldp x11, x12, [x0, #64]
118 ldp x13, x14, [x0, #80]
120 * Restore x18, as it may be used as a platform register, and clear
121 * the buffer to minimize the risk of exposure when used for shadow
128 msr contextidr_el1, x4
131 /* Don't change t0sz here, mask those bits when restoring */
133 bfi x8, x7, TCR_T0SZ_OFFSET, TCR_TxSZ_WIDTH
139 * __cpu_setup() cleared MDSCR_EL1.MDE and friends, before unmasking
140 * debug exceptions. By restoring MDSCR_EL1 here, we may take a debug
141 * exception. Mask them until local_daif_restore() in cpu_suspend()
148 set_this_cpu_offset x13
151 * Restore oslsr_el1 by writing oslar_el1
154 ubfx x11, x11, #1, #1
156 reset_pmuserenr_el0 x0 // Disable PMU access from EL0
157 reset_amuserenr_el0 x0 // Disable AMU access from EL0
159 alternative_if ARM64_HAS_RAS_EXTN
160 msr_s SYS_DISR_EL1, xzr
161 alternative_else_nop_endif
163 ptrauth_keys_install_kernel_nosync x14, x1, x2, x3
166 SYM_FUNC_END(cpu_do_resume)
170 .pushsection ".idmap.text", "awx"
172 .macro __idmap_cpu_set_reserved_ttbr1, tmp1, tmp2
173 adrp \tmp1, reserved_pg_dir
174 phys_to_ttbr \tmp2, \tmp1
175 offset_ttbr1 \tmp2, \tmp1
184 * void idmap_cpu_replace_ttbr1(phys_addr_t ttbr1)
186 * This is the low-level counterpart to cpu_replace_ttbr1, and should not be
187 * called by anything else. It can only be executed from a TTBR0 mapping.
189 SYM_FUNC_START(idmap_cpu_replace_ttbr1)
190 save_and_disable_daif flags=x2
192 __idmap_cpu_set_reserved_ttbr1 x1, x3
201 SYM_FUNC_END(idmap_cpu_replace_ttbr1)
204 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0
205 .pushsection ".idmap.text", "awx"
207 .macro __idmap_kpti_get_pgtable_ent, type
208 dc cvac, cur_\()\type\()p // Ensure any existing dirty
209 dmb sy // lines are written back before
210 ldr \type, [cur_\()\type\()p] // loading the entry
211 tbz \type, #0, skip_\()\type // Skip invalid and
212 tbnz \type, #11, skip_\()\type // non-global entries
215 .macro __idmap_kpti_put_pgtable_ent_ng, type
216 orr \type, \type, #PTE_NG // Same bit for blocks and pages
217 str \type, [cur_\()\type\()p] // Update the entry and ensure
218 dmb sy // that it is visible to all
219 dc civac, cur_\()\type\()p // CPUs.
223 * void __kpti_install_ng_mappings(int cpu, int num_cpus, phys_addr_t swapper)
225 * Called exactly once from stop_machine context by each CPU found during boot.
229 SYM_FUNC_START(idmap_kpti_install_ng_mappings)
248 mrs swapper_ttb, ttbr1_el1
249 restore_ttbr1 swapper_ttb
250 adr flag_ptr, __idmap_kpti_flag
252 cbnz cpu, __idmap_kpti_secondary
254 /* We're the boot CPU. Wait for the others to catch up */
257 ldaxr w17, [flag_ptr]
258 eor w17, w17, num_cpus
261 /* We need to walk swapper, so turn off the MMU. */
262 pre_disable_mmu_workaround
264 bic x17, x17, #SCTLR_ELx_M
268 /* Everybody is enjoying the idmap, so we can rewrite swapper. */
270 mov cur_pgdp, swapper_pa
271 add end_pgdp, cur_pgdp, #(PTRS_PER_PGD * 8)
272 do_pgd: __idmap_kpti_get_pgtable_ent pgd
273 tbnz pgd, #1, walk_puds
275 __idmap_kpti_put_pgtable_ent_ng pgd
277 add cur_pgdp, cur_pgdp, #8
278 cmp cur_pgdp, end_pgdp
281 /* Publish the updated tables and nuke all the TLBs */
287 /* We're done: fire up the MMU again */
289 orr x17, x17, #SCTLR_ELx_M
292 /* Set the flag to zero to indicate that we're all done */
298 .if CONFIG_PGTABLE_LEVELS > 3
299 pte_to_phys cur_pudp, pgd
300 add end_pudp, cur_pudp, #(PTRS_PER_PUD * 8)
301 do_pud: __idmap_kpti_get_pgtable_ent pud
302 tbnz pud, #1, walk_pmds
304 __idmap_kpti_put_pgtable_ent_ng pud
306 add cur_pudp, cur_pudp, 8
307 cmp cur_pudp, end_pudp
310 .else /* CONFIG_PGTABLE_LEVELS <= 3 */
319 .if CONFIG_PGTABLE_LEVELS > 2
320 pte_to_phys cur_pmdp, pud
321 add end_pmdp, cur_pmdp, #(PTRS_PER_PMD * 8)
322 do_pmd: __idmap_kpti_get_pgtable_ent pmd
323 tbnz pmd, #1, walk_ptes
325 __idmap_kpti_put_pgtable_ent_ng pmd
327 add cur_pmdp, cur_pmdp, #8
328 cmp cur_pmdp, end_pmdp
331 .else /* CONFIG_PGTABLE_LEVELS <= 2 */
340 pte_to_phys cur_ptep, pmd
341 add end_ptep, cur_ptep, #(PTRS_PER_PTE * 8)
342 do_pte: __idmap_kpti_get_pgtable_ent pte
343 __idmap_kpti_put_pgtable_ent_ng pte
345 add cur_ptep, cur_ptep, #8
346 cmp cur_ptep, end_ptep
366 /* Secondary CPUs end up here */
367 __idmap_kpti_secondary:
368 /* Uninstall swapper before surgery begins */
369 __idmap_cpu_set_reserved_ttbr1 x16, x17
371 /* Increment the flag to let the boot CPU we're ready */
372 1: ldxr w16, [flag_ptr]
374 stxr w17, w16, [flag_ptr]
377 /* Wait for the boot CPU to finish messing around with swapper */
383 /* All done, act like nothing happened */
384 offset_ttbr1 swapper_ttb, x16
385 msr ttbr1_el1, swapper_ttb
391 SYM_FUNC_END(idmap_kpti_install_ng_mappings)
398 * Initialise the processor for turning the MMU on.
401 * Return in x0 the value of the SCTLR_EL1 register.
403 .pushsection ".idmap.text", "awx"
404 SYM_FUNC_START(__cpu_setup)
405 tlbi vmalle1 // Invalidate local TLB
409 msr cpacr_el1, x1 // Enable FP/ASIMD
410 mov x1, #1 << 12 // Reset mdscr_el1 and disable
411 msr mdscr_el1, x1 // access to the DCC from EL0
412 isb // Unmask debug exceptions now,
413 enable_dbg // since this is per-cpu
414 reset_pmuserenr_el0 x1 // Disable PMU access from EL0
415 reset_amuserenr_el0 x1 // Disable AMU access from EL0
418 * Default values for VMSA control registers. These will be adjusted
419 * below depending on detected CPU features.
423 mov_q mair, MAIR_EL1_SET
424 mov_q tcr, TCR_TxSZ(VA_BITS) | TCR_CACHE_FLAGS | TCR_SMP_FLAGS | \
425 TCR_TG_FLAGS | TCR_KASLR_FLAGS | TCR_ASID16 | \
426 TCR_TBI0 | TCR_A1 | TCR_KASAN_SW_FLAGS | TCR_MTE_FLAGS
428 tcr_clear_errata_bits tcr, x9, x5
430 #ifdef CONFIG_ARM64_VA_BITS_52
431 ldr_l x9, vabits_actual
441 * Set the IPS bits in TCR_EL1.
443 tcr_compute_pa_size tcr, #TCR_IPS_SHIFT, x5, x6
444 #ifdef CONFIG_ARM64_HW_AFDBM
446 * Enable hardware update of the Access Flags bit.
447 * Hardware dirty bit management is enabled later,
450 mrs x9, ID_AA64MMFR1_EL1
453 orr tcr, tcr, #TCR_HA // hardware Access flag update
455 #endif /* CONFIG_ARM64_HW_AFDBM */
461 mov_q x0, INIT_SCTLR_EL1_MMU_ON
462 ret // return to head.S
466 SYM_FUNC_END(__cpu_setup)