2 * SWIOTLB-based DMA API implementation
4 * Copyright (C) 2012 ARM Ltd.
5 * Author: Catalin Marinas <catalin.marinas@arm.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program. If not, see <http://www.gnu.org/licenses/>.
20 #include <linux/gfp.h>
21 #include <linux/acpi.h>
22 #include <linux/bootmem.h>
23 #include <linux/cache.h>
24 #include <linux/export.h>
25 #include <linux/slab.h>
26 #include <linux/genalloc.h>
27 #include <linux/dma-mapping.h>
28 #include <linux/dma-contiguous.h>
29 #include <linux/vmalloc.h>
30 #include <linux/swiotlb.h>
32 #include <asm/cacheflush.h>
34 static int swiotlb __ro_after_init;
36 static pgprot_t __get_dma_pgprot(unsigned long attrs, pgprot_t prot,
39 if (!coherent || (attrs & DMA_ATTR_WRITE_COMBINE))
40 return pgprot_writecombine(prot);
44 static struct gen_pool *atomic_pool;
46 #define DEFAULT_DMA_COHERENT_POOL_SIZE SZ_256K
47 static size_t atomic_pool_size __initdata = DEFAULT_DMA_COHERENT_POOL_SIZE;
49 static int __init early_coherent_pool(char *p)
51 atomic_pool_size = memparse(p, &p);
54 early_param("coherent_pool", early_coherent_pool);
56 static void *__alloc_from_pool(size_t size, struct page **ret_page, gfp_t flags)
62 WARN(1, "coherent pool not initialised!\n");
66 val = gen_pool_alloc(atomic_pool, size);
68 phys_addr_t phys = gen_pool_virt_to_phys(atomic_pool, val);
70 *ret_page = phys_to_page(phys);
78 static bool __in_atomic_pool(void *start, size_t size)
80 return addr_in_gen_pool(atomic_pool, (unsigned long)start, size);
83 static int __free_from_pool(void *start, size_t size)
85 if (!__in_atomic_pool(start, size))
88 gen_pool_free(atomic_pool, (unsigned long)start, size);
93 static void *__dma_alloc_coherent(struct device *dev, size_t size,
94 dma_addr_t *dma_handle, gfp_t flags,
98 WARN_ONCE(1, "Use an actual device structure for DMA allocation\n");
102 if (IS_ENABLED(CONFIG_ZONE_DMA) &&
103 dev->coherent_dma_mask <= DMA_BIT_MASK(32))
105 if (dev_get_cma_area(dev) && gfpflags_allow_blocking(flags)) {
109 page = dma_alloc_from_contiguous(dev, size >> PAGE_SHIFT,
114 *dma_handle = phys_to_dma(dev, page_to_phys(page));
115 addr = page_address(page);
116 memset(addr, 0, size);
119 return swiotlb_alloc_coherent(dev, size, dma_handle, flags);
123 static void __dma_free_coherent(struct device *dev, size_t size,
124 void *vaddr, dma_addr_t dma_handle,
128 phys_addr_t paddr = dma_to_phys(dev, dma_handle);
131 WARN_ONCE(1, "Use an actual device structure for DMA allocation\n");
135 freed = dma_release_from_contiguous(dev,
139 swiotlb_free_coherent(dev, size, vaddr, dma_handle);
142 static void *__dma_alloc(struct device *dev, size_t size,
143 dma_addr_t *dma_handle, gfp_t flags,
147 void *ptr, *coherent_ptr;
148 bool coherent = is_device_dma_coherent(dev);
149 pgprot_t prot = __get_dma_pgprot(attrs, PAGE_KERNEL, false);
151 size = PAGE_ALIGN(size);
153 if (!coherent && !gfpflags_allow_blocking(flags)) {
154 struct page *page = NULL;
155 void *addr = __alloc_from_pool(size, &page, flags);
158 *dma_handle = phys_to_dma(dev, page_to_phys(page));
163 ptr = __dma_alloc_coherent(dev, size, dma_handle, flags, attrs);
167 /* no need for non-cacheable mapping if coherent */
171 /* remove any dirty cache lines on the kernel alias */
172 __dma_flush_area(ptr, size);
174 /* create a coherent mapping */
175 page = virt_to_page(ptr);
176 coherent_ptr = dma_common_contiguous_remap(page, size, VM_USERMAP,
184 __dma_free_coherent(dev, size, ptr, *dma_handle, attrs);
186 *dma_handle = DMA_ERROR_CODE;
190 static void __dma_free(struct device *dev, size_t size,
191 void *vaddr, dma_addr_t dma_handle,
194 void *swiotlb_addr = phys_to_virt(dma_to_phys(dev, dma_handle));
196 size = PAGE_ALIGN(size);
198 if (!is_device_dma_coherent(dev)) {
199 if (__free_from_pool(vaddr, size))
203 __dma_free_coherent(dev, size, swiotlb_addr, dma_handle, attrs);
206 static dma_addr_t __swiotlb_map_page(struct device *dev, struct page *page,
207 unsigned long offset, size_t size,
208 enum dma_data_direction dir,
213 dev_addr = swiotlb_map_page(dev, page, offset, size, dir, attrs);
214 if (!is_device_dma_coherent(dev))
215 __dma_map_area(phys_to_virt(dma_to_phys(dev, dev_addr)), size, dir);
221 static void __swiotlb_unmap_page(struct device *dev, dma_addr_t dev_addr,
222 size_t size, enum dma_data_direction dir,
225 if (!is_device_dma_coherent(dev))
226 __dma_unmap_area(phys_to_virt(dma_to_phys(dev, dev_addr)), size, dir);
227 swiotlb_unmap_page(dev, dev_addr, size, dir, attrs);
230 static int __swiotlb_map_sg_attrs(struct device *dev, struct scatterlist *sgl,
231 int nelems, enum dma_data_direction dir,
234 struct scatterlist *sg;
237 ret = swiotlb_map_sg_attrs(dev, sgl, nelems, dir, attrs);
238 if (!is_device_dma_coherent(dev))
239 for_each_sg(sgl, sg, ret, i)
240 __dma_map_area(phys_to_virt(dma_to_phys(dev, sg->dma_address)),
246 static void __swiotlb_unmap_sg_attrs(struct device *dev,
247 struct scatterlist *sgl, int nelems,
248 enum dma_data_direction dir,
251 struct scatterlist *sg;
254 if (!is_device_dma_coherent(dev))
255 for_each_sg(sgl, sg, nelems, i)
256 __dma_unmap_area(phys_to_virt(dma_to_phys(dev, sg->dma_address)),
258 swiotlb_unmap_sg_attrs(dev, sgl, nelems, dir, attrs);
261 static void __swiotlb_sync_single_for_cpu(struct device *dev,
262 dma_addr_t dev_addr, size_t size,
263 enum dma_data_direction dir)
265 if (!is_device_dma_coherent(dev))
266 __dma_unmap_area(phys_to_virt(dma_to_phys(dev, dev_addr)), size, dir);
267 swiotlb_sync_single_for_cpu(dev, dev_addr, size, dir);
270 static void __swiotlb_sync_single_for_device(struct device *dev,
271 dma_addr_t dev_addr, size_t size,
272 enum dma_data_direction dir)
274 swiotlb_sync_single_for_device(dev, dev_addr, size, dir);
275 if (!is_device_dma_coherent(dev))
276 __dma_map_area(phys_to_virt(dma_to_phys(dev, dev_addr)), size, dir);
279 static void __swiotlb_sync_sg_for_cpu(struct device *dev,
280 struct scatterlist *sgl, int nelems,
281 enum dma_data_direction dir)
283 struct scatterlist *sg;
286 if (!is_device_dma_coherent(dev))
287 for_each_sg(sgl, sg, nelems, i)
288 __dma_unmap_area(phys_to_virt(dma_to_phys(dev, sg->dma_address)),
290 swiotlb_sync_sg_for_cpu(dev, sgl, nelems, dir);
293 static void __swiotlb_sync_sg_for_device(struct device *dev,
294 struct scatterlist *sgl, int nelems,
295 enum dma_data_direction dir)
297 struct scatterlist *sg;
300 swiotlb_sync_sg_for_device(dev, sgl, nelems, dir);
301 if (!is_device_dma_coherent(dev))
302 for_each_sg(sgl, sg, nelems, i)
303 __dma_map_area(phys_to_virt(dma_to_phys(dev, sg->dma_address)),
307 static int __swiotlb_mmap(struct device *dev,
308 struct vm_area_struct *vma,
309 void *cpu_addr, dma_addr_t dma_addr, size_t size,
313 unsigned long nr_vma_pages = (vma->vm_end - vma->vm_start) >>
315 unsigned long nr_pages = PAGE_ALIGN(size) >> PAGE_SHIFT;
316 unsigned long pfn = dma_to_phys(dev, dma_addr) >> PAGE_SHIFT;
317 unsigned long off = vma->vm_pgoff;
319 vma->vm_page_prot = __get_dma_pgprot(attrs, vma->vm_page_prot,
320 is_device_dma_coherent(dev));
322 if (dma_mmap_from_coherent(dev, vma, cpu_addr, size, &ret))
325 if (off < nr_pages && nr_vma_pages <= (nr_pages - off)) {
326 ret = remap_pfn_range(vma, vma->vm_start,
328 vma->vm_end - vma->vm_start,
335 static int __swiotlb_get_sgtable(struct device *dev, struct sg_table *sgt,
336 void *cpu_addr, dma_addr_t handle, size_t size,
339 int ret = sg_alloc_table(sgt, 1, GFP_KERNEL);
342 sg_set_page(sgt->sgl, phys_to_page(dma_to_phys(dev, handle)),
343 PAGE_ALIGN(size), 0);
348 static int __swiotlb_dma_supported(struct device *hwdev, u64 mask)
351 return swiotlb_dma_supported(hwdev, mask);
355 static int __swiotlb_dma_mapping_error(struct device *hwdev, dma_addr_t addr)
358 return swiotlb_dma_mapping_error(hwdev, addr);
362 static struct dma_map_ops swiotlb_dma_ops = {
363 .alloc = __dma_alloc,
365 .mmap = __swiotlb_mmap,
366 .get_sgtable = __swiotlb_get_sgtable,
367 .map_page = __swiotlb_map_page,
368 .unmap_page = __swiotlb_unmap_page,
369 .map_sg = __swiotlb_map_sg_attrs,
370 .unmap_sg = __swiotlb_unmap_sg_attrs,
371 .sync_single_for_cpu = __swiotlb_sync_single_for_cpu,
372 .sync_single_for_device = __swiotlb_sync_single_for_device,
373 .sync_sg_for_cpu = __swiotlb_sync_sg_for_cpu,
374 .sync_sg_for_device = __swiotlb_sync_sg_for_device,
375 .dma_supported = __swiotlb_dma_supported,
376 .mapping_error = __swiotlb_dma_mapping_error,
379 static int __init atomic_pool_init(void)
381 pgprot_t prot = __pgprot(PROT_NORMAL_NC);
382 unsigned long nr_pages = atomic_pool_size >> PAGE_SHIFT;
385 unsigned int pool_size_order = get_order(atomic_pool_size);
387 if (dev_get_cma_area(NULL))
388 page = dma_alloc_from_contiguous(NULL, nr_pages,
391 page = alloc_pages(GFP_DMA, pool_size_order);
395 void *page_addr = page_address(page);
397 memset(page_addr, 0, atomic_pool_size);
398 __dma_flush_area(page_addr, atomic_pool_size);
400 atomic_pool = gen_pool_create(PAGE_SHIFT, -1);
404 addr = dma_common_contiguous_remap(page, atomic_pool_size,
405 VM_USERMAP, prot, atomic_pool_init);
408 goto destroy_genpool;
410 ret = gen_pool_add_virt(atomic_pool, (unsigned long)addr,
412 atomic_pool_size, -1);
416 gen_pool_set_algo(atomic_pool,
417 gen_pool_first_fit_order_align,
420 pr_info("DMA: preallocated %zu KiB pool for atomic allocations\n",
421 atomic_pool_size / 1024);
427 dma_common_free_remap(addr, atomic_pool_size, VM_USERMAP);
429 gen_pool_destroy(atomic_pool);
432 if (!dma_release_from_contiguous(NULL, page, nr_pages))
433 __free_pages(page, pool_size_order);
435 pr_err("DMA: failed to allocate %zu KiB pool for atomic coherent allocation\n",
436 atomic_pool_size / 1024);
440 /********************************************
441 * The following APIs are for dummy DMA ops *
442 ********************************************/
444 static void *__dummy_alloc(struct device *dev, size_t size,
445 dma_addr_t *dma_handle, gfp_t flags,
451 static void __dummy_free(struct device *dev, size_t size,
452 void *vaddr, dma_addr_t dma_handle,
457 static int __dummy_mmap(struct device *dev,
458 struct vm_area_struct *vma,
459 void *cpu_addr, dma_addr_t dma_addr, size_t size,
465 static dma_addr_t __dummy_map_page(struct device *dev, struct page *page,
466 unsigned long offset, size_t size,
467 enum dma_data_direction dir,
470 return DMA_ERROR_CODE;
473 static void __dummy_unmap_page(struct device *dev, dma_addr_t dev_addr,
474 size_t size, enum dma_data_direction dir,
479 static int __dummy_map_sg(struct device *dev, struct scatterlist *sgl,
480 int nelems, enum dma_data_direction dir,
486 static void __dummy_unmap_sg(struct device *dev,
487 struct scatterlist *sgl, int nelems,
488 enum dma_data_direction dir,
493 static void __dummy_sync_single(struct device *dev,
494 dma_addr_t dev_addr, size_t size,
495 enum dma_data_direction dir)
499 static void __dummy_sync_sg(struct device *dev,
500 struct scatterlist *sgl, int nelems,
501 enum dma_data_direction dir)
505 static int __dummy_mapping_error(struct device *hwdev, dma_addr_t dma_addr)
510 static int __dummy_dma_supported(struct device *hwdev, u64 mask)
515 struct dma_map_ops dummy_dma_ops = {
516 .alloc = __dummy_alloc,
517 .free = __dummy_free,
518 .mmap = __dummy_mmap,
519 .map_page = __dummy_map_page,
520 .unmap_page = __dummy_unmap_page,
521 .map_sg = __dummy_map_sg,
522 .unmap_sg = __dummy_unmap_sg,
523 .sync_single_for_cpu = __dummy_sync_single,
524 .sync_single_for_device = __dummy_sync_single,
525 .sync_sg_for_cpu = __dummy_sync_sg,
526 .sync_sg_for_device = __dummy_sync_sg,
527 .mapping_error = __dummy_mapping_error,
528 .dma_supported = __dummy_dma_supported,
530 EXPORT_SYMBOL(dummy_dma_ops);
532 static int __init arm64_dma_init(void)
534 if (swiotlb_force == SWIOTLB_FORCE ||
535 max_pfn > (arm64_dma_phys_limit >> PAGE_SHIFT))
538 return atomic_pool_init();
540 arch_initcall(arm64_dma_init);
542 #define PREALLOC_DMA_DEBUG_ENTRIES 4096
544 static int __init dma_debug_do_init(void)
546 dma_debug_init(PREALLOC_DMA_DEBUG_ENTRIES);
549 fs_initcall(dma_debug_do_init);
552 #ifdef CONFIG_IOMMU_DMA
553 #include <linux/dma-iommu.h>
554 #include <linux/platform_device.h>
555 #include <linux/amba/bus.h>
557 /* Thankfully, all cache ops are by VA so we can ignore phys here */
558 static void flush_page(struct device *dev, const void *virt, phys_addr_t phys)
560 __dma_flush_area(virt, PAGE_SIZE);
563 static void *__iommu_alloc_attrs(struct device *dev, size_t size,
564 dma_addr_t *handle, gfp_t gfp,
567 bool coherent = is_device_dma_coherent(dev);
568 int ioprot = dma_direction_to_prot(DMA_BIDIRECTIONAL, coherent);
569 size_t iosize = size;
572 if (WARN(!dev, "cannot create IOMMU mapping for unknown device\n"))
575 size = PAGE_ALIGN(size);
578 * Some drivers rely on this, and we probably don't want the
579 * possibility of stale kernel data being read by devices anyway.
583 if (gfpflags_allow_blocking(gfp)) {
585 pgprot_t prot = __get_dma_pgprot(attrs, PAGE_KERNEL, coherent);
587 pages = iommu_dma_alloc(dev, iosize, gfp, attrs, ioprot,
592 addr = dma_common_pages_remap(pages, size, VM_USERMAP, prot,
593 __builtin_return_address(0));
595 iommu_dma_free(dev, pages, iosize, handle);
599 * In atomic context we can't remap anything, so we'll only
600 * get the virtually contiguous buffer we need by way of a
601 * physically contiguous allocation.
604 page = alloc_pages(gfp, get_order(size));
605 addr = page ? page_address(page) : NULL;
607 addr = __alloc_from_pool(size, &page, gfp);
612 *handle = iommu_dma_map_page(dev, page, 0, iosize, ioprot);
613 if (iommu_dma_mapping_error(dev, *handle)) {
615 __free_pages(page, get_order(size));
617 __free_from_pool(addr, size);
624 static void __iommu_free_attrs(struct device *dev, size_t size, void *cpu_addr,
625 dma_addr_t handle, unsigned long attrs)
627 size_t iosize = size;
629 size = PAGE_ALIGN(size);
631 * @cpu_addr will be one of 3 things depending on how it was allocated:
632 * - A remapped array of pages from iommu_dma_alloc(), for all
633 * non-atomic allocations.
634 * - A non-cacheable alias from the atomic pool, for atomic
635 * allocations by non-coherent devices.
636 * - A normal lowmem address, for atomic allocations by
638 * Hence how dodgy the below logic looks...
640 if (__in_atomic_pool(cpu_addr, size)) {
641 iommu_dma_unmap_page(dev, handle, iosize, 0, 0);
642 __free_from_pool(cpu_addr, size);
643 } else if (is_vmalloc_addr(cpu_addr)){
644 struct vm_struct *area = find_vm_area(cpu_addr);
646 if (WARN_ON(!area || !area->pages))
648 iommu_dma_free(dev, area->pages, iosize, &handle);
649 dma_common_free_remap(cpu_addr, size, VM_USERMAP);
651 iommu_dma_unmap_page(dev, handle, iosize, 0, 0);
652 __free_pages(virt_to_page(cpu_addr), get_order(size));
656 static int __iommu_mmap_attrs(struct device *dev, struct vm_area_struct *vma,
657 void *cpu_addr, dma_addr_t dma_addr, size_t size,
660 struct vm_struct *area;
663 vma->vm_page_prot = __get_dma_pgprot(attrs, vma->vm_page_prot,
664 is_device_dma_coherent(dev));
666 if (dma_mmap_from_coherent(dev, vma, cpu_addr, size, &ret))
669 area = find_vm_area(cpu_addr);
670 if (WARN_ON(!area || !area->pages))
673 return iommu_dma_mmap(area->pages, size, vma);
676 static int __iommu_get_sgtable(struct device *dev, struct sg_table *sgt,
677 void *cpu_addr, dma_addr_t dma_addr,
678 size_t size, unsigned long attrs)
680 unsigned int count = PAGE_ALIGN(size) >> PAGE_SHIFT;
681 struct vm_struct *area = find_vm_area(cpu_addr);
683 if (WARN_ON(!area || !area->pages))
686 return sg_alloc_table_from_pages(sgt, area->pages, count, 0, size,
690 static void __iommu_sync_single_for_cpu(struct device *dev,
691 dma_addr_t dev_addr, size_t size,
692 enum dma_data_direction dir)
696 if (is_device_dma_coherent(dev))
699 phys = iommu_iova_to_phys(iommu_get_domain_for_dev(dev), dev_addr);
700 __dma_unmap_area(phys_to_virt(phys), size, dir);
703 static void __iommu_sync_single_for_device(struct device *dev,
704 dma_addr_t dev_addr, size_t size,
705 enum dma_data_direction dir)
709 if (is_device_dma_coherent(dev))
712 phys = iommu_iova_to_phys(iommu_get_domain_for_dev(dev), dev_addr);
713 __dma_map_area(phys_to_virt(phys), size, dir);
716 static dma_addr_t __iommu_map_page(struct device *dev, struct page *page,
717 unsigned long offset, size_t size,
718 enum dma_data_direction dir,
721 bool coherent = is_device_dma_coherent(dev);
722 int prot = dma_direction_to_prot(dir, coherent);
723 dma_addr_t dev_addr = iommu_dma_map_page(dev, page, offset, size, prot);
725 if (!iommu_dma_mapping_error(dev, dev_addr) &&
726 (attrs & DMA_ATTR_SKIP_CPU_SYNC) == 0)
727 __iommu_sync_single_for_device(dev, dev_addr, size, dir);
732 static void __iommu_unmap_page(struct device *dev, dma_addr_t dev_addr,
733 size_t size, enum dma_data_direction dir,
736 if ((attrs & DMA_ATTR_SKIP_CPU_SYNC) == 0)
737 __iommu_sync_single_for_cpu(dev, dev_addr, size, dir);
739 iommu_dma_unmap_page(dev, dev_addr, size, dir, attrs);
742 static void __iommu_sync_sg_for_cpu(struct device *dev,
743 struct scatterlist *sgl, int nelems,
744 enum dma_data_direction dir)
746 struct scatterlist *sg;
749 if (is_device_dma_coherent(dev))
752 for_each_sg(sgl, sg, nelems, i)
753 __dma_unmap_area(sg_virt(sg), sg->length, dir);
756 static void __iommu_sync_sg_for_device(struct device *dev,
757 struct scatterlist *sgl, int nelems,
758 enum dma_data_direction dir)
760 struct scatterlist *sg;
763 if (is_device_dma_coherent(dev))
766 for_each_sg(sgl, sg, nelems, i)
767 __dma_map_area(sg_virt(sg), sg->length, dir);
770 static int __iommu_map_sg_attrs(struct device *dev, struct scatterlist *sgl,
771 int nelems, enum dma_data_direction dir,
774 bool coherent = is_device_dma_coherent(dev);
776 if ((attrs & DMA_ATTR_SKIP_CPU_SYNC) == 0)
777 __iommu_sync_sg_for_device(dev, sgl, nelems, dir);
779 return iommu_dma_map_sg(dev, sgl, nelems,
780 dma_direction_to_prot(dir, coherent));
783 static void __iommu_unmap_sg_attrs(struct device *dev,
784 struct scatterlist *sgl, int nelems,
785 enum dma_data_direction dir,
788 if ((attrs & DMA_ATTR_SKIP_CPU_SYNC) == 0)
789 __iommu_sync_sg_for_cpu(dev, sgl, nelems, dir);
791 iommu_dma_unmap_sg(dev, sgl, nelems, dir, attrs);
794 static struct dma_map_ops iommu_dma_ops = {
795 .alloc = __iommu_alloc_attrs,
796 .free = __iommu_free_attrs,
797 .mmap = __iommu_mmap_attrs,
798 .get_sgtable = __iommu_get_sgtable,
799 .map_page = __iommu_map_page,
800 .unmap_page = __iommu_unmap_page,
801 .map_sg = __iommu_map_sg_attrs,
802 .unmap_sg = __iommu_unmap_sg_attrs,
803 .sync_single_for_cpu = __iommu_sync_single_for_cpu,
804 .sync_single_for_device = __iommu_sync_single_for_device,
805 .sync_sg_for_cpu = __iommu_sync_sg_for_cpu,
806 .sync_sg_for_device = __iommu_sync_sg_for_device,
807 .dma_supported = iommu_dma_supported,
808 .mapping_error = iommu_dma_mapping_error,
812 * TODO: Right now __iommu_setup_dma_ops() gets called too early to do
813 * everything it needs to - the device is only partially created and the
814 * IOMMU driver hasn't seen it yet, so it can't have a group. Thus we
815 * need this delayed attachment dance. Once IOMMU probe ordering is sorted
816 * to move the arch_setup_dma_ops() call later, all the notifier bits below
817 * become unnecessary, and will go away.
819 struct iommu_dma_notifier_data {
820 struct list_head list;
822 const struct iommu_ops *ops;
826 static LIST_HEAD(iommu_dma_masters);
827 static DEFINE_MUTEX(iommu_dma_notifier_lock);
829 static bool do_iommu_attach(struct device *dev, const struct iommu_ops *ops,
830 u64 dma_base, u64 size)
832 struct iommu_domain *domain = iommu_get_domain_for_dev(dev);
835 * If the IOMMU driver has the DMA domain support that we require,
836 * then the IOMMU core will have already configured a group for this
837 * device, and allocated the default domain for that group.
842 if (domain->type == IOMMU_DOMAIN_DMA) {
843 if (iommu_dma_init_domain(domain, dma_base, size, dev))
846 dev->archdata.dma_ops = &iommu_dma_ops;
851 pr_warn("Failed to set up IOMMU for device %s; retaining platform DMA ops\n",
856 static void queue_iommu_attach(struct device *dev, const struct iommu_ops *ops,
857 u64 dma_base, u64 size)
859 struct iommu_dma_notifier_data *iommudata;
861 iommudata = kzalloc(sizeof(*iommudata), GFP_KERNEL);
865 iommudata->dev = dev;
866 iommudata->ops = ops;
867 iommudata->dma_base = dma_base;
868 iommudata->size = size;
870 mutex_lock(&iommu_dma_notifier_lock);
871 list_add(&iommudata->list, &iommu_dma_masters);
872 mutex_unlock(&iommu_dma_notifier_lock);
875 static int __iommu_attach_notifier(struct notifier_block *nb,
876 unsigned long action, void *data)
878 struct iommu_dma_notifier_data *master, *tmp;
880 if (action != BUS_NOTIFY_BIND_DRIVER)
883 mutex_lock(&iommu_dma_notifier_lock);
884 list_for_each_entry_safe(master, tmp, &iommu_dma_masters, list) {
885 if (data == master->dev && do_iommu_attach(master->dev,
886 master->ops, master->dma_base, master->size)) {
887 list_del(&master->list);
892 mutex_unlock(&iommu_dma_notifier_lock);
896 static int __init register_iommu_dma_ops_notifier(struct bus_type *bus)
898 struct notifier_block *nb = kzalloc(sizeof(*nb), GFP_KERNEL);
904 nb->notifier_call = __iommu_attach_notifier;
906 ret = bus_register_notifier(bus, nb);
908 pr_warn("Failed to register DMA domain notifier; IOMMU DMA ops unavailable on bus '%s'\n",
915 static int __init __iommu_dma_init(void)
919 ret = iommu_dma_init();
921 ret = register_iommu_dma_ops_notifier(&platform_bus_type);
923 ret = register_iommu_dma_ops_notifier(&amba_bustype);
926 ret = register_iommu_dma_ops_notifier(&pci_bus_type);
930 arch_initcall(__iommu_dma_init);
932 static void __iommu_setup_dma_ops(struct device *dev, u64 dma_base, u64 size,
933 const struct iommu_ops *ops)
935 struct iommu_group *group;
940 * TODO: As a concession to the future, we're ready to handle being
941 * called both early and late (i.e. after bus_add_device). Once all
942 * the platform bus code is reworked to call us late and the notifier
943 * junk above goes away, move the body of do_iommu_attach here.
945 group = iommu_group_get(dev);
947 do_iommu_attach(dev, ops, dma_base, size);
948 iommu_group_put(group);
950 queue_iommu_attach(dev, ops, dma_base, size);
954 void arch_teardown_dma_ops(struct device *dev)
956 struct iommu_domain *domain = iommu_get_domain_for_dev(dev);
959 iommu_detach_device(domain, dev);
961 dev->archdata.dma_ops = NULL;
966 static void __iommu_setup_dma_ops(struct device *dev, u64 dma_base, u64 size,
967 const struct iommu_ops *iommu)
970 #endif /* CONFIG_IOMMU_DMA */
972 void arch_setup_dma_ops(struct device *dev, u64 dma_base, u64 size,
973 const struct iommu_ops *iommu, bool coherent)
975 if (!dev->archdata.dma_ops)
976 dev->archdata.dma_ops = &swiotlb_dma_ops;
978 dev->archdata.dma_coherent = coherent;
979 __iommu_setup_dma_ops(dev, dma_base, size, iommu);