1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2012 ARM Ltd.
4 * Author: Catalin Marinas <catalin.marinas@arm.com>
8 #include <linux/cache.h>
9 #include <linux/dma-map-ops.h>
10 #include <linux/iommu.h>
13 #include <asm/cacheflush.h>
14 #include <asm/xen/xen-ops.h>
16 void arch_sync_dma_for_device(phys_addr_t paddr, size_t size,
17 enum dma_data_direction dir)
19 unsigned long start = (unsigned long)phys_to_virt(paddr);
21 dcache_clean_poc(start, start + size);
24 void arch_sync_dma_for_cpu(phys_addr_t paddr, size_t size,
25 enum dma_data_direction dir)
27 unsigned long start = (unsigned long)phys_to_virt(paddr);
29 if (dir == DMA_TO_DEVICE)
32 dcache_inval_poc(start, start + size);
35 void arch_dma_prep_coherent(struct page *page, size_t size)
37 unsigned long start = (unsigned long)page_address(page);
40 * The architecture only requires a clean to the PoC here in order to
41 * meet the requirements of the DMA API. However, some vendors (i.e.
42 * Qualcomm) abuse the DMA API for transferring buffers from the
43 * non-secure to the secure world, resetting the system if a non-secure
44 * access shows up after the buffer has been transferred:
46 * https://lore.kernel.org/r/20221114110329.68413-1-manivannan.sadhasivam@linaro.org
48 * Using clean+invalidate appears to make this issue less likely, but
49 * the drivers themselves still need fixing as the CPU could issue a
50 * speculative read from the buffer via the linear mapping irrespective
51 * of the cache maintenance we use. Once the drivers are fixed, we can
52 * relax this to a clean operation.
54 dcache_clean_inval_poc(start, start + size);
57 #ifdef CONFIG_IOMMU_DMA
58 void arch_teardown_dma_ops(struct device *dev)
64 void arch_setup_dma_ops(struct device *dev, u64 dma_base, u64 size,
65 const struct iommu_ops *iommu, bool coherent)
67 int cls = cache_line_size_of_cpu();
69 WARN_TAINT(!coherent && cls > ARCH_DMA_MINALIGN,
70 TAINT_CPU_OUT_OF_SPEC,
71 "%s %s: ARCH_DMA_MINALIGN smaller than CTR_EL0.CWG (%d < %d)",
72 dev_driver_string(dev), dev_name(dev),
73 ARCH_DMA_MINALIGN, cls);
75 dev->dma_coherent = coherent;
77 iommu_setup_dma_ops(dev, dma_base, dma_base + size - 1);
79 xen_setup_dma_ops(dev);