2 * Based on arch/arm/mm/context.c
4 * Copyright (C) 2002-2003 Deep Blue Solutions Ltd, all rights reserved.
5 * Copyright (C) 2012 ARM Ltd.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program. If not, see <http://www.gnu.org/licenses/>.
20 #include <linux/bitops.h>
21 #include <linux/sched.h>
22 #include <linux/slab.h>
25 #include <asm/cpufeature.h>
26 #include <asm/mmu_context.h>
28 #include <asm/tlbflush.h>
31 static DEFINE_RAW_SPINLOCK(cpu_asid_lock);
33 static atomic64_t asid_generation;
34 static unsigned long *asid_map;
36 static DEFINE_PER_CPU(atomic64_t, active_asids);
37 static DEFINE_PER_CPU(u64, reserved_asids);
38 static cpumask_t tlb_flush_pending;
40 #define ASID_MASK (~GENMASK(asid_bits - 1, 0))
41 #define ASID_FIRST_VERSION (1UL << asid_bits)
43 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0
44 #define NUM_USER_ASIDS (ASID_FIRST_VERSION >> 1)
45 #define asid2idx(asid) (((asid) & ~ASID_MASK) >> 1)
46 #define idx2asid(idx) (((idx) << 1) & ~ASID_MASK)
48 #define NUM_USER_ASIDS (ASID_FIRST_VERSION)
49 #define asid2idx(asid) ((asid) & ~ASID_MASK)
50 #define idx2asid(idx) asid2idx(idx)
53 /* Get the ASIDBits supported by the current CPU */
54 static u32 get_cpu_asid_bits(void)
57 int fld = cpuid_feature_extract_unsigned_field(read_cpuid(ID_AA64MMFR0_EL1),
58 ID_AA64MMFR0_ASID_SHIFT);
62 pr_warn("CPU%d: Unknown ASID size (%d); assuming 8-bit\n",
63 smp_processor_id(), fld);
75 /* Check if the current cpu's ASIDBits is compatible with asid_bits */
76 void verify_cpu_asid_bits(void)
78 u32 asid = get_cpu_asid_bits();
80 if (asid < asid_bits) {
82 * We cannot decrease the ASID size at runtime, so panic if we support
83 * fewer ASID bits than the boot CPU.
85 pr_crit("CPU%d: smaller ASID size(%u) than boot CPU (%u)\n",
86 smp_processor_id(), asid, asid_bits);
91 static void flush_context(unsigned int cpu)
96 /* Update the list of reserved ASIDs and the ASID bitmap. */
97 bitmap_clear(asid_map, 0, NUM_USER_ASIDS);
100 * Ensure the generation bump is observed before we xchg the
105 for_each_possible_cpu(i) {
106 asid = atomic64_xchg_relaxed(&per_cpu(active_asids, i), 0);
108 * If this CPU has already been through a
109 * rollover, but hasn't run another task in
110 * the meantime, we must preserve its reserved
111 * ASID, as this is the only trace we have of
112 * the process it is still running.
115 asid = per_cpu(reserved_asids, i);
116 __set_bit(asid2idx(asid), asid_map);
117 per_cpu(reserved_asids, i) = asid;
120 /* Queue a TLB invalidate and flush the I-cache if necessary. */
121 cpumask_setall(&tlb_flush_pending);
123 if (icache_is_aivivt())
124 __flush_icache_all();
127 static bool check_update_reserved_asid(u64 asid, u64 newasid)
133 * Iterate over the set of reserved ASIDs looking for a match.
134 * If we find one, then we can update our mm to use newasid
135 * (i.e. the same ASID in the current generation) but we can't
136 * exit the loop early, since we need to ensure that all copies
137 * of the old ASID are updated to reflect the mm. Failure to do
138 * so could result in us missing the reserved ASID in a future
141 for_each_possible_cpu(cpu) {
142 if (per_cpu(reserved_asids, cpu) == asid) {
144 per_cpu(reserved_asids, cpu) = newasid;
151 static u64 new_context(struct mm_struct *mm, unsigned int cpu)
153 static u32 cur_idx = 1;
154 u64 asid = atomic64_read(&mm->context.id);
155 u64 generation = atomic64_read(&asid_generation);
158 u64 newasid = generation | (asid & ~ASID_MASK);
161 * If our current ASID was active during a rollover, we
162 * can continue to use it and this was just a false alarm.
164 if (check_update_reserved_asid(asid, newasid))
168 * We had a valid ASID in a previous life, so try to re-use
171 if (!__test_and_set_bit(asid2idx(asid), asid_map))
176 * Allocate a free ASID. If we can't find one, take a note of the
177 * currently active ASIDs and mark the TLBs as requiring flushes. We
178 * always count from ASID #2 (index 1), as we use ASID #0 when setting
179 * a reserved TTBR0 for the init_mm and we allocate ASIDs in even/odd
182 asid = find_next_zero_bit(asid_map, NUM_USER_ASIDS, cur_idx);
183 if (asid != NUM_USER_ASIDS)
186 /* We're out of ASIDs, so increment the global generation count */
187 generation = atomic64_add_return_relaxed(ASID_FIRST_VERSION,
191 /* We have more ASIDs than CPUs, so this will always succeed */
192 asid = find_next_zero_bit(asid_map, NUM_USER_ASIDS, 1);
195 __set_bit(asid, asid_map);
197 return idx2asid(asid) | generation;
200 void check_and_switch_context(struct mm_struct *mm, unsigned int cpu)
205 asid = atomic64_read(&mm->context.id);
208 * The memory ordering here is subtle. We rely on the control
209 * dependency between the generation read and the update of
210 * active_asids to ensure that we are synchronised with a
211 * parallel rollover (i.e. this pairs with the smp_wmb() in
214 if (!((asid ^ atomic64_read(&asid_generation)) >> asid_bits)
215 && atomic64_xchg_relaxed(&per_cpu(active_asids, cpu), asid))
216 goto switch_mm_fastpath;
218 raw_spin_lock_irqsave(&cpu_asid_lock, flags);
219 /* Check that our ASID belongs to the current generation. */
220 asid = atomic64_read(&mm->context.id);
221 if ((asid ^ atomic64_read(&asid_generation)) >> asid_bits) {
222 asid = new_context(mm, cpu);
223 atomic64_set(&mm->context.id, asid);
226 if (cpumask_test_and_clear_cpu(cpu, &tlb_flush_pending))
227 local_flush_tlb_all();
229 atomic64_set(&per_cpu(active_asids, cpu), asid);
230 raw_spin_unlock_irqrestore(&cpu_asid_lock, flags);
234 arm64_apply_bp_hardening();
236 cpu_switch_mm(mm->pgd, mm);
239 /* Errata workaround post TTBRx_EL1 update. */
240 asmlinkage void post_ttbr_update_workaround(void)
242 asm(ALTERNATIVE("nop; nop; nop",
243 "ic iallu; dsb nsh; isb",
244 ARM64_WORKAROUND_CAVIUM_27456,
245 CONFIG_CAVIUM_ERRATUM_27456));
248 static int asids_init(void)
250 asid_bits = get_cpu_asid_bits();
252 * Expect allocation after rollover to fail if we don't have at least
253 * one more ASID than CPUs. ASID #0 is reserved for init_mm.
255 WARN_ON(NUM_USER_ASIDS - 1 <= num_possible_cpus());
256 atomic64_set(&asid_generation, ASID_FIRST_VERSION);
257 asid_map = kzalloc(BITS_TO_LONGS(NUM_USER_ASIDS) * sizeof(*asid_map),
260 panic("Failed to allocate bitmap for %lu ASIDs\n",
263 pr_info("ASID allocator initialised with %lu entries\n", NUM_USER_ASIDS);
266 early_initcall(asids_init);