1 // SPDX-License-Identifier: GPL-2.0-only
3 #include <linux/irqchip/arm-gic-v3.h>
5 #include <linux/irqdomain.h>
7 #include <linux/kvm_host.h>
8 #include <kvm/arm_vgic.h>
9 #include <asm/kvm_hyp.h>
10 #include <asm/kvm_mmu.h>
11 #include <asm/kvm_asm.h>
15 static bool group0_trap;
16 static bool group1_trap;
17 static bool common_trap;
18 static bool gicv4_enable;
20 void vgic_v3_set_underflow(struct kvm_vcpu *vcpu)
22 struct vgic_v3_cpu_if *cpuif = &vcpu->arch.vgic_cpu.vgic_v3;
24 cpuif->vgic_hcr |= ICH_HCR_UIE;
27 static bool lr_signals_eoi_mi(u64 lr_val)
29 return !(lr_val & ICH_LR_STATE) && (lr_val & ICH_LR_EOI) &&
30 !(lr_val & ICH_LR_HW);
33 void vgic_v3_fold_lr_state(struct kvm_vcpu *vcpu)
35 struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
36 struct vgic_v3_cpu_if *cpuif = &vgic_cpu->vgic_v3;
37 u32 model = vcpu->kvm->arch.vgic.vgic_model;
40 DEBUG_SPINLOCK_BUG_ON(!irqs_disabled());
42 cpuif->vgic_hcr &= ~ICH_HCR_UIE;
44 for (lr = 0; lr < cpuif->used_lrs; lr++) {
45 u64 val = cpuif->vgic_lr[lr];
48 bool is_v2_sgi = false;
51 cpuid = val & GICH_LR_PHYSID_CPUID;
52 cpuid >>= GICH_LR_PHYSID_CPUID_SHIFT;
54 if (model == KVM_DEV_TYPE_ARM_VGIC_V3) {
55 intid = val & ICH_LR_VIRTUAL_ID_MASK;
57 intid = val & GICH_LR_VIRTUALID;
58 is_v2_sgi = vgic_irq_is_sgi(intid);
61 /* Notify fds when the guest EOI'ed a level-triggered IRQ */
62 if (lr_signals_eoi_mi(val) && vgic_valid_spi(vcpu->kvm, intid))
63 kvm_notify_acked_irq(vcpu->kvm, 0,
64 intid - VGIC_NR_PRIVATE_IRQS);
66 irq = vgic_get_irq(vcpu->kvm, vcpu, intid);
67 if (!irq) /* An LPI could have been unmapped. */
70 raw_spin_lock(&irq->irq_lock);
72 /* Always preserve the active bit, note deactivation */
73 deactivated = irq->active && !(val & ICH_LR_ACTIVE_BIT);
74 irq->active = !!(val & ICH_LR_ACTIVE_BIT);
76 if (irq->active && is_v2_sgi)
77 irq->active_source = cpuid;
79 /* Edge is the only case where we preserve the pending bit */
80 if (irq->config == VGIC_CONFIG_EDGE &&
81 (val & ICH_LR_PENDING_BIT)) {
82 irq->pending_latch = true;
85 irq->source |= (1 << cpuid);
89 * Clear soft pending state when level irqs have been acked.
91 if (irq->config == VGIC_CONFIG_LEVEL && !(val & ICH_LR_STATE))
92 irq->pending_latch = false;
94 /* Handle resampling for mapped interrupts if required */
95 vgic_irq_handle_resampling(irq, deactivated, val & ICH_LR_PENDING_BIT);
97 raw_spin_unlock(&irq->irq_lock);
98 vgic_put_irq(vcpu->kvm, irq);
104 /* Requires the irq to be locked already */
105 void vgic_v3_populate_lr(struct kvm_vcpu *vcpu, struct vgic_irq *irq, int lr)
107 u32 model = vcpu->kvm->arch.vgic.vgic_model;
108 u64 val = irq->intid;
109 bool allow_pending = true, is_v2_sgi;
111 is_v2_sgi = (vgic_irq_is_sgi(irq->intid) &&
112 model == KVM_DEV_TYPE_ARM_VGIC_V2);
115 val |= ICH_LR_ACTIVE_BIT;
117 val |= irq->active_source << GICH_LR_PHYSID_CPUID_SHIFT;
118 if (vgic_irq_is_multi_sgi(irq)) {
119 allow_pending = false;
124 if (irq->hw && !vgic_irq_needs_resampling(irq)) {
126 val |= ((u64)irq->hwintid) << ICH_LR_PHYS_ID_SHIFT;
128 * Never set pending+active on a HW interrupt, as the
129 * pending state is kept at the physical distributor
133 allow_pending = false;
135 if (irq->config == VGIC_CONFIG_LEVEL) {
139 * Software resampling doesn't work very well
140 * if we allow P+A, so let's not do that.
143 allow_pending = false;
147 if (allow_pending && irq_is_pending(irq)) {
148 val |= ICH_LR_PENDING_BIT;
150 if (irq->config == VGIC_CONFIG_EDGE)
151 irq->pending_latch = false;
153 if (vgic_irq_is_sgi(irq->intid) &&
154 model == KVM_DEV_TYPE_ARM_VGIC_V2) {
155 u32 src = ffs(irq->source);
157 if (WARN_RATELIMIT(!src, "No SGI source for INTID %d\n",
161 val |= (src - 1) << GICH_LR_PHYSID_CPUID_SHIFT;
162 irq->source &= ~(1 << (src - 1));
164 irq->pending_latch = true;
171 * Level-triggered mapped IRQs are special because we only observe
172 * rising edges as input to the VGIC. We therefore lower the line
173 * level here, so that we can take new virtual IRQs. See
174 * vgic_v3_fold_lr_state for more info.
176 if (vgic_irq_is_mapped_level(irq) && (val & ICH_LR_PENDING_BIT))
177 irq->line_level = false;
182 val |= (u64)irq->priority << ICH_LR_PRIORITY_SHIFT;
184 vcpu->arch.vgic_cpu.vgic_v3.vgic_lr[lr] = val;
187 void vgic_v3_clear_lr(struct kvm_vcpu *vcpu, int lr)
189 vcpu->arch.vgic_cpu.vgic_v3.vgic_lr[lr] = 0;
192 void vgic_v3_set_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcrp)
194 struct vgic_v3_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v3;
195 u32 model = vcpu->kvm->arch.vgic.vgic_model;
198 if (model == KVM_DEV_TYPE_ARM_VGIC_V2) {
199 vmcr = (vmcrp->ackctl << ICH_VMCR_ACK_CTL_SHIFT) &
200 ICH_VMCR_ACK_CTL_MASK;
201 vmcr |= (vmcrp->fiqen << ICH_VMCR_FIQ_EN_SHIFT) &
202 ICH_VMCR_FIQ_EN_MASK;
205 * When emulating GICv3 on GICv3 with SRE=1 on the
206 * VFIQEn bit is RES1 and the VAckCtl bit is RES0.
208 vmcr = ICH_VMCR_FIQ_EN_MASK;
211 vmcr |= (vmcrp->cbpr << ICH_VMCR_CBPR_SHIFT) & ICH_VMCR_CBPR_MASK;
212 vmcr |= (vmcrp->eoim << ICH_VMCR_EOIM_SHIFT) & ICH_VMCR_EOIM_MASK;
213 vmcr |= (vmcrp->abpr << ICH_VMCR_BPR1_SHIFT) & ICH_VMCR_BPR1_MASK;
214 vmcr |= (vmcrp->bpr << ICH_VMCR_BPR0_SHIFT) & ICH_VMCR_BPR0_MASK;
215 vmcr |= (vmcrp->pmr << ICH_VMCR_PMR_SHIFT) & ICH_VMCR_PMR_MASK;
216 vmcr |= (vmcrp->grpen0 << ICH_VMCR_ENG0_SHIFT) & ICH_VMCR_ENG0_MASK;
217 vmcr |= (vmcrp->grpen1 << ICH_VMCR_ENG1_SHIFT) & ICH_VMCR_ENG1_MASK;
219 cpu_if->vgic_vmcr = vmcr;
222 void vgic_v3_get_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcrp)
224 struct vgic_v3_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v3;
225 u32 model = vcpu->kvm->arch.vgic.vgic_model;
228 vmcr = cpu_if->vgic_vmcr;
230 if (model == KVM_DEV_TYPE_ARM_VGIC_V2) {
231 vmcrp->ackctl = (vmcr & ICH_VMCR_ACK_CTL_MASK) >>
232 ICH_VMCR_ACK_CTL_SHIFT;
233 vmcrp->fiqen = (vmcr & ICH_VMCR_FIQ_EN_MASK) >>
234 ICH_VMCR_FIQ_EN_SHIFT;
237 * When emulating GICv3 on GICv3 with SRE=1 on the
238 * VFIQEn bit is RES1 and the VAckCtl bit is RES0.
244 vmcrp->cbpr = (vmcr & ICH_VMCR_CBPR_MASK) >> ICH_VMCR_CBPR_SHIFT;
245 vmcrp->eoim = (vmcr & ICH_VMCR_EOIM_MASK) >> ICH_VMCR_EOIM_SHIFT;
246 vmcrp->abpr = (vmcr & ICH_VMCR_BPR1_MASK) >> ICH_VMCR_BPR1_SHIFT;
247 vmcrp->bpr = (vmcr & ICH_VMCR_BPR0_MASK) >> ICH_VMCR_BPR0_SHIFT;
248 vmcrp->pmr = (vmcr & ICH_VMCR_PMR_MASK) >> ICH_VMCR_PMR_SHIFT;
249 vmcrp->grpen0 = (vmcr & ICH_VMCR_ENG0_MASK) >> ICH_VMCR_ENG0_SHIFT;
250 vmcrp->grpen1 = (vmcr & ICH_VMCR_ENG1_MASK) >> ICH_VMCR_ENG1_SHIFT;
253 #define INITIAL_PENDBASER_VALUE \
254 (GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, RaWb) | \
255 GIC_BASER_CACHEABILITY(GICR_PENDBASER, OUTER, SameAsInner) | \
256 GIC_BASER_SHAREABILITY(GICR_PENDBASER, InnerShareable))
258 void vgic_v3_enable(struct kvm_vcpu *vcpu)
260 struct vgic_v3_cpu_if *vgic_v3 = &vcpu->arch.vgic_cpu.vgic_v3;
263 * By forcing VMCR to zero, the GIC will restore the binary
264 * points to their reset values. Anything else resets to zero
267 vgic_v3->vgic_vmcr = 0;
270 * If we are emulating a GICv3, we do it in an non-GICv2-compatible
271 * way, so we force SRE to 1 to demonstrate this to the guest.
272 * Also, we don't support any form of IRQ/FIQ bypass.
273 * This goes with the spec allowing the value to be RAO/WI.
275 if (vcpu->kvm->arch.vgic.vgic_model == KVM_DEV_TYPE_ARM_VGIC_V3) {
276 vgic_v3->vgic_sre = (ICC_SRE_EL1_DIB |
279 vcpu->arch.vgic_cpu.pendbaser = INITIAL_PENDBASER_VALUE;
281 vgic_v3->vgic_sre = 0;
284 vcpu->arch.vgic_cpu.num_id_bits = (kvm_vgic_global_state.ich_vtr_el2 &
285 ICH_VTR_ID_BITS_MASK) >>
286 ICH_VTR_ID_BITS_SHIFT;
287 vcpu->arch.vgic_cpu.num_pri_bits = ((kvm_vgic_global_state.ich_vtr_el2 &
288 ICH_VTR_PRI_BITS_MASK) >>
289 ICH_VTR_PRI_BITS_SHIFT) + 1;
291 /* Get the show on the road... */
292 vgic_v3->vgic_hcr = ICH_HCR_EN;
294 vgic_v3->vgic_hcr |= ICH_HCR_TALL0;
296 vgic_v3->vgic_hcr |= ICH_HCR_TALL1;
298 vgic_v3->vgic_hcr |= ICH_HCR_TC;
301 int vgic_v3_lpi_sync_pending_status(struct kvm *kvm, struct vgic_irq *irq)
303 struct kvm_vcpu *vcpu;
304 int byte_offset, bit_nr;
312 vcpu = irq->target_vcpu;
316 pendbase = GICR_PENDBASER_ADDRESS(vcpu->arch.vgic_cpu.pendbaser);
318 byte_offset = irq->intid / BITS_PER_BYTE;
319 bit_nr = irq->intid % BITS_PER_BYTE;
320 ptr = pendbase + byte_offset;
322 ret = kvm_read_guest_lock(kvm, ptr, &val, 1);
326 status = val & (1 << bit_nr);
328 raw_spin_lock_irqsave(&irq->irq_lock, flags);
329 if (irq->target_vcpu != vcpu) {
330 raw_spin_unlock_irqrestore(&irq->irq_lock, flags);
333 irq->pending_latch = status;
334 vgic_queue_irq_unlock(vcpu->kvm, irq, flags);
337 /* clear consumed data */
338 val &= ~(1 << bit_nr);
339 ret = kvm_write_guest_lock(kvm, ptr, &val, 1);
347 * The deactivation of the doorbell interrupt will trigger the
348 * unmapping of the associated vPE.
350 static void unmap_all_vpes(struct vgic_dist *dist)
352 struct irq_desc *desc;
355 for (i = 0; i < dist->its_vm.nr_vpes; i++) {
356 desc = irq_to_desc(dist->its_vm.vpes[i]->irq);
357 irq_domain_deactivate_irq(irq_desc_get_irq_data(desc));
361 static void map_all_vpes(struct vgic_dist *dist)
363 struct irq_desc *desc;
366 for (i = 0; i < dist->its_vm.nr_vpes; i++) {
367 desc = irq_to_desc(dist->its_vm.vpes[i]->irq);
368 irq_domain_activate_irq(irq_desc_get_irq_data(desc), false);
373 * vgic_v3_save_pending_tables - Save the pending tables into guest RAM
374 * kvm lock and all vcpu lock must be held
376 int vgic_v3_save_pending_tables(struct kvm *kvm)
378 struct vgic_dist *dist = &kvm->arch.vgic;
379 struct vgic_irq *irq;
380 gpa_t last_ptr = ~(gpa_t)0;
381 bool vlpi_avail = false;
385 if (unlikely(!vgic_initialized(kvm)))
389 * A preparation for getting any VLPI states.
390 * The above vgic initialized check also ensures that the allocation
391 * and enabling of the doorbells have already been done.
393 if (kvm_vgic_global_state.has_gicv4_1) {
394 unmap_all_vpes(dist);
398 list_for_each_entry(irq, &dist->lpi_list_head, lpi_list) {
399 int byte_offset, bit_nr;
400 struct kvm_vcpu *vcpu;
405 vcpu = irq->target_vcpu;
409 pendbase = GICR_PENDBASER_ADDRESS(vcpu->arch.vgic_cpu.pendbaser);
411 byte_offset = irq->intid / BITS_PER_BYTE;
412 bit_nr = irq->intid % BITS_PER_BYTE;
413 ptr = pendbase + byte_offset;
415 if (ptr != last_ptr) {
416 ret = kvm_read_guest_lock(kvm, ptr, &val, 1);
422 stored = val & (1U << bit_nr);
424 is_pending = irq->pending_latch;
426 if (irq->hw && vlpi_avail)
427 vgic_v4_get_vlpi_state(irq, &is_pending);
429 if (stored == is_pending)
435 val &= ~(1 << bit_nr);
437 ret = kvm_write_guest_lock(kvm, ptr, &val, 1);
450 * vgic_v3_rdist_overlap - check if a region overlaps with any
451 * existing redistributor region
454 * @base: base of the region
455 * @size: size of region
457 * Return: true if there is an overlap
459 bool vgic_v3_rdist_overlap(struct kvm *kvm, gpa_t base, size_t size)
461 struct vgic_dist *d = &kvm->arch.vgic;
462 struct vgic_redist_region *rdreg;
464 list_for_each_entry(rdreg, &d->rd_regions, list) {
465 if ((base + size > rdreg->base) &&
466 (base < rdreg->base + vgic_v3_rd_region_size(kvm, rdreg)))
473 * Check for overlapping regions and for regions crossing the end of memory
474 * for base addresses which have already been set.
476 bool vgic_v3_check_base(struct kvm *kvm)
478 struct vgic_dist *d = &kvm->arch.vgic;
479 struct vgic_redist_region *rdreg;
481 if (!IS_VGIC_ADDR_UNDEF(d->vgic_dist_base) &&
482 d->vgic_dist_base + KVM_VGIC_V3_DIST_SIZE < d->vgic_dist_base)
485 list_for_each_entry(rdreg, &d->rd_regions, list) {
486 if (rdreg->base + vgic_v3_rd_region_size(kvm, rdreg) <
491 if (IS_VGIC_ADDR_UNDEF(d->vgic_dist_base))
494 return !vgic_v3_rdist_overlap(kvm, d->vgic_dist_base,
495 KVM_VGIC_V3_DIST_SIZE);
499 * vgic_v3_rdist_free_slot - Look up registered rdist regions and identify one
500 * which has free space to put a new rdist region.
502 * @rd_regions: redistributor region list head
504 * A redistributor regions maps n redistributors, n = region size / (2 x 64kB).
505 * Stride between redistributors is 0 and regions are filled in the index order.
507 * Return: the redist region handle, if any, that has space to map a new rdist
510 struct vgic_redist_region *vgic_v3_rdist_free_slot(struct list_head *rd_regions)
512 struct vgic_redist_region *rdreg;
514 list_for_each_entry(rdreg, rd_regions, list) {
515 if (!vgic_v3_redist_region_full(rdreg))
521 struct vgic_redist_region *vgic_v3_rdist_region_from_index(struct kvm *kvm,
524 struct list_head *rd_regions = &kvm->arch.vgic.rd_regions;
525 struct vgic_redist_region *rdreg;
527 list_for_each_entry(rdreg, rd_regions, list) {
528 if (rdreg->index == index)
535 int vgic_v3_map_resources(struct kvm *kvm)
537 struct vgic_dist *dist = &kvm->arch.vgic;
538 struct kvm_vcpu *vcpu;
542 kvm_for_each_vcpu(c, vcpu, kvm) {
543 struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
545 if (IS_VGIC_ADDR_UNDEF(vgic_cpu->rd_iodev.base_addr)) {
546 kvm_debug("vcpu %d redistributor base not set\n", c);
551 if (IS_VGIC_ADDR_UNDEF(dist->vgic_dist_base)) {
552 kvm_err("Need to set vgic distributor addresses first\n");
556 if (!vgic_v3_check_base(kvm)) {
557 kvm_err("VGIC redist and dist frames overlap\n");
562 * For a VGICv3 we require the userland to explicitly initialize
563 * the VGIC before we need to use it.
565 if (!vgic_initialized(kvm)) {
569 ret = vgic_register_dist_iodev(kvm, dist->vgic_dist_base, VGIC_V3);
571 kvm_err("Unable to register VGICv3 dist MMIO regions\n");
575 if (kvm_vgic_global_state.has_gicv4_1)
576 vgic_v4_configure_vsgis(kvm);
581 DEFINE_STATIC_KEY_FALSE(vgic_v3_cpuif_trap);
583 static int __init early_group0_trap_cfg(char *buf)
585 return strtobool(buf, &group0_trap);
587 early_param("kvm-arm.vgic_v3_group0_trap", early_group0_trap_cfg);
589 static int __init early_group1_trap_cfg(char *buf)
591 return strtobool(buf, &group1_trap);
593 early_param("kvm-arm.vgic_v3_group1_trap", early_group1_trap_cfg);
595 static int __init early_common_trap_cfg(char *buf)
597 return strtobool(buf, &common_trap);
599 early_param("kvm-arm.vgic_v3_common_trap", early_common_trap_cfg);
601 static int __init early_gicv4_enable(char *buf)
603 return strtobool(buf, &gicv4_enable);
605 early_param("kvm-arm.vgic_v4_enable", early_gicv4_enable);
608 * vgic_v3_probe - probe for a VGICv3 compatible interrupt controller
609 * @info: pointer to the GIC description
611 * Returns 0 if the VGICv3 has been probed successfully, returns an error code
614 int vgic_v3_probe(const struct gic_kvm_info *info)
616 u64 ich_vtr_el2 = kvm_call_hyp_ret(__vgic_v3_get_gic_config);
620 has_v2 = ich_vtr_el2 >> 63;
621 ich_vtr_el2 = (u32)ich_vtr_el2;
624 * The ListRegs field is 5 bits, but there is an architectural
625 * maximum of 16 list registers. Just ignore bit 4...
627 kvm_vgic_global_state.nr_lr = (ich_vtr_el2 & 0xf) + 1;
628 kvm_vgic_global_state.can_emulate_gicv2 = false;
629 kvm_vgic_global_state.ich_vtr_el2 = ich_vtr_el2;
633 kvm_vgic_global_state.has_gicv4 = gicv4_enable;
634 kvm_vgic_global_state.has_gicv4_1 = info->has_v4_1 && gicv4_enable;
635 kvm_info("GICv4%s support %sabled\n",
636 kvm_vgic_global_state.has_gicv4_1 ? ".1" : "",
637 gicv4_enable ? "en" : "dis");
640 kvm_vgic_global_state.vcpu_base = 0;
642 if (!info->vcpu.start) {
643 kvm_info("GICv3: no GICV resource entry\n");
644 } else if (!has_v2) {
645 pr_warn(FW_BUG "CPU interface incapable of MMIO access\n");
646 } else if (!PAGE_ALIGNED(info->vcpu.start)) {
647 pr_warn("GICV physical address 0x%llx not page aligned\n",
648 (unsigned long long)info->vcpu.start);
650 kvm_vgic_global_state.vcpu_base = info->vcpu.start;
651 kvm_vgic_global_state.can_emulate_gicv2 = true;
652 ret = kvm_register_vgic_device(KVM_DEV_TYPE_ARM_VGIC_V2);
654 kvm_err("Cannot register GICv2 KVM device.\n");
657 kvm_info("vgic-v2@%llx\n", info->vcpu.start);
659 ret = kvm_register_vgic_device(KVM_DEV_TYPE_ARM_VGIC_V3);
661 kvm_err("Cannot register GICv3 KVM device.\n");
662 kvm_unregister_device_ops(KVM_DEV_TYPE_ARM_VGIC_V2);
666 if (kvm_vgic_global_state.vcpu_base == 0)
667 kvm_info("disabling GICv2 emulation\n");
669 if (cpus_have_const_cap(ARM64_WORKAROUND_CAVIUM_30115)) {
674 if (group0_trap || group1_trap || common_trap) {
675 kvm_info("GICv3 sysreg trapping enabled ([%s%s%s], reduced performance)\n",
676 group0_trap ? "G0" : "",
677 group1_trap ? "G1" : "",
678 common_trap ? "C" : "");
679 static_branch_enable(&vgic_v3_cpuif_trap);
682 kvm_vgic_global_state.vctrl_base = NULL;
683 kvm_vgic_global_state.type = VGIC_V3;
684 kvm_vgic_global_state.max_gic_vcpus = VGIC_V3_MAX_CPUS;
689 void vgic_v3_load(struct kvm_vcpu *vcpu)
691 struct vgic_v3_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v3;
694 * If dealing with a GICv2 emulation on GICv3, VMCR_EL2.VFIQen
695 * is dependent on ICC_SRE_EL1.SRE, and we have to perform the
696 * VMCR_EL2 save/restore in the world switch.
698 if (likely(cpu_if->vgic_sre))
699 kvm_call_hyp(__vgic_v3_write_vmcr, cpu_if->vgic_vmcr);
701 kvm_call_hyp(__vgic_v3_restore_aprs, cpu_if);
704 __vgic_v3_activate_traps(cpu_if);
706 WARN_ON(vgic_v4_load(vcpu));
709 void vgic_v3_vmcr_sync(struct kvm_vcpu *vcpu)
711 struct vgic_v3_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v3;
713 if (likely(cpu_if->vgic_sre))
714 cpu_if->vgic_vmcr = kvm_call_hyp_ret(__vgic_v3_read_vmcr);
717 void vgic_v3_put(struct kvm_vcpu *vcpu)
719 struct vgic_v3_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v3;
721 WARN_ON(vgic_v4_put(vcpu, false));
723 vgic_v3_vmcr_sync(vcpu);
725 kvm_call_hyp(__vgic_v3_save_aprs, cpu_if);
728 __vgic_v3_deactivate_traps(cpu_if);