1 // SPDX-License-Identifier: GPL-2.0-only
3 * VGIC MMIO handling functions
6 #include <linux/bitops.h>
7 #include <linux/bsearch.h>
8 #include <linux/interrupt.h>
10 #include <linux/kvm.h>
11 #include <linux/kvm_host.h>
12 #include <kvm/iodev.h>
13 #include <kvm/arm_arch_timer.h>
14 #include <kvm/arm_vgic.h>
17 #include "vgic-mmio.h"
19 unsigned long vgic_mmio_read_raz(struct kvm_vcpu *vcpu,
20 gpa_t addr, unsigned int len)
25 unsigned long vgic_mmio_read_rao(struct kvm_vcpu *vcpu,
26 gpa_t addr, unsigned int len)
31 void vgic_mmio_write_wi(struct kvm_vcpu *vcpu, gpa_t addr,
32 unsigned int len, unsigned long val)
37 int vgic_mmio_uaccess_write_wi(struct kvm_vcpu *vcpu, gpa_t addr,
38 unsigned int len, unsigned long val)
44 unsigned long vgic_mmio_read_group(struct kvm_vcpu *vcpu,
45 gpa_t addr, unsigned int len)
47 u32 intid = VGIC_ADDR_TO_INTID(addr, 1);
51 /* Loop over all IRQs affected by this read */
52 for (i = 0; i < len * 8; i++) {
53 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
58 vgic_put_irq(vcpu->kvm, irq);
64 static void vgic_update_vsgi(struct vgic_irq *irq)
66 WARN_ON(its_prop_update_vsgi(irq->host_irq, irq->priority, irq->group));
69 void vgic_mmio_write_group(struct kvm_vcpu *vcpu, gpa_t addr,
70 unsigned int len, unsigned long val)
72 u32 intid = VGIC_ADDR_TO_INTID(addr, 1);
76 for (i = 0; i < len * 8; i++) {
77 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
79 raw_spin_lock_irqsave(&irq->irq_lock, flags);
80 irq->group = !!(val & BIT(i));
81 if (irq->hw && vgic_irq_is_sgi(irq->intid)) {
82 vgic_update_vsgi(irq);
83 raw_spin_unlock_irqrestore(&irq->irq_lock, flags);
85 vgic_queue_irq_unlock(vcpu->kvm, irq, flags);
88 vgic_put_irq(vcpu->kvm, irq);
93 * Read accesses to both GICD_ICENABLER and GICD_ISENABLER return the value
94 * of the enabled bit, so there is only one function for both here.
96 unsigned long vgic_mmio_read_enable(struct kvm_vcpu *vcpu,
97 gpa_t addr, unsigned int len)
99 u32 intid = VGIC_ADDR_TO_INTID(addr, 1);
103 /* Loop over all IRQs affected by this read */
104 for (i = 0; i < len * 8; i++) {
105 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
110 vgic_put_irq(vcpu->kvm, irq);
116 void vgic_mmio_write_senable(struct kvm_vcpu *vcpu,
117 gpa_t addr, unsigned int len,
120 u32 intid = VGIC_ADDR_TO_INTID(addr, 1);
124 for_each_set_bit(i, &val, len * 8) {
125 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
127 raw_spin_lock_irqsave(&irq->irq_lock, flags);
128 if (irq->hw && vgic_irq_is_sgi(irq->intid)) {
130 struct irq_data *data;
133 data = &irq_to_desc(irq->host_irq)->irq_data;
134 while (irqd_irq_disabled(data))
135 enable_irq(irq->host_irq);
138 raw_spin_unlock_irqrestore(&irq->irq_lock, flags);
139 vgic_put_irq(vcpu->kvm, irq);
142 } else if (vgic_irq_is_mapped_level(irq)) {
143 bool was_high = irq->line_level;
146 * We need to update the state of the interrupt because
147 * the guest might have changed the state of the device
148 * while the interrupt was disabled at the VGIC level.
150 irq->line_level = vgic_get_phys_line_level(irq);
152 * Deactivate the physical interrupt so the GIC will let
153 * us know when it is asserted again.
155 if (!irq->active && was_high && !irq->line_level)
156 vgic_irq_set_phys_active(irq, false);
159 vgic_queue_irq_unlock(vcpu->kvm, irq, flags);
161 vgic_put_irq(vcpu->kvm, irq);
165 void vgic_mmio_write_cenable(struct kvm_vcpu *vcpu,
166 gpa_t addr, unsigned int len,
169 u32 intid = VGIC_ADDR_TO_INTID(addr, 1);
173 for_each_set_bit(i, &val, len * 8) {
174 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
176 raw_spin_lock_irqsave(&irq->irq_lock, flags);
177 if (irq->hw && vgic_irq_is_sgi(irq->intid) && irq->enabled)
178 disable_irq_nosync(irq->host_irq);
180 irq->enabled = false;
182 raw_spin_unlock_irqrestore(&irq->irq_lock, flags);
183 vgic_put_irq(vcpu->kvm, irq);
187 int vgic_uaccess_write_senable(struct kvm_vcpu *vcpu,
188 gpa_t addr, unsigned int len,
191 u32 intid = VGIC_ADDR_TO_INTID(addr, 1);
195 for_each_set_bit(i, &val, len * 8) {
196 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
198 raw_spin_lock_irqsave(&irq->irq_lock, flags);
200 vgic_queue_irq_unlock(vcpu->kvm, irq, flags);
202 vgic_put_irq(vcpu->kvm, irq);
208 int vgic_uaccess_write_cenable(struct kvm_vcpu *vcpu,
209 gpa_t addr, unsigned int len,
212 u32 intid = VGIC_ADDR_TO_INTID(addr, 1);
216 for_each_set_bit(i, &val, len * 8) {
217 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
219 raw_spin_lock_irqsave(&irq->irq_lock, flags);
220 irq->enabled = false;
221 raw_spin_unlock_irqrestore(&irq->irq_lock, flags);
223 vgic_put_irq(vcpu->kvm, irq);
229 static unsigned long __read_pending(struct kvm_vcpu *vcpu,
230 gpa_t addr, unsigned int len,
233 u32 intid = VGIC_ADDR_TO_INTID(addr, 1);
237 /* Loop over all IRQs affected by this read */
238 for (i = 0; i < len * 8; i++) {
239 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
244 * When used from userspace with a GICv3 model:
246 * Pending state of interrupt is latched in pending_latch
247 * variable. Userspace will save and restore pending state
248 * and line_level separately.
249 * Refer to Documentation/virt/kvm/devices/arm-vgic-v3.rst
250 * for handling of ISPENDR and ICPENDR.
252 raw_spin_lock_irqsave(&irq->irq_lock, flags);
253 if (irq->hw && vgic_irq_is_sgi(irq->intid)) {
257 err = irq_get_irqchip_state(irq->host_irq,
258 IRQCHIP_STATE_PENDING,
260 WARN_RATELIMIT(err, "IRQ %d", irq->host_irq);
261 } else if (!is_user && vgic_irq_is_mapped_level(irq)) {
262 val = vgic_get_phys_line_level(irq);
264 switch (vcpu->kvm->arch.vgic.vgic_model) {
265 case KVM_DEV_TYPE_ARM_VGIC_V3:
267 val = irq->pending_latch;
272 val = irq_is_pending(irq);
277 value |= ((u32)val << i);
278 raw_spin_unlock_irqrestore(&irq->irq_lock, flags);
280 vgic_put_irq(vcpu->kvm, irq);
286 unsigned long vgic_mmio_read_pending(struct kvm_vcpu *vcpu,
287 gpa_t addr, unsigned int len)
289 return __read_pending(vcpu, addr, len, false);
292 unsigned long vgic_uaccess_read_pending(struct kvm_vcpu *vcpu,
293 gpa_t addr, unsigned int len)
295 return __read_pending(vcpu, addr, len, true);
298 static bool is_vgic_v2_sgi(struct kvm_vcpu *vcpu, struct vgic_irq *irq)
300 return (vgic_irq_is_sgi(irq->intid) &&
301 vcpu->kvm->arch.vgic.vgic_model == KVM_DEV_TYPE_ARM_VGIC_V2);
304 void vgic_mmio_write_spending(struct kvm_vcpu *vcpu,
305 gpa_t addr, unsigned int len,
308 u32 intid = VGIC_ADDR_TO_INTID(addr, 1);
312 for_each_set_bit(i, &val, len * 8) {
313 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
315 /* GICD_ISPENDR0 SGI bits are WI */
316 if (is_vgic_v2_sgi(vcpu, irq)) {
317 vgic_put_irq(vcpu->kvm, irq);
321 raw_spin_lock_irqsave(&irq->irq_lock, flags);
323 if (irq->hw && vgic_irq_is_sgi(irq->intid)) {
324 /* HW SGI? Ask the GIC to inject it */
326 err = irq_set_irqchip_state(irq->host_irq,
327 IRQCHIP_STATE_PENDING,
329 WARN_RATELIMIT(err, "IRQ %d", irq->host_irq);
331 raw_spin_unlock_irqrestore(&irq->irq_lock, flags);
332 vgic_put_irq(vcpu->kvm, irq);
337 irq->pending_latch = true;
339 vgic_irq_set_phys_active(irq, true);
341 vgic_queue_irq_unlock(vcpu->kvm, irq, flags);
342 vgic_put_irq(vcpu->kvm, irq);
346 int vgic_uaccess_write_spending(struct kvm_vcpu *vcpu,
347 gpa_t addr, unsigned int len,
350 u32 intid = VGIC_ADDR_TO_INTID(addr, 1);
354 for_each_set_bit(i, &val, len * 8) {
355 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
357 raw_spin_lock_irqsave(&irq->irq_lock, flags);
358 irq->pending_latch = true;
361 * GICv2 SGIs are terribly broken. We can't restore
362 * the source of the interrupt, so just pick the vcpu
363 * itself as the source...
365 if (is_vgic_v2_sgi(vcpu, irq))
366 irq->source |= BIT(vcpu->vcpu_id);
368 vgic_queue_irq_unlock(vcpu->kvm, irq, flags);
370 vgic_put_irq(vcpu->kvm, irq);
376 /* Must be called with irq->irq_lock held */
377 static void vgic_hw_irq_cpending(struct kvm_vcpu *vcpu, struct vgic_irq *irq)
379 irq->pending_latch = false;
382 * We don't want the guest to effectively mask the physical
383 * interrupt by doing a write to SPENDR followed by a write to
384 * CPENDR for HW interrupts, so we clear the active state on
385 * the physical side if the virtual interrupt is not active.
386 * This may lead to taking an additional interrupt on the
387 * host, but that should not be a problem as the worst that
388 * can happen is an additional vgic injection. We also clear
389 * the pending state to maintain proper semantics for edge HW
392 vgic_irq_set_phys_pending(irq, false);
394 vgic_irq_set_phys_active(irq, false);
397 void vgic_mmio_write_cpending(struct kvm_vcpu *vcpu,
398 gpa_t addr, unsigned int len,
401 u32 intid = VGIC_ADDR_TO_INTID(addr, 1);
405 for_each_set_bit(i, &val, len * 8) {
406 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
408 /* GICD_ICPENDR0 SGI bits are WI */
409 if (is_vgic_v2_sgi(vcpu, irq)) {
410 vgic_put_irq(vcpu->kvm, irq);
414 raw_spin_lock_irqsave(&irq->irq_lock, flags);
416 if (irq->hw && vgic_irq_is_sgi(irq->intid)) {
417 /* HW SGI? Ask the GIC to clear its pending bit */
419 err = irq_set_irqchip_state(irq->host_irq,
420 IRQCHIP_STATE_PENDING,
422 WARN_RATELIMIT(err, "IRQ %d", irq->host_irq);
424 raw_spin_unlock_irqrestore(&irq->irq_lock, flags);
425 vgic_put_irq(vcpu->kvm, irq);
431 vgic_hw_irq_cpending(vcpu, irq);
433 irq->pending_latch = false;
435 raw_spin_unlock_irqrestore(&irq->irq_lock, flags);
436 vgic_put_irq(vcpu->kvm, irq);
440 int vgic_uaccess_write_cpending(struct kvm_vcpu *vcpu,
441 gpa_t addr, unsigned int len,
444 u32 intid = VGIC_ADDR_TO_INTID(addr, 1);
448 for_each_set_bit(i, &val, len * 8) {
449 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
451 raw_spin_lock_irqsave(&irq->irq_lock, flags);
453 * More fun with GICv2 SGIs! If we're clearing one of them
454 * from userspace, which source vcpu to clear? Let's not
455 * even think of it, and blow the whole set.
457 if (is_vgic_v2_sgi(vcpu, irq))
460 irq->pending_latch = false;
462 raw_spin_unlock_irqrestore(&irq->irq_lock, flags);
464 vgic_put_irq(vcpu->kvm, irq);
471 * If we are fiddling with an IRQ's active state, we have to make sure the IRQ
472 * is not queued on some running VCPU's LRs, because then the change to the
473 * active state can be overwritten when the VCPU's state is synced coming back
476 * For shared interrupts as well as GICv3 private interrupts accessed from the
477 * non-owning CPU, we have to stop all the VCPUs because interrupts can be
478 * migrated while we don't hold the IRQ locks and we don't want to be chasing
481 * For GICv2 private interrupts we don't have to do anything because
482 * userspace accesses to the VGIC state already require all VCPUs to be
483 * stopped, and only the VCPU itself can modify its private interrupts
484 * active state, which guarantees that the VCPU is not running.
486 static void vgic_access_active_prepare(struct kvm_vcpu *vcpu, u32 intid)
488 if ((vcpu->kvm->arch.vgic.vgic_model == KVM_DEV_TYPE_ARM_VGIC_V3 &&
489 vcpu != kvm_get_running_vcpu()) ||
490 intid >= VGIC_NR_PRIVATE_IRQS)
491 kvm_arm_halt_guest(vcpu->kvm);
494 /* See vgic_access_active_prepare */
495 static void vgic_access_active_finish(struct kvm_vcpu *vcpu, u32 intid)
497 if ((vcpu->kvm->arch.vgic.vgic_model == KVM_DEV_TYPE_ARM_VGIC_V3 &&
498 vcpu != kvm_get_running_vcpu()) ||
499 intid >= VGIC_NR_PRIVATE_IRQS)
500 kvm_arm_resume_guest(vcpu->kvm);
503 static unsigned long __vgic_mmio_read_active(struct kvm_vcpu *vcpu,
504 gpa_t addr, unsigned int len)
506 u32 intid = VGIC_ADDR_TO_INTID(addr, 1);
510 /* Loop over all IRQs affected by this read */
511 for (i = 0; i < len * 8; i++) {
512 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
515 * Even for HW interrupts, don't evaluate the HW state as
516 * all the guest is interested in is the virtual state.
521 vgic_put_irq(vcpu->kvm, irq);
527 unsigned long vgic_mmio_read_active(struct kvm_vcpu *vcpu,
528 gpa_t addr, unsigned int len)
530 u32 intid = VGIC_ADDR_TO_INTID(addr, 1);
533 mutex_lock(&vcpu->kvm->arch.config_lock);
534 vgic_access_active_prepare(vcpu, intid);
536 val = __vgic_mmio_read_active(vcpu, addr, len);
538 vgic_access_active_finish(vcpu, intid);
539 mutex_unlock(&vcpu->kvm->arch.config_lock);
544 unsigned long vgic_uaccess_read_active(struct kvm_vcpu *vcpu,
545 gpa_t addr, unsigned int len)
547 return __vgic_mmio_read_active(vcpu, addr, len);
550 /* Must be called with irq->irq_lock held */
551 static void vgic_hw_irq_change_active(struct kvm_vcpu *vcpu, struct vgic_irq *irq,
552 bool active, bool is_uaccess)
557 irq->active = active;
558 vgic_irq_set_phys_active(irq, active);
561 static void vgic_mmio_change_active(struct kvm_vcpu *vcpu, struct vgic_irq *irq,
565 struct kvm_vcpu *requester_vcpu = kvm_get_running_vcpu();
567 raw_spin_lock_irqsave(&irq->irq_lock, flags);
569 if (irq->hw && !vgic_irq_is_sgi(irq->intid)) {
570 vgic_hw_irq_change_active(vcpu, irq, active, !requester_vcpu);
571 } else if (irq->hw && vgic_irq_is_sgi(irq->intid)) {
573 * GICv4.1 VSGI feature doesn't track an active state,
574 * so let's not kid ourselves, there is nothing we can
579 u32 model = vcpu->kvm->arch.vgic.vgic_model;
582 irq->active = active;
585 * The GICv2 architecture indicates that the source CPUID for
586 * an SGI should be provided during an EOI which implies that
587 * the active state is stored somewhere, but at the same time
588 * this state is not architecturally exposed anywhere and we
589 * have no way of knowing the right source.
591 * This may lead to a VCPU not being able to receive
592 * additional instances of a particular SGI after migration
593 * for a GICv2 VM on some GIC implementations. Oh well.
595 active_source = (requester_vcpu) ? requester_vcpu->vcpu_id : 0;
597 if (model == KVM_DEV_TYPE_ARM_VGIC_V2 &&
598 active && vgic_irq_is_sgi(irq->intid))
599 irq->active_source = active_source;
603 vgic_queue_irq_unlock(vcpu->kvm, irq, flags);
605 raw_spin_unlock_irqrestore(&irq->irq_lock, flags);
608 static void __vgic_mmio_write_cactive(struct kvm_vcpu *vcpu,
609 gpa_t addr, unsigned int len,
612 u32 intid = VGIC_ADDR_TO_INTID(addr, 1);
615 for_each_set_bit(i, &val, len * 8) {
616 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
617 vgic_mmio_change_active(vcpu, irq, false);
618 vgic_put_irq(vcpu->kvm, irq);
622 void vgic_mmio_write_cactive(struct kvm_vcpu *vcpu,
623 gpa_t addr, unsigned int len,
626 u32 intid = VGIC_ADDR_TO_INTID(addr, 1);
628 mutex_lock(&vcpu->kvm->arch.config_lock);
629 vgic_access_active_prepare(vcpu, intid);
631 __vgic_mmio_write_cactive(vcpu, addr, len, val);
633 vgic_access_active_finish(vcpu, intid);
634 mutex_unlock(&vcpu->kvm->arch.config_lock);
637 int vgic_mmio_uaccess_write_cactive(struct kvm_vcpu *vcpu,
638 gpa_t addr, unsigned int len,
641 __vgic_mmio_write_cactive(vcpu, addr, len, val);
645 static void __vgic_mmio_write_sactive(struct kvm_vcpu *vcpu,
646 gpa_t addr, unsigned int len,
649 u32 intid = VGIC_ADDR_TO_INTID(addr, 1);
652 for_each_set_bit(i, &val, len * 8) {
653 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
654 vgic_mmio_change_active(vcpu, irq, true);
655 vgic_put_irq(vcpu->kvm, irq);
659 void vgic_mmio_write_sactive(struct kvm_vcpu *vcpu,
660 gpa_t addr, unsigned int len,
663 u32 intid = VGIC_ADDR_TO_INTID(addr, 1);
665 mutex_lock(&vcpu->kvm->arch.config_lock);
666 vgic_access_active_prepare(vcpu, intid);
668 __vgic_mmio_write_sactive(vcpu, addr, len, val);
670 vgic_access_active_finish(vcpu, intid);
671 mutex_unlock(&vcpu->kvm->arch.config_lock);
674 int vgic_mmio_uaccess_write_sactive(struct kvm_vcpu *vcpu,
675 gpa_t addr, unsigned int len,
678 __vgic_mmio_write_sactive(vcpu, addr, len, val);
682 unsigned long vgic_mmio_read_priority(struct kvm_vcpu *vcpu,
683 gpa_t addr, unsigned int len)
685 u32 intid = VGIC_ADDR_TO_INTID(addr, 8);
689 for (i = 0; i < len; i++) {
690 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
692 val |= (u64)irq->priority << (i * 8);
694 vgic_put_irq(vcpu->kvm, irq);
701 * We currently don't handle changing the priority of an interrupt that
702 * is already pending on a VCPU. If there is a need for this, we would
703 * need to make this VCPU exit and re-evaluate the priorities, potentially
704 * leading to this interrupt getting presented now to the guest (if it has
705 * been masked by the priority mask before).
707 void vgic_mmio_write_priority(struct kvm_vcpu *vcpu,
708 gpa_t addr, unsigned int len,
711 u32 intid = VGIC_ADDR_TO_INTID(addr, 8);
715 for (i = 0; i < len; i++) {
716 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
718 raw_spin_lock_irqsave(&irq->irq_lock, flags);
719 /* Narrow the priority range to what we actually support */
720 irq->priority = (val >> (i * 8)) & GENMASK(7, 8 - VGIC_PRI_BITS);
721 if (irq->hw && vgic_irq_is_sgi(irq->intid))
722 vgic_update_vsgi(irq);
723 raw_spin_unlock_irqrestore(&irq->irq_lock, flags);
725 vgic_put_irq(vcpu->kvm, irq);
729 unsigned long vgic_mmio_read_config(struct kvm_vcpu *vcpu,
730 gpa_t addr, unsigned int len)
732 u32 intid = VGIC_ADDR_TO_INTID(addr, 2);
736 for (i = 0; i < len * 4; i++) {
737 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
739 if (irq->config == VGIC_CONFIG_EDGE)
740 value |= (2U << (i * 2));
742 vgic_put_irq(vcpu->kvm, irq);
748 void vgic_mmio_write_config(struct kvm_vcpu *vcpu,
749 gpa_t addr, unsigned int len,
752 u32 intid = VGIC_ADDR_TO_INTID(addr, 2);
756 for (i = 0; i < len * 4; i++) {
757 struct vgic_irq *irq;
760 * The configuration cannot be changed for SGIs in general,
761 * for PPIs this is IMPLEMENTATION DEFINED. The arch timer
762 * code relies on PPIs being level triggered, so we also
763 * make them read-only here.
765 if (intid + i < VGIC_NR_PRIVATE_IRQS)
768 irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
769 raw_spin_lock_irqsave(&irq->irq_lock, flags);
771 if (test_bit(i * 2 + 1, &val))
772 irq->config = VGIC_CONFIG_EDGE;
774 irq->config = VGIC_CONFIG_LEVEL;
776 raw_spin_unlock_irqrestore(&irq->irq_lock, flags);
777 vgic_put_irq(vcpu->kvm, irq);
781 u32 vgic_read_irq_line_level_info(struct kvm_vcpu *vcpu, u32 intid)
785 int nr_irqs = vcpu->kvm->arch.vgic.nr_spis + VGIC_NR_PRIVATE_IRQS;
787 for (i = 0; i < 32; i++) {
788 struct vgic_irq *irq;
790 if ((intid + i) < VGIC_NR_SGIS || (intid + i) >= nr_irqs)
793 irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
794 if (irq->config == VGIC_CONFIG_LEVEL && irq->line_level)
797 vgic_put_irq(vcpu->kvm, irq);
803 void vgic_write_irq_line_level_info(struct kvm_vcpu *vcpu, u32 intid,
807 int nr_irqs = vcpu->kvm->arch.vgic.nr_spis + VGIC_NR_PRIVATE_IRQS;
810 for (i = 0; i < 32; i++) {
811 struct vgic_irq *irq;
814 if ((intid + i) < VGIC_NR_SGIS || (intid + i) >= nr_irqs)
817 irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
820 * Line level is set irrespective of irq type
821 * (level or edge) to avoid dependency that VM should
822 * restore irq config before line level.
824 new_level = !!(val & (1U << i));
825 raw_spin_lock_irqsave(&irq->irq_lock, flags);
826 irq->line_level = new_level;
828 vgic_queue_irq_unlock(vcpu->kvm, irq, flags);
830 raw_spin_unlock_irqrestore(&irq->irq_lock, flags);
832 vgic_put_irq(vcpu->kvm, irq);
836 static int match_region(const void *key, const void *elt)
838 const unsigned int offset = (unsigned long)key;
839 const struct vgic_register_region *region = elt;
841 if (offset < region->reg_offset)
844 if (offset >= region->reg_offset + region->len)
850 const struct vgic_register_region *
851 vgic_find_mmio_region(const struct vgic_register_region *regions,
852 int nr_regions, unsigned int offset)
854 return bsearch((void *)(uintptr_t)offset, regions, nr_regions,
855 sizeof(regions[0]), match_region);
858 void vgic_set_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr)
860 if (kvm_vgic_global_state.type == VGIC_V2)
861 vgic_v2_set_vmcr(vcpu, vmcr);
863 vgic_v3_set_vmcr(vcpu, vmcr);
866 void vgic_get_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr)
868 if (kvm_vgic_global_state.type == VGIC_V2)
869 vgic_v2_get_vmcr(vcpu, vmcr);
871 vgic_v3_get_vmcr(vcpu, vmcr);
875 * kvm_mmio_read_buf() returns a value in a format where it can be converted
876 * to a byte array and be directly observed as the guest wanted it to appear
877 * in memory if it had done the store itself, which is LE for the GIC, as the
878 * guest knows the GIC is always LE.
880 * We convert this value to the CPUs native format to deal with it as a data
883 unsigned long vgic_data_mmio_bus_to_host(const void *val, unsigned int len)
885 unsigned long data = kvm_mmio_read_buf(val, len);
891 return le16_to_cpu(data);
893 return le32_to_cpu(data);
895 return le64_to_cpu(data);
900 * kvm_mmio_write_buf() expects a value in a format such that if converted to
901 * a byte array it is observed as the guest would see it if it could perform
902 * the load directly. Since the GIC is LE, and the guest knows this, the
903 * guest expects a value in little endian format.
905 * We convert the data value from the CPUs native format to LE so that the
906 * value is returned in the proper format.
908 void vgic_data_host_to_mmio_bus(void *buf, unsigned int len,
915 data = cpu_to_le16(data);
918 data = cpu_to_le32(data);
921 data = cpu_to_le64(data);
924 kvm_mmio_write_buf(buf, len, data);
928 struct vgic_io_device *kvm_to_vgic_iodev(const struct kvm_io_device *dev)
930 return container_of(dev, struct vgic_io_device, dev);
933 static bool check_region(const struct kvm *kvm,
934 const struct vgic_register_region *region,
937 int flags, nr_irqs = kvm->arch.vgic.nr_spis + VGIC_NR_PRIVATE_IRQS;
941 flags = VGIC_ACCESS_8bit;
944 flags = VGIC_ACCESS_32bit;
947 flags = VGIC_ACCESS_64bit;
953 if ((region->access_flags & flags) && IS_ALIGNED(addr, len)) {
954 if (!region->bits_per_irq)
957 /* Do we access a non-allocated IRQ? */
958 return VGIC_ADDR_TO_INTID(addr, region->bits_per_irq) < nr_irqs;
964 const struct vgic_register_region *
965 vgic_get_mmio_region(struct kvm_vcpu *vcpu, struct vgic_io_device *iodev,
968 const struct vgic_register_region *region;
970 region = vgic_find_mmio_region(iodev->regions, iodev->nr_regions,
971 addr - iodev->base_addr);
972 if (!region || !check_region(vcpu->kvm, region, addr, len))
978 static int vgic_uaccess_read(struct kvm_vcpu *vcpu, struct vgic_io_device *iodev,
979 gpa_t addr, u32 *val)
981 const struct vgic_register_region *region;
982 struct kvm_vcpu *r_vcpu;
984 region = vgic_get_mmio_region(vcpu, iodev, addr, sizeof(u32));
990 r_vcpu = iodev->redist_vcpu ? iodev->redist_vcpu : vcpu;
991 if (region->uaccess_read)
992 *val = region->uaccess_read(r_vcpu, addr, sizeof(u32));
994 *val = region->read(r_vcpu, addr, sizeof(u32));
999 static int vgic_uaccess_write(struct kvm_vcpu *vcpu, struct vgic_io_device *iodev,
1000 gpa_t addr, const u32 *val)
1002 const struct vgic_register_region *region;
1003 struct kvm_vcpu *r_vcpu;
1005 region = vgic_get_mmio_region(vcpu, iodev, addr, sizeof(u32));
1009 r_vcpu = iodev->redist_vcpu ? iodev->redist_vcpu : vcpu;
1010 if (region->uaccess_write)
1011 return region->uaccess_write(r_vcpu, addr, sizeof(u32), *val);
1013 region->write(r_vcpu, addr, sizeof(u32), *val);
1018 * Userland access to VGIC registers.
1020 int vgic_uaccess(struct kvm_vcpu *vcpu, struct vgic_io_device *dev,
1021 bool is_write, int offset, u32 *val)
1024 return vgic_uaccess_write(vcpu, dev, offset, val);
1026 return vgic_uaccess_read(vcpu, dev, offset, val);
1029 static int dispatch_mmio_read(struct kvm_vcpu *vcpu, struct kvm_io_device *dev,
1030 gpa_t addr, int len, void *val)
1032 struct vgic_io_device *iodev = kvm_to_vgic_iodev(dev);
1033 const struct vgic_register_region *region;
1034 unsigned long data = 0;
1036 region = vgic_get_mmio_region(vcpu, iodev, addr, len);
1038 memset(val, 0, len);
1042 switch (iodev->iodev_type) {
1044 data = region->read(vcpu, addr, len);
1047 data = region->read(vcpu, addr, len);
1050 data = region->read(iodev->redist_vcpu, addr, len);
1053 data = region->its_read(vcpu->kvm, iodev->its, addr, len);
1057 vgic_data_host_to_mmio_bus(val, len, data);
1061 static int dispatch_mmio_write(struct kvm_vcpu *vcpu, struct kvm_io_device *dev,
1062 gpa_t addr, int len, const void *val)
1064 struct vgic_io_device *iodev = kvm_to_vgic_iodev(dev);
1065 const struct vgic_register_region *region;
1066 unsigned long data = vgic_data_mmio_bus_to_host(val, len);
1068 region = vgic_get_mmio_region(vcpu, iodev, addr, len);
1072 switch (iodev->iodev_type) {
1074 region->write(vcpu, addr, len, data);
1077 region->write(vcpu, addr, len, data);
1080 region->write(iodev->redist_vcpu, addr, len, data);
1083 region->its_write(vcpu->kvm, iodev->its, addr, len, data);
1090 const struct kvm_io_device_ops kvm_io_gic_ops = {
1091 .read = dispatch_mmio_read,
1092 .write = dispatch_mmio_write,
1095 int vgic_register_dist_iodev(struct kvm *kvm, gpa_t dist_base_address,
1096 enum vgic_type type)
1098 struct vgic_io_device *io_device = &kvm->arch.vgic.dist_iodev;
1103 len = vgic_v2_init_dist_iodev(io_device);
1106 len = vgic_v3_init_dist_iodev(io_device);
1112 io_device->base_addr = dist_base_address;
1113 io_device->iodev_type = IODEV_DIST;
1114 io_device->redist_vcpu = NULL;
1116 return kvm_io_bus_register_dev(kvm, KVM_MMIO_BUS, dist_base_address,
1117 len, &io_device->dev);