1 // SPDX-License-Identifier: GPL-2.0-only
3 * VGICv3 MMIO handling functions
6 #include <linux/bitfield.h>
7 #include <linux/irqchip/arm-gic-v3.h>
9 #include <linux/kvm_host.h>
10 #include <linux/interrupt.h>
11 #include <kvm/iodev.h>
12 #include <kvm/arm_vgic.h>
14 #include <asm/kvm_emulate.h>
15 #include <asm/kvm_arm.h>
16 #include <asm/kvm_mmu.h>
19 #include "vgic-mmio.h"
21 /* extract @num bytes at @offset bytes offset in data */
22 unsigned long extract_bytes(u64 data, unsigned int offset,
25 return (data >> (offset * 8)) & GENMASK_ULL(num * 8 - 1, 0);
28 /* allows updates of any half of a 64-bit register (or the whole thing) */
29 u64 update_64bit_reg(u64 reg, unsigned int offset, unsigned int len,
32 int lower = (offset & 4) * 8;
33 int upper = lower + 8 * len - 1;
35 reg &= ~GENMASK_ULL(upper, lower);
36 val &= GENMASK_ULL(len * 8 - 1, 0);
38 return reg | ((u64)val << lower);
41 bool vgic_has_its(struct kvm *kvm)
43 struct vgic_dist *dist = &kvm->arch.vgic;
45 if (dist->vgic_model != KVM_DEV_TYPE_ARM_VGIC_V3)
51 bool vgic_supports_direct_msis(struct kvm *kvm)
53 return (kvm_vgic_global_state.has_gicv4_1 ||
54 (kvm_vgic_global_state.has_gicv4 && vgic_has_its(kvm)));
58 * The Revision field in the IIDR have the following meanings:
60 * Revision 2: Interrupt groups are guest-configurable and signaled using
61 * their configured groups.
64 static unsigned long vgic_mmio_read_v3_misc(struct kvm_vcpu *vcpu,
65 gpa_t addr, unsigned int len)
67 struct vgic_dist *vgic = &vcpu->kvm->arch.vgic;
70 switch (addr & 0x0c) {
73 value |= GICD_CTLR_ENABLE_SS_G1;
74 value |= GICD_CTLR_ARE_NS | GICD_CTLR_DS;
76 value |= GICD_CTLR_nASSGIreq;
79 value = vgic->nr_spis + VGIC_NR_PRIVATE_IRQS;
80 value = (value >> 5) - 1;
81 if (vgic_has_its(vcpu->kvm)) {
82 value |= (INTERRUPT_ID_BITS_ITS - 1) << 19;
83 value |= GICD_TYPER_LPIS;
85 value |= (INTERRUPT_ID_BITS_SPIS - 1) << 19;
89 if (kvm_vgic_global_state.has_gicv4_1 && gic_cpuif_has_vsgi())
90 value = GICD_TYPER2_nASSGIcap;
93 value = (PRODUCT_ID_KVM << GICD_IIDR_PRODUCT_ID_SHIFT) |
94 (vgic->implementation_rev << GICD_IIDR_REVISION_SHIFT) |
95 (IMPLEMENTER_ARM << GICD_IIDR_IMPLEMENTER_SHIFT);
104 static void vgic_mmio_write_v3_misc(struct kvm_vcpu *vcpu,
105 gpa_t addr, unsigned int len,
108 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
110 switch (addr & 0x0c) {
112 bool was_enabled, is_hwsgi;
114 mutex_lock(&vcpu->kvm->arch.config_lock);
116 was_enabled = dist->enabled;
117 is_hwsgi = dist->nassgireq;
119 dist->enabled = val & GICD_CTLR_ENABLE_SS_G1;
121 /* Not a GICv4.1? No HW SGIs */
122 if (!kvm_vgic_global_state.has_gicv4_1 || !gic_cpuif_has_vsgi())
123 val &= ~GICD_CTLR_nASSGIreq;
125 /* Dist stays enabled? nASSGIreq is RO */
126 if (was_enabled && dist->enabled) {
127 val &= ~GICD_CTLR_nASSGIreq;
128 val |= FIELD_PREP(GICD_CTLR_nASSGIreq, is_hwsgi);
131 /* Switching HW SGIs? */
132 dist->nassgireq = val & GICD_CTLR_nASSGIreq;
133 if (is_hwsgi != dist->nassgireq)
134 vgic_v4_configure_vsgis(vcpu->kvm);
136 if (kvm_vgic_global_state.has_gicv4_1 &&
137 was_enabled != dist->enabled)
138 kvm_make_all_cpus_request(vcpu->kvm, KVM_REQ_RELOAD_GICv4);
139 else if (!was_enabled && dist->enabled)
140 vgic_kick_vcpus(vcpu->kvm);
142 mutex_unlock(&vcpu->kvm->arch.config_lock);
148 /* This is at best for documentation purposes... */
153 static int vgic_mmio_uaccess_write_v3_misc(struct kvm_vcpu *vcpu,
154 gpa_t addr, unsigned int len,
157 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
160 switch (addr & 0x0c) {
162 if (val != vgic_mmio_read_v3_misc(vcpu, addr, len))
166 reg = vgic_mmio_read_v3_misc(vcpu, addr, len);
167 if ((reg ^ val) & ~GICD_IIDR_REVISION_MASK)
170 reg = FIELD_GET(GICD_IIDR_REVISION_MASK, reg);
172 case KVM_VGIC_IMP_REV_2:
173 case KVM_VGIC_IMP_REV_3:
174 dist->implementation_rev = reg;
180 /* Not a GICv4.1? No HW SGIs */
181 if (!kvm_vgic_global_state.has_gicv4_1)
182 val &= ~GICD_CTLR_nASSGIreq;
184 dist->enabled = val & GICD_CTLR_ENABLE_SS_G1;
185 dist->nassgireq = val & GICD_CTLR_nASSGIreq;
189 vgic_mmio_write_v3_misc(vcpu, addr, len, val);
193 static unsigned long vgic_mmio_read_irouter(struct kvm_vcpu *vcpu,
194 gpa_t addr, unsigned int len)
196 int intid = VGIC_ADDR_TO_INTID(addr, 64);
197 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, NULL, intid);
198 unsigned long ret = 0;
203 /* The upper word is RAZ for us. */
205 ret = extract_bytes(READ_ONCE(irq->mpidr), addr & 7, len);
207 vgic_put_irq(vcpu->kvm, irq);
211 static void vgic_mmio_write_irouter(struct kvm_vcpu *vcpu,
212 gpa_t addr, unsigned int len,
215 int intid = VGIC_ADDR_TO_INTID(addr, 64);
216 struct vgic_irq *irq;
219 /* The upper word is WI for us since we don't implement Aff3. */
223 irq = vgic_get_irq(vcpu->kvm, NULL, intid);
228 raw_spin_lock_irqsave(&irq->irq_lock, flags);
230 /* We only care about and preserve Aff0, Aff1 and Aff2. */
231 irq->mpidr = val & GENMASK(23, 0);
232 irq->target_vcpu = kvm_mpidr_to_vcpu(vcpu->kvm, irq->mpidr);
234 raw_spin_unlock_irqrestore(&irq->irq_lock, flags);
235 vgic_put_irq(vcpu->kvm, irq);
238 bool vgic_lpis_enabled(struct kvm_vcpu *vcpu)
240 struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
242 return atomic_read(&vgic_cpu->ctlr) == GICR_CTLR_ENABLE_LPIS;
245 static unsigned long vgic_mmio_read_v3r_ctlr(struct kvm_vcpu *vcpu,
246 gpa_t addr, unsigned int len)
248 struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
251 val = atomic_read(&vgic_cpu->ctlr);
252 if (vgic_get_implementation_rev(vcpu) >= KVM_VGIC_IMP_REV_3)
253 val |= GICR_CTLR_IR | GICR_CTLR_CES;
258 static void vgic_mmio_write_v3r_ctlr(struct kvm_vcpu *vcpu,
259 gpa_t addr, unsigned int len,
262 struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
265 if (!vgic_has_its(vcpu->kvm))
268 if (!(val & GICR_CTLR_ENABLE_LPIS)) {
270 * Don't disable if RWP is set, as there already an
271 * ongoing disable. Funky guest...
273 ctlr = atomic_cmpxchg_acquire(&vgic_cpu->ctlr,
274 GICR_CTLR_ENABLE_LPIS,
276 if (ctlr != GICR_CTLR_ENABLE_LPIS)
279 vgic_flush_pending_lpis(vcpu);
280 vgic_its_invalidate_cache(vcpu->kvm);
281 atomic_set_release(&vgic_cpu->ctlr, 0);
283 ctlr = atomic_cmpxchg_acquire(&vgic_cpu->ctlr, 0,
284 GICR_CTLR_ENABLE_LPIS);
288 vgic_enable_lpis(vcpu);
292 static bool vgic_mmio_vcpu_rdist_is_last(struct kvm_vcpu *vcpu)
294 struct vgic_dist *vgic = &vcpu->kvm->arch.vgic;
295 struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
296 struct vgic_redist_region *iter, *rdreg = vgic_cpu->rdreg;
301 if (vgic_cpu->rdreg_index < rdreg->free_index - 1) {
303 } else if (rdreg->count && vgic_cpu->rdreg_index == (rdreg->count - 1)) {
304 struct list_head *rd_regions = &vgic->rd_regions;
305 gpa_t end = rdreg->base + rdreg->count * KVM_VGIC_V3_REDIST_SIZE;
308 * the rdist is the last one of the redist region,
309 * check whether there is no other contiguous rdist region
311 list_for_each_entry(iter, rd_regions, list) {
312 if (iter->base == end && iter->free_index > 0)
319 static unsigned long vgic_mmio_read_v3r_typer(struct kvm_vcpu *vcpu,
320 gpa_t addr, unsigned int len)
322 unsigned long mpidr = kvm_vcpu_get_mpidr_aff(vcpu);
323 int target_vcpu_id = vcpu->vcpu_id;
326 value = (u64)(mpidr & GENMASK(23, 0)) << 32;
327 value |= ((target_vcpu_id & 0xffff) << 8);
329 if (vgic_has_its(vcpu->kvm))
330 value |= GICR_TYPER_PLPIS;
332 if (vgic_mmio_vcpu_rdist_is_last(vcpu))
333 value |= GICR_TYPER_LAST;
335 return extract_bytes(value, addr & 7, len);
338 static unsigned long vgic_mmio_read_v3r_iidr(struct kvm_vcpu *vcpu,
339 gpa_t addr, unsigned int len)
341 return (PRODUCT_ID_KVM << 24) | (IMPLEMENTER_ARM << 0);
344 static unsigned long vgic_mmio_read_v3_idregs(struct kvm_vcpu *vcpu,
345 gpa_t addr, unsigned int len)
347 switch (addr & 0xffff) {
349 /* report a GICv3 compliant implementation */
356 static int vgic_v3_uaccess_write_pending(struct kvm_vcpu *vcpu,
357 gpa_t addr, unsigned int len,
360 u32 intid = VGIC_ADDR_TO_INTID(addr, 1);
364 for (i = 0; i < len * 8; i++) {
365 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
367 raw_spin_lock_irqsave(&irq->irq_lock, flags);
368 if (test_bit(i, &val)) {
370 * pending_latch is set irrespective of irq type
371 * (level or edge) to avoid dependency that VM should
372 * restore irq config before pending info.
374 irq->pending_latch = true;
375 vgic_queue_irq_unlock(vcpu->kvm, irq, flags);
377 irq->pending_latch = false;
378 raw_spin_unlock_irqrestore(&irq->irq_lock, flags);
381 vgic_put_irq(vcpu->kvm, irq);
387 /* We want to avoid outer shareable. */
388 u64 vgic_sanitise_shareability(u64 field)
391 case GIC_BASER_OuterShareable:
392 return GIC_BASER_InnerShareable;
398 /* Avoid any inner non-cacheable mapping. */
399 u64 vgic_sanitise_inner_cacheability(u64 field)
402 case GIC_BASER_CACHE_nCnB:
403 case GIC_BASER_CACHE_nC:
404 return GIC_BASER_CACHE_RaWb;
410 /* Non-cacheable or same-as-inner are OK. */
411 u64 vgic_sanitise_outer_cacheability(u64 field)
414 case GIC_BASER_CACHE_SameAsInner:
415 case GIC_BASER_CACHE_nC:
418 return GIC_BASER_CACHE_SameAsInner;
422 u64 vgic_sanitise_field(u64 reg, u64 field_mask, int field_shift,
423 u64 (*sanitise_fn)(u64))
425 u64 field = (reg & field_mask) >> field_shift;
427 field = sanitise_fn(field) << field_shift;
428 return (reg & ~field_mask) | field;
431 #define PROPBASER_RES0_MASK \
432 (GENMASK_ULL(63, 59) | GENMASK_ULL(55, 52) | GENMASK_ULL(6, 5))
433 #define PENDBASER_RES0_MASK \
434 (BIT_ULL(63) | GENMASK_ULL(61, 59) | GENMASK_ULL(55, 52) | \
435 GENMASK_ULL(15, 12) | GENMASK_ULL(6, 0))
437 static u64 vgic_sanitise_pendbaser(u64 reg)
439 reg = vgic_sanitise_field(reg, GICR_PENDBASER_SHAREABILITY_MASK,
440 GICR_PENDBASER_SHAREABILITY_SHIFT,
441 vgic_sanitise_shareability);
442 reg = vgic_sanitise_field(reg, GICR_PENDBASER_INNER_CACHEABILITY_MASK,
443 GICR_PENDBASER_INNER_CACHEABILITY_SHIFT,
444 vgic_sanitise_inner_cacheability);
445 reg = vgic_sanitise_field(reg, GICR_PENDBASER_OUTER_CACHEABILITY_MASK,
446 GICR_PENDBASER_OUTER_CACHEABILITY_SHIFT,
447 vgic_sanitise_outer_cacheability);
449 reg &= ~PENDBASER_RES0_MASK;
454 static u64 vgic_sanitise_propbaser(u64 reg)
456 reg = vgic_sanitise_field(reg, GICR_PROPBASER_SHAREABILITY_MASK,
457 GICR_PROPBASER_SHAREABILITY_SHIFT,
458 vgic_sanitise_shareability);
459 reg = vgic_sanitise_field(reg, GICR_PROPBASER_INNER_CACHEABILITY_MASK,
460 GICR_PROPBASER_INNER_CACHEABILITY_SHIFT,
461 vgic_sanitise_inner_cacheability);
462 reg = vgic_sanitise_field(reg, GICR_PROPBASER_OUTER_CACHEABILITY_MASK,
463 GICR_PROPBASER_OUTER_CACHEABILITY_SHIFT,
464 vgic_sanitise_outer_cacheability);
466 reg &= ~PROPBASER_RES0_MASK;
470 static unsigned long vgic_mmio_read_propbase(struct kvm_vcpu *vcpu,
471 gpa_t addr, unsigned int len)
473 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
475 return extract_bytes(dist->propbaser, addr & 7, len);
478 static void vgic_mmio_write_propbase(struct kvm_vcpu *vcpu,
479 gpa_t addr, unsigned int len,
482 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
483 u64 old_propbaser, propbaser;
485 /* Storing a value with LPIs already enabled is undefined */
486 if (vgic_lpis_enabled(vcpu))
490 old_propbaser = READ_ONCE(dist->propbaser);
491 propbaser = old_propbaser;
492 propbaser = update_64bit_reg(propbaser, addr & 4, len, val);
493 propbaser = vgic_sanitise_propbaser(propbaser);
494 } while (cmpxchg64(&dist->propbaser, old_propbaser,
495 propbaser) != old_propbaser);
498 static unsigned long vgic_mmio_read_pendbase(struct kvm_vcpu *vcpu,
499 gpa_t addr, unsigned int len)
501 struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
502 u64 value = vgic_cpu->pendbaser;
504 value &= ~GICR_PENDBASER_PTZ;
506 return extract_bytes(value, addr & 7, len);
509 static void vgic_mmio_write_pendbase(struct kvm_vcpu *vcpu,
510 gpa_t addr, unsigned int len,
513 struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
514 u64 old_pendbaser, pendbaser;
516 /* Storing a value with LPIs already enabled is undefined */
517 if (vgic_lpis_enabled(vcpu))
521 old_pendbaser = READ_ONCE(vgic_cpu->pendbaser);
522 pendbaser = old_pendbaser;
523 pendbaser = update_64bit_reg(pendbaser, addr & 4, len, val);
524 pendbaser = vgic_sanitise_pendbaser(pendbaser);
525 } while (cmpxchg64(&vgic_cpu->pendbaser, old_pendbaser,
526 pendbaser) != old_pendbaser);
529 static unsigned long vgic_mmio_read_sync(struct kvm_vcpu *vcpu,
530 gpa_t addr, unsigned int len)
532 return !!atomic_read(&vcpu->arch.vgic_cpu.syncr_busy);
535 static void vgic_set_rdist_busy(struct kvm_vcpu *vcpu, bool busy)
538 atomic_inc(&vcpu->arch.vgic_cpu.syncr_busy);
539 smp_mb__after_atomic();
541 smp_mb__before_atomic();
542 atomic_dec(&vcpu->arch.vgic_cpu.syncr_busy);
546 static void vgic_mmio_write_invlpi(struct kvm_vcpu *vcpu,
547 gpa_t addr, unsigned int len,
550 struct vgic_irq *irq;
553 * If the guest wrote only to the upper 32bit part of the
554 * register, drop the write on the floor, as it is only for
555 * vPEs (which we don't support for obvious reasons).
557 * Also discard the access if LPIs are not enabled.
559 if ((addr & 4) || !vgic_lpis_enabled(vcpu))
562 vgic_set_rdist_busy(vcpu, true);
564 irq = vgic_get_irq(vcpu->kvm, NULL, lower_32_bits(val));
566 vgic_its_inv_lpi(vcpu->kvm, irq);
567 vgic_put_irq(vcpu->kvm, irq);
570 vgic_set_rdist_busy(vcpu, false);
573 static void vgic_mmio_write_invall(struct kvm_vcpu *vcpu,
574 gpa_t addr, unsigned int len,
577 /* See vgic_mmio_write_invlpi() for the early return rationale */
578 if ((addr & 4) || !vgic_lpis_enabled(vcpu))
581 vgic_set_rdist_busy(vcpu, true);
582 vgic_its_invall(vcpu);
583 vgic_set_rdist_busy(vcpu, false);
587 * The GICv3 per-IRQ registers are split to control PPIs and SGIs in the
588 * redistributors, while SPIs are covered by registers in the distributor
589 * block. Trying to set private IRQs in this block gets ignored.
590 * We take some special care here to fix the calculation of the register
593 #define REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(off, rd, wr, ur, uw, bpi, acc) \
596 .bits_per_irq = bpi, \
597 .len = (bpi * VGIC_NR_PRIVATE_IRQS) / 8, \
598 .access_flags = acc, \
599 .read = vgic_mmio_read_raz, \
600 .write = vgic_mmio_write_wi, \
602 .reg_offset = off + (bpi * VGIC_NR_PRIVATE_IRQS) / 8, \
603 .bits_per_irq = bpi, \
604 .len = (bpi * (1024 - VGIC_NR_PRIVATE_IRQS)) / 8, \
605 .access_flags = acc, \
608 .uaccess_read = ur, \
609 .uaccess_write = uw, \
612 static const struct vgic_register_region vgic_v3_dist_registers[] = {
613 REGISTER_DESC_WITH_LENGTH_UACCESS(GICD_CTLR,
614 vgic_mmio_read_v3_misc, vgic_mmio_write_v3_misc,
615 NULL, vgic_mmio_uaccess_write_v3_misc,
616 16, VGIC_ACCESS_32bit),
617 REGISTER_DESC_WITH_LENGTH(GICD_STATUSR,
618 vgic_mmio_read_rao, vgic_mmio_write_wi, 4,
620 REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_IGROUPR,
621 vgic_mmio_read_group, vgic_mmio_write_group, NULL, NULL, 1,
623 REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ISENABLER,
624 vgic_mmio_read_enable, vgic_mmio_write_senable,
625 NULL, vgic_uaccess_write_senable, 1,
627 REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ICENABLER,
628 vgic_mmio_read_enable, vgic_mmio_write_cenable,
629 NULL, vgic_uaccess_write_cenable, 1,
631 REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ISPENDR,
632 vgic_mmio_read_pending, vgic_mmio_write_spending,
633 vgic_uaccess_read_pending, vgic_v3_uaccess_write_pending, 1,
635 REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ICPENDR,
636 vgic_mmio_read_pending, vgic_mmio_write_cpending,
637 vgic_mmio_read_raz, vgic_mmio_uaccess_write_wi, 1,
639 REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ISACTIVER,
640 vgic_mmio_read_active, vgic_mmio_write_sactive,
641 vgic_uaccess_read_active, vgic_mmio_uaccess_write_sactive, 1,
643 REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ICACTIVER,
644 vgic_mmio_read_active, vgic_mmio_write_cactive,
645 vgic_uaccess_read_active, vgic_mmio_uaccess_write_cactive,
646 1, VGIC_ACCESS_32bit),
647 REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_IPRIORITYR,
648 vgic_mmio_read_priority, vgic_mmio_write_priority, NULL, NULL,
649 8, VGIC_ACCESS_32bit | VGIC_ACCESS_8bit),
650 REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ITARGETSR,
651 vgic_mmio_read_raz, vgic_mmio_write_wi, NULL, NULL, 8,
652 VGIC_ACCESS_32bit | VGIC_ACCESS_8bit),
653 REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ICFGR,
654 vgic_mmio_read_config, vgic_mmio_write_config, NULL, NULL, 2,
656 REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_IGRPMODR,
657 vgic_mmio_read_raz, vgic_mmio_write_wi, NULL, NULL, 1,
659 REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_IROUTER,
660 vgic_mmio_read_irouter, vgic_mmio_write_irouter, NULL, NULL, 64,
661 VGIC_ACCESS_64bit | VGIC_ACCESS_32bit),
662 REGISTER_DESC_WITH_LENGTH(GICD_IDREGS,
663 vgic_mmio_read_v3_idregs, vgic_mmio_write_wi, 48,
667 static const struct vgic_register_region vgic_v3_rd_registers[] = {
668 /* RD_base registers */
669 REGISTER_DESC_WITH_LENGTH(GICR_CTLR,
670 vgic_mmio_read_v3r_ctlr, vgic_mmio_write_v3r_ctlr, 4,
672 REGISTER_DESC_WITH_LENGTH(GICR_STATUSR,
673 vgic_mmio_read_raz, vgic_mmio_write_wi, 4,
675 REGISTER_DESC_WITH_LENGTH(GICR_IIDR,
676 vgic_mmio_read_v3r_iidr, vgic_mmio_write_wi, 4,
678 REGISTER_DESC_WITH_LENGTH_UACCESS(GICR_TYPER,
679 vgic_mmio_read_v3r_typer, vgic_mmio_write_wi,
680 NULL, vgic_mmio_uaccess_write_wi, 8,
681 VGIC_ACCESS_64bit | VGIC_ACCESS_32bit),
682 REGISTER_DESC_WITH_LENGTH(GICR_WAKER,
683 vgic_mmio_read_raz, vgic_mmio_write_wi, 4,
685 REGISTER_DESC_WITH_LENGTH(GICR_PROPBASER,
686 vgic_mmio_read_propbase, vgic_mmio_write_propbase, 8,
687 VGIC_ACCESS_64bit | VGIC_ACCESS_32bit),
688 REGISTER_DESC_WITH_LENGTH(GICR_PENDBASER,
689 vgic_mmio_read_pendbase, vgic_mmio_write_pendbase, 8,
690 VGIC_ACCESS_64bit | VGIC_ACCESS_32bit),
691 REGISTER_DESC_WITH_LENGTH(GICR_INVLPIR,
692 vgic_mmio_read_raz, vgic_mmio_write_invlpi, 8,
693 VGIC_ACCESS_64bit | VGIC_ACCESS_32bit),
694 REGISTER_DESC_WITH_LENGTH(GICR_INVALLR,
695 vgic_mmio_read_raz, vgic_mmio_write_invall, 8,
696 VGIC_ACCESS_64bit | VGIC_ACCESS_32bit),
697 REGISTER_DESC_WITH_LENGTH(GICR_SYNCR,
698 vgic_mmio_read_sync, vgic_mmio_write_wi, 4,
700 REGISTER_DESC_WITH_LENGTH(GICR_IDREGS,
701 vgic_mmio_read_v3_idregs, vgic_mmio_write_wi, 48,
703 /* SGI_base registers */
704 REGISTER_DESC_WITH_LENGTH(SZ_64K + GICR_IGROUPR0,
705 vgic_mmio_read_group, vgic_mmio_write_group, 4,
707 REGISTER_DESC_WITH_LENGTH_UACCESS(SZ_64K + GICR_ISENABLER0,
708 vgic_mmio_read_enable, vgic_mmio_write_senable,
709 NULL, vgic_uaccess_write_senable, 4,
711 REGISTER_DESC_WITH_LENGTH_UACCESS(SZ_64K + GICR_ICENABLER0,
712 vgic_mmio_read_enable, vgic_mmio_write_cenable,
713 NULL, vgic_uaccess_write_cenable, 4,
715 REGISTER_DESC_WITH_LENGTH_UACCESS(SZ_64K + GICR_ISPENDR0,
716 vgic_mmio_read_pending, vgic_mmio_write_spending,
717 vgic_uaccess_read_pending, vgic_v3_uaccess_write_pending, 4,
719 REGISTER_DESC_WITH_LENGTH_UACCESS(SZ_64K + GICR_ICPENDR0,
720 vgic_mmio_read_pending, vgic_mmio_write_cpending,
721 vgic_mmio_read_raz, vgic_mmio_uaccess_write_wi, 4,
723 REGISTER_DESC_WITH_LENGTH_UACCESS(SZ_64K + GICR_ISACTIVER0,
724 vgic_mmio_read_active, vgic_mmio_write_sactive,
725 vgic_uaccess_read_active, vgic_mmio_uaccess_write_sactive, 4,
727 REGISTER_DESC_WITH_LENGTH_UACCESS(SZ_64K + GICR_ICACTIVER0,
728 vgic_mmio_read_active, vgic_mmio_write_cactive,
729 vgic_uaccess_read_active, vgic_mmio_uaccess_write_cactive, 4,
731 REGISTER_DESC_WITH_LENGTH(SZ_64K + GICR_IPRIORITYR0,
732 vgic_mmio_read_priority, vgic_mmio_write_priority, 32,
733 VGIC_ACCESS_32bit | VGIC_ACCESS_8bit),
734 REGISTER_DESC_WITH_LENGTH(SZ_64K + GICR_ICFGR0,
735 vgic_mmio_read_config, vgic_mmio_write_config, 8,
737 REGISTER_DESC_WITH_LENGTH(SZ_64K + GICR_IGRPMODR0,
738 vgic_mmio_read_raz, vgic_mmio_write_wi, 4,
740 REGISTER_DESC_WITH_LENGTH(SZ_64K + GICR_NSACR,
741 vgic_mmio_read_raz, vgic_mmio_write_wi, 4,
745 unsigned int vgic_v3_init_dist_iodev(struct vgic_io_device *dev)
747 dev->regions = vgic_v3_dist_registers;
748 dev->nr_regions = ARRAY_SIZE(vgic_v3_dist_registers);
750 kvm_iodevice_init(&dev->dev, &kvm_io_gic_ops);
756 * vgic_register_redist_iodev - register a single redist iodev
757 * @vcpu: The VCPU to which the redistributor belongs
759 * Register a KVM iodev for this VCPU's redistributor using the address
762 * Return 0 on success, -ERRNO otherwise.
764 int vgic_register_redist_iodev(struct kvm_vcpu *vcpu)
766 struct kvm *kvm = vcpu->kvm;
767 struct vgic_dist *vgic = &kvm->arch.vgic;
768 struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
769 struct vgic_io_device *rd_dev = &vcpu->arch.vgic_cpu.rd_iodev;
770 struct vgic_redist_region *rdreg;
774 lockdep_assert_held(&kvm->slots_lock);
775 mutex_lock(&kvm->arch.config_lock);
777 if (!IS_VGIC_ADDR_UNDEF(vgic_cpu->rd_iodev.base_addr))
781 * We may be creating VCPUs before having set the base address for the
782 * redistributor region, in which case we will come back to this
783 * function for all VCPUs when the base address is set. Just return
784 * without doing any work for now.
786 rdreg = vgic_v3_rdist_free_slot(&vgic->rd_regions);
790 if (!vgic_v3_check_base(kvm)) {
795 vgic_cpu->rdreg = rdreg;
796 vgic_cpu->rdreg_index = rdreg->free_index;
798 rd_base = rdreg->base + rdreg->free_index * KVM_VGIC_V3_REDIST_SIZE;
800 kvm_iodevice_init(&rd_dev->dev, &kvm_io_gic_ops);
801 rd_dev->base_addr = rd_base;
802 rd_dev->iodev_type = IODEV_REDIST;
803 rd_dev->regions = vgic_v3_rd_registers;
804 rd_dev->nr_regions = ARRAY_SIZE(vgic_v3_rd_registers);
805 rd_dev->redist_vcpu = vcpu;
807 mutex_unlock(&kvm->arch.config_lock);
809 ret = kvm_io_bus_register_dev(kvm, KVM_MMIO_BUS, rd_base,
810 2 * SZ_64K, &rd_dev->dev);
814 /* Protected by slots_lock */
819 mutex_unlock(&kvm->arch.config_lock);
823 void vgic_unregister_redist_iodev(struct kvm_vcpu *vcpu)
825 struct vgic_io_device *rd_dev = &vcpu->arch.vgic_cpu.rd_iodev;
827 kvm_io_bus_unregister_dev(vcpu->kvm, KVM_MMIO_BUS, &rd_dev->dev);
830 static int vgic_register_all_redist_iodevs(struct kvm *kvm)
832 struct kvm_vcpu *vcpu;
836 lockdep_assert_held(&kvm->slots_lock);
838 kvm_for_each_vcpu(c, vcpu, kvm) {
839 ret = vgic_register_redist_iodev(vcpu);
845 /* The current c failed, so iterate over the previous ones. */
848 for (i = 0; i < c; i++) {
849 vcpu = kvm_get_vcpu(kvm, i);
850 vgic_unregister_redist_iodev(vcpu);
858 * vgic_v3_alloc_redist_region - Allocate a new redistributor region
860 * Performs various checks before inserting the rdist region in the list.
861 * Those tests depend on whether the size of the rdist region is known
862 * (ie. count != 0). The list is sorted by rdist region index.
865 * @index: redist region index
866 * @base: base of the new rdist region
867 * @count: number of redistributors the region is made of (0 in the old style
868 * single region, whose size is induced from the number of vcpus)
870 * Return 0 on success, < 0 otherwise
872 static int vgic_v3_alloc_redist_region(struct kvm *kvm, uint32_t index,
873 gpa_t base, uint32_t count)
875 struct vgic_dist *d = &kvm->arch.vgic;
876 struct vgic_redist_region *rdreg;
877 struct list_head *rd_regions = &d->rd_regions;
878 int nr_vcpus = atomic_read(&kvm->online_vcpus);
879 size_t size = count ? count * KVM_VGIC_V3_REDIST_SIZE
880 : nr_vcpus * KVM_VGIC_V3_REDIST_SIZE;
883 /* cross the end of memory ? */
884 if (base + size < base)
887 if (list_empty(rd_regions)) {
891 rdreg = list_last_entry(rd_regions,
892 struct vgic_redist_region, list);
894 /* Don't mix single region and discrete redist regions */
895 if (!count && rdreg->count)
901 if (index != rdreg->index + 1)
906 * For legacy single-region redistributor regions (!count),
907 * check that the redistributor region does not overlap with the
908 * distributor's address space.
910 if (!count && !IS_VGIC_ADDR_UNDEF(d->vgic_dist_base) &&
911 vgic_dist_overlap(kvm, base, size))
914 /* collision with any other rdist region? */
915 if (vgic_v3_rdist_overlap(kvm, base, size))
918 rdreg = kzalloc(sizeof(*rdreg), GFP_KERNEL_ACCOUNT);
922 rdreg->base = VGIC_ADDR_UNDEF;
924 ret = vgic_check_iorange(kvm, rdreg->base, base, SZ_64K, size);
929 rdreg->count = count;
930 rdreg->free_index = 0;
931 rdreg->index = index;
933 list_add_tail(&rdreg->list, rd_regions);
940 void vgic_v3_free_redist_region(struct vgic_redist_region *rdreg)
942 list_del(&rdreg->list);
946 int vgic_v3_set_redist_base(struct kvm *kvm, u32 index, u64 addr, u32 count)
950 mutex_lock(&kvm->arch.config_lock);
951 ret = vgic_v3_alloc_redist_region(kvm, index, addr, count);
952 mutex_unlock(&kvm->arch.config_lock);
957 * Register iodevs for each existing VCPU. Adding more VCPUs
958 * afterwards will register the iodevs when needed.
960 ret = vgic_register_all_redist_iodevs(kvm);
962 struct vgic_redist_region *rdreg;
964 mutex_lock(&kvm->arch.config_lock);
965 rdreg = vgic_v3_rdist_region_from_index(kvm, index);
966 vgic_v3_free_redist_region(rdreg);
967 mutex_unlock(&kvm->arch.config_lock);
974 int vgic_v3_has_attr_regs(struct kvm_device *dev, struct kvm_device_attr *attr)
976 const struct vgic_register_region *region;
977 struct vgic_io_device iodev;
978 struct vgic_reg_attr reg_attr;
979 struct kvm_vcpu *vcpu;
983 ret = vgic_v3_parse_attr(dev, attr, ®_attr);
987 vcpu = reg_attr.vcpu;
988 addr = reg_attr.addr;
990 switch (attr->group) {
991 case KVM_DEV_ARM_VGIC_GRP_DIST_REGS:
992 iodev.regions = vgic_v3_dist_registers;
993 iodev.nr_regions = ARRAY_SIZE(vgic_v3_dist_registers);
996 case KVM_DEV_ARM_VGIC_GRP_REDIST_REGS:{
997 iodev.regions = vgic_v3_rd_registers;
998 iodev.nr_regions = ARRAY_SIZE(vgic_v3_rd_registers);
1002 case KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS:
1003 return vgic_v3_has_cpu_sysregs_attr(vcpu, attr);
1008 /* We only support aligned 32-bit accesses. */
1012 region = vgic_get_mmio_region(vcpu, &iodev, addr, sizeof(u32));
1020 * The ICC_SGI* registers encode the affinity differently from the MPIDR,
1021 * so provide a wrapper to use the existing defines to isolate a certain
1024 #define SGI_AFFINITY_LEVEL(reg, level) \
1025 ((((reg) & ICC_SGI1R_AFFINITY_## level ##_MASK) \
1026 >> ICC_SGI1R_AFFINITY_## level ##_SHIFT) << MPIDR_LEVEL_SHIFT(level))
1028 static void vgic_v3_queue_sgi(struct kvm_vcpu *vcpu, u32 sgi, bool allow_group1)
1030 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, sgi);
1031 unsigned long flags;
1033 raw_spin_lock_irqsave(&irq->irq_lock, flags);
1036 * An access targeting Group0 SGIs can only generate
1037 * those, while an access targeting Group1 SGIs can
1038 * generate interrupts of either group.
1040 if (!irq->group || allow_group1) {
1042 irq->pending_latch = true;
1043 vgic_queue_irq_unlock(vcpu->kvm, irq, flags);
1045 /* HW SGI? Ask the GIC to inject it */
1047 err = irq_set_irqchip_state(irq->host_irq,
1048 IRQCHIP_STATE_PENDING,
1050 WARN_RATELIMIT(err, "IRQ %d", irq->host_irq);
1051 raw_spin_unlock_irqrestore(&irq->irq_lock, flags);
1054 raw_spin_unlock_irqrestore(&irq->irq_lock, flags);
1057 vgic_put_irq(vcpu->kvm, irq);
1061 * vgic_v3_dispatch_sgi - handle SGI requests from VCPUs
1062 * @vcpu: The VCPU requesting a SGI
1063 * @reg: The value written into ICC_{ASGI1,SGI0,SGI1}R by that VCPU
1064 * @allow_group1: Does the sysreg access allow generation of G1 SGIs
1066 * With GICv3 (and ARE=1) CPUs trigger SGIs by writing to a system register.
1067 * This will trap in sys_regs.c and call this function.
1068 * This ICC_SGI1R_EL1 register contains the upper three affinity levels of the
1069 * target processors as well as a bitmask of 16 Aff0 CPUs.
1071 * If the interrupt routing mode bit is not set, we iterate over the Aff0
1072 * bits and signal the VCPUs matching the provided Aff{3,2,1}.
1074 * If this bit is set, we signal all, but not the calling VCPU.
1076 void vgic_v3_dispatch_sgi(struct kvm_vcpu *vcpu, u64 reg, bool allow_group1)
1078 struct kvm *kvm = vcpu->kvm;
1079 struct kvm_vcpu *c_vcpu;
1080 unsigned long target_cpus;
1085 sgi = FIELD_GET(ICC_SGI1R_SGI_ID_MASK, reg);
1088 if (unlikely(reg & BIT_ULL(ICC_SGI1R_IRQ_ROUTING_MODE_BIT))) {
1089 kvm_for_each_vcpu(c, c_vcpu, kvm) {
1090 /* Don't signal the calling VCPU */
1094 vgic_v3_queue_sgi(c_vcpu, sgi, allow_group1);
1100 /* We iterate over affinities to find the corresponding vcpus */
1101 mpidr = SGI_AFFINITY_LEVEL(reg, 3);
1102 mpidr |= SGI_AFFINITY_LEVEL(reg, 2);
1103 mpidr |= SGI_AFFINITY_LEVEL(reg, 1);
1104 target_cpus = FIELD_GET(ICC_SGI1R_TARGET_LIST_MASK, reg);
1106 for_each_set_bit(aff0, &target_cpus, hweight_long(ICC_SGI1R_TARGET_LIST_MASK)) {
1107 c_vcpu = kvm_mpidr_to_vcpu(kvm, mpidr | aff0);
1109 vgic_v3_queue_sgi(c_vcpu, sgi, allow_group1);
1113 int vgic_v3_dist_uaccess(struct kvm_vcpu *vcpu, bool is_write,
1114 int offset, u32 *val)
1116 struct vgic_io_device dev = {
1117 .regions = vgic_v3_dist_registers,
1118 .nr_regions = ARRAY_SIZE(vgic_v3_dist_registers),
1121 return vgic_uaccess(vcpu, &dev, is_write, offset, val);
1124 int vgic_v3_redist_uaccess(struct kvm_vcpu *vcpu, bool is_write,
1125 int offset, u32 *val)
1127 struct vgic_io_device rd_dev = {
1128 .regions = vgic_v3_rd_registers,
1129 .nr_regions = ARRAY_SIZE(vgic_v3_rd_registers),
1132 return vgic_uaccess(vcpu, &rd_dev, is_write, offset, val);
1135 int vgic_v3_line_level_info_uaccess(struct kvm_vcpu *vcpu, bool is_write,
1136 u32 intid, u32 *val)
1142 vgic_write_irq_line_level_info(vcpu, intid, *val);
1144 *val = vgic_read_irq_line_level_info(vcpu, intid);