1 // SPDX-License-Identifier: GPL-2.0-only
3 * VGICv3 MMIO handling functions
6 #include <linux/bitfield.h>
7 #include <linux/irqchip/arm-gic-v3.h>
9 #include <linux/kvm_host.h>
10 #include <linux/interrupt.h>
11 #include <kvm/iodev.h>
12 #include <kvm/arm_vgic.h>
14 #include <asm/kvm_emulate.h>
15 #include <asm/kvm_arm.h>
16 #include <asm/kvm_mmu.h>
19 #include "vgic-mmio.h"
21 /* extract @num bytes at @offset bytes offset in data */
22 unsigned long extract_bytes(u64 data, unsigned int offset,
25 return (data >> (offset * 8)) & GENMASK_ULL(num * 8 - 1, 0);
28 /* allows updates of any half of a 64-bit register (or the whole thing) */
29 u64 update_64bit_reg(u64 reg, unsigned int offset, unsigned int len,
32 int lower = (offset & 4) * 8;
33 int upper = lower + 8 * len - 1;
35 reg &= ~GENMASK_ULL(upper, lower);
36 val &= GENMASK_ULL(len * 8 - 1, 0);
38 return reg | ((u64)val << lower);
41 bool vgic_has_its(struct kvm *kvm)
43 struct vgic_dist *dist = &kvm->arch.vgic;
45 if (dist->vgic_model != KVM_DEV_TYPE_ARM_VGIC_V3)
51 bool vgic_supports_direct_msis(struct kvm *kvm)
53 return (kvm_vgic_global_state.has_gicv4_1 ||
54 (kvm_vgic_global_state.has_gicv4 && vgic_has_its(kvm)));
58 * The Revision field in the IIDR have the following meanings:
60 * Revision 2: Interrupt groups are guest-configurable and signaled using
61 * their configured groups.
64 static unsigned long vgic_mmio_read_v3_misc(struct kvm_vcpu *vcpu,
65 gpa_t addr, unsigned int len)
67 struct vgic_dist *vgic = &vcpu->kvm->arch.vgic;
70 switch (addr & 0x0c) {
73 value |= GICD_CTLR_ENABLE_SS_G1;
74 value |= GICD_CTLR_ARE_NS | GICD_CTLR_DS;
76 value |= GICD_CTLR_nASSGIreq;
79 value = vgic->nr_spis + VGIC_NR_PRIVATE_IRQS;
80 value = (value >> 5) - 1;
81 if (vgic_has_its(vcpu->kvm)) {
82 value |= (INTERRUPT_ID_BITS_ITS - 1) << 19;
83 value |= GICD_TYPER_LPIS;
85 value |= (INTERRUPT_ID_BITS_SPIS - 1) << 19;
89 if (kvm_vgic_global_state.has_gicv4_1 && gic_cpuif_has_vsgi())
90 value = GICD_TYPER2_nASSGIcap;
93 value = (PRODUCT_ID_KVM << GICD_IIDR_PRODUCT_ID_SHIFT) |
94 (vgic->implementation_rev << GICD_IIDR_REVISION_SHIFT) |
95 (IMPLEMENTER_ARM << GICD_IIDR_IMPLEMENTER_SHIFT);
104 static void vgic_mmio_write_v3_misc(struct kvm_vcpu *vcpu,
105 gpa_t addr, unsigned int len,
108 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
110 switch (addr & 0x0c) {
112 bool was_enabled, is_hwsgi;
114 mutex_lock(&vcpu->kvm->lock);
116 was_enabled = dist->enabled;
117 is_hwsgi = dist->nassgireq;
119 dist->enabled = val & GICD_CTLR_ENABLE_SS_G1;
121 /* Not a GICv4.1? No HW SGIs */
122 if (!kvm_vgic_global_state.has_gicv4_1 || !gic_cpuif_has_vsgi())
123 val &= ~GICD_CTLR_nASSGIreq;
125 /* Dist stays enabled? nASSGIreq is RO */
126 if (was_enabled && dist->enabled) {
127 val &= ~GICD_CTLR_nASSGIreq;
128 val |= FIELD_PREP(GICD_CTLR_nASSGIreq, is_hwsgi);
131 /* Switching HW SGIs? */
132 dist->nassgireq = val & GICD_CTLR_nASSGIreq;
133 if (is_hwsgi != dist->nassgireq)
134 vgic_v4_configure_vsgis(vcpu->kvm);
136 if (kvm_vgic_global_state.has_gicv4_1 &&
137 was_enabled != dist->enabled)
138 kvm_make_all_cpus_request(vcpu->kvm, KVM_REQ_RELOAD_GICv4);
139 else if (!was_enabled && dist->enabled)
140 vgic_kick_vcpus(vcpu->kvm);
142 mutex_unlock(&vcpu->kvm->lock);
148 /* This is at best for documentation purposes... */
153 static int vgic_mmio_uaccess_write_v3_misc(struct kvm_vcpu *vcpu,
154 gpa_t addr, unsigned int len,
157 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
159 switch (addr & 0x0c) {
162 if (val != vgic_mmio_read_v3_misc(vcpu, addr, len))
166 /* Not a GICv4.1? No HW SGIs */
167 if (!kvm_vgic_global_state.has_gicv4_1)
168 val &= ~GICD_CTLR_nASSGIreq;
170 dist->enabled = val & GICD_CTLR_ENABLE_SS_G1;
171 dist->nassgireq = val & GICD_CTLR_nASSGIreq;
175 vgic_mmio_write_v3_misc(vcpu, addr, len, val);
179 static unsigned long vgic_mmio_read_irouter(struct kvm_vcpu *vcpu,
180 gpa_t addr, unsigned int len)
182 int intid = VGIC_ADDR_TO_INTID(addr, 64);
183 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, NULL, intid);
184 unsigned long ret = 0;
189 /* The upper word is RAZ for us. */
191 ret = extract_bytes(READ_ONCE(irq->mpidr), addr & 7, len);
193 vgic_put_irq(vcpu->kvm, irq);
197 static void vgic_mmio_write_irouter(struct kvm_vcpu *vcpu,
198 gpa_t addr, unsigned int len,
201 int intid = VGIC_ADDR_TO_INTID(addr, 64);
202 struct vgic_irq *irq;
205 /* The upper word is WI for us since we don't implement Aff3. */
209 irq = vgic_get_irq(vcpu->kvm, NULL, intid);
214 raw_spin_lock_irqsave(&irq->irq_lock, flags);
216 /* We only care about and preserve Aff0, Aff1 and Aff2. */
217 irq->mpidr = val & GENMASK(23, 0);
218 irq->target_vcpu = kvm_mpidr_to_vcpu(vcpu->kvm, irq->mpidr);
220 raw_spin_unlock_irqrestore(&irq->irq_lock, flags);
221 vgic_put_irq(vcpu->kvm, irq);
224 static unsigned long vgic_mmio_read_v3r_ctlr(struct kvm_vcpu *vcpu,
225 gpa_t addr, unsigned int len)
227 struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
229 return vgic_cpu->lpis_enabled ? GICR_CTLR_ENABLE_LPIS : 0;
233 static void vgic_mmio_write_v3r_ctlr(struct kvm_vcpu *vcpu,
234 gpa_t addr, unsigned int len,
237 struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
238 bool was_enabled = vgic_cpu->lpis_enabled;
240 if (!vgic_has_its(vcpu->kvm))
243 vgic_cpu->lpis_enabled = val & GICR_CTLR_ENABLE_LPIS;
245 if (was_enabled && !vgic_cpu->lpis_enabled) {
246 vgic_flush_pending_lpis(vcpu);
247 vgic_its_invalidate_cache(vcpu->kvm);
250 if (!was_enabled && vgic_cpu->lpis_enabled)
251 vgic_enable_lpis(vcpu);
254 static bool vgic_mmio_vcpu_rdist_is_last(struct kvm_vcpu *vcpu)
256 struct vgic_dist *vgic = &vcpu->kvm->arch.vgic;
257 struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
258 struct vgic_redist_region *iter, *rdreg = vgic_cpu->rdreg;
263 if (vgic_cpu->rdreg_index < rdreg->free_index - 1) {
265 } else if (rdreg->count && vgic_cpu->rdreg_index == (rdreg->count - 1)) {
266 struct list_head *rd_regions = &vgic->rd_regions;
267 gpa_t end = rdreg->base + rdreg->count * KVM_VGIC_V3_REDIST_SIZE;
270 * the rdist is the last one of the redist region,
271 * check whether there is no other contiguous rdist region
273 list_for_each_entry(iter, rd_regions, list) {
274 if (iter->base == end && iter->free_index > 0)
281 static unsigned long vgic_mmio_read_v3r_typer(struct kvm_vcpu *vcpu,
282 gpa_t addr, unsigned int len)
284 unsigned long mpidr = kvm_vcpu_get_mpidr_aff(vcpu);
285 int target_vcpu_id = vcpu->vcpu_id;
288 value = (u64)(mpidr & GENMASK(23, 0)) << 32;
289 value |= ((target_vcpu_id & 0xffff) << 8);
291 if (vgic_has_its(vcpu->kvm))
292 value |= GICR_TYPER_PLPIS;
294 if (vgic_mmio_vcpu_rdist_is_last(vcpu))
295 value |= GICR_TYPER_LAST;
297 return extract_bytes(value, addr & 7, len);
300 static unsigned long vgic_mmio_read_v3r_iidr(struct kvm_vcpu *vcpu,
301 gpa_t addr, unsigned int len)
303 return (PRODUCT_ID_KVM << 24) | (IMPLEMENTER_ARM << 0);
306 static unsigned long vgic_mmio_read_v3_idregs(struct kvm_vcpu *vcpu,
307 gpa_t addr, unsigned int len)
309 switch (addr & 0xffff) {
311 /* report a GICv3 compliant implementation */
318 static unsigned long vgic_v3_uaccess_read_pending(struct kvm_vcpu *vcpu,
319 gpa_t addr, unsigned int len)
321 u32 intid = VGIC_ADDR_TO_INTID(addr, 1);
326 * pending state of interrupt is latched in pending_latch variable.
327 * Userspace will save and restore pending state and line_level
329 * Refer to Documentation/virt/kvm/devices/arm-vgic-v3.rst
330 * for handling of ISPENDR and ICPENDR.
332 for (i = 0; i < len * 8; i++) {
333 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
334 bool state = irq->pending_latch;
336 if (irq->hw && vgic_irq_is_sgi(irq->intid)) {
339 err = irq_get_irqchip_state(irq->host_irq,
340 IRQCHIP_STATE_PENDING,
348 vgic_put_irq(vcpu->kvm, irq);
354 static int vgic_v3_uaccess_write_pending(struct kvm_vcpu *vcpu,
355 gpa_t addr, unsigned int len,
358 u32 intid = VGIC_ADDR_TO_INTID(addr, 1);
362 for (i = 0; i < len * 8; i++) {
363 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
365 raw_spin_lock_irqsave(&irq->irq_lock, flags);
366 if (test_bit(i, &val)) {
368 * pending_latch is set irrespective of irq type
369 * (level or edge) to avoid dependency that VM should
370 * restore irq config before pending info.
372 irq->pending_latch = true;
373 vgic_queue_irq_unlock(vcpu->kvm, irq, flags);
375 irq->pending_latch = false;
376 raw_spin_unlock_irqrestore(&irq->irq_lock, flags);
379 vgic_put_irq(vcpu->kvm, irq);
385 /* We want to avoid outer shareable. */
386 u64 vgic_sanitise_shareability(u64 field)
389 case GIC_BASER_OuterShareable:
390 return GIC_BASER_InnerShareable;
396 /* Avoid any inner non-cacheable mapping. */
397 u64 vgic_sanitise_inner_cacheability(u64 field)
400 case GIC_BASER_CACHE_nCnB:
401 case GIC_BASER_CACHE_nC:
402 return GIC_BASER_CACHE_RaWb;
408 /* Non-cacheable or same-as-inner are OK. */
409 u64 vgic_sanitise_outer_cacheability(u64 field)
412 case GIC_BASER_CACHE_SameAsInner:
413 case GIC_BASER_CACHE_nC:
416 return GIC_BASER_CACHE_SameAsInner;
420 u64 vgic_sanitise_field(u64 reg, u64 field_mask, int field_shift,
421 u64 (*sanitise_fn)(u64))
423 u64 field = (reg & field_mask) >> field_shift;
425 field = sanitise_fn(field) << field_shift;
426 return (reg & ~field_mask) | field;
429 #define PROPBASER_RES0_MASK \
430 (GENMASK_ULL(63, 59) | GENMASK_ULL(55, 52) | GENMASK_ULL(6, 5))
431 #define PENDBASER_RES0_MASK \
432 (BIT_ULL(63) | GENMASK_ULL(61, 59) | GENMASK_ULL(55, 52) | \
433 GENMASK_ULL(15, 12) | GENMASK_ULL(6, 0))
435 static u64 vgic_sanitise_pendbaser(u64 reg)
437 reg = vgic_sanitise_field(reg, GICR_PENDBASER_SHAREABILITY_MASK,
438 GICR_PENDBASER_SHAREABILITY_SHIFT,
439 vgic_sanitise_shareability);
440 reg = vgic_sanitise_field(reg, GICR_PENDBASER_INNER_CACHEABILITY_MASK,
441 GICR_PENDBASER_INNER_CACHEABILITY_SHIFT,
442 vgic_sanitise_inner_cacheability);
443 reg = vgic_sanitise_field(reg, GICR_PENDBASER_OUTER_CACHEABILITY_MASK,
444 GICR_PENDBASER_OUTER_CACHEABILITY_SHIFT,
445 vgic_sanitise_outer_cacheability);
447 reg &= ~PENDBASER_RES0_MASK;
452 static u64 vgic_sanitise_propbaser(u64 reg)
454 reg = vgic_sanitise_field(reg, GICR_PROPBASER_SHAREABILITY_MASK,
455 GICR_PROPBASER_SHAREABILITY_SHIFT,
456 vgic_sanitise_shareability);
457 reg = vgic_sanitise_field(reg, GICR_PROPBASER_INNER_CACHEABILITY_MASK,
458 GICR_PROPBASER_INNER_CACHEABILITY_SHIFT,
459 vgic_sanitise_inner_cacheability);
460 reg = vgic_sanitise_field(reg, GICR_PROPBASER_OUTER_CACHEABILITY_MASK,
461 GICR_PROPBASER_OUTER_CACHEABILITY_SHIFT,
462 vgic_sanitise_outer_cacheability);
464 reg &= ~PROPBASER_RES0_MASK;
468 static unsigned long vgic_mmio_read_propbase(struct kvm_vcpu *vcpu,
469 gpa_t addr, unsigned int len)
471 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
473 return extract_bytes(dist->propbaser, addr & 7, len);
476 static void vgic_mmio_write_propbase(struct kvm_vcpu *vcpu,
477 gpa_t addr, unsigned int len,
480 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
481 struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
482 u64 old_propbaser, propbaser;
484 /* Storing a value with LPIs already enabled is undefined */
485 if (vgic_cpu->lpis_enabled)
489 old_propbaser = READ_ONCE(dist->propbaser);
490 propbaser = old_propbaser;
491 propbaser = update_64bit_reg(propbaser, addr & 4, len, val);
492 propbaser = vgic_sanitise_propbaser(propbaser);
493 } while (cmpxchg64(&dist->propbaser, old_propbaser,
494 propbaser) != old_propbaser);
497 static unsigned long vgic_mmio_read_pendbase(struct kvm_vcpu *vcpu,
498 gpa_t addr, unsigned int len)
500 struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
501 u64 value = vgic_cpu->pendbaser;
503 value &= ~GICR_PENDBASER_PTZ;
505 return extract_bytes(value, addr & 7, len);
508 static void vgic_mmio_write_pendbase(struct kvm_vcpu *vcpu,
509 gpa_t addr, unsigned int len,
512 struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
513 u64 old_pendbaser, pendbaser;
515 /* Storing a value with LPIs already enabled is undefined */
516 if (vgic_cpu->lpis_enabled)
520 old_pendbaser = READ_ONCE(vgic_cpu->pendbaser);
521 pendbaser = old_pendbaser;
522 pendbaser = update_64bit_reg(pendbaser, addr & 4, len, val);
523 pendbaser = vgic_sanitise_pendbaser(pendbaser);
524 } while (cmpxchg64(&vgic_cpu->pendbaser, old_pendbaser,
525 pendbaser) != old_pendbaser);
529 * The GICv3 per-IRQ registers are split to control PPIs and SGIs in the
530 * redistributors, while SPIs are covered by registers in the distributor
531 * block. Trying to set private IRQs in this block gets ignored.
532 * We take some special care here to fix the calculation of the register
535 #define REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(off, rd, wr, ur, uw, bpi, acc) \
538 .bits_per_irq = bpi, \
539 .len = (bpi * VGIC_NR_PRIVATE_IRQS) / 8, \
540 .access_flags = acc, \
541 .read = vgic_mmio_read_raz, \
542 .write = vgic_mmio_write_wi, \
544 .reg_offset = off + (bpi * VGIC_NR_PRIVATE_IRQS) / 8, \
545 .bits_per_irq = bpi, \
546 .len = (bpi * (1024 - VGIC_NR_PRIVATE_IRQS)) / 8, \
547 .access_flags = acc, \
550 .uaccess_read = ur, \
551 .uaccess_write = uw, \
554 static const struct vgic_register_region vgic_v3_dist_registers[] = {
555 REGISTER_DESC_WITH_LENGTH_UACCESS(GICD_CTLR,
556 vgic_mmio_read_v3_misc, vgic_mmio_write_v3_misc,
557 NULL, vgic_mmio_uaccess_write_v3_misc,
558 16, VGIC_ACCESS_32bit),
559 REGISTER_DESC_WITH_LENGTH(GICD_STATUSR,
560 vgic_mmio_read_rao, vgic_mmio_write_wi, 4,
562 REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_IGROUPR,
563 vgic_mmio_read_group, vgic_mmio_write_group, NULL, NULL, 1,
565 REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ISENABLER,
566 vgic_mmio_read_enable, vgic_mmio_write_senable,
567 NULL, vgic_uaccess_write_senable, 1,
569 REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ICENABLER,
570 vgic_mmio_read_enable, vgic_mmio_write_cenable,
571 NULL, vgic_uaccess_write_cenable, 1,
573 REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ISPENDR,
574 vgic_mmio_read_pending, vgic_mmio_write_spending,
575 vgic_v3_uaccess_read_pending, vgic_v3_uaccess_write_pending, 1,
577 REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ICPENDR,
578 vgic_mmio_read_pending, vgic_mmio_write_cpending,
579 vgic_mmio_read_raz, vgic_mmio_uaccess_write_wi, 1,
581 REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ISACTIVER,
582 vgic_mmio_read_active, vgic_mmio_write_sactive,
583 vgic_uaccess_read_active, vgic_mmio_uaccess_write_sactive, 1,
585 REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ICACTIVER,
586 vgic_mmio_read_active, vgic_mmio_write_cactive,
587 vgic_uaccess_read_active, vgic_mmio_uaccess_write_cactive,
588 1, VGIC_ACCESS_32bit),
589 REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_IPRIORITYR,
590 vgic_mmio_read_priority, vgic_mmio_write_priority, NULL, NULL,
591 8, VGIC_ACCESS_32bit | VGIC_ACCESS_8bit),
592 REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ITARGETSR,
593 vgic_mmio_read_raz, vgic_mmio_write_wi, NULL, NULL, 8,
594 VGIC_ACCESS_32bit | VGIC_ACCESS_8bit),
595 REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ICFGR,
596 vgic_mmio_read_config, vgic_mmio_write_config, NULL, NULL, 2,
598 REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_IGRPMODR,
599 vgic_mmio_read_raz, vgic_mmio_write_wi, NULL, NULL, 1,
601 REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_IROUTER,
602 vgic_mmio_read_irouter, vgic_mmio_write_irouter, NULL, NULL, 64,
603 VGIC_ACCESS_64bit | VGIC_ACCESS_32bit),
604 REGISTER_DESC_WITH_LENGTH(GICD_IDREGS,
605 vgic_mmio_read_v3_idregs, vgic_mmio_write_wi, 48,
609 static const struct vgic_register_region vgic_v3_rd_registers[] = {
610 /* RD_base registers */
611 REGISTER_DESC_WITH_LENGTH(GICR_CTLR,
612 vgic_mmio_read_v3r_ctlr, vgic_mmio_write_v3r_ctlr, 4,
614 REGISTER_DESC_WITH_LENGTH(GICR_STATUSR,
615 vgic_mmio_read_raz, vgic_mmio_write_wi, 4,
617 REGISTER_DESC_WITH_LENGTH(GICR_IIDR,
618 vgic_mmio_read_v3r_iidr, vgic_mmio_write_wi, 4,
620 REGISTER_DESC_WITH_LENGTH_UACCESS(GICR_TYPER,
621 vgic_mmio_read_v3r_typer, vgic_mmio_write_wi,
622 NULL, vgic_mmio_uaccess_write_wi, 8,
623 VGIC_ACCESS_64bit | VGIC_ACCESS_32bit),
624 REGISTER_DESC_WITH_LENGTH(GICR_WAKER,
625 vgic_mmio_read_raz, vgic_mmio_write_wi, 4,
627 REGISTER_DESC_WITH_LENGTH(GICR_PROPBASER,
628 vgic_mmio_read_propbase, vgic_mmio_write_propbase, 8,
629 VGIC_ACCESS_64bit | VGIC_ACCESS_32bit),
630 REGISTER_DESC_WITH_LENGTH(GICR_PENDBASER,
631 vgic_mmio_read_pendbase, vgic_mmio_write_pendbase, 8,
632 VGIC_ACCESS_64bit | VGIC_ACCESS_32bit),
633 REGISTER_DESC_WITH_LENGTH(GICR_IDREGS,
634 vgic_mmio_read_v3_idregs, vgic_mmio_write_wi, 48,
636 /* SGI_base registers */
637 REGISTER_DESC_WITH_LENGTH(SZ_64K + GICR_IGROUPR0,
638 vgic_mmio_read_group, vgic_mmio_write_group, 4,
640 REGISTER_DESC_WITH_LENGTH_UACCESS(SZ_64K + GICR_ISENABLER0,
641 vgic_mmio_read_enable, vgic_mmio_write_senable,
642 NULL, vgic_uaccess_write_senable, 4,
644 REGISTER_DESC_WITH_LENGTH_UACCESS(SZ_64K + GICR_ICENABLER0,
645 vgic_mmio_read_enable, vgic_mmio_write_cenable,
646 NULL, vgic_uaccess_write_cenable, 4,
648 REGISTER_DESC_WITH_LENGTH_UACCESS(SZ_64K + GICR_ISPENDR0,
649 vgic_mmio_read_pending, vgic_mmio_write_spending,
650 vgic_v3_uaccess_read_pending, vgic_v3_uaccess_write_pending, 4,
652 REGISTER_DESC_WITH_LENGTH_UACCESS(SZ_64K + GICR_ICPENDR0,
653 vgic_mmio_read_pending, vgic_mmio_write_cpending,
654 vgic_mmio_read_raz, vgic_mmio_uaccess_write_wi, 4,
656 REGISTER_DESC_WITH_LENGTH_UACCESS(SZ_64K + GICR_ISACTIVER0,
657 vgic_mmio_read_active, vgic_mmio_write_sactive,
658 vgic_uaccess_read_active, vgic_mmio_uaccess_write_sactive, 4,
660 REGISTER_DESC_WITH_LENGTH_UACCESS(SZ_64K + GICR_ICACTIVER0,
661 vgic_mmio_read_active, vgic_mmio_write_cactive,
662 vgic_uaccess_read_active, vgic_mmio_uaccess_write_cactive, 4,
664 REGISTER_DESC_WITH_LENGTH(SZ_64K + GICR_IPRIORITYR0,
665 vgic_mmio_read_priority, vgic_mmio_write_priority, 32,
666 VGIC_ACCESS_32bit | VGIC_ACCESS_8bit),
667 REGISTER_DESC_WITH_LENGTH(SZ_64K + GICR_ICFGR0,
668 vgic_mmio_read_config, vgic_mmio_write_config, 8,
670 REGISTER_DESC_WITH_LENGTH(SZ_64K + GICR_IGRPMODR0,
671 vgic_mmio_read_raz, vgic_mmio_write_wi, 4,
673 REGISTER_DESC_WITH_LENGTH(SZ_64K + GICR_NSACR,
674 vgic_mmio_read_raz, vgic_mmio_write_wi, 4,
678 unsigned int vgic_v3_init_dist_iodev(struct vgic_io_device *dev)
680 dev->regions = vgic_v3_dist_registers;
681 dev->nr_regions = ARRAY_SIZE(vgic_v3_dist_registers);
683 kvm_iodevice_init(&dev->dev, &kvm_io_gic_ops);
689 * vgic_register_redist_iodev - register a single redist iodev
690 * @vcpu: The VCPU to which the redistributor belongs
692 * Register a KVM iodev for this VCPU's redistributor using the address
695 * Return 0 on success, -ERRNO otherwise.
697 int vgic_register_redist_iodev(struct kvm_vcpu *vcpu)
699 struct kvm *kvm = vcpu->kvm;
700 struct vgic_dist *vgic = &kvm->arch.vgic;
701 struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
702 struct vgic_io_device *rd_dev = &vcpu->arch.vgic_cpu.rd_iodev;
703 struct vgic_redist_region *rdreg;
707 if (!IS_VGIC_ADDR_UNDEF(vgic_cpu->rd_iodev.base_addr))
711 * We may be creating VCPUs before having set the base address for the
712 * redistributor region, in which case we will come back to this
713 * function for all VCPUs when the base address is set. Just return
714 * without doing any work for now.
716 rdreg = vgic_v3_rdist_free_slot(&vgic->rd_regions);
720 if (!vgic_v3_check_base(kvm))
723 vgic_cpu->rdreg = rdreg;
724 vgic_cpu->rdreg_index = rdreg->free_index;
726 rd_base = rdreg->base + rdreg->free_index * KVM_VGIC_V3_REDIST_SIZE;
728 kvm_iodevice_init(&rd_dev->dev, &kvm_io_gic_ops);
729 rd_dev->base_addr = rd_base;
730 rd_dev->iodev_type = IODEV_REDIST;
731 rd_dev->regions = vgic_v3_rd_registers;
732 rd_dev->nr_regions = ARRAY_SIZE(vgic_v3_rd_registers);
733 rd_dev->redist_vcpu = vcpu;
735 mutex_lock(&kvm->slots_lock);
736 ret = kvm_io_bus_register_dev(kvm, KVM_MMIO_BUS, rd_base,
737 2 * SZ_64K, &rd_dev->dev);
738 mutex_unlock(&kvm->slots_lock);
747 static void vgic_unregister_redist_iodev(struct kvm_vcpu *vcpu)
749 struct vgic_io_device *rd_dev = &vcpu->arch.vgic_cpu.rd_iodev;
751 kvm_io_bus_unregister_dev(vcpu->kvm, KVM_MMIO_BUS, &rd_dev->dev);
754 static int vgic_register_all_redist_iodevs(struct kvm *kvm)
756 struct kvm_vcpu *vcpu;
759 kvm_for_each_vcpu(c, vcpu, kvm) {
760 ret = vgic_register_redist_iodev(vcpu);
766 /* The current c failed, so we start with the previous one. */
767 mutex_lock(&kvm->slots_lock);
768 for (c--; c >= 0; c--) {
769 vcpu = kvm_get_vcpu(kvm, c);
770 vgic_unregister_redist_iodev(vcpu);
772 mutex_unlock(&kvm->slots_lock);
779 * vgic_v3_alloc_redist_region - Allocate a new redistributor region
781 * Performs various checks before inserting the rdist region in the list.
782 * Those tests depend on whether the size of the rdist region is known
783 * (ie. count != 0). The list is sorted by rdist region index.
786 * @index: redist region index
787 * @base: base of the new rdist region
788 * @count: number of redistributors the region is made of (0 in the old style
789 * single region, whose size is induced from the number of vcpus)
791 * Return 0 on success, < 0 otherwise
793 static int vgic_v3_alloc_redist_region(struct kvm *kvm, uint32_t index,
794 gpa_t base, uint32_t count)
796 struct vgic_dist *d = &kvm->arch.vgic;
797 struct vgic_redist_region *rdreg;
798 struct list_head *rd_regions = &d->rd_regions;
799 size_t size = count * KVM_VGIC_V3_REDIST_SIZE;
802 /* cross the end of memory ? */
803 if (base + size < base)
806 if (list_empty(rd_regions)) {
810 rdreg = list_last_entry(rd_regions,
811 struct vgic_redist_region, list);
813 /* Don't mix single region and discrete redist regions */
814 if (!count && rdreg->count)
820 if (index != rdreg->index + 1)
825 * For legacy single-region redistributor regions (!count),
826 * check that the redistributor region does not overlap with the
827 * distributor's address space.
829 if (!count && !IS_VGIC_ADDR_UNDEF(d->vgic_dist_base) &&
830 vgic_dist_overlap(kvm, base, size))
833 /* collision with any other rdist region? */
834 if (vgic_v3_rdist_overlap(kvm, base, size))
837 rdreg = kzalloc(sizeof(*rdreg), GFP_KERNEL);
841 rdreg->base = VGIC_ADDR_UNDEF;
843 ret = vgic_check_ioaddr(kvm, &rdreg->base, base, SZ_64K);
848 rdreg->count = count;
849 rdreg->free_index = 0;
850 rdreg->index = index;
852 list_add_tail(&rdreg->list, rd_regions);
859 void vgic_v3_free_redist_region(struct vgic_redist_region *rdreg)
861 list_del(&rdreg->list);
865 int vgic_v3_set_redist_base(struct kvm *kvm, u32 index, u64 addr, u32 count)
869 ret = vgic_v3_alloc_redist_region(kvm, index, addr, count);
874 * Register iodevs for each existing VCPU. Adding more VCPUs
875 * afterwards will register the iodevs when needed.
877 ret = vgic_register_all_redist_iodevs(kvm);
879 struct vgic_redist_region *rdreg;
881 rdreg = vgic_v3_rdist_region_from_index(kvm, index);
882 vgic_v3_free_redist_region(rdreg);
889 int vgic_v3_has_attr_regs(struct kvm_device *dev, struct kvm_device_attr *attr)
891 const struct vgic_register_region *region;
892 struct vgic_io_device iodev;
893 struct vgic_reg_attr reg_attr;
894 struct kvm_vcpu *vcpu;
898 ret = vgic_v3_parse_attr(dev, attr, ®_attr);
902 vcpu = reg_attr.vcpu;
903 addr = reg_attr.addr;
905 switch (attr->group) {
906 case KVM_DEV_ARM_VGIC_GRP_DIST_REGS:
907 iodev.regions = vgic_v3_dist_registers;
908 iodev.nr_regions = ARRAY_SIZE(vgic_v3_dist_registers);
911 case KVM_DEV_ARM_VGIC_GRP_REDIST_REGS:{
912 iodev.regions = vgic_v3_rd_registers;
913 iodev.nr_regions = ARRAY_SIZE(vgic_v3_rd_registers);
917 case KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS: {
920 id = (attr->attr & KVM_DEV_ARM_VGIC_SYSREG_INSTR_MASK);
921 return vgic_v3_has_cpu_sysregs_attr(vcpu, 0, id, ®);
927 /* We only support aligned 32-bit accesses. */
931 region = vgic_get_mmio_region(vcpu, &iodev, addr, sizeof(u32));
938 * Compare a given affinity (level 1-3 and a level 0 mask, from the SGI
939 * generation register ICC_SGI1R_EL1) with a given VCPU.
940 * If the VCPU's MPIDR matches, return the level0 affinity, otherwise
943 static int match_mpidr(u64 sgi_aff, u16 sgi_cpu_mask, struct kvm_vcpu *vcpu)
945 unsigned long affinity;
949 * Split the current VCPU's MPIDR into affinity level 0 and the
950 * rest as this is what we have to compare against.
952 affinity = kvm_vcpu_get_mpidr_aff(vcpu);
953 level0 = MPIDR_AFFINITY_LEVEL(affinity, 0);
954 affinity &= ~MPIDR_LEVEL_MASK;
956 /* bail out if the upper three levels don't match */
957 if (sgi_aff != affinity)
960 /* Is this VCPU's bit set in the mask ? */
961 if (!(sgi_cpu_mask & BIT(level0)))
968 * The ICC_SGI* registers encode the affinity differently from the MPIDR,
969 * so provide a wrapper to use the existing defines to isolate a certain
972 #define SGI_AFFINITY_LEVEL(reg, level) \
973 ((((reg) & ICC_SGI1R_AFFINITY_## level ##_MASK) \
974 >> ICC_SGI1R_AFFINITY_## level ##_SHIFT) << MPIDR_LEVEL_SHIFT(level))
977 * vgic_v3_dispatch_sgi - handle SGI requests from VCPUs
978 * @vcpu: The VCPU requesting a SGI
979 * @reg: The value written into ICC_{ASGI1,SGI0,SGI1}R by that VCPU
980 * @allow_group1: Does the sysreg access allow generation of G1 SGIs
982 * With GICv3 (and ARE=1) CPUs trigger SGIs by writing to a system register.
983 * This will trap in sys_regs.c and call this function.
984 * This ICC_SGI1R_EL1 register contains the upper three affinity levels of the
985 * target processors as well as a bitmask of 16 Aff0 CPUs.
986 * If the interrupt routing mode bit is not set, we iterate over all VCPUs to
987 * check for matching ones. If this bit is set, we signal all, but not the
990 void vgic_v3_dispatch_sgi(struct kvm_vcpu *vcpu, u64 reg, bool allow_group1)
992 struct kvm *kvm = vcpu->kvm;
993 struct kvm_vcpu *c_vcpu;
997 int vcpu_id = vcpu->vcpu_id;
1001 sgi = (reg & ICC_SGI1R_SGI_ID_MASK) >> ICC_SGI1R_SGI_ID_SHIFT;
1002 broadcast = reg & BIT_ULL(ICC_SGI1R_IRQ_ROUTING_MODE_BIT);
1003 target_cpus = (reg & ICC_SGI1R_TARGET_LIST_MASK) >> ICC_SGI1R_TARGET_LIST_SHIFT;
1004 mpidr = SGI_AFFINITY_LEVEL(reg, 3);
1005 mpidr |= SGI_AFFINITY_LEVEL(reg, 2);
1006 mpidr |= SGI_AFFINITY_LEVEL(reg, 1);
1009 * We iterate over all VCPUs to find the MPIDRs matching the request.
1010 * If we have handled one CPU, we clear its bit to detect early
1011 * if we are already finished. This avoids iterating through all
1012 * VCPUs when most of the times we just signal a single VCPU.
1014 kvm_for_each_vcpu(c, c_vcpu, kvm) {
1015 struct vgic_irq *irq;
1017 /* Exit early if we have dealt with all requested CPUs */
1018 if (!broadcast && target_cpus == 0)
1021 /* Don't signal the calling VCPU */
1022 if (broadcast && c == vcpu_id)
1028 level0 = match_mpidr(mpidr, target_cpus, c_vcpu);
1032 /* remove this matching VCPU from the mask */
1033 target_cpus &= ~BIT(level0);
1036 irq = vgic_get_irq(vcpu->kvm, c_vcpu, sgi);
1038 raw_spin_lock_irqsave(&irq->irq_lock, flags);
1041 * An access targeting Group0 SGIs can only generate
1042 * those, while an access targeting Group1 SGIs can
1043 * generate interrupts of either group.
1045 if (!irq->group || allow_group1) {
1047 irq->pending_latch = true;
1048 vgic_queue_irq_unlock(vcpu->kvm, irq, flags);
1050 /* HW SGI? Ask the GIC to inject it */
1052 err = irq_set_irqchip_state(irq->host_irq,
1053 IRQCHIP_STATE_PENDING,
1055 WARN_RATELIMIT(err, "IRQ %d", irq->host_irq);
1056 raw_spin_unlock_irqrestore(&irq->irq_lock, flags);
1059 raw_spin_unlock_irqrestore(&irq->irq_lock, flags);
1062 vgic_put_irq(vcpu->kvm, irq);
1066 int vgic_v3_dist_uaccess(struct kvm_vcpu *vcpu, bool is_write,
1067 int offset, u32 *val)
1069 struct vgic_io_device dev = {
1070 .regions = vgic_v3_dist_registers,
1071 .nr_regions = ARRAY_SIZE(vgic_v3_dist_registers),
1074 return vgic_uaccess(vcpu, &dev, is_write, offset, val);
1077 int vgic_v3_redist_uaccess(struct kvm_vcpu *vcpu, bool is_write,
1078 int offset, u32 *val)
1080 struct vgic_io_device rd_dev = {
1081 .regions = vgic_v3_rd_registers,
1082 .nr_regions = ARRAY_SIZE(vgic_v3_rd_registers),
1085 return vgic_uaccess(vcpu, &rd_dev, is_write, offset, val);
1088 int vgic_v3_line_level_info_uaccess(struct kvm_vcpu *vcpu, bool is_write,
1089 u32 intid, u64 *val)
1095 vgic_write_irq_line_level_info(vcpu, intid, *val);
1097 *val = vgic_read_irq_line_level_info(vcpu, intid);