1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2015 ARM Ltd.
6 * Author: Marc Zyngier <marc.zyngier@arm.com>
8 #include <linux/kvm_host.h>
9 #include <kvm/arm_vgic.h>
10 #include <linux/uaccess.h>
11 #include <asm/kvm_mmu.h>
12 #include <asm/cputype.h>
17 int vgic_check_iorange(struct kvm *kvm, phys_addr_t ioaddr,
18 phys_addr_t addr, phys_addr_t alignment,
21 if (!IS_VGIC_ADDR_UNDEF(ioaddr))
24 if (!IS_ALIGNED(addr, alignment) || !IS_ALIGNED(size, alignment))
27 if (addr + size < addr)
30 if (addr & ~kvm_phys_mask(&kvm->arch.mmu) ||
31 (addr + size) > kvm_phys_size(&kvm->arch.mmu))
37 static int vgic_check_type(struct kvm *kvm, int type_needed)
39 if (kvm->arch.vgic.vgic_model != type_needed)
45 int kvm_set_legacy_vgic_v2_addr(struct kvm *kvm, struct kvm_arm_device_addr *dev_addr)
47 struct vgic_dist *vgic = &kvm->arch.vgic;
50 mutex_lock(&kvm->arch.config_lock);
51 switch (FIELD_GET(KVM_ARM_DEVICE_TYPE_MASK, dev_addr->id)) {
52 case KVM_VGIC_V2_ADDR_TYPE_DIST:
53 r = vgic_check_type(kvm, KVM_DEV_TYPE_ARM_VGIC_V2);
55 r = vgic_check_iorange(kvm, vgic->vgic_dist_base, dev_addr->addr,
56 SZ_4K, KVM_VGIC_V2_DIST_SIZE);
58 vgic->vgic_dist_base = dev_addr->addr;
60 case KVM_VGIC_V2_ADDR_TYPE_CPU:
61 r = vgic_check_type(kvm, KVM_DEV_TYPE_ARM_VGIC_V2);
63 r = vgic_check_iorange(kvm, vgic->vgic_cpu_base, dev_addr->addr,
64 SZ_4K, KVM_VGIC_V2_CPU_SIZE);
66 vgic->vgic_cpu_base = dev_addr->addr;
72 mutex_unlock(&kvm->arch.config_lock);
78 * kvm_vgic_addr - set or get vgic VM base addresses
79 * @kvm: pointer to the vm struct
80 * @attr: pointer to the attribute being retrieved/updated
81 * @write: if true set the address in the VM address space, if false read the
84 * Set or get the vgic base addresses for the distributor and the virtual CPU
85 * interface in the VM physical address space. These addresses are properties
86 * of the emulated core/SoC and therefore user space initially knows this
88 * Check them for sanity (alignment, double assignment). We can't check for
89 * overlapping regions in case of a virtual GICv3 here, since we don't know
90 * the number of VCPUs yet, so we defer this check to map_resources().
92 static int kvm_vgic_addr(struct kvm *kvm, struct kvm_device_attr *attr, bool write)
94 u64 __user *uaddr = (u64 __user *)attr->addr;
95 struct vgic_dist *vgic = &kvm->arch.vgic;
96 phys_addr_t *addr_ptr, alignment, size;
97 u64 undef_value = VGIC_ADDR_UNDEF;
101 /* Reading a redistributor region addr implies getting the index */
102 if (write || attr->attr == KVM_VGIC_V3_ADDR_TYPE_REDIST_REGION)
103 if (get_user(addr, uaddr))
107 * Since we can't hold config_lock while registering the redistributor
108 * iodevs, take the slots_lock immediately.
110 mutex_lock(&kvm->slots_lock);
111 switch (attr->attr) {
112 case KVM_VGIC_V2_ADDR_TYPE_DIST:
113 r = vgic_check_type(kvm, KVM_DEV_TYPE_ARM_VGIC_V2);
114 addr_ptr = &vgic->vgic_dist_base;
116 size = KVM_VGIC_V2_DIST_SIZE;
118 case KVM_VGIC_V2_ADDR_TYPE_CPU:
119 r = vgic_check_type(kvm, KVM_DEV_TYPE_ARM_VGIC_V2);
120 addr_ptr = &vgic->vgic_cpu_base;
122 size = KVM_VGIC_V2_CPU_SIZE;
124 case KVM_VGIC_V3_ADDR_TYPE_DIST:
125 r = vgic_check_type(kvm, KVM_DEV_TYPE_ARM_VGIC_V3);
126 addr_ptr = &vgic->vgic_dist_base;
128 size = KVM_VGIC_V3_DIST_SIZE;
130 case KVM_VGIC_V3_ADDR_TYPE_REDIST: {
131 struct vgic_redist_region *rdreg;
133 r = vgic_check_type(kvm, KVM_DEV_TYPE_ARM_VGIC_V3);
137 r = vgic_v3_set_redist_base(kvm, 0, addr, 0);
140 rdreg = list_first_entry_or_null(&vgic->rd_regions,
141 struct vgic_redist_region, list);
143 addr_ptr = &undef_value;
145 addr_ptr = &rdreg->base;
148 case KVM_VGIC_V3_ADDR_TYPE_REDIST_REGION:
150 struct vgic_redist_region *rdreg;
153 r = vgic_check_type(kvm, KVM_DEV_TYPE_ARM_VGIC_V3);
157 index = addr & KVM_VGIC_V3_RDIST_INDEX_MASK;
160 gpa_t base = addr & KVM_VGIC_V3_RDIST_BASE_MASK;
161 u32 count = FIELD_GET(KVM_VGIC_V3_RDIST_COUNT_MASK, addr);
162 u8 flags = FIELD_GET(KVM_VGIC_V3_RDIST_FLAGS_MASK, addr);
167 r = vgic_v3_set_redist_base(kvm, index,
172 rdreg = vgic_v3_rdist_region_from_index(kvm, index);
180 addr |= (u64)rdreg->count << KVM_VGIC_V3_RDIST_COUNT_SHIFT;
190 mutex_lock(&kvm->arch.config_lock);
192 r = vgic_check_iorange(kvm, *addr_ptr, addr, alignment, size);
198 mutex_unlock(&kvm->arch.config_lock);
201 mutex_unlock(&kvm->slots_lock);
204 r = put_user(addr, uaddr);
209 static int vgic_set_common_attr(struct kvm_device *dev,
210 struct kvm_device_attr *attr)
214 switch (attr->group) {
215 case KVM_DEV_ARM_VGIC_GRP_ADDR:
216 r = kvm_vgic_addr(dev->kvm, attr, true);
217 return (r == -ENODEV) ? -ENXIO : r;
218 case KVM_DEV_ARM_VGIC_GRP_NR_IRQS: {
219 u32 __user *uaddr = (u32 __user *)(long)attr->addr;
223 if (get_user(val, uaddr))
228 * - at least 32 SPIs on top of the 16 SGIs and 16 PPIs
229 * - at most 1024 interrupts
230 * - a multiple of 32 interrupts
232 if (val < (VGIC_NR_PRIVATE_IRQS + 32) ||
233 val > VGIC_MAX_RESERVED ||
237 mutex_lock(&dev->kvm->arch.config_lock);
239 if (vgic_ready(dev->kvm) || dev->kvm->arch.vgic.nr_spis)
242 dev->kvm->arch.vgic.nr_spis =
243 val - VGIC_NR_PRIVATE_IRQS;
245 mutex_unlock(&dev->kvm->arch.config_lock);
249 case KVM_DEV_ARM_VGIC_GRP_CTRL: {
250 switch (attr->attr) {
251 case KVM_DEV_ARM_VGIC_CTRL_INIT:
252 mutex_lock(&dev->kvm->arch.config_lock);
253 r = vgic_init(dev->kvm);
254 mutex_unlock(&dev->kvm->arch.config_lock);
256 case KVM_DEV_ARM_VGIC_SAVE_PENDING_TABLES:
258 * OK, this one isn't common at all, but we
259 * want to handle all control group attributes
262 if (vgic_check_type(dev->kvm, KVM_DEV_TYPE_ARM_VGIC_V3))
264 mutex_lock(&dev->kvm->lock);
266 if (!lock_all_vcpus(dev->kvm)) {
267 mutex_unlock(&dev->kvm->lock);
271 mutex_lock(&dev->kvm->arch.config_lock);
272 r = vgic_v3_save_pending_tables(dev->kvm);
273 mutex_unlock(&dev->kvm->arch.config_lock);
274 unlock_all_vcpus(dev->kvm);
275 mutex_unlock(&dev->kvm->lock);
285 static int vgic_get_common_attr(struct kvm_device *dev,
286 struct kvm_device_attr *attr)
290 switch (attr->group) {
291 case KVM_DEV_ARM_VGIC_GRP_ADDR:
292 r = kvm_vgic_addr(dev->kvm, attr, false);
293 return (r == -ENODEV) ? -ENXIO : r;
294 case KVM_DEV_ARM_VGIC_GRP_NR_IRQS: {
295 u32 __user *uaddr = (u32 __user *)(long)attr->addr;
297 r = put_user(dev->kvm->arch.vgic.nr_spis +
298 VGIC_NR_PRIVATE_IRQS, uaddr);
306 static int vgic_create(struct kvm_device *dev, u32 type)
308 return kvm_vgic_create(dev->kvm, type);
311 static void vgic_destroy(struct kvm_device *dev)
316 int kvm_register_vgic_device(unsigned long type)
321 case KVM_DEV_TYPE_ARM_VGIC_V2:
322 ret = kvm_register_device_ops(&kvm_arm_vgic_v2_ops,
323 KVM_DEV_TYPE_ARM_VGIC_V2);
325 case KVM_DEV_TYPE_ARM_VGIC_V3:
326 ret = kvm_register_device_ops(&kvm_arm_vgic_v3_ops,
327 KVM_DEV_TYPE_ARM_VGIC_V3);
331 ret = kvm_vgic_register_its_device();
338 int vgic_v2_parse_attr(struct kvm_device *dev, struct kvm_device_attr *attr,
339 struct vgic_reg_attr *reg_attr)
343 cpuid = FIELD_GET(KVM_DEV_ARM_VGIC_CPUID_MASK, attr->attr);
345 reg_attr->vcpu = kvm_get_vcpu_by_id(dev->kvm, cpuid);
346 reg_attr->addr = attr->attr & KVM_DEV_ARM_VGIC_OFFSET_MASK;
352 * vgic_v2_attr_regs_access - allows user space to access VGIC v2 state
354 * @dev: kvm device handle
355 * @attr: kvm device attribute
356 * @is_write: true if userspace is writing a register
358 static int vgic_v2_attr_regs_access(struct kvm_device *dev,
359 struct kvm_device_attr *attr,
362 u32 __user *uaddr = (u32 __user *)(unsigned long)attr->addr;
363 struct vgic_reg_attr reg_attr;
365 struct kvm_vcpu *vcpu;
369 ret = vgic_v2_parse_attr(dev, attr, ®_attr);
373 vcpu = reg_attr.vcpu;
374 addr = reg_attr.addr;
377 if (get_user(val, uaddr))
380 mutex_lock(&dev->kvm->lock);
382 if (!lock_all_vcpus(dev->kvm)) {
383 mutex_unlock(&dev->kvm->lock);
387 mutex_lock(&dev->kvm->arch.config_lock);
389 ret = vgic_init(dev->kvm);
393 switch (attr->group) {
394 case KVM_DEV_ARM_VGIC_GRP_CPU_REGS:
395 ret = vgic_v2_cpuif_uaccess(vcpu, is_write, addr, &val);
397 case KVM_DEV_ARM_VGIC_GRP_DIST_REGS:
398 ret = vgic_v2_dist_uaccess(vcpu, is_write, addr, &val);
406 mutex_unlock(&dev->kvm->arch.config_lock);
407 unlock_all_vcpus(dev->kvm);
408 mutex_unlock(&dev->kvm->lock);
410 if (!ret && !is_write)
411 ret = put_user(val, uaddr);
416 static int vgic_v2_set_attr(struct kvm_device *dev,
417 struct kvm_device_attr *attr)
419 switch (attr->group) {
420 case KVM_DEV_ARM_VGIC_GRP_DIST_REGS:
421 case KVM_DEV_ARM_VGIC_GRP_CPU_REGS:
422 return vgic_v2_attr_regs_access(dev, attr, true);
424 return vgic_set_common_attr(dev, attr);
428 static int vgic_v2_get_attr(struct kvm_device *dev,
429 struct kvm_device_attr *attr)
431 switch (attr->group) {
432 case KVM_DEV_ARM_VGIC_GRP_DIST_REGS:
433 case KVM_DEV_ARM_VGIC_GRP_CPU_REGS:
434 return vgic_v2_attr_regs_access(dev, attr, false);
436 return vgic_get_common_attr(dev, attr);
440 static int vgic_v2_has_attr(struct kvm_device *dev,
441 struct kvm_device_attr *attr)
443 switch (attr->group) {
444 case KVM_DEV_ARM_VGIC_GRP_ADDR:
445 switch (attr->attr) {
446 case KVM_VGIC_V2_ADDR_TYPE_DIST:
447 case KVM_VGIC_V2_ADDR_TYPE_CPU:
451 case KVM_DEV_ARM_VGIC_GRP_DIST_REGS:
452 case KVM_DEV_ARM_VGIC_GRP_CPU_REGS:
453 return vgic_v2_has_attr_regs(dev, attr);
454 case KVM_DEV_ARM_VGIC_GRP_NR_IRQS:
456 case KVM_DEV_ARM_VGIC_GRP_CTRL:
457 switch (attr->attr) {
458 case KVM_DEV_ARM_VGIC_CTRL_INIT:
465 struct kvm_device_ops kvm_arm_vgic_v2_ops = {
466 .name = "kvm-arm-vgic-v2",
467 .create = vgic_create,
468 .destroy = vgic_destroy,
469 .set_attr = vgic_v2_set_attr,
470 .get_attr = vgic_v2_get_attr,
471 .has_attr = vgic_v2_has_attr,
474 int vgic_v3_parse_attr(struct kvm_device *dev, struct kvm_device_attr *attr,
475 struct vgic_reg_attr *reg_attr)
477 unsigned long vgic_mpidr, mpidr_reg;
480 * For KVM_DEV_ARM_VGIC_GRP_DIST_REGS group,
481 * attr might not hold MPIDR. Hence assume vcpu0.
483 if (attr->group != KVM_DEV_ARM_VGIC_GRP_DIST_REGS) {
484 vgic_mpidr = (attr->attr & KVM_DEV_ARM_VGIC_V3_MPIDR_MASK) >>
485 KVM_DEV_ARM_VGIC_V3_MPIDR_SHIFT;
487 mpidr_reg = VGIC_TO_MPIDR(vgic_mpidr);
488 reg_attr->vcpu = kvm_mpidr_to_vcpu(dev->kvm, mpidr_reg);
490 reg_attr->vcpu = kvm_get_vcpu(dev->kvm, 0);
496 reg_attr->addr = attr->attr & KVM_DEV_ARM_VGIC_OFFSET_MASK;
502 * vgic_v3_attr_regs_access - allows user space to access VGIC v3 state
504 * @dev: kvm device handle
505 * @attr: kvm device attribute
506 * @is_write: true if userspace is writing a register
508 static int vgic_v3_attr_regs_access(struct kvm_device *dev,
509 struct kvm_device_attr *attr,
512 struct vgic_reg_attr reg_attr;
514 struct kvm_vcpu *vcpu;
519 ret = vgic_v3_parse_attr(dev, attr, ®_attr);
523 vcpu = reg_attr.vcpu;
524 addr = reg_attr.addr;
526 switch (attr->group) {
527 case KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS:
528 /* Sysregs uaccess is performed by the sysreg handling code */
535 if (uaccess && is_write) {
536 u32 __user *uaddr = (u32 __user *)(unsigned long)attr->addr;
537 if (get_user(val, uaddr))
541 mutex_lock(&dev->kvm->lock);
543 if (!lock_all_vcpus(dev->kvm)) {
544 mutex_unlock(&dev->kvm->lock);
548 mutex_lock(&dev->kvm->arch.config_lock);
550 if (unlikely(!vgic_initialized(dev->kvm))) {
555 switch (attr->group) {
556 case KVM_DEV_ARM_VGIC_GRP_DIST_REGS:
557 ret = vgic_v3_dist_uaccess(vcpu, is_write, addr, &val);
559 case KVM_DEV_ARM_VGIC_GRP_REDIST_REGS:
560 ret = vgic_v3_redist_uaccess(vcpu, is_write, addr, &val);
562 case KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS:
563 ret = vgic_v3_cpu_sysregs_uaccess(vcpu, attr, is_write);
565 case KVM_DEV_ARM_VGIC_GRP_LEVEL_INFO: {
566 unsigned int info, intid;
568 info = (attr->attr & KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_MASK) >>
569 KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_SHIFT;
570 if (info == VGIC_LEVEL_INFO_LINE_LEVEL) {
572 KVM_DEV_ARM_VGIC_LINE_LEVEL_INTID_MASK;
573 ret = vgic_v3_line_level_info_uaccess(vcpu, is_write,
586 mutex_unlock(&dev->kvm->arch.config_lock);
587 unlock_all_vcpus(dev->kvm);
588 mutex_unlock(&dev->kvm->lock);
590 if (!ret && uaccess && !is_write) {
591 u32 __user *uaddr = (u32 __user *)(unsigned long)attr->addr;
592 ret = put_user(val, uaddr);
598 static int vgic_v3_set_attr(struct kvm_device *dev,
599 struct kvm_device_attr *attr)
601 switch (attr->group) {
602 case KVM_DEV_ARM_VGIC_GRP_DIST_REGS:
603 case KVM_DEV_ARM_VGIC_GRP_REDIST_REGS:
604 case KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS:
605 case KVM_DEV_ARM_VGIC_GRP_LEVEL_INFO:
606 return vgic_v3_attr_regs_access(dev, attr, true);
608 return vgic_set_common_attr(dev, attr);
612 static int vgic_v3_get_attr(struct kvm_device *dev,
613 struct kvm_device_attr *attr)
615 switch (attr->group) {
616 case KVM_DEV_ARM_VGIC_GRP_DIST_REGS:
617 case KVM_DEV_ARM_VGIC_GRP_REDIST_REGS:
618 case KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS:
619 case KVM_DEV_ARM_VGIC_GRP_LEVEL_INFO:
620 return vgic_v3_attr_regs_access(dev, attr, false);
622 return vgic_get_common_attr(dev, attr);
626 static int vgic_v3_has_attr(struct kvm_device *dev,
627 struct kvm_device_attr *attr)
629 switch (attr->group) {
630 case KVM_DEV_ARM_VGIC_GRP_ADDR:
631 switch (attr->attr) {
632 case KVM_VGIC_V3_ADDR_TYPE_DIST:
633 case KVM_VGIC_V3_ADDR_TYPE_REDIST:
634 case KVM_VGIC_V3_ADDR_TYPE_REDIST_REGION:
638 case KVM_DEV_ARM_VGIC_GRP_DIST_REGS:
639 case KVM_DEV_ARM_VGIC_GRP_REDIST_REGS:
640 case KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS:
641 return vgic_v3_has_attr_regs(dev, attr);
642 case KVM_DEV_ARM_VGIC_GRP_NR_IRQS:
644 case KVM_DEV_ARM_VGIC_GRP_LEVEL_INFO: {
645 if (((attr->attr & KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_MASK) >>
646 KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_SHIFT) ==
647 VGIC_LEVEL_INFO_LINE_LEVEL)
651 case KVM_DEV_ARM_VGIC_GRP_CTRL:
652 switch (attr->attr) {
653 case KVM_DEV_ARM_VGIC_CTRL_INIT:
655 case KVM_DEV_ARM_VGIC_SAVE_PENDING_TABLES:
662 struct kvm_device_ops kvm_arm_vgic_v3_ops = {
663 .name = "kvm-arm-vgic-v3",
664 .create = vgic_create,
665 .destroy = vgic_destroy,
666 .set_attr = vgic_v3_set_attr,
667 .get_attr = vgic_v3_get_attr,
668 .has_attr = vgic_v3_has_attr,