1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2015 ARM Ltd.
6 * Author: Marc Zyngier <marc.zyngier@arm.com>
8 #include <linux/kvm_host.h>
9 #include <kvm/arm_vgic.h>
10 #include <linux/uaccess.h>
11 #include <asm/kvm_mmu.h>
12 #include <asm/cputype.h>
17 int vgic_check_ioaddr(struct kvm *kvm, phys_addr_t *ioaddr,
18 phys_addr_t addr, phys_addr_t alignment)
20 if (addr & ~kvm_phys_mask(kvm))
23 if (!IS_ALIGNED(addr, alignment))
26 if (!IS_VGIC_ADDR_UNDEF(*ioaddr))
32 static int vgic_check_type(struct kvm *kvm, int type_needed)
34 if (kvm->arch.vgic.vgic_model != type_needed)
41 * kvm_vgic_addr - set or get vgic VM base addresses
42 * @kvm: pointer to the vm struct
43 * @type: the VGIC addr type, one of KVM_VGIC_V[23]_ADDR_TYPE_XXX
44 * @addr: pointer to address value
45 * @write: if true set the address in the VM address space, if false read the
48 * Set or get the vgic base addresses for the distributor and the virtual CPU
49 * interface in the VM physical address space. These addresses are properties
50 * of the emulated core/SoC and therefore user space initially knows this
52 * Check them for sanity (alignment, double assignment). We can't check for
53 * overlapping regions in case of a virtual GICv3 here, since we don't know
54 * the number of VCPUs yet, so we defer this check to map_resources().
56 int kvm_vgic_addr(struct kvm *kvm, unsigned long type, u64 *addr, bool write)
59 struct vgic_dist *vgic = &kvm->arch.vgic;
60 phys_addr_t *addr_ptr, alignment;
61 u64 undef_value = VGIC_ADDR_UNDEF;
63 mutex_lock(&kvm->lock);
65 case KVM_VGIC_V2_ADDR_TYPE_DIST:
66 r = vgic_check_type(kvm, KVM_DEV_TYPE_ARM_VGIC_V2);
67 addr_ptr = &vgic->vgic_dist_base;
70 case KVM_VGIC_V2_ADDR_TYPE_CPU:
71 r = vgic_check_type(kvm, KVM_DEV_TYPE_ARM_VGIC_V2);
72 addr_ptr = &vgic->vgic_cpu_base;
75 case KVM_VGIC_V3_ADDR_TYPE_DIST:
76 r = vgic_check_type(kvm, KVM_DEV_TYPE_ARM_VGIC_V3);
77 addr_ptr = &vgic->vgic_dist_base;
80 case KVM_VGIC_V3_ADDR_TYPE_REDIST: {
81 struct vgic_redist_region *rdreg;
83 r = vgic_check_type(kvm, KVM_DEV_TYPE_ARM_VGIC_V3);
87 r = vgic_v3_set_redist_base(kvm, 0, *addr, 0);
90 rdreg = list_first_entry_or_null(&vgic->rd_regions,
91 struct vgic_redist_region, list);
93 addr_ptr = &undef_value;
95 addr_ptr = &rdreg->base;
98 case KVM_VGIC_V3_ADDR_TYPE_REDIST_REGION:
100 struct vgic_redist_region *rdreg;
103 r = vgic_check_type(kvm, KVM_DEV_TYPE_ARM_VGIC_V3);
107 index = *addr & KVM_VGIC_V3_RDIST_INDEX_MASK;
110 gpa_t base = *addr & KVM_VGIC_V3_RDIST_BASE_MASK;
111 u32 count = (*addr & KVM_VGIC_V3_RDIST_COUNT_MASK)
112 >> KVM_VGIC_V3_RDIST_COUNT_SHIFT;
113 u8 flags = (*addr & KVM_VGIC_V3_RDIST_FLAGS_MASK)
114 >> KVM_VGIC_V3_RDIST_FLAGS_SHIFT;
119 r = vgic_v3_set_redist_base(kvm, index,
124 rdreg = vgic_v3_rdist_region_from_index(kvm, index);
131 *addr |= rdreg->base;
132 *addr |= (u64)rdreg->count << KVM_VGIC_V3_RDIST_COUNT_SHIFT;
143 r = vgic_check_ioaddr(kvm, addr_ptr, *addr, alignment);
151 mutex_unlock(&kvm->lock);
155 static int vgic_set_common_attr(struct kvm_device *dev,
156 struct kvm_device_attr *attr)
160 switch (attr->group) {
161 case KVM_DEV_ARM_VGIC_GRP_ADDR: {
162 u64 __user *uaddr = (u64 __user *)(long)attr->addr;
164 unsigned long type = (unsigned long)attr->attr;
166 if (copy_from_user(&addr, uaddr, sizeof(addr)))
169 r = kvm_vgic_addr(dev->kvm, type, &addr, true);
170 return (r == -ENODEV) ? -ENXIO : r;
172 case KVM_DEV_ARM_VGIC_GRP_NR_IRQS: {
173 u32 __user *uaddr = (u32 __user *)(long)attr->addr;
177 if (get_user(val, uaddr))
182 * - at least 32 SPIs on top of the 16 SGIs and 16 PPIs
183 * - at most 1024 interrupts
184 * - a multiple of 32 interrupts
186 if (val < (VGIC_NR_PRIVATE_IRQS + 32) ||
187 val > VGIC_MAX_RESERVED ||
191 mutex_lock(&dev->kvm->lock);
193 if (vgic_ready(dev->kvm) || dev->kvm->arch.vgic.nr_spis)
196 dev->kvm->arch.vgic.nr_spis =
197 val - VGIC_NR_PRIVATE_IRQS;
199 mutex_unlock(&dev->kvm->lock);
203 case KVM_DEV_ARM_VGIC_GRP_CTRL: {
204 switch (attr->attr) {
205 case KVM_DEV_ARM_VGIC_CTRL_INIT:
206 mutex_lock(&dev->kvm->lock);
207 r = vgic_init(dev->kvm);
208 mutex_unlock(&dev->kvm->lock);
218 static int vgic_get_common_attr(struct kvm_device *dev,
219 struct kvm_device_attr *attr)
223 switch (attr->group) {
224 case KVM_DEV_ARM_VGIC_GRP_ADDR: {
225 u64 __user *uaddr = (u64 __user *)(long)attr->addr;
227 unsigned long type = (unsigned long)attr->attr;
229 if (copy_from_user(&addr, uaddr, sizeof(addr)))
232 r = kvm_vgic_addr(dev->kvm, type, &addr, false);
234 return (r == -ENODEV) ? -ENXIO : r;
236 if (copy_to_user(uaddr, &addr, sizeof(addr)))
240 case KVM_DEV_ARM_VGIC_GRP_NR_IRQS: {
241 u32 __user *uaddr = (u32 __user *)(long)attr->addr;
243 r = put_user(dev->kvm->arch.vgic.nr_spis +
244 VGIC_NR_PRIVATE_IRQS, uaddr);
252 static int vgic_create(struct kvm_device *dev, u32 type)
254 return kvm_vgic_create(dev->kvm, type);
257 static void vgic_destroy(struct kvm_device *dev)
262 int kvm_register_vgic_device(unsigned long type)
267 case KVM_DEV_TYPE_ARM_VGIC_V2:
268 ret = kvm_register_device_ops(&kvm_arm_vgic_v2_ops,
269 KVM_DEV_TYPE_ARM_VGIC_V2);
271 case KVM_DEV_TYPE_ARM_VGIC_V3:
272 ret = kvm_register_device_ops(&kvm_arm_vgic_v3_ops,
273 KVM_DEV_TYPE_ARM_VGIC_V3);
277 ret = kvm_vgic_register_its_device();
284 int vgic_v2_parse_attr(struct kvm_device *dev, struct kvm_device_attr *attr,
285 struct vgic_reg_attr *reg_attr)
289 cpuid = (attr->attr & KVM_DEV_ARM_VGIC_CPUID_MASK) >>
290 KVM_DEV_ARM_VGIC_CPUID_SHIFT;
292 if (cpuid >= atomic_read(&dev->kvm->online_vcpus))
295 reg_attr->vcpu = kvm_get_vcpu(dev->kvm, cpuid);
296 reg_attr->addr = attr->attr & KVM_DEV_ARM_VGIC_OFFSET_MASK;
301 /* unlocks vcpus from @vcpu_lock_idx and smaller */
302 static void unlock_vcpus(struct kvm *kvm, int vcpu_lock_idx)
304 struct kvm_vcpu *tmp_vcpu;
306 for (; vcpu_lock_idx >= 0; vcpu_lock_idx--) {
307 tmp_vcpu = kvm_get_vcpu(kvm, vcpu_lock_idx);
308 mutex_unlock(&tmp_vcpu->mutex);
312 void unlock_all_vcpus(struct kvm *kvm)
314 unlock_vcpus(kvm, atomic_read(&kvm->online_vcpus) - 1);
317 /* Returns true if all vcpus were locked, false otherwise */
318 bool lock_all_vcpus(struct kvm *kvm)
320 struct kvm_vcpu *tmp_vcpu;
324 * Any time a vcpu is run, vcpu_load is called which tries to grab the
325 * vcpu->mutex. By grabbing the vcpu->mutex of all VCPUs we ensure
326 * that no other VCPUs are run and fiddle with the vgic state while we
329 kvm_for_each_vcpu(c, tmp_vcpu, kvm) {
330 if (!mutex_trylock(&tmp_vcpu->mutex)) {
331 unlock_vcpus(kvm, c - 1);
340 * vgic_v2_attr_regs_access - allows user space to access VGIC v2 state
342 * @dev: kvm device handle
343 * @attr: kvm device attribute
344 * @reg: address the value is read or written
345 * @is_write: true if userspace is writing a register
347 static int vgic_v2_attr_regs_access(struct kvm_device *dev,
348 struct kvm_device_attr *attr,
349 u32 *reg, bool is_write)
351 struct vgic_reg_attr reg_attr;
353 struct kvm_vcpu *vcpu;
356 ret = vgic_v2_parse_attr(dev, attr, ®_attr);
360 vcpu = reg_attr.vcpu;
361 addr = reg_attr.addr;
363 mutex_lock(&dev->kvm->lock);
365 ret = vgic_init(dev->kvm);
369 if (!lock_all_vcpus(dev->kvm)) {
374 switch (attr->group) {
375 case KVM_DEV_ARM_VGIC_GRP_CPU_REGS:
376 ret = vgic_v2_cpuif_uaccess(vcpu, is_write, addr, reg);
378 case KVM_DEV_ARM_VGIC_GRP_DIST_REGS:
379 ret = vgic_v2_dist_uaccess(vcpu, is_write, addr, reg);
386 unlock_all_vcpus(dev->kvm);
388 mutex_unlock(&dev->kvm->lock);
392 static int vgic_v2_set_attr(struct kvm_device *dev,
393 struct kvm_device_attr *attr)
397 ret = vgic_set_common_attr(dev, attr);
401 switch (attr->group) {
402 case KVM_DEV_ARM_VGIC_GRP_DIST_REGS:
403 case KVM_DEV_ARM_VGIC_GRP_CPU_REGS: {
404 u32 __user *uaddr = (u32 __user *)(long)attr->addr;
407 if (get_user(reg, uaddr))
410 return vgic_v2_attr_regs_access(dev, attr, ®, true);
417 static int vgic_v2_get_attr(struct kvm_device *dev,
418 struct kvm_device_attr *attr)
422 ret = vgic_get_common_attr(dev, attr);
426 switch (attr->group) {
427 case KVM_DEV_ARM_VGIC_GRP_DIST_REGS:
428 case KVM_DEV_ARM_VGIC_GRP_CPU_REGS: {
429 u32 __user *uaddr = (u32 __user *)(long)attr->addr;
432 ret = vgic_v2_attr_regs_access(dev, attr, ®, false);
435 return put_user(reg, uaddr);
442 static int vgic_v2_has_attr(struct kvm_device *dev,
443 struct kvm_device_attr *attr)
445 switch (attr->group) {
446 case KVM_DEV_ARM_VGIC_GRP_ADDR:
447 switch (attr->attr) {
448 case KVM_VGIC_V2_ADDR_TYPE_DIST:
449 case KVM_VGIC_V2_ADDR_TYPE_CPU:
453 case KVM_DEV_ARM_VGIC_GRP_DIST_REGS:
454 case KVM_DEV_ARM_VGIC_GRP_CPU_REGS:
455 return vgic_v2_has_attr_regs(dev, attr);
456 case KVM_DEV_ARM_VGIC_GRP_NR_IRQS:
458 case KVM_DEV_ARM_VGIC_GRP_CTRL:
459 switch (attr->attr) {
460 case KVM_DEV_ARM_VGIC_CTRL_INIT:
467 struct kvm_device_ops kvm_arm_vgic_v2_ops = {
468 .name = "kvm-arm-vgic-v2",
469 .create = vgic_create,
470 .destroy = vgic_destroy,
471 .set_attr = vgic_v2_set_attr,
472 .get_attr = vgic_v2_get_attr,
473 .has_attr = vgic_v2_has_attr,
476 int vgic_v3_parse_attr(struct kvm_device *dev, struct kvm_device_attr *attr,
477 struct vgic_reg_attr *reg_attr)
479 unsigned long vgic_mpidr, mpidr_reg;
482 * For KVM_DEV_ARM_VGIC_GRP_DIST_REGS group,
483 * attr might not hold MPIDR. Hence assume vcpu0.
485 if (attr->group != KVM_DEV_ARM_VGIC_GRP_DIST_REGS) {
486 vgic_mpidr = (attr->attr & KVM_DEV_ARM_VGIC_V3_MPIDR_MASK) >>
487 KVM_DEV_ARM_VGIC_V3_MPIDR_SHIFT;
489 mpidr_reg = VGIC_TO_MPIDR(vgic_mpidr);
490 reg_attr->vcpu = kvm_mpidr_to_vcpu(dev->kvm, mpidr_reg);
492 reg_attr->vcpu = kvm_get_vcpu(dev->kvm, 0);
498 reg_attr->addr = attr->attr & KVM_DEV_ARM_VGIC_OFFSET_MASK;
504 * vgic_v3_attr_regs_access - allows user space to access VGIC v3 state
506 * @dev: kvm device handle
507 * @attr: kvm device attribute
508 * @reg: address the value is read or written
509 * @is_write: true if userspace is writing a register
511 static int vgic_v3_attr_regs_access(struct kvm_device *dev,
512 struct kvm_device_attr *attr,
513 u64 *reg, bool is_write)
515 struct vgic_reg_attr reg_attr;
517 struct kvm_vcpu *vcpu;
521 ret = vgic_v3_parse_attr(dev, attr, ®_attr);
525 vcpu = reg_attr.vcpu;
526 addr = reg_attr.addr;
528 mutex_lock(&dev->kvm->lock);
530 if (unlikely(!vgic_initialized(dev->kvm))) {
535 if (!lock_all_vcpus(dev->kvm)) {
540 switch (attr->group) {
541 case KVM_DEV_ARM_VGIC_GRP_DIST_REGS:
545 ret = vgic_v3_dist_uaccess(vcpu, is_write, addr, &tmp32);
549 case KVM_DEV_ARM_VGIC_GRP_REDIST_REGS:
553 ret = vgic_v3_redist_uaccess(vcpu, is_write, addr, &tmp32);
557 case KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS: {
560 regid = (attr->attr & KVM_DEV_ARM_VGIC_SYSREG_INSTR_MASK);
561 ret = vgic_v3_cpu_sysregs_uaccess(vcpu, is_write,
565 case KVM_DEV_ARM_VGIC_GRP_LEVEL_INFO: {
566 unsigned int info, intid;
568 info = (attr->attr & KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_MASK) >>
569 KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_SHIFT;
570 if (info == VGIC_LEVEL_INFO_LINE_LEVEL) {
572 KVM_DEV_ARM_VGIC_LINE_LEVEL_INTID_MASK;
573 ret = vgic_v3_line_level_info_uaccess(vcpu, is_write,
585 unlock_all_vcpus(dev->kvm);
587 mutex_unlock(&dev->kvm->lock);
591 static int vgic_v3_set_attr(struct kvm_device *dev,
592 struct kvm_device_attr *attr)
596 ret = vgic_set_common_attr(dev, attr);
600 switch (attr->group) {
601 case KVM_DEV_ARM_VGIC_GRP_DIST_REGS:
602 case KVM_DEV_ARM_VGIC_GRP_REDIST_REGS: {
603 u32 __user *uaddr = (u32 __user *)(long)attr->addr;
607 if (get_user(tmp32, uaddr))
611 return vgic_v3_attr_regs_access(dev, attr, ®, true);
613 case KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS: {
614 u64 __user *uaddr = (u64 __user *)(long)attr->addr;
617 if (get_user(reg, uaddr))
620 return vgic_v3_attr_regs_access(dev, attr, ®, true);
622 case KVM_DEV_ARM_VGIC_GRP_LEVEL_INFO: {
623 u32 __user *uaddr = (u32 __user *)(long)attr->addr;
627 if (get_user(tmp32, uaddr))
631 return vgic_v3_attr_regs_access(dev, attr, ®, true);
633 case KVM_DEV_ARM_VGIC_GRP_CTRL: {
636 switch (attr->attr) {
637 case KVM_DEV_ARM_VGIC_SAVE_PENDING_TABLES:
638 mutex_lock(&dev->kvm->lock);
640 if (!lock_all_vcpus(dev->kvm)) {
641 mutex_unlock(&dev->kvm->lock);
644 ret = vgic_v3_save_pending_tables(dev->kvm);
645 unlock_all_vcpus(dev->kvm);
646 mutex_unlock(&dev->kvm->lock);
655 static int vgic_v3_get_attr(struct kvm_device *dev,
656 struct kvm_device_attr *attr)
660 ret = vgic_get_common_attr(dev, attr);
664 switch (attr->group) {
665 case KVM_DEV_ARM_VGIC_GRP_DIST_REGS:
666 case KVM_DEV_ARM_VGIC_GRP_REDIST_REGS: {
667 u32 __user *uaddr = (u32 __user *)(long)attr->addr;
671 ret = vgic_v3_attr_regs_access(dev, attr, ®, false);
675 return put_user(tmp32, uaddr);
677 case KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS: {
678 u64 __user *uaddr = (u64 __user *)(long)attr->addr;
681 ret = vgic_v3_attr_regs_access(dev, attr, ®, false);
684 return put_user(reg, uaddr);
686 case KVM_DEV_ARM_VGIC_GRP_LEVEL_INFO: {
687 u32 __user *uaddr = (u32 __user *)(long)attr->addr;
691 ret = vgic_v3_attr_regs_access(dev, attr, ®, false);
695 return put_user(tmp32, uaddr);
701 static int vgic_v3_has_attr(struct kvm_device *dev,
702 struct kvm_device_attr *attr)
704 switch (attr->group) {
705 case KVM_DEV_ARM_VGIC_GRP_ADDR:
706 switch (attr->attr) {
707 case KVM_VGIC_V3_ADDR_TYPE_DIST:
708 case KVM_VGIC_V3_ADDR_TYPE_REDIST:
709 case KVM_VGIC_V3_ADDR_TYPE_REDIST_REGION:
713 case KVM_DEV_ARM_VGIC_GRP_DIST_REGS:
714 case KVM_DEV_ARM_VGIC_GRP_REDIST_REGS:
715 case KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS:
716 return vgic_v3_has_attr_regs(dev, attr);
717 case KVM_DEV_ARM_VGIC_GRP_NR_IRQS:
719 case KVM_DEV_ARM_VGIC_GRP_LEVEL_INFO: {
720 if (((attr->attr & KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_MASK) >>
721 KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_SHIFT) ==
722 VGIC_LEVEL_INFO_LINE_LEVEL)
726 case KVM_DEV_ARM_VGIC_GRP_CTRL:
727 switch (attr->attr) {
728 case KVM_DEV_ARM_VGIC_CTRL_INIT:
730 case KVM_DEV_ARM_VGIC_SAVE_PENDING_TABLES:
737 struct kvm_device_ops kvm_arm_vgic_v3_ops = {
738 .name = "kvm-arm-vgic-v3",
739 .create = vgic_create,
740 .destroy = vgic_destroy,
741 .set_attr = vgic_v3_set_attr,
742 .get_attr = vgic_v3_get_attr,
743 .has_attr = vgic_v3_has_attr,