arch/arm64/kvm/sys_regs.c

   1 /*
   2  * Copyright (C) 2012,2013 - ARM Ltd
   3  * Author: Marc Zyngier <marc.zyngier@arm.com>
   4  *
   5  * Derived from arch/arm/kvm/coproc.c:
   6  * Copyright (C) 2012 - Virtual Open Systems and Columbia University
   7  * Authors: Rusty Russell <rusty@rustcorp.com.au>
   8  *          Christoffer Dall <c.dall@virtualopensystems.com>
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License, version 2, as
  12  * published by the Free Software Foundation.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  21  */
  22
  23 #include <linux/bsearch.h>
  24 #include <linux/kvm_host.h>
  25 #include <linux/mm.h>
  26 #include <linux/printk.h>
  27 #include <linux/uaccess.h>
  28
  29 #include <asm/cacheflush.h>
  30 #include <asm/cputype.h>
  31 #include <asm/debug-monitors.h>
  32 #include <asm/esr.h>
  33 #include <asm/kvm_arm.h>
  34 #include <asm/kvm_coproc.h>
  35 #include <asm/kvm_emulate.h>
  36 #include <asm/kvm_host.h>
  37 #include <asm/kvm_hyp.h>
  38 #include <asm/kvm_mmu.h>
  39 #include <asm/perf_event.h>
  40 #include <asm/sysreg.h>
  41
  42 #include <trace/events/kvm.h>
  43
  44 #include "sys_regs.h"
  45
  46 #include "trace.h"
  47
  48 /*
  49  * All of this file is extremly similar to the ARM coproc.c, but the
  50  * types are different. My gut feeling is that it should be pretty
  51  * easy to merge, but that would be an ABI breakage -- again. VFP
  52  * would also need to be abstracted.
  53  *
  54  * For AArch32, we only take care of what is being trapped. Anything
  55  * that has to do with init and userspace access has to go via the
  56  * 64bit interface.
  57  */
  58
  59 static bool read_from_write_only(struct kvm_vcpu *vcpu,
  60                                  struct sys_reg_params *params,
  61                                  const struct sys_reg_desc *r)
  62 {
  63         WARN_ONCE(1, "Unexpected sys_reg read to write-only register\n");
  64         print_sys_reg_instr(params);
  65         kvm_inject_undefined(vcpu);
  66         return false;
  67 }
  68
  69 static bool write_to_read_only(struct kvm_vcpu *vcpu,
  70                                struct sys_reg_params *params,
  71                                const struct sys_reg_desc *r)
  72 {
  73         WARN_ONCE(1, "Unexpected sys_reg write to read-only register\n");
  74         print_sys_reg_instr(params);
  75         kvm_inject_undefined(vcpu);
  76         return false;
  77 }
  78
  79 u64 vcpu_read_sys_reg(struct kvm_vcpu *vcpu, int reg)
  80 {
  81         if (!vcpu->arch.sysregs_loaded_on_cpu)
  82                 goto immediate_read;
  83
  84         /*
  85          * System registers listed in the switch are not saved on every
  86          * exit from the guest but are only saved on vcpu_put.
  87          *
  88          * Note that MPIDR_EL1 for the guest is set by KVM via VMPIDR_EL2 but
  89          * should never be listed below, because the guest cannot modify its
  90          * own MPIDR_EL1 and MPIDR_EL1 is accessed for VCPU A from VCPU B's
  91          * thread when emulating cross-VCPU communication.
  92          */
  93         switch (reg) {
  94         case CSSELR_EL1:        return read_sysreg_s(SYS_CSSELR_EL1);
  95         case SCTLR_EL1:         return read_sysreg_s(sctlr_EL12);
  96         case ACTLR_EL1:         return read_sysreg_s(SYS_ACTLR_EL1);
  97         case CPACR_EL1:         return read_sysreg_s(cpacr_EL12);
  98         case TTBR0_EL1:         return read_sysreg_s(ttbr0_EL12);
  99         case TTBR1_EL1:         return read_sysreg_s(ttbr1_EL12);
 100         case TCR_EL1:           return read_sysreg_s(tcr_EL12);
 101         case ESR_EL1:           return read_sysreg_s(esr_EL12);
 102         case AFSR0_EL1:         return read_sysreg_s(afsr0_EL12);
 103         case AFSR1_EL1:         return read_sysreg_s(afsr1_EL12);
 104         case FAR_EL1:           return read_sysreg_s(far_EL12);
 105         case MAIR_EL1:          return read_sysreg_s(mair_EL12);
 106         case VBAR_EL1:          return read_sysreg_s(vbar_EL12);
 107         case CONTEXTIDR_EL1:    return read_sysreg_s(contextidr_EL12);
 108         case TPIDR_EL0:         return read_sysreg_s(SYS_TPIDR_EL0);
 109         case TPIDRRO_EL0:       return read_sysreg_s(SYS_TPIDRRO_EL0);
 110         case TPIDR_EL1:         return read_sysreg_s(SYS_TPIDR_EL1);
 111         case AMAIR_EL1:         return read_sysreg_s(amair_EL12);
 112         case CNTKCTL_EL1:       return read_sysreg_s(cntkctl_EL12);
 113         case PAR_EL1:           return read_sysreg_s(SYS_PAR_EL1);
 114         case DACR32_EL2:        return read_sysreg_s(SYS_DACR32_EL2);
 115         case IFSR32_EL2:        return read_sysreg_s(SYS_IFSR32_EL2);
 116         case DBGVCR32_EL2:      return read_sysreg_s(SYS_DBGVCR32_EL2);
 117         }
 118
 119 immediate_read:
 120         return __vcpu_sys_reg(vcpu, reg);
 121 }
 122
 123 void vcpu_write_sys_reg(struct kvm_vcpu *vcpu, u64 val, int reg)
 124 {
 125         if (!vcpu->arch.sysregs_loaded_on_cpu)
 126                 goto immediate_write;
 127
 128         /*
 129          * System registers listed in the switch are not restored on every
 130          * entry to the guest but are only restored on vcpu_load.
 131          *
 132          * Note that MPIDR_EL1 for the guest is set by KVM via VMPIDR_EL2 but
 133          * should never be listed below, because the the MPIDR should only be
 134          * set once, before running the VCPU, and never changed later.
 135          */
 136         switch (reg) {
 137         case CSSELR_EL1:        write_sysreg_s(val, SYS_CSSELR_EL1);    return;
 138         case SCTLR_EL1:         write_sysreg_s(val, sctlr_EL12);        return;
 139         case ACTLR_EL1:         write_sysreg_s(val, SYS_ACTLR_EL1);     return;
 140         case CPACR_EL1:         write_sysreg_s(val, cpacr_EL12);        return;
 141         case TTBR0_EL1:         write_sysreg_s(val, ttbr0_EL12);        return;
 142         case TTBR1_EL1:         write_sysreg_s(val, ttbr1_EL12);        return;
 143         case TCR_EL1:           write_sysreg_s(val, tcr_EL12);          return;
 144         case ESR_EL1:           write_sysreg_s(val, esr_EL12);          return;
 145         case AFSR0_EL1:         write_sysreg_s(val, afsr0_EL12);        return;
 146         case AFSR1_EL1:         write_sysreg_s(val, afsr1_EL12);        return;
 147         case FAR_EL1:           write_sysreg_s(val, far_EL12);          return;
 148         case MAIR_EL1:          write_sysreg_s(val, mair_EL12);         return;
 149         case VBAR_EL1:          write_sysreg_s(val, vbar_EL12);         return;
 150         case CONTEXTIDR_EL1:    write_sysreg_s(val, contextidr_EL12);   return;
 151         case TPIDR_EL0:         write_sysreg_s(val, SYS_TPIDR_EL0);     return;
 152         case TPIDRRO_EL0:       write_sysreg_s(val, SYS_TPIDRRO_EL0);   return;
 153         case TPIDR_EL1:         write_sysreg_s(val, SYS_TPIDR_EL1);     return;
 154         case AMAIR_EL1:         write_sysreg_s(val, amair_EL12);        return;
 155         case CNTKCTL_EL1:       write_sysreg_s(val, cntkctl_EL12);      return;
 156         case PAR_EL1:           write_sysreg_s(val, SYS_PAR_EL1);       return;
 157         case DACR32_EL2:        write_sysreg_s(val, SYS_DACR32_EL2);    return;
 158         case IFSR32_EL2:        write_sysreg_s(val, SYS_IFSR32_EL2);    return;
 159         case DBGVCR32_EL2:      write_sysreg_s(val, SYS_DBGVCR32_EL2);  return;
 160         }
 161
 162 immediate_write:
 163          __vcpu_sys_reg(vcpu, reg) = val;
 164 }
 165
 166 /* 3 bits per cache level, as per CLIDR, but non-existent caches always 0 */
 167 static u32 cache_levels;
 168
 169 /* CSSELR values; used to index KVM_REG_ARM_DEMUX_ID_CCSIDR */
 170 #define CSSELR_MAX 12
 171
 172 /* Which cache CCSIDR represents depends on CSSELR value. */
 173 static u32 get_ccsidr(u32 csselr)
 174 {
 175         u32 ccsidr;
 176
 177         /* Make sure noone else changes CSSELR during this! */
 178         local_irq_disable();
 179         write_sysreg(csselr, csselr_el1);
 180         isb();
 181         ccsidr = read_sysreg(ccsidr_el1);
 182         local_irq_enable();
 183
 184         return ccsidr;
 185 }
 186
 187 /*
 188  * See note at ARMv7 ARM B1.14.4 (TL;DR: S/W ops are not easily virtualized).
 189  */
 190 static bool access_dcsw(struct kvm_vcpu *vcpu,
 191                         struct sys_reg_params *p,
 192                         const struct sys_reg_desc *r)
 193 {
 194         if (!p->is_write)
 195                 return read_from_write_only(vcpu, p, r);
 196
 197         /*
 198          * Only track S/W ops if we don't have FWB. It still indicates
 199          * that the guest is a bit broken (S/W operations should only
 200          * be done by firmware, knowing that there is only a single
 201          * CPU left in the system, and certainly not from non-secure
 202          * software).
 203          */
 204         if (!cpus_have_const_cap(ARM64_HAS_STAGE2_FWB))
 205                 kvm_set_way_flush(vcpu);
 206
 207         return true;
 208 }
 209
 210 /*
 211  * Generic accessor for VM registers. Only called as long as HCR_TVM
 212  * is set. If the guest enables the MMU, we stop trapping the VM
 213  * sys_regs and leave it in complete control of the caches.
 214  */
 215 static bool access_vm_reg(struct kvm_vcpu *vcpu,
 216                           struct sys_reg_params *p,
 217                           const struct sys_reg_desc *r)
 218 {
 219         bool was_enabled = vcpu_has_cache_enabled(vcpu);
 220         u64 val;
 221         int reg = r->reg;
 222
 223         BUG_ON(!p->is_write);
 224
 225         /* See the 32bit mapping in kvm_host.h */
 226         if (p->is_aarch32)
 227                 reg = r->reg / 2;
 228
 229         if (!p->is_aarch32 || !p->is_32bit) {
 230                 val = p->regval;
 231         } else {
 232                 val = vcpu_read_sys_reg(vcpu, reg);
 233                 if (r->reg % 2)
 234                         val = (p->regval << 32) | (u64)lower_32_bits(val);
 235                 else
 236                         val = ((u64)upper_32_bits(val) << 32) |
 237                                 lower_32_bits(p->regval);
 238         }
 239         vcpu_write_sys_reg(vcpu, val, reg);
 240
 241         kvm_toggle_cache(vcpu, was_enabled);
 242         return true;
 243 }
 244
 245 /*
 246  * Trap handler for the GICv3 SGI generation system register.
 247  * Forward the request to the VGIC emulation.
 248  * The cp15_64 code makes sure this automatically works
 249  * for both AArch64 and AArch32 accesses.
 250  */
 251 static bool access_gic_sgi(struct kvm_vcpu *vcpu,
 252                            struct sys_reg_params *p,
 253                            const struct sys_reg_desc *r)
 254 {
 255         bool g1;
 256
 257         if (!p->is_write)
 258                 return read_from_write_only(vcpu, p, r);
 259
 260         /*
 261          * In a system where GICD_CTLR.DS=1, a ICC_SGI0R_EL1 access generates
 262          * Group0 SGIs only, while ICC_SGI1R_EL1 can generate either group,
 263          * depending on the SGI configuration. ICC_ASGI1R_EL1 is effectively
 264          * equivalent to ICC_SGI0R_EL1, as there is no "alternative" secure
 265          * group.
 266          */
 267         if (p->is_aarch32) {
 268                 switch (p->Op1) {
 269                 default:                /* Keep GCC quiet */
 270                 case 0:                 /* ICC_SGI1R */
 271                         g1 = true;
 272                         break;
 273                 case 1:                 /* ICC_ASGI1R */
 274                 case 2:                 /* ICC_SGI0R */
 275                         g1 = false;
 276                         break;
 277                 }
 278         } else {
 279                 switch (p->Op2) {
 280                 default:                /* Keep GCC quiet */
 281                 case 5:                 /* ICC_SGI1R_EL1 */
 282                         g1 = true;
 283                         break;
 284                 case 6:                 /* ICC_ASGI1R_EL1 */
 285                 case 7:                 /* ICC_SGI0R_EL1 */
 286                         g1 = false;
 287                         break;
 288                 }
 289         }
 290
 291         vgic_v3_dispatch_sgi(vcpu, p->regval, g1);
 292
 293         return true;
 294 }
 295
 296 static bool access_gic_sre(struct kvm_vcpu *vcpu,
 297                            struct sys_reg_params *p,
 298                            const struct sys_reg_desc *r)
 299 {
 300         if (p->is_write)
 301                 return ignore_write(vcpu, p);
 302
 303         p->regval = vcpu->arch.vgic_cpu.vgic_v3.vgic_sre;
 304         return true;
 305 }
 306
 307 static bool trap_raz_wi(struct kvm_vcpu *vcpu,
 308                         struct sys_reg_params *p,
 309                         const struct sys_reg_desc *r)
 310 {
 311         if (p->is_write)
 312                 return ignore_write(vcpu, p);
 313         else
 314                 return read_zero(vcpu, p);
 315 }
 316
 317 static bool trap_undef(struct kvm_vcpu *vcpu,
 318                        struct sys_reg_params *p,
 319                        const struct sys_reg_desc *r)
 320 {
 321         kvm_inject_undefined(vcpu);
 322         return false;
 323 }
 324
 325 static bool trap_oslsr_el1(struct kvm_vcpu *vcpu,
 326                            struct sys_reg_params *p,
 327                            const struct sys_reg_desc *r)
 328 {
 329         if (p->is_write) {
 330                 return ignore_write(vcpu, p);
 331         } else {
 332                 p->regval = (1 << 3);
 333                 return true;
 334         }
 335 }
 336
 337 static bool trap_dbgauthstatus_el1(struct kvm_vcpu *vcpu,
 338                                    struct sys_reg_params *p,
 339                                    const struct sys_reg_desc *r)
 340 {
 341         if (p->is_write) {
 342                 return ignore_write(vcpu, p);
 343         } else {
 344                 p->regval = read_sysreg(dbgauthstatus_el1);
 345                 return true;
 346         }
 347 }
 348
 349 /*
 350  * We want to avoid world-switching all the DBG registers all the
 351  * time:
 352  *
 353  * - If we've touched any debug register, it is likely that we're
 354  *   going to touch more of them. It then makes sense to disable the
 355  *   traps and start doing the save/restore dance
 356  * - If debug is active (DBG_MDSCR_KDE or DBG_MDSCR_MDE set), it is
 357  *   then mandatory to save/restore the registers, as the guest
 358  *   depends on them.
 359  *
 360  * For this, we use a DIRTY bit, indicating the guest has modified the
 361  * debug registers, used as follow:
 362  *
 363  * On guest entry:
 364  * - If the dirty bit is set (because we're coming back from trapping),
 365  *   disable the traps, save host registers, restore guest registers.
 366  * - If debug is actively in use (DBG_MDSCR_KDE or DBG_MDSCR_MDE set),
 367  *   set the dirty bit, disable the traps, save host registers,
 368  *   restore guest registers.
 369  * - Otherwise, enable the traps
 370  *
 371  * On guest exit:
 372  * - If the dirty bit is set, save guest registers, restore host
 373  *   registers and clear the dirty bit. This ensure that the host can
 374  *   now use the debug registers.
 375  */
 376 static bool trap_debug_regs(struct kvm_vcpu *vcpu,
 377                             struct sys_reg_params *p,
 378                             const struct sys_reg_desc *r)
 379 {
 380         if (p->is_write) {
 381                 vcpu_write_sys_reg(vcpu, p->regval, r->reg);
 382                 vcpu->arch.flags |= KVM_ARM64_DEBUG_DIRTY;
 383         } else {
 384                 p->regval = vcpu_read_sys_reg(vcpu, r->reg);
 385         }
 386
 387         trace_trap_reg(__func__, r->reg, p->is_write, p->regval);
 388
 389         return true;
 390 }
 391
 392 /*
 393  * reg_to_dbg/dbg_to_reg
 394  *
 395  * A 32 bit write to a debug register leave top bits alone
 396  * A 32 bit read from a debug register only returns the bottom bits
 397  *
 398  * All writes will set the KVM_ARM64_DEBUG_DIRTY flag to ensure the
 399  * hyp.S code switches between host and guest values in future.
 400  */
 401 static void reg_to_dbg(struct kvm_vcpu *vcpu,
 402                        struct sys_reg_params *p,
 403                        u64 *dbg_reg)
 404 {
 405         u64 val = p->regval;
 406
 407         if (p->is_32bit) {
 408                 val &= 0xffffffffUL;
 409                 val |= ((*dbg_reg >> 32) << 32);
 410         }
 411
 412         *dbg_reg = val;
 413         vcpu->arch.flags |= KVM_ARM64_DEBUG_DIRTY;
 414 }
 415
 416 static void dbg_to_reg(struct kvm_vcpu *vcpu,
 417                        struct sys_reg_params *p,
 418                        u64 *dbg_reg)
 419 {
 420         p->regval = *dbg_reg;
 421         if (p->is_32bit)
 422                 p->regval &= 0xffffffffUL;
 423 }
 424
 425 static bool trap_bvr(struct kvm_vcpu *vcpu,
 426                      struct sys_reg_params *p,
 427                      const struct sys_reg_desc *rd)
 428 {
 429         u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_bvr[rd->CRm];
 430
 431         if (p->is_write)
 432                 reg_to_dbg(vcpu, p, dbg_reg);
 433         else
 434                 dbg_to_reg(vcpu, p, dbg_reg);
 435
 436         trace_trap_reg(__func__, rd->CRm, p->is_write, *dbg_reg);
 437
 438         return true;
 439 }
 440
 441 static int set_bvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
 442                 const struct kvm_one_reg *reg, void __user *uaddr)
 443 {
 444         __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_bvr[rd->CRm];
 445
 446         if (copy_from_user(r, uaddr, KVM_REG_SIZE(reg->id)) != 0)
 447                 return -EFAULT;
 448         return 0;
 449 }
 450
 451 static int get_bvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
 452         const struct kvm_one_reg *reg, void __user *uaddr)
 453 {
 454         __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_bvr[rd->CRm];
 455
 456         if (copy_to_user(uaddr, r, KVM_REG_SIZE(reg->id)) != 0)
 457                 return -EFAULT;
 458         return 0;
 459 }
 460
 461 static void reset_bvr(struct kvm_vcpu *vcpu,
 462                       const struct sys_reg_desc *rd)
 463 {
 464         vcpu->arch.vcpu_debug_state.dbg_bvr[rd->CRm] = rd->val;
 465 }
 466
 467 static bool trap_bcr(struct kvm_vcpu *vcpu,
 468                      struct sys_reg_params *p,
 469                      const struct sys_reg_desc *rd)
 470 {
 471         u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_bcr[rd->CRm];
 472
 473         if (p->is_write)
 474                 reg_to_dbg(vcpu, p, dbg_reg);
 475         else
 476                 dbg_to_reg(vcpu, p, dbg_reg);
 477
 478         trace_trap_reg(__func__, rd->CRm, p->is_write, *dbg_reg);
 479
 480         return true;
 481 }
 482
 483 static int set_bcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
 484                 const struct kvm_one_reg *reg, void __user *uaddr)
 485 {
 486         __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_bcr[rd->CRm];
 487
 488         if (copy_from_user(r, uaddr, KVM_REG_SIZE(reg->id)) != 0)
 489                 return -EFAULT;
 490
 491         return 0;
 492 }
 493
 494 static int get_bcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
 495         const struct kvm_one_reg *reg, void __user *uaddr)
 496 {
 497         __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_bcr[rd->CRm];
 498
 499         if (copy_to_user(uaddr, r, KVM_REG_SIZE(reg->id)) != 0)
 500                 return -EFAULT;
 501         return 0;
 502 }
 503
 504 static void reset_bcr(struct kvm_vcpu *vcpu,
 505                       const struct sys_reg_desc *rd)
 506 {
 507         vcpu->arch.vcpu_debug_state.dbg_bcr[rd->CRm] = rd->val;
 508 }
 509
 510 static bool trap_wvr(struct kvm_vcpu *vcpu,
 511                      struct sys_reg_params *p,
 512                      const struct sys_reg_desc *rd)
 513 {
 514         u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_wvr[rd->CRm];
 515
 516         if (p->is_write)
 517                 reg_to_dbg(vcpu, p, dbg_reg);
 518         else
 519                 dbg_to_reg(vcpu, p, dbg_reg);
 520
 521         trace_trap_reg(__func__, rd->CRm, p->is_write,
 522                 vcpu->arch.vcpu_debug_state.dbg_wvr[rd->CRm]);
 523
 524         return true;
 525 }
 526
 527 static int set_wvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
 528                 const struct kvm_one_reg *reg, void __user *uaddr)
 529 {
 530         __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_wvr[rd->CRm];
 531
 532         if (copy_from_user(r, uaddr, KVM_REG_SIZE(reg->id)) != 0)
 533                 return -EFAULT;
 534         return 0;
 535 }
 536
 537 static int get_wvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
 538         const struct kvm_one_reg *reg, void __user *uaddr)
 539 {
 540         __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_wvr[rd->CRm];
 541
 542         if (copy_to_user(uaddr, r, KVM_REG_SIZE(reg->id)) != 0)
 543                 return -EFAULT;
 544         return 0;
 545 }
 546
 547 static void reset_wvr(struct kvm_vcpu *vcpu,
 548                       const struct sys_reg_desc *rd)
 549 {
 550         vcpu->arch.vcpu_debug_state.dbg_wvr[rd->CRm] = rd->val;
 551 }
 552
 553 static bool trap_wcr(struct kvm_vcpu *vcpu,
 554                      struct sys_reg_params *p,
 555                      const struct sys_reg_desc *rd)
 556 {
 557         u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_wcr[rd->CRm];
 558
 559         if (p->is_write)
 560                 reg_to_dbg(vcpu, p, dbg_reg);
 561         else
 562                 dbg_to_reg(vcpu, p, dbg_reg);
 563
 564         trace_trap_reg(__func__, rd->CRm, p->is_write, *dbg_reg);
 565
 566         return true;
 567 }
 568
 569 static int set_wcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
 570                 const struct kvm_one_reg *reg, void __user *uaddr)
 571 {
 572         __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_wcr[rd->CRm];
 573
 574         if (copy_from_user(r, uaddr, KVM_REG_SIZE(reg->id)) != 0)
 575                 return -EFAULT;
 576         return 0;
 577 }
 578
 579 static int get_wcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
 580         const struct kvm_one_reg *reg, void __user *uaddr)
 581 {
 582         __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_wcr[rd->CRm];
 583
 584         if (copy_to_user(uaddr, r, KVM_REG_SIZE(reg->id)) != 0)
 585                 return -EFAULT;
 586         return 0;
 587 }
 588
 589 static void reset_wcr(struct kvm_vcpu *vcpu,
 590                       const struct sys_reg_desc *rd)
 591 {
 592         vcpu->arch.vcpu_debug_state.dbg_wcr[rd->CRm] = rd->val;
 593 }
 594
 595 static void reset_amair_el1(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
 596 {
 597         u64 amair = read_sysreg(amair_el1);
 598         vcpu_write_sys_reg(vcpu, amair, AMAIR_EL1);
 599 }
 600
 601 static void reset_mpidr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
 602 {
 603         u64 mpidr;
 604
 605         /*
 606          * Map the vcpu_id into the first three affinity level fields of
 607          * the MPIDR. We limit the number of VCPUs in level 0 due to a
 608          * limitation to 16 CPUs in that level in the ICC_SGIxR registers
 609          * of the GICv3 to be able to address each CPU directly when
 610          * sending IPIs.
 611          */
 612         mpidr = (vcpu->vcpu_id & 0x0f) << MPIDR_LEVEL_SHIFT(0);
 613         mpidr |= ((vcpu->vcpu_id >> 4) & 0xff) << MPIDR_LEVEL_SHIFT(1);
 614         mpidr |= ((vcpu->vcpu_id >> 12) & 0xff) << MPIDR_LEVEL_SHIFT(2);
 615         vcpu_write_sys_reg(vcpu, (1ULL << 31) | mpidr, MPIDR_EL1);
 616 }
 617
 618 static void reset_pmcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
 619 {
 620         u64 pmcr, val;
 621
 622         /* No PMU available, PMCR_EL0 may UNDEF... */
 623         if (!kvm_arm_support_pmu_v3())
 624                 return;
 625
 626         pmcr = read_sysreg(pmcr_el0);
 627         /*
 628          * Writable bits of PMCR_EL0 (ARMV8_PMU_PMCR_MASK) are reset to UNKNOWN
 629          * except PMCR.E resetting to zero.
 630          */
 631         val = ((pmcr & ~ARMV8_PMU_PMCR_MASK)
 632                | (ARMV8_PMU_PMCR_MASK & 0xdecafbad)) & (~ARMV8_PMU_PMCR_E);
 633         __vcpu_sys_reg(vcpu, r->reg) = val;
 634 }
 635
 636 static bool check_pmu_access_disabled(struct kvm_vcpu *vcpu, u64 flags)
 637 {
 638         u64 reg = __vcpu_sys_reg(vcpu, PMUSERENR_EL0);
 639         bool enabled = (reg & flags) || vcpu_mode_priv(vcpu);
 640
 641         if (!enabled)
 642                 kvm_inject_undefined(vcpu);
 643
 644         return !enabled;
 645 }
 646
 647 static bool pmu_access_el0_disabled(struct kvm_vcpu *vcpu)
 648 {
 649         return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_EN);
 650 }
 651
 652 static bool pmu_write_swinc_el0_disabled(struct kvm_vcpu *vcpu)
 653 {
 654         return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_SW | ARMV8_PMU_USERENR_EN);
 655 }
 656
 657 static bool pmu_access_cycle_counter_el0_disabled(struct kvm_vcpu *vcpu)
 658 {
 659         return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_CR | ARMV8_PMU_USERENR_EN);
 660 }
 661
 662 static bool pmu_access_event_counter_el0_disabled(struct kvm_vcpu *vcpu)
 663 {
 664         return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_ER | ARMV8_PMU_USERENR_EN);
 665 }
 666
 667 static bool access_pmcr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
 668                         const struct sys_reg_desc *r)
 669 {
 670         u64 val;
 671
 672         if (!kvm_arm_pmu_v3_ready(vcpu))
 673                 return trap_raz_wi(vcpu, p, r);
 674
 675         if (pmu_access_el0_disabled(vcpu))
 676                 return false;
 677
 678         if (p->is_write) {
 679                 /* Only update writeable bits of PMCR */
 680                 val = __vcpu_sys_reg(vcpu, PMCR_EL0);
 681                 val &= ~ARMV8_PMU_PMCR_MASK;
 682                 val |= p->regval & ARMV8_PMU_PMCR_MASK;
 683                 __vcpu_sys_reg(vcpu, PMCR_EL0) = val;
 684                 kvm_pmu_handle_pmcr(vcpu, val);
 685         } else {
 686                 /* PMCR.P & PMCR.C are RAZ */
 687                 val = __vcpu_sys_reg(vcpu, PMCR_EL0)
 688                       & ~(ARMV8_PMU_PMCR_P | ARMV8_PMU_PMCR_C);
 689                 p->regval = val;
 690         }
 691
 692         return true;
 693 }
 694
 695 static bool access_pmselr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
 696                           const struct sys_reg_desc *r)
 697 {
 698         if (!kvm_arm_pmu_v3_ready(vcpu))
 699                 return trap_raz_wi(vcpu, p, r);
 700
 701         if (pmu_access_event_counter_el0_disabled(vcpu))
 702                 return false;
 703
 704         if (p->is_write)
 705                 __vcpu_sys_reg(vcpu, PMSELR_EL0) = p->regval;
 706         else
 707                 /* return PMSELR.SEL field */
 708                 p->regval = __vcpu_sys_reg(vcpu, PMSELR_EL0)
 709                             & ARMV8_PMU_COUNTER_MASK;
 710
 711         return true;
 712 }
 713
 714 static bool access_pmceid(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
 715                           const struct sys_reg_desc *r)
 716 {
 717         u64 pmceid;
 718
 719         if (!kvm_arm_pmu_v3_ready(vcpu))
 720                 return trap_raz_wi(vcpu, p, r);
 721
 722         BUG_ON(p->is_write);
 723
 724         if (pmu_access_el0_disabled(vcpu))
 725                 return false;
 726
 727         if (!(p->Op2 & 1))
 728                 pmceid = read_sysreg(pmceid0_el0);
 729         else
 730                 pmceid = read_sysreg(pmceid1_el0);
 731
 732         p->regval = pmceid;
 733
 734         return true;
 735 }
 736
 737 static bool pmu_counter_idx_valid(struct kvm_vcpu *vcpu, u64 idx)
 738 {
 739         u64 pmcr, val;
 740
 741         pmcr = __vcpu_sys_reg(vcpu, PMCR_EL0);
 742         val = (pmcr >> ARMV8_PMU_PMCR_N_SHIFT) & ARMV8_PMU_PMCR_N_MASK;
 743         if (idx >= val && idx != ARMV8_PMU_CYCLE_IDX) {
 744                 kvm_inject_undefined(vcpu);
 745                 return false;
 746         }
 747
 748         return true;
 749 }
 750
 751 static bool access_pmu_evcntr(struct kvm_vcpu *vcpu,
 752                               struct sys_reg_params *p,
 753                               const struct sys_reg_desc *r)
 754 {
 755         u64 idx;
 756
 757         if (!kvm_arm_pmu_v3_ready(vcpu))
 758                 return trap_raz_wi(vcpu, p, r);
 759
 760         if (r->CRn == 9 && r->CRm == 13) {
 761                 if (r->Op2 == 2) {
 762                         /* PMXEVCNTR_EL0 */
 763                         if (pmu_access_event_counter_el0_disabled(vcpu))
 764                                 return false;
 765
 766                         idx = __vcpu_sys_reg(vcpu, PMSELR_EL0)
 767                               & ARMV8_PMU_COUNTER_MASK;
 768                 } else if (r->Op2 == 0) {
 769                         /* PMCCNTR_EL0 */
 770                         if (pmu_access_cycle_counter_el0_disabled(vcpu))
 771                                 return false;
 772
 773                         idx = ARMV8_PMU_CYCLE_IDX;
 774                 } else {
 775                         return false;
 776                 }
 777         } else if (r->CRn == 0 && r->CRm == 9) {
 778                 /* PMCCNTR */
 779                 if (pmu_access_event_counter_el0_disabled(vcpu))
 780                         return false;
 781
 782                 idx = ARMV8_PMU_CYCLE_IDX;
 783         } else if (r->CRn == 14 && (r->CRm & 12) == 8) {
 784                 /* PMEVCNTRn_EL0 */
 785                 if (pmu_access_event_counter_el0_disabled(vcpu))
 786                         return false;
 787
 788                 idx = ((r->CRm & 3) << 3) | (r->Op2 & 7);
 789         } else {
 790                 return false;
 791         }
 792
 793         if (!pmu_counter_idx_valid(vcpu, idx))
 794                 return false;
 795
 796         if (p->is_write) {
 797                 if (pmu_access_el0_disabled(vcpu))
 798                         return false;
 799
 800                 kvm_pmu_set_counter_value(vcpu, idx, p->regval);
 801         } else {
 802                 p->regval = kvm_pmu_get_counter_value(vcpu, idx);
 803         }
 804
 805         return true;
 806 }
 807
 808 static bool access_pmu_evtyper(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
 809                                const struct sys_reg_desc *r)
 810 {
 811         u64 idx, reg;
 812
 813         if (!kvm_arm_pmu_v3_ready(vcpu))
 814                 return trap_raz_wi(vcpu, p, r);
 815
 816         if (pmu_access_el0_disabled(vcpu))
 817                 return false;
 818
 819         if (r->CRn == 9 && r->CRm == 13 && r->Op2 == 1) {
 820                 /* PMXEVTYPER_EL0 */
 821                 idx = __vcpu_sys_reg(vcpu, PMSELR_EL0) & ARMV8_PMU_COUNTER_MASK;
 822                 reg = PMEVTYPER0_EL0 + idx;
 823         } else if (r->CRn == 14 && (r->CRm & 12) == 12) {
 824                 idx = ((r->CRm & 3) << 3) | (r->Op2 & 7);
 825                 if (idx == ARMV8_PMU_CYCLE_IDX)
 826                         reg = PMCCFILTR_EL0;
 827                 else
 828                         /* PMEVTYPERn_EL0 */
 829                         reg = PMEVTYPER0_EL0 + idx;
 830         } else {
 831                 BUG();
 832         }
 833
 834         if (!pmu_counter_idx_valid(vcpu, idx))
 835                 return false;
 836
 837         if (p->is_write) {
 838                 kvm_pmu_set_counter_event_type(vcpu, p->regval, idx);
 839                 __vcpu_sys_reg(vcpu, reg) = p->regval & ARMV8_PMU_EVTYPE_MASK;
 840         } else {
 841                 p->regval = __vcpu_sys_reg(vcpu, reg) & ARMV8_PMU_EVTYPE_MASK;
 842         }
 843
 844         return true;
 845 }
 846
 847 static bool access_pmcnten(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
 848                            const struct sys_reg_desc *r)
 849 {
 850         u64 val, mask;
 851
 852         if (!kvm_arm_pmu_v3_ready(vcpu))
 853                 return trap_raz_wi(vcpu, p, r);
 854
 855         if (pmu_access_el0_disabled(vcpu))
 856                 return false;
 857
 858         mask = kvm_pmu_valid_counter_mask(vcpu);
 859         if (p->is_write) {
 860                 val = p->regval & mask;
 861                 if (r->Op2 & 0x1) {
 862                         /* accessing PMCNTENSET_EL0 */
 863                         __vcpu_sys_reg(vcpu, PMCNTENSET_EL0) |= val;
 864                         kvm_pmu_enable_counter(vcpu, val);
 865                 } else {
 866                         /* accessing PMCNTENCLR_EL0 */
 867                         __vcpu_sys_reg(vcpu, PMCNTENSET_EL0) &= ~val;
 868                         kvm_pmu_disable_counter(vcpu, val);
 869                 }
 870         } else {
 871                 p->regval = __vcpu_sys_reg(vcpu, PMCNTENSET_EL0) & mask;
 872         }
 873
 874         return true;
 875 }
 876
 877 static bool access_pminten(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
 878                            const struct sys_reg_desc *r)
 879 {
 880         u64 mask = kvm_pmu_valid_counter_mask(vcpu);
 881
 882         if (!kvm_arm_pmu_v3_ready(vcpu))
 883                 return trap_raz_wi(vcpu, p, r);
 884
 885         if (!vcpu_mode_priv(vcpu)) {
 886                 kvm_inject_undefined(vcpu);
 887                 return false;
 888         }
 889
 890         if (p->is_write) {
 891                 u64 val = p->regval & mask;
 892
 893                 if (r->Op2 & 0x1)
 894                         /* accessing PMINTENSET_EL1 */
 895                         __vcpu_sys_reg(vcpu, PMINTENSET_EL1) |= val;
 896                 else
 897                         /* accessing PMINTENCLR_EL1 */
 898                         __vcpu_sys_reg(vcpu, PMINTENSET_EL1) &= ~val;
 899         } else {
 900                 p->regval = __vcpu_sys_reg(vcpu, PMINTENSET_EL1) & mask;
 901         }
 902
 903         return true;
 904 }
 905
 906 static bool access_pmovs(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
 907                          const struct sys_reg_desc *r)
 908 {
 909         u64 mask = kvm_pmu_valid_counter_mask(vcpu);
 910
 911         if (!kvm_arm_pmu_v3_ready(vcpu))
 912                 return trap_raz_wi(vcpu, p, r);
 913
 914         if (pmu_access_el0_disabled(vcpu))
 915                 return false;
 916
 917         if (p->is_write) {
 918                 if (r->CRm & 0x2)
 919                         /* accessing PMOVSSET_EL0 */
 920                         __vcpu_sys_reg(vcpu, PMOVSSET_EL0) |= (p->regval & mask);
 921                 else
 922                         /* accessing PMOVSCLR_EL0 */
 923                         __vcpu_sys_reg(vcpu, PMOVSSET_EL0) &= ~(p->regval & mask);
 924         } else {
 925                 p->regval = __vcpu_sys_reg(vcpu, PMOVSSET_EL0) & mask;
 926         }
 927
 928         return true;
 929 }
 930
 931 static bool access_pmswinc(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
 932                            const struct sys_reg_desc *r)
 933 {
 934         u64 mask;
 935
 936         if (!kvm_arm_pmu_v3_ready(vcpu))
 937                 return trap_raz_wi(vcpu, p, r);
 938
 939         if (!p->is_write)
 940                 return read_from_write_only(vcpu, p, r);
 941
 942         if (pmu_write_swinc_el0_disabled(vcpu))
 943                 return false;
 944
 945         mask = kvm_pmu_valid_counter_mask(vcpu);
 946         kvm_pmu_software_increment(vcpu, p->regval & mask);
 947         return true;
 948 }
 949
 950 static bool access_pmuserenr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
 951                              const struct sys_reg_desc *r)
 952 {
 953         if (!kvm_arm_pmu_v3_ready(vcpu))
 954                 return trap_raz_wi(vcpu, p, r);
 955
 956         if (p->is_write) {
 957                 if (!vcpu_mode_priv(vcpu)) {
 958                         kvm_inject_undefined(vcpu);
 959                         return false;
 960                 }
 961
 962                 __vcpu_sys_reg(vcpu, PMUSERENR_EL0) =
 963                                p->regval & ARMV8_PMU_USERENR_MASK;
 964         } else {
 965                 p->regval = __vcpu_sys_reg(vcpu, PMUSERENR_EL0)
 966                             & ARMV8_PMU_USERENR_MASK;
 967         }
 968
 969         return true;
 970 }
 971
 972 /* Silly macro to expand the DBG{BCR,BVR,WVR,WCR}n_EL1 registers in one go */
 973 #define DBG_BCR_BVR_WCR_WVR_EL1(n)                                      \
 974         { SYS_DESC(SYS_DBGBVRn_EL1(n)),                                 \
 975           trap_bvr, reset_bvr, 0, 0, get_bvr, set_bvr },                \
 976         { SYS_DESC(SYS_DBGBCRn_EL1(n)),                                 \
 977           trap_bcr, reset_bcr, 0, 0, get_bcr, set_bcr },                \
 978         { SYS_DESC(SYS_DBGWVRn_EL1(n)),                                 \
 979           trap_wvr, reset_wvr, 0, 0,  get_wvr, set_wvr },               \
 980         { SYS_DESC(SYS_DBGWCRn_EL1(n)),                                 \
 981           trap_wcr, reset_wcr, 0, 0,  get_wcr, set_wcr }
 982
 983 /* Macro to expand the PMEVCNTRn_EL0 register */
 984 #define PMU_PMEVCNTR_EL0(n)                                             \
 985         { SYS_DESC(SYS_PMEVCNTRn_EL0(n)),                                       \
 986           access_pmu_evcntr, reset_unknown, (PMEVCNTR0_EL0 + n), }
 987
 988 /* Macro to expand the PMEVTYPERn_EL0 register */
 989 #define PMU_PMEVTYPER_EL0(n)                                            \
 990         { SYS_DESC(SYS_PMEVTYPERn_EL0(n)),                                      \
 991           access_pmu_evtyper, reset_unknown, (PMEVTYPER0_EL0 + n), }
 992
 993 static bool access_cntp_tval(struct kvm_vcpu *vcpu,
 994                 struct sys_reg_params *p,
 995                 const struct sys_reg_desc *r)
 996 {
 997         u64 now = kvm_phys_timer_read();
 998         u64 cval;
 999
1000         if (p->is_write) {
1001                 kvm_arm_timer_set_reg(vcpu, KVM_REG_ARM_PTIMER_CVAL,
1002                                       p->regval + now);
1003         } else {
1004                 cval = kvm_arm_timer_get_reg(vcpu, KVM_REG_ARM_PTIMER_CVAL);
1005                 p->regval = cval - now;
1006         }
1007
1008         return true;
1009 }
1010
1011 static bool access_cntp_ctl(struct kvm_vcpu *vcpu,
1012                 struct sys_reg_params *p,
1013                 const struct sys_reg_desc *r)
1014 {
1015         if (p->is_write)
1016                 kvm_arm_timer_set_reg(vcpu, KVM_REG_ARM_PTIMER_CTL, p->regval);
1017         else
1018                 p->regval = kvm_arm_timer_get_reg(vcpu, KVM_REG_ARM_PTIMER_CTL);
1019
1020         return true;
1021 }
1022
1023 static bool access_cntp_cval(struct kvm_vcpu *vcpu,
1024                 struct sys_reg_params *p,
1025                 const struct sys_reg_desc *r)
1026 {
1027         if (p->is_write)
1028                 kvm_arm_timer_set_reg(vcpu, KVM_REG_ARM_PTIMER_CVAL, p->regval);
1029         else
1030                 p->regval = kvm_arm_timer_get_reg(vcpu, KVM_REG_ARM_PTIMER_CVAL);
1031
1032         return true;
1033 }
1034
1035 /* Read a sanitised cpufeature ID register by sys_reg_desc */
1036 static u64 read_id_reg(struct sys_reg_desc const *r, bool raz)
1037 {
1038         u32 id = sys_reg((u32)r->Op0, (u32)r->Op1,
1039                          (u32)r->CRn, (u32)r->CRm, (u32)r->Op2);
1040         u64 val = raz ? 0 : read_sanitised_ftr_reg(id);
1041
1042         if (id == SYS_ID_AA64PFR0_EL1) {
1043                 if (val & (0xfUL << ID_AA64PFR0_SVE_SHIFT))
1044                         kvm_debug("SVE unsupported for guests, suppressing\n");
1045
1046                 val &= ~(0xfUL << ID_AA64PFR0_SVE_SHIFT);
1047         } else if (id == SYS_ID_AA64MMFR1_EL1) {
1048                 if (val & (0xfUL << ID_AA64MMFR1_LOR_SHIFT))
1049                         kvm_debug("LORegions unsupported for guests, suppressing\n");
1050
1051                 val &= ~(0xfUL << ID_AA64MMFR1_LOR_SHIFT);
1052         } else if (id == SYS_ID_AA64DFR0_EL1) {
1053                 /* Limit guests to PMUv3 for ARMv8.1 */
1054                 val = cpuid_feature_cap_perfmon_field(val,
1055                                                 ID_AA64DFR0_PMUVER_SHIFT,
1056                                                 ID_AA64DFR0_PMUVER_8_1);
1057         } else if (id == SYS_ID_DFR0_EL1) {
1058                 /* Limit guests to PMUv3 for ARMv8.1 */
1059                 val = cpuid_feature_cap_perfmon_field(val,
1060                                                 ID_DFR0_PERFMON_SHIFT,
1061                                                 ID_DFR0_PERFMON_8_1);
1062         }
1063
1064         return val;
1065 }
1066
1067 /* cpufeature ID register access trap handlers */
1068
1069 static bool __access_id_reg(struct kvm_vcpu *vcpu,
1070                             struct sys_reg_params *p,
1071                             const struct sys_reg_desc *r,
1072                             bool raz)
1073 {
1074         if (p->is_write)
1075                 return write_to_read_only(vcpu, p, r);
1076
1077         p->regval = read_id_reg(r, raz);
1078         return true;
1079 }
1080
1081 static bool access_id_reg(struct kvm_vcpu *vcpu,
1082                           struct sys_reg_params *p,
1083                           const struct sys_reg_desc *r)
1084 {
1085         return __access_id_reg(vcpu, p, r, false);
1086 }
1087
1088 static bool access_raz_id_reg(struct kvm_vcpu *vcpu,
1089                               struct sys_reg_params *p,
1090                               const struct sys_reg_desc *r)
1091 {
1092         return __access_id_reg(vcpu, p, r, true);
1093 }
1094
1095 static int reg_from_user(u64 *val, const void __user *uaddr, u64 id);
1096 static int reg_to_user(void __user *uaddr, const u64 *val, u64 id);
1097 static u64 sys_reg_to_index(const struct sys_reg_desc *reg);
1098
1099 /*
1100  * cpufeature ID register user accessors
1101  *
1102  * For now, these registers are immutable for userspace, so no values
1103  * are stored, and for set_id_reg() we don't allow the effective value
1104  * to be changed.
1105  */
1106 static int __get_id_reg(const struct sys_reg_desc *rd, void __user *uaddr,
1107                         bool raz)
1108 {
1109         const u64 id = sys_reg_to_index(rd);
1110         const u64 val = read_id_reg(rd, raz);
1111
1112         return reg_to_user(uaddr, &val, id);
1113 }
1114
1115 static int __set_id_reg(const struct sys_reg_desc *rd, void __user *uaddr,
1116                         bool raz)
1117 {
1118         const u64 id = sys_reg_to_index(rd);
1119         int err;
1120         u64 val;
1121
1122         err = reg_from_user(&val, uaddr, id);
1123         if (err)
1124                 return err;
1125
1126         /* This is what we mean by invariant: you can't change it. */
1127         if (val != read_id_reg(rd, raz))
1128                 return -EINVAL;
1129
1130         return 0;
1131 }
1132
1133 static int get_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
1134                       const struct kvm_one_reg *reg, void __user *uaddr)
1135 {
1136         return __get_id_reg(rd, uaddr, false);
1137 }
1138
1139 static int set_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
1140                       const struct kvm_one_reg *reg, void __user *uaddr)
1141 {
1142         return __set_id_reg(rd, uaddr, false);
1143 }
1144
1145 static int get_raz_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
1146                           const struct kvm_one_reg *reg, void __user *uaddr)
1147 {
1148         return __get_id_reg(rd, uaddr, true);
1149 }
1150
1151 static int set_raz_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
1152                           const struct kvm_one_reg *reg, void __user *uaddr)
1153 {
1154         return __set_id_reg(rd, uaddr, true);
1155 }
1156
1157 /* sys_reg_desc initialiser for known cpufeature ID registers */
1158 #define ID_SANITISED(name) {                    \
1159         SYS_DESC(SYS_##name),                   \
1160         .access = access_id_reg,                \
1161         .get_user = get_id_reg,                 \
1162         .set_user = set_id_reg,                 \
1163 }
1164
1165 /*
1166  * sys_reg_desc initialiser for architecturally unallocated cpufeature ID
1167  * register with encoding Op0=3, Op1=0, CRn=0, CRm=crm, Op2=op2
1168  * (1 <= crm < 8, 0 <= Op2 < 8).
1169  */
1170 #define ID_UNALLOCATED(crm, op2) {                      \
1171         Op0(3), Op1(0), CRn(0), CRm(crm), Op2(op2),     \
1172         .access = access_raz_id_reg,                    \
1173         .get_user = get_raz_id_reg,                     \
1174         .set_user = set_raz_id_reg,                     \
1175 }
1176
1177 /*
1178  * sys_reg_desc initialiser for known ID registers that we hide from guests.
1179  * For now, these are exposed just like unallocated ID regs: they appear
1180  * RAZ for the guest.
1181  */
1182 #define ID_HIDDEN(name) {                       \
1183         SYS_DESC(SYS_##name),                   \
1184         .access = access_raz_id_reg,            \
1185         .get_user = get_raz_id_reg,             \
1186         .set_user = set_raz_id_reg,             \
1187 }
1188
1189 /*
1190  * Architected system registers.
1191  * Important: Must be sorted ascending by Op0, Op1, CRn, CRm, Op2
1192  *
1193  * Debug handling: We do trap most, if not all debug related system
1194  * registers. The implementation is good enough to ensure that a guest
1195  * can use these with minimal performance degradation. The drawback is
1196  * that we don't implement any of the external debug, none of the
1197  * OSlock protocol. This should be revisited if we ever encounter a
1198  * more demanding guest...
1199  */
1200 static const struct sys_reg_desc sys_reg_descs[] = {
1201         { SYS_DESC(SYS_DC_ISW), access_dcsw },
1202         { SYS_DESC(SYS_DC_CSW), access_dcsw },
1203         { SYS_DESC(SYS_DC_CISW), access_dcsw },
1204
1205         DBG_BCR_BVR_WCR_WVR_EL1(0),
1206         DBG_BCR_BVR_WCR_WVR_EL1(1),
1207         { SYS_DESC(SYS_MDCCINT_EL1), trap_debug_regs, reset_val, MDCCINT_EL1, 0 },
1208         { SYS_DESC(SYS_MDSCR_EL1), trap_debug_regs, reset_val, MDSCR_EL1, 0 },
1209         DBG_BCR_BVR_WCR_WVR_EL1(2),
1210         DBG_BCR_BVR_WCR_WVR_EL1(3),
1211         DBG_BCR_BVR_WCR_WVR_EL1(4),
1212         DBG_BCR_BVR_WCR_WVR_EL1(5),
1213         DBG_BCR_BVR_WCR_WVR_EL1(6),
1214         DBG_BCR_BVR_WCR_WVR_EL1(7),
1215         DBG_BCR_BVR_WCR_WVR_EL1(8),
1216         DBG_BCR_BVR_WCR_WVR_EL1(9),
1217         DBG_BCR_BVR_WCR_WVR_EL1(10),
1218         DBG_BCR_BVR_WCR_WVR_EL1(11),
1219         DBG_BCR_BVR_WCR_WVR_EL1(12),
1220         DBG_BCR_BVR_WCR_WVR_EL1(13),
1221         DBG_BCR_BVR_WCR_WVR_EL1(14),
1222         DBG_BCR_BVR_WCR_WVR_EL1(15),
1223
1224         { SYS_DESC(SYS_MDRAR_EL1), trap_raz_wi },
1225         { SYS_DESC(SYS_OSLAR_EL1), trap_raz_wi },
1226         { SYS_DESC(SYS_OSLSR_EL1), trap_oslsr_el1 },
1227         { SYS_DESC(SYS_OSDLR_EL1), trap_raz_wi },
1228         { SYS_DESC(SYS_DBGPRCR_EL1), trap_raz_wi },
1229         { SYS_DESC(SYS_DBGCLAIMSET_EL1), trap_raz_wi },
1230         { SYS_DESC(SYS_DBGCLAIMCLR_EL1), trap_raz_wi },
1231         { SYS_DESC(SYS_DBGAUTHSTATUS_EL1), trap_dbgauthstatus_el1 },
1232
1233         { SYS_DESC(SYS_MDCCSR_EL0), trap_raz_wi },
1234         { SYS_DESC(SYS_DBGDTR_EL0), trap_raz_wi },
1235         // DBGDTR[TR]X_EL0 share the same encoding
1236         { SYS_DESC(SYS_DBGDTRTX_EL0), trap_raz_wi },
1237
1238         { SYS_DESC(SYS_DBGVCR32_EL2), NULL, reset_val, DBGVCR32_EL2, 0 },
1239
1240         { SYS_DESC(SYS_MPIDR_EL1), NULL, reset_mpidr, MPIDR_EL1 },
1241
1242         /*
1243          * ID regs: all ID_SANITISED() entries here must have corresponding
1244          * entries in arm64_ftr_regs[].
1245          */
1246
1247         /* AArch64 mappings of the AArch32 ID registers */
1248         /* CRm=1 */
1249         ID_SANITISED(ID_PFR0_EL1),
1250         ID_SANITISED(ID_PFR1_EL1),
1251         ID_SANITISED(ID_DFR0_EL1),
1252         ID_HIDDEN(ID_AFR0_EL1),
1253         ID_SANITISED(ID_MMFR0_EL1),
1254         ID_SANITISED(ID_MMFR1_EL1),
1255         ID_SANITISED(ID_MMFR2_EL1),
1256         ID_SANITISED(ID_MMFR3_EL1),
1257
1258         /* CRm=2 */
1259         ID_SANITISED(ID_ISAR0_EL1),
1260         ID_SANITISED(ID_ISAR1_EL1),
1261         ID_SANITISED(ID_ISAR2_EL1),
1262         ID_SANITISED(ID_ISAR3_EL1),
1263         ID_SANITISED(ID_ISAR4_EL1),
1264         ID_SANITISED(ID_ISAR5_EL1),
1265         ID_SANITISED(ID_MMFR4_EL1),
1266         ID_UNALLOCATED(2,7),
1267
1268         /* CRm=3 */
1269         ID_SANITISED(MVFR0_EL1),
1270         ID_SANITISED(MVFR1_EL1),
1271         ID_SANITISED(MVFR2_EL1),
1272         ID_UNALLOCATED(3,3),
1273         ID_UNALLOCATED(3,4),
1274         ID_UNALLOCATED(3,5),
1275         ID_UNALLOCATED(3,6),
1276         ID_UNALLOCATED(3,7),
1277
1278         /* AArch64 ID registers */
1279         /* CRm=4 */
1280         ID_SANITISED(ID_AA64PFR0_EL1),
1281         ID_SANITISED(ID_AA64PFR1_EL1),
1282         ID_UNALLOCATED(4,2),
1283         ID_UNALLOCATED(4,3),
1284         ID_UNALLOCATED(4,4),
1285         ID_UNALLOCATED(4,5),
1286         ID_UNALLOCATED(4,6),
1287         ID_UNALLOCATED(4,7),
1288
1289         /* CRm=5 */
1290         ID_SANITISED(ID_AA64DFR0_EL1),
1291         ID_SANITISED(ID_AA64DFR1_EL1),
1292         ID_UNALLOCATED(5,2),
1293         ID_UNALLOCATED(5,3),
1294         ID_HIDDEN(ID_AA64AFR0_EL1),
1295         ID_HIDDEN(ID_AA64AFR1_EL1),
1296         ID_UNALLOCATED(5,6),
1297         ID_UNALLOCATED(5,7),
1298
1299         /* CRm=6 */
1300         ID_SANITISED(ID_AA64ISAR0_EL1),
1301         ID_SANITISED(ID_AA64ISAR1_EL1),
1302         ID_SANITISED(ID_AA64ISAR2_EL1),
1303         ID_UNALLOCATED(6,3),
1304         ID_UNALLOCATED(6,4),
1305         ID_UNALLOCATED(6,5),
1306         ID_UNALLOCATED(6,6),
1307         ID_UNALLOCATED(6,7),
1308
1309         /* CRm=7 */
1310         ID_SANITISED(ID_AA64MMFR0_EL1),
1311         ID_SANITISED(ID_AA64MMFR1_EL1),
1312         ID_SANITISED(ID_AA64MMFR2_EL1),
1313         ID_UNALLOCATED(7,3),
1314         ID_UNALLOCATED(7,4),
1315         ID_UNALLOCATED(7,5),
1316         ID_UNALLOCATED(7,6),
1317         ID_UNALLOCATED(7,7),
1318
1319         { SYS_DESC(SYS_SCTLR_EL1), access_vm_reg, reset_val, SCTLR_EL1, 0x00C50078 },
1320         { SYS_DESC(SYS_CPACR_EL1), NULL, reset_val, CPACR_EL1, 0 },
1321         { SYS_DESC(SYS_TTBR0_EL1), access_vm_reg, reset_unknown, TTBR0_EL1 },
1322         { SYS_DESC(SYS_TTBR1_EL1), access_vm_reg, reset_unknown, TTBR1_EL1 },
1323         { SYS_DESC(SYS_TCR_EL1), access_vm_reg, reset_val, TCR_EL1, 0 },
1324
1325         { SYS_DESC(SYS_AFSR0_EL1), access_vm_reg, reset_unknown, AFSR0_EL1 },
1326         { SYS_DESC(SYS_AFSR1_EL1), access_vm_reg, reset_unknown, AFSR1_EL1 },
1327         { SYS_DESC(SYS_ESR_EL1), access_vm_reg, reset_unknown, ESR_EL1 },
1328
1329         { SYS_DESC(SYS_ERRIDR_EL1), trap_raz_wi },
1330         { SYS_DESC(SYS_ERRSELR_EL1), trap_raz_wi },
1331         { SYS_DESC(SYS_ERXFR_EL1), trap_raz_wi },
1332         { SYS_DESC(SYS_ERXCTLR_EL1), trap_raz_wi },
1333         { SYS_DESC(SYS_ERXSTATUS_EL1), trap_raz_wi },
1334         { SYS_DESC(SYS_ERXADDR_EL1), trap_raz_wi },
1335         { SYS_DESC(SYS_ERXMISC0_EL1), trap_raz_wi },
1336         { SYS_DESC(SYS_ERXMISC1_EL1), trap_raz_wi },
1337
1338         { SYS_DESC(SYS_FAR_EL1), access_vm_reg, reset_unknown, FAR_EL1 },
1339         { SYS_DESC(SYS_PAR_EL1), NULL, reset_unknown, PAR_EL1 },
1340
1341         { SYS_DESC(SYS_PMINTENSET_EL1), access_pminten, reset_unknown, PMINTENSET_EL1 },
1342         { SYS_DESC(SYS_PMINTENCLR_EL1), access_pminten, NULL, PMINTENSET_EL1 },
1343
1344         { SYS_DESC(SYS_MAIR_EL1), access_vm_reg, reset_unknown, MAIR_EL1 },
1345         { SYS_DESC(SYS_AMAIR_EL1), access_vm_reg, reset_amair_el1, AMAIR_EL1 },
1346
1347         { SYS_DESC(SYS_LORSA_EL1), trap_undef },
1348         { SYS_DESC(SYS_LOREA_EL1), trap_undef },
1349         { SYS_DESC(SYS_LORN_EL1), trap_undef },
1350         { SYS_DESC(SYS_LORC_EL1), trap_undef },
1351         { SYS_DESC(SYS_LORID_EL1), trap_undef },
1352
1353         { SYS_DESC(SYS_VBAR_EL1), NULL, reset_val, VBAR_EL1, 0 },
1354         { SYS_DESC(SYS_DISR_EL1), NULL, reset_val, DISR_EL1, 0 },
1355
1356         { SYS_DESC(SYS_ICC_IAR0_EL1), write_to_read_only },
1357         { SYS_DESC(SYS_ICC_EOIR0_EL1), read_from_write_only },
1358         { SYS_DESC(SYS_ICC_HPPIR0_EL1), write_to_read_only },
1359         { SYS_DESC(SYS_ICC_DIR_EL1), read_from_write_only },
1360         { SYS_DESC(SYS_ICC_RPR_EL1), write_to_read_only },
1361         { SYS_DESC(SYS_ICC_SGI1R_EL1), access_gic_sgi },
1362         { SYS_DESC(SYS_ICC_ASGI1R_EL1), access_gic_sgi },
1363         { SYS_DESC(SYS_ICC_SGI0R_EL1), access_gic_sgi },
1364         { SYS_DESC(SYS_ICC_IAR1_EL1), write_to_read_only },
1365         { SYS_DESC(SYS_ICC_EOIR1_EL1), read_from_write_only },
1366         { SYS_DESC(SYS_ICC_HPPIR1_EL1), write_to_read_only },
1367         { SYS_DESC(SYS_ICC_SRE_EL1), access_gic_sre },
1368
1369         { SYS_DESC(SYS_CONTEXTIDR_EL1), access_vm_reg, reset_val, CONTEXTIDR_EL1, 0 },
1370         { SYS_DESC(SYS_TPIDR_EL1), NULL, reset_unknown, TPIDR_EL1 },
1371
1372         { SYS_DESC(SYS_CNTKCTL_EL1), NULL, reset_val, CNTKCTL_EL1, 0},
1373
1374         { SYS_DESC(SYS_CSSELR_EL1), NULL, reset_unknown, CSSELR_EL1 },
1375
1376         { SYS_DESC(SYS_PMCR_EL0), access_pmcr, reset_pmcr, PMCR_EL0 },
1377         { SYS_DESC(SYS_PMCNTENSET_EL0), access_pmcnten, reset_unknown, PMCNTENSET_EL0 },
1378         { SYS_DESC(SYS_PMCNTENCLR_EL0), access_pmcnten, NULL, PMCNTENSET_EL0 },
1379         { SYS_DESC(SYS_PMOVSCLR_EL0), access_pmovs, NULL, PMOVSSET_EL0 },
1380         { SYS_DESC(SYS_PMSWINC_EL0), access_pmswinc, reset_unknown, PMSWINC_EL0 },
1381         { SYS_DESC(SYS_PMSELR_EL0), access_pmselr, reset_unknown, PMSELR_EL0 },
1382         { SYS_DESC(SYS_PMCEID0_EL0), access_pmceid },
1383         { SYS_DESC(SYS_PMCEID1_EL0), access_pmceid },
1384         { SYS_DESC(SYS_PMCCNTR_EL0), access_pmu_evcntr, reset_unknown, PMCCNTR_EL0 },
1385         { SYS_DESC(SYS_PMXEVTYPER_EL0), access_pmu_evtyper },
1386         { SYS_DESC(SYS_PMXEVCNTR_EL0), access_pmu_evcntr },
1387         /*
1388          * PMUSERENR_EL0 resets as unknown in 64bit mode while it resets as zero
1389          * in 32bit mode. Here we choose to reset it as zero for consistency.
1390          */
1391         { SYS_DESC(SYS_PMUSERENR_EL0), access_pmuserenr, reset_val, PMUSERENR_EL0, 0 },
1392         { SYS_DESC(SYS_PMOVSSET_EL0), access_pmovs, reset_unknown, PMOVSSET_EL0 },
1393
1394         { SYS_DESC(SYS_TPIDR_EL0), NULL, reset_unknown, TPIDR_EL0 },
1395         { SYS_DESC(SYS_TPIDRRO_EL0), NULL, reset_unknown, TPIDRRO_EL0 },
1396
1397         { SYS_DESC(SYS_CNTP_TVAL_EL0), access_cntp_tval },
1398         { SYS_DESC(SYS_CNTP_CTL_EL0), access_cntp_ctl },
1399         { SYS_DESC(SYS_CNTP_CVAL_EL0), access_cntp_cval },
1400
1401         /* PMEVCNTRn_EL0 */
1402         PMU_PMEVCNTR_EL0(0),
1403         PMU_PMEVCNTR_EL0(1),
1404         PMU_PMEVCNTR_EL0(2),
1405         PMU_PMEVCNTR_EL0(3),
1406         PMU_PMEVCNTR_EL0(4),
1407         PMU_PMEVCNTR_EL0(5),
1408         PMU_PMEVCNTR_EL0(6),
1409         PMU_PMEVCNTR_EL0(7),
1410         PMU_PMEVCNTR_EL0(8),
1411         PMU_PMEVCNTR_EL0(9),
1412         PMU_PMEVCNTR_EL0(10),
1413         PMU_PMEVCNTR_EL0(11),
1414         PMU_PMEVCNTR_EL0(12),
1415         PMU_PMEVCNTR_EL0(13),
1416         PMU_PMEVCNTR_EL0(14),
1417         PMU_PMEVCNTR_EL0(15),
1418         PMU_PMEVCNTR_EL0(16),
1419         PMU_PMEVCNTR_EL0(17),
1420         PMU_PMEVCNTR_EL0(18),
1421         PMU_PMEVCNTR_EL0(19),
1422         PMU_PMEVCNTR_EL0(20),
1423         PMU_PMEVCNTR_EL0(21),
1424         PMU_PMEVCNTR_EL0(22),
1425         PMU_PMEVCNTR_EL0(23),
1426         PMU_PMEVCNTR_EL0(24),
1427         PMU_PMEVCNTR_EL0(25),
1428         PMU_PMEVCNTR_EL0(26),
1429         PMU_PMEVCNTR_EL0(27),
1430         PMU_PMEVCNTR_EL0(28),
1431         PMU_PMEVCNTR_EL0(29),
1432         PMU_PMEVCNTR_EL0(30),
1433         /* PMEVTYPERn_EL0 */
1434         PMU_PMEVTYPER_EL0(0),
1435         PMU_PMEVTYPER_EL0(1),
1436         PMU_PMEVTYPER_EL0(2),
1437         PMU_PMEVTYPER_EL0(3),
1438         PMU_PMEVTYPER_EL0(4),
1439         PMU_PMEVTYPER_EL0(5),
1440         PMU_PMEVTYPER_EL0(6),
1441         PMU_PMEVTYPER_EL0(7),
1442         PMU_PMEVTYPER_EL0(8),
1443         PMU_PMEVTYPER_EL0(9),
1444         PMU_PMEVTYPER_EL0(10),
1445         PMU_PMEVTYPER_EL0(11),
1446         PMU_PMEVTYPER_EL0(12),
1447         PMU_PMEVTYPER_EL0(13),
1448         PMU_PMEVTYPER_EL0(14),
1449         PMU_PMEVTYPER_EL0(15),
1450         PMU_PMEVTYPER_EL0(16),
1451         PMU_PMEVTYPER_EL0(17),
1452         PMU_PMEVTYPER_EL0(18),
1453         PMU_PMEVTYPER_EL0(19),
1454         PMU_PMEVTYPER_EL0(20),
1455         PMU_PMEVTYPER_EL0(21),
1456         PMU_PMEVTYPER_EL0(22),
1457         PMU_PMEVTYPER_EL0(23),
1458         PMU_PMEVTYPER_EL0(24),
1459         PMU_PMEVTYPER_EL0(25),
1460         PMU_PMEVTYPER_EL0(26),
1461         PMU_PMEVTYPER_EL0(27),
1462         PMU_PMEVTYPER_EL0(28),
1463         PMU_PMEVTYPER_EL0(29),
1464         PMU_PMEVTYPER_EL0(30),
1465         /*
1466          * PMCCFILTR_EL0 resets as unknown in 64bit mode while it resets as zero
1467          * in 32bit mode. Here we choose to reset it as zero for consistency.
1468          */
1469         { SYS_DESC(SYS_PMCCFILTR_EL0), access_pmu_evtyper, reset_val, PMCCFILTR_EL0, 0 },
1470
1471         { SYS_DESC(SYS_DACR32_EL2), NULL, reset_unknown, DACR32_EL2 },
1472         { SYS_DESC(SYS_IFSR32_EL2), NULL, reset_unknown, IFSR32_EL2 },
1473         { SYS_DESC(SYS_FPEXC32_EL2), NULL, reset_val, FPEXC32_EL2, 0x700 },
1474 };
1475
1476 static bool trap_dbgidr(struct kvm_vcpu *vcpu,
1477                         struct sys_reg_params *p,
1478                         const struct sys_reg_desc *r)
1479 {
1480         if (p->is_write) {
1481                 return ignore_write(vcpu, p);
1482         } else {
1483                 u64 dfr = read_sanitised_ftr_reg(SYS_ID_AA64DFR0_EL1);
1484                 u64 pfr = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1);
1485                 u32 el3 = !!cpuid_feature_extract_unsigned_field(pfr, ID_AA64PFR0_EL3_SHIFT);
1486
1487                 p->regval = ((((dfr >> ID_AA64DFR0_WRPS_SHIFT) & 0xf) << 28) |
1488                              (((dfr >> ID_AA64DFR0_BRPS_SHIFT) & 0xf) << 24) |
1489                              (((dfr >> ID_AA64DFR0_CTX_CMPS_SHIFT) & 0xf) << 20)
1490                              | (6 << 16) | (el3 << 14) | (el3 << 12));
1491                 return true;
1492         }
1493 }
1494
1495 static bool trap_debug32(struct kvm_vcpu *vcpu,
1496                          struct sys_reg_params *p,
1497                          const struct sys_reg_desc *r)
1498 {
1499         if (p->is_write) {
1500                 vcpu_cp14(vcpu, r->reg) = p->regval;
1501                 vcpu->arch.flags |= KVM_ARM64_DEBUG_DIRTY;
1502         } else {
1503                 p->regval = vcpu_cp14(vcpu, r->reg);
1504         }
1505
1506         return true;
1507 }
1508
1509 /* AArch32 debug register mappings
1510  *
1511  * AArch32 DBGBVRn is mapped to DBGBVRn_EL1[31:0]
1512  * AArch32 DBGBXVRn is mapped to DBGBVRn_EL1[63:32]
1513  *
1514  * All control registers and watchpoint value registers are mapped to
1515  * the lower 32 bits of their AArch64 equivalents. We share the trap
1516  * handlers with the above AArch64 code which checks what mode the
1517  * system is in.
1518  */
1519
1520 static bool trap_xvr(struct kvm_vcpu *vcpu,
1521                      struct sys_reg_params *p,
1522                      const struct sys_reg_desc *rd)
1523 {
1524         u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_bvr[rd->reg];
1525
1526         if (p->is_write) {
1527                 u64 val = *dbg_reg;
1528
1529                 val &= 0xffffffffUL;
1530                 val |= p->regval << 32;
1531                 *dbg_reg = val;
1532
1533                 vcpu->arch.flags |= KVM_ARM64_DEBUG_DIRTY;
1534         } else {
1535                 p->regval = *dbg_reg >> 32;
1536         }
1537
1538         trace_trap_reg(__func__, rd->reg, p->is_write, *dbg_reg);
1539
1540         return true;
1541 }
1542
1543 #define DBG_BCR_BVR_WCR_WVR(n)                                          \
1544         /* DBGBVRn */                                                   \
1545         { Op1( 0), CRn( 0), CRm((n)), Op2( 4), trap_bvr, NULL, n },     \
1546         /* DBGBCRn */                                                   \
1547         { Op1( 0), CRn( 0), CRm((n)), Op2( 5), trap_bcr, NULL, n },     \
1548         /* DBGWVRn */                                                   \
1549         { Op1( 0), CRn( 0), CRm((n)), Op2( 6), trap_wvr, NULL, n },     \
1550         /* DBGWCRn */                                                   \
1551         { Op1( 0), CRn( 0), CRm((n)), Op2( 7), trap_wcr, NULL, n }
1552
1553 #define DBGBXVR(n)                                                      \
1554         { Op1( 0), CRn( 1), CRm((n)), Op2( 1), trap_xvr, NULL, n }
1555
1556 /*
1557  * Trapped cp14 registers. We generally ignore most of the external
1558  * debug, on the principle that they don't really make sense to a
1559  * guest. Revisit this one day, would this principle change.
1560  */
1561 static const struct sys_reg_desc cp14_regs[] = {
1562         /* DBGIDR */
1563         { Op1( 0), CRn( 0), CRm( 0), Op2( 0), trap_dbgidr },
1564         /* DBGDTRRXext */
1565         { Op1( 0), CRn( 0), CRm( 0), Op2( 2), trap_raz_wi },
1566
1567         DBG_BCR_BVR_WCR_WVR(0),
1568         /* DBGDSCRint */
1569         { Op1( 0), CRn( 0), CRm( 1), Op2( 0), trap_raz_wi },
1570         DBG_BCR_BVR_WCR_WVR(1),
1571         /* DBGDCCINT */
1572         { Op1( 0), CRn( 0), CRm( 2), Op2( 0), trap_debug32, NULL, cp14_DBGDCCINT },
1573         /* DBGDSCRext */
1574         { Op1( 0), CRn( 0), CRm( 2), Op2( 2), trap_debug32, NULL, cp14_DBGDSCRext },
1575         DBG_BCR_BVR_WCR_WVR(2),
1576         /* DBGDTR[RT]Xint */
1577         { Op1( 0), CRn( 0), CRm( 3), Op2( 0), trap_raz_wi },
1578         /* DBGDTR[RT]Xext */
1579         { Op1( 0), CRn( 0), CRm( 3), Op2( 2), trap_raz_wi },
1580         DBG_BCR_BVR_WCR_WVR(3),
1581         DBG_BCR_BVR_WCR_WVR(4),
1582         DBG_BCR_BVR_WCR_WVR(5),
1583         /* DBGWFAR */
1584         { Op1( 0), CRn( 0), CRm( 6), Op2( 0), trap_raz_wi },
1585         /* DBGOSECCR */
1586         { Op1( 0), CRn( 0), CRm( 6), Op2( 2), trap_raz_wi },
1587         DBG_BCR_BVR_WCR_WVR(6),
1588         /* DBGVCR */
1589         { Op1( 0), CRn( 0), CRm( 7), Op2( 0), trap_debug32, NULL, cp14_DBGVCR },
1590         DBG_BCR_BVR_WCR_WVR(7),
1591         DBG_BCR_BVR_WCR_WVR(8),
1592         DBG_BCR_BVR_WCR_WVR(9),
1593         DBG_BCR_BVR_WCR_WVR(10),
1594         DBG_BCR_BVR_WCR_WVR(11),
1595         DBG_BCR_BVR_WCR_WVR(12),
1596         DBG_BCR_BVR_WCR_WVR(13),
1597         DBG_BCR_BVR_WCR_WVR(14),
1598         DBG_BCR_BVR_WCR_WVR(15),
1599
1600         /* DBGDRAR (32bit) */
1601         { Op1( 0), CRn( 1), CRm( 0), Op2( 0), trap_raz_wi },
1602
1603         DBGBXVR(0),
1604         /* DBGOSLAR */
1605         { Op1( 0), CRn( 1), CRm( 0), Op2( 4), trap_raz_wi },
1606         DBGBXVR(1),
1607         /* DBGOSLSR */
1608         { Op1( 0), CRn( 1), CRm( 1), Op2( 4), trap_oslsr_el1 },
1609         DBGBXVR(2),
1610         DBGBXVR(3),
1611         /* DBGOSDLR */
1612         { Op1( 0), CRn( 1), CRm( 3), Op2( 4), trap_raz_wi },
1613         DBGBXVR(4),
1614         /* DBGPRCR */
1615         { Op1( 0), CRn( 1), CRm( 4), Op2( 4), trap_raz_wi },
1616         DBGBXVR(5),
1617         DBGBXVR(6),
1618         DBGBXVR(7),
1619         DBGBXVR(8),
1620         DBGBXVR(9),
1621         DBGBXVR(10),
1622         DBGBXVR(11),
1623         DBGBXVR(12),
1624         DBGBXVR(13),
1625         DBGBXVR(14),
1626         DBGBXVR(15),
1627
1628         /* DBGDSAR (32bit) */
1629         { Op1( 0), CRn( 2), CRm( 0), Op2( 0), trap_raz_wi },
1630
1631         /* DBGDEVID2 */
1632         { Op1( 0), CRn( 7), CRm( 0), Op2( 7), trap_raz_wi },
1633         /* DBGDEVID1 */
1634         { Op1( 0), CRn( 7), CRm( 1), Op2( 7), trap_raz_wi },
1635         /* DBGDEVID */
1636         { Op1( 0), CRn( 7), CRm( 2), Op2( 7), trap_raz_wi },
1637         /* DBGCLAIMSET */
1638         { Op1( 0), CRn( 7), CRm( 8), Op2( 6), trap_raz_wi },
1639         /* DBGCLAIMCLR */
1640         { Op1( 0), CRn( 7), CRm( 9), Op2( 6), trap_raz_wi },
1641         /* DBGAUTHSTATUS */
1642         { Op1( 0), CRn( 7), CRm(14), Op2( 6), trap_dbgauthstatus_el1 },
1643 };
1644
1645 /* Trapped cp14 64bit registers */
1646 static const struct sys_reg_desc cp14_64_regs[] = {
1647         /* DBGDRAR (64bit) */
1648         { Op1( 0), CRm( 1), .access = trap_raz_wi },
1649
1650         /* DBGDSAR (64bit) */
1651         { Op1( 0), CRm( 2), .access = trap_raz_wi },
1652 };
1653
1654 /* Macro to expand the PMEVCNTRn register */
1655 #define PMU_PMEVCNTR(n)                                                 \
1656         /* PMEVCNTRn */                                                 \
1657         { Op1(0), CRn(0b1110),                                          \
1658           CRm((0b1000 | (((n) >> 3) & 0x3))), Op2(((n) & 0x7)),         \
1659           access_pmu_evcntr }
1660
1661 /* Macro to expand the PMEVTYPERn register */
1662 #define PMU_PMEVTYPER(n)                                                \
1663         /* PMEVTYPERn */                                                \
1664         { Op1(0), CRn(0b1110),                                          \
1665           CRm((0b1100 | (((n) >> 3) & 0x3))), Op2(((n) & 0x7)),         \
1666           access_pmu_evtyper }
1667
1668 /*
1669  * Trapped cp15 registers. TTBR0/TTBR1 get a double encoding,
1670  * depending on the way they are accessed (as a 32bit or a 64bit
1671  * register).
1672  */
1673 static const struct sys_reg_desc cp15_regs[] = {
1674         { Op1( 0), CRn( 1), CRm( 0), Op2( 0), access_vm_reg, NULL, c1_SCTLR },
1675         { Op1( 0), CRn( 2), CRm( 0), Op2( 0), access_vm_reg, NULL, c2_TTBR0 },
1676         { Op1( 0), CRn( 2), CRm( 0), Op2( 1), access_vm_reg, NULL, c2_TTBR1 },
1677         { Op1( 0), CRn( 2), CRm( 0), Op2( 2), access_vm_reg, NULL, c2_TTBCR },
1678         { Op1( 0), CRn( 2), CRm( 0), Op2( 3), access_vm_reg, NULL, c2_TTBCR2 },
1679         { Op1( 0), CRn( 3), CRm( 0), Op2( 0), access_vm_reg, NULL, c3_DACR },
1680         { Op1( 0), CRn( 5), CRm( 0), Op2( 0), access_vm_reg, NULL, c5_DFSR },
1681         { Op1( 0), CRn( 5), CRm( 0), Op2( 1), access_vm_reg, NULL, c5_IFSR },
1682         { Op1( 0), CRn( 5), CRm( 1), Op2( 0), access_vm_reg, NULL, c5_ADFSR },
1683         { Op1( 0), CRn( 5), CRm( 1), Op2( 1), access_vm_reg, NULL, c5_AIFSR },
1684         { Op1( 0), CRn( 6), CRm( 0), Op2( 0), access_vm_reg, NULL, c6_DFAR },
1685         { Op1( 0), CRn( 6), CRm( 0), Op2( 2), access_vm_reg, NULL, c6_IFAR },
1686
1687         /*
1688          * DC{C,I,CI}SW operations:
1689          */
1690         { Op1( 0), CRn( 7), CRm( 6), Op2( 2), access_dcsw },
1691         { Op1( 0), CRn( 7), CRm(10), Op2( 2), access_dcsw },
1692         { Op1( 0), CRn( 7), CRm(14), Op2( 2), access_dcsw },
1693
1694         /* PMU */
1695         { Op1( 0), CRn( 9), CRm(12), Op2( 0), access_pmcr },
1696         { Op1( 0), CRn( 9), CRm(12), Op2( 1), access_pmcnten },
1697         { Op1( 0), CRn( 9), CRm(12), Op2( 2), access_pmcnten },
1698         { Op1( 0), CRn( 9), CRm(12), Op2( 3), access_pmovs },
1699         { Op1( 0), CRn( 9), CRm(12), Op2( 4), access_pmswinc },
1700         { Op1( 0), CRn( 9), CRm(12), Op2( 5), access_pmselr },
1701         { Op1( 0), CRn( 9), CRm(12), Op2( 6), access_pmceid },
1702         { Op1( 0), CRn( 9), CRm(12), Op2( 7), access_pmceid },
1703         { Op1( 0), CRn( 9), CRm(13), Op2( 0), access_pmu_evcntr },
1704         { Op1( 0), CRn( 9), CRm(13), Op2( 1), access_pmu_evtyper },
1705         { Op1( 0), CRn( 9), CRm(13), Op2( 2), access_pmu_evcntr },
1706         { Op1( 0), CRn( 9), CRm(14), Op2( 0), access_pmuserenr },
1707         { Op1( 0), CRn( 9), CRm(14), Op2( 1), access_pminten },
1708         { Op1( 0), CRn( 9), CRm(14), Op2( 2), access_pminten },
1709         { Op1( 0), CRn( 9), CRm(14), Op2( 3), access_pmovs },
1710
1711         { Op1( 0), CRn(10), CRm( 2), Op2( 0), access_vm_reg, NULL, c10_PRRR },
1712         { Op1( 0), CRn(10), CRm( 2), Op2( 1), access_vm_reg, NULL, c10_NMRR },
1713         { Op1( 0), CRn(10), CRm( 3), Op2( 0), access_vm_reg, NULL, c10_AMAIR0 },
1714         { Op1( 0), CRn(10), CRm( 3), Op2( 1), access_vm_reg, NULL, c10_AMAIR1 },
1715
1716         /* ICC_SRE */
1717         { Op1( 0), CRn(12), CRm(12), Op2( 5), access_gic_sre },
1718
1719         { Op1( 0), CRn(13), CRm( 0), Op2( 1), access_vm_reg, NULL, c13_CID },
1720
1721         /* CNTP_TVAL */
1722         { Op1( 0), CRn(14), CRm( 2), Op2( 0), access_cntp_tval },
1723         /* CNTP_CTL */
1724         { Op1( 0), CRn(14), CRm( 2), Op2( 1), access_cntp_ctl },
1725
1726         /* PMEVCNTRn */
1727         PMU_PMEVCNTR(0),
1728         PMU_PMEVCNTR(1),
1729         PMU_PMEVCNTR(2),
1730         PMU_PMEVCNTR(3),
1731         PMU_PMEVCNTR(4),
1732         PMU_PMEVCNTR(5),
1733         PMU_PMEVCNTR(6),
1734         PMU_PMEVCNTR(7),
1735         PMU_PMEVCNTR(8),
1736         PMU_PMEVCNTR(9),
1737         PMU_PMEVCNTR(10),
1738         PMU_PMEVCNTR(11),
1739         PMU_PMEVCNTR(12),
1740         PMU_PMEVCNTR(13),
1741         PMU_PMEVCNTR(14),
1742         PMU_PMEVCNTR(15),
1743         PMU_PMEVCNTR(16),
1744         PMU_PMEVCNTR(17),
1745         PMU_PMEVCNTR(18),
1746         PMU_PMEVCNTR(19),
1747         PMU_PMEVCNTR(20),
1748         PMU_PMEVCNTR(21),
1749         PMU_PMEVCNTR(22),
1750         PMU_PMEVCNTR(23),
1751         PMU_PMEVCNTR(24),
1752         PMU_PMEVCNTR(25),
1753         PMU_PMEVCNTR(26),
1754         PMU_PMEVCNTR(27),
1755         PMU_PMEVCNTR(28),
1756         PMU_PMEVCNTR(29),
1757         PMU_PMEVCNTR(30),
1758         /* PMEVTYPERn */
1759         PMU_PMEVTYPER(0),
1760         PMU_PMEVTYPER(1),
1761         PMU_PMEVTYPER(2),
1762         PMU_PMEVTYPER(3),
1763         PMU_PMEVTYPER(4),
1764         PMU_PMEVTYPER(5),
1765         PMU_PMEVTYPER(6),
1766         PMU_PMEVTYPER(7),
1767         PMU_PMEVTYPER(8),
1768         PMU_PMEVTYPER(9),
1769         PMU_PMEVTYPER(10),
1770         PMU_PMEVTYPER(11),
1771         PMU_PMEVTYPER(12),
1772         PMU_PMEVTYPER(13),
1773         PMU_PMEVTYPER(14),
1774         PMU_PMEVTYPER(15),
1775         PMU_PMEVTYPER(16),
1776         PMU_PMEVTYPER(17),
1777         PMU_PMEVTYPER(18),
1778         PMU_PMEVTYPER(19),
1779         PMU_PMEVTYPER(20),
1780         PMU_PMEVTYPER(21),
1781         PMU_PMEVTYPER(22),
1782         PMU_PMEVTYPER(23),
1783         PMU_PMEVTYPER(24),
1784         PMU_PMEVTYPER(25),
1785         PMU_PMEVTYPER(26),
1786         PMU_PMEVTYPER(27),
1787         PMU_PMEVTYPER(28),
1788         PMU_PMEVTYPER(29),
1789         PMU_PMEVTYPER(30),
1790         /* PMCCFILTR */
1791         { Op1(0), CRn(14), CRm(15), Op2(7), access_pmu_evtyper },
1792 };
1793
1794 static const struct sys_reg_desc cp15_64_regs[] = {
1795         { Op1( 0), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, c2_TTBR0 },
1796         { Op1( 0), CRn( 0), CRm( 9), Op2( 0), access_pmu_evcntr },
1797         { Op1( 0), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_SGI1R */
1798         { Op1( 1), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, c2_TTBR1 },
1799         { Op1( 1), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_ASGI1R */
1800         { Op1( 2), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_SGI0R */
1801         { Op1( 2), CRn( 0), CRm(14), Op2( 0), access_cntp_cval },
1802 };
1803
1804 /* Target specific emulation tables */
1805 static struct kvm_sys_reg_target_table *target_tables[KVM_ARM_NUM_TARGETS];
1806
1807 void kvm_register_target_sys_reg_table(unsigned int target,
1808                                        struct kvm_sys_reg_target_table *table)
1809 {
1810         target_tables[target] = table;
1811 }
1812
1813 /* Get specific register table for this target. */
1814 static const struct sys_reg_desc *get_target_table(unsigned target,
1815                                                    bool mode_is_64,
1816                                                    size_t *num)
1817 {
1818         struct kvm_sys_reg_target_table *table;
1819
1820         table = target_tables[target];
1821         if (mode_is_64) {
1822                 *num = table->table64.num;
1823                 return table->table64.table;
1824         } else {
1825                 *num = table->table32.num;
1826                 return table->table32.table;
1827         }
1828 }
1829
1830 #define reg_to_match_value(x)                                           \
1831         ({                                                              \
1832                 unsigned long val;                                      \
1833                 val  = (x)->Op0 << 14;                                  \
1834                 val |= (x)->Op1 << 11;                                  \
1835                 val |= (x)->CRn << 7;                                   \
1836                 val |= (x)->CRm << 3;                                   \
1837                 val |= (x)->Op2;                                        \
1838                 val;                                                    \
1839          })
1840
1841 static int match_sys_reg(const void *key, const void *elt)
1842 {
1843         const unsigned long pval = (unsigned long)key;
1844         const struct sys_reg_desc *r = elt;
1845
1846         return pval - reg_to_match_value(r);
1847 }
1848
1849 static const struct sys_reg_desc *find_reg(const struct sys_reg_params *params,
1850                                          const struct sys_reg_desc table[],
1851                                          unsigned int num)
1852 {
1853         unsigned long pval = reg_to_match_value(params);
1854
1855         return bsearch((void *)pval, table, num, sizeof(table[0]), match_sys_reg);
1856 }
1857
1858 int kvm_handle_cp14_load_store(struct kvm_vcpu *vcpu, struct kvm_run *run)
1859 {
1860         kvm_inject_undefined(vcpu);
1861         return 1;
1862 }
1863
1864 static void perform_access(struct kvm_vcpu *vcpu,
1865                            struct sys_reg_params *params,
1866                            const struct sys_reg_desc *r)
1867 {
1868         /*
1869          * Not having an accessor means that we have configured a trap
1870          * that we don't know how to handle. This certainly qualifies
1871          * as a gross bug that should be fixed right away.
1872          */
1873         BUG_ON(!r->access);
1874
1875         /* Skip instruction if instructed so */
1876         if (likely(r->access(vcpu, params, r)))
1877                 kvm_skip_instr(vcpu, kvm_vcpu_trap_il_is32bit(vcpu));
1878 }
1879
1880 /*
1881  * emulate_cp --  tries to match a sys_reg access in a handling table, and
1882  *                call the corresponding trap handler.
1883  *
1884  * @params: pointer to the descriptor of the access
1885  * @table: array of trap descriptors
1886  * @num: size of the trap descriptor array
1887  *
1888  * Return 0 if the access has been handled, and -1 if not.
1889  */
1890 static int emulate_cp(struct kvm_vcpu *vcpu,
1891                       struct sys_reg_params *params,
1892                       const struct sys_reg_desc *table,
1893                       size_t num)
1894 {
1895         const struct sys_reg_desc *r;
1896
1897         if (!table)
1898                 return -1;      /* Not handled */
1899
1900         r = find_reg(params, table, num);
1901
1902         if (r) {
1903                 perform_access(vcpu, params, r);
1904                 return 0;
1905         }
1906
1907         /* Not handled */
1908         return -1;
1909 }
1910
1911 static void unhandled_cp_access(struct kvm_vcpu *vcpu,
1912                                 struct sys_reg_params *params)
1913 {
1914         u8 hsr_ec = kvm_vcpu_trap_get_class(vcpu);
1915         int cp = -1;
1916
1917         switch(hsr_ec) {
1918         case ESR_ELx_EC_CP15_32:
1919         case ESR_ELx_EC_CP15_64:
1920                 cp = 15;
1921                 break;
1922         case ESR_ELx_EC_CP14_MR:
1923         case ESR_ELx_EC_CP14_64:
1924                 cp = 14;
1925                 break;
1926         default:
1927                 WARN_ON(1);
1928         }
1929
1930         kvm_err("Unsupported guest CP%d access at: %08lx\n",
1931                 cp, *vcpu_pc(vcpu));
1932         print_sys_reg_instr(params);
1933         kvm_inject_undefined(vcpu);
1934 }
1935
1936 /**
1937  * kvm_handle_cp_64 -- handles a mrrc/mcrr trap on a guest CP14/CP15 access
1938  * @vcpu: The VCPU pointer
1939  * @run:  The kvm_run struct
1940  */
1941 static int kvm_handle_cp_64(struct kvm_vcpu *vcpu,
1942                             const struct sys_reg_desc *global,
1943                             size_t nr_global,
1944                             const struct sys_reg_desc *target_specific,
1945                             size_t nr_specific)
1946 {
1947         struct sys_reg_params params;
1948         u32 hsr = kvm_vcpu_get_hsr(vcpu);
1949         int Rt = kvm_vcpu_sys_get_rt(vcpu);
1950         int Rt2 = (hsr >> 10) & 0x1f;
1951
1952         params.is_aarch32 = true;
1953         params.is_32bit = false;
1954         params.CRm = (hsr >> 1) & 0xf;
1955         params.is_write = ((hsr & 1) == 0);
1956
1957         params.Op0 = 0;
1958         params.Op1 = (hsr >> 16) & 0xf;
1959         params.Op2 = 0;
1960         params.CRn = 0;
1961
1962         /*
1963          * Make a 64-bit value out of Rt and Rt2. As we use the same trap
1964          * backends between AArch32 and AArch64, we get away with it.
1965          */
1966         if (params.is_write) {
1967                 params.regval = vcpu_get_reg(vcpu, Rt) & 0xffffffff;
1968                 params.regval |= vcpu_get_reg(vcpu, Rt2) << 32;
1969         }
1970
1971         /*
1972          * Try to emulate the coprocessor access using the target
1973          * specific table first, and using the global table afterwards.
1974          * If either of the tables contains a handler, handle the
1975          * potential register operation in the case of a read and return
1976          * with success.
1977          */
1978         if (!emulate_cp(vcpu, &params, target_specific, nr_specific) ||
1979             !emulate_cp(vcpu, &params, global, nr_global)) {
1980                 /* Split up the value between registers for the read side */
1981                 if (!params.is_write) {
1982                         vcpu_set_reg(vcpu, Rt, lower_32_bits(params.regval));
1983                         vcpu_set_reg(vcpu, Rt2, upper_32_bits(params.regval));
1984                 }
1985
1986                 return 1;
1987         }
1988
1989         unhandled_cp_access(vcpu, &params);
1990         return 1;
1991 }
1992
1993 /**
1994  * kvm_handle_cp_32 -- handles a mrc/mcr trap on a guest CP14/CP15 access
1995  * @vcpu: The VCPU pointer
1996  * @run:  The kvm_run struct
1997  */
1998 static int kvm_handle_cp_32(struct kvm_vcpu *vcpu,
1999                             const struct sys_reg_desc *global,
2000                             size_t nr_global,
2001                             const struct sys_reg_desc *target_specific,
2002                             size_t nr_specific)
2003 {
2004         struct sys_reg_params params;
2005         u32 hsr = kvm_vcpu_get_hsr(vcpu);
2006         int Rt  = kvm_vcpu_sys_get_rt(vcpu);
2007
2008         params.is_aarch32 = true;
2009         params.is_32bit = true;
2010         params.CRm = (hsr >> 1) & 0xf;
2011         params.regval = vcpu_get_reg(vcpu, Rt);
2012         params.is_write = ((hsr & 1) == 0);
2013         params.CRn = (hsr >> 10) & 0xf;
2014         params.Op0 = 0;
2015         params.Op1 = (hsr >> 14) & 0x7;
2016         params.Op2 = (hsr >> 17) & 0x7;
2017
2018         if (!emulate_cp(vcpu, &params, target_specific, nr_specific) ||
2019             !emulate_cp(vcpu, &params, global, nr_global)) {
2020                 if (!params.is_write)
2021                         vcpu_set_reg(vcpu, Rt, params.regval);
2022                 return 1;
2023         }
2024
2025         unhandled_cp_access(vcpu, &params);
2026         return 1;
2027 }
2028
2029 int kvm_handle_cp15_64(struct kvm_vcpu *vcpu, struct kvm_run *run)
2030 {
2031         const struct sys_reg_desc *target_specific;
2032         size_t num;
2033
2034         target_specific = get_target_table(vcpu->arch.target, false, &num);
2035         return kvm_handle_cp_64(vcpu,
2036                                 cp15_64_regs, ARRAY_SIZE(cp15_64_regs),
2037                                 target_specific, num);
2038 }
2039
2040 int kvm_handle_cp15_32(struct kvm_vcpu *vcpu, struct kvm_run *run)
2041 {
2042         const struct sys_reg_desc *target_specific;
2043         size_t num;
2044
2045         target_specific = get_target_table(vcpu->arch.target, false, &num);
2046         return kvm_handle_cp_32(vcpu,
2047                                 cp15_regs, ARRAY_SIZE(cp15_regs),
2048                                 target_specific, num);
2049 }
2050
2051 int kvm_handle_cp14_64(struct kvm_vcpu *vcpu, struct kvm_run *run)
2052 {
2053         return kvm_handle_cp_64(vcpu,
2054                                 cp14_64_regs, ARRAY_SIZE(cp14_64_regs),
2055                                 NULL, 0);
2056 }
2057
2058 int kvm_handle_cp14_32(struct kvm_vcpu *vcpu, struct kvm_run *run)
2059 {
2060         return kvm_handle_cp_32(vcpu,
2061                                 cp14_regs, ARRAY_SIZE(cp14_regs),
2062                                 NULL, 0);
2063 }
2064
2065 static int emulate_sys_reg(struct kvm_vcpu *vcpu,
2066                            struct sys_reg_params *params)
2067 {
2068         size_t num;
2069         const struct sys_reg_desc *table, *r;
2070
2071         table = get_target_table(vcpu->arch.target, true, &num);
2072
2073         /* Search target-specific then generic table. */
2074         r = find_reg(params, table, num);
2075         if (!r)
2076                 r = find_reg(params, sys_reg_descs, ARRAY_SIZE(sys_reg_descs));
2077
2078         if (likely(r)) {
2079                 perform_access(vcpu, params, r);
2080         } else {
2081                 kvm_err("Unsupported guest sys_reg access at: %lx\n",
2082                         *vcpu_pc(vcpu));
2083                 print_sys_reg_instr(params);
2084                 kvm_inject_undefined(vcpu);
2085         }
2086         return 1;
2087 }
2088
2089 static void reset_sys_reg_descs(struct kvm_vcpu *vcpu,
2090                                 const struct sys_reg_desc *table, size_t num,
2091                                 unsigned long *bmap)
2092 {
2093         unsigned long i;
2094
2095         for (i = 0; i < num; i++)
2096                 if (table[i].reset) {
2097                         int reg = table[i].reg;
2098
2099                         table[i].reset(vcpu, &table[i]);
2100                         if (reg > 0 && reg < NR_SYS_REGS)
2101                                 set_bit(reg, bmap);
2102                 }
2103 }
2104
2105 /**
2106  * kvm_handle_sys_reg -- handles a mrs/msr trap on a guest sys_reg access
2107  * @vcpu: The VCPU pointer
2108  * @run:  The kvm_run struct
2109  */
2110 int kvm_handle_sys_reg(struct kvm_vcpu *vcpu, struct kvm_run *run)
2111 {
2112         struct sys_reg_params params;
2113         unsigned long esr = kvm_vcpu_get_hsr(vcpu);
2114         int Rt = kvm_vcpu_sys_get_rt(vcpu);
2115         int ret;
2116
2117         trace_kvm_handle_sys_reg(esr);
2118
2119         params.is_aarch32 = false;
2120         params.is_32bit = false;
2121         params.Op0 = (esr >> 20) & 3;
2122         params.Op1 = (esr >> 14) & 0x7;
2123         params.CRn = (esr >> 10) & 0xf;
2124         params.CRm = (esr >> 1) & 0xf;
2125         params.Op2 = (esr >> 17) & 0x7;
2126         params.regval = vcpu_get_reg(vcpu, Rt);
2127         params.is_write = !(esr & 1);
2128
2129         ret = emulate_sys_reg(vcpu, &params);
2130
2131         if (!params.is_write)
2132                 vcpu_set_reg(vcpu, Rt, params.regval);
2133         return ret;
2134 }
2135
2136 /******************************************************************************
2137  * Userspace API
2138  *****************************************************************************/
2139
2140 static bool index_to_params(u64 id, struct sys_reg_params *params)
2141 {
2142         switch (id & KVM_REG_SIZE_MASK) {
2143         case KVM_REG_SIZE_U64:
2144                 /* Any unused index bits means it's not valid. */
2145                 if (id & ~(KVM_REG_ARCH_MASK | KVM_REG_SIZE_MASK
2146                               | KVM_REG_ARM_COPROC_MASK
2147                               | KVM_REG_ARM64_SYSREG_OP0_MASK
2148                               | KVM_REG_ARM64_SYSREG_OP1_MASK
2149                               | KVM_REG_ARM64_SYSREG_CRN_MASK
2150                               | KVM_REG_ARM64_SYSREG_CRM_MASK
2151                               | KVM_REG_ARM64_SYSREG_OP2_MASK))
2152                         return false;
2153                 params->Op0 = ((id & KVM_REG_ARM64_SYSREG_OP0_MASK)
2154                                >> KVM_REG_ARM64_SYSREG_OP0_SHIFT);
2155                 params->Op1 = ((id & KVM_REG_ARM64_SYSREG_OP1_MASK)
2156                                >> KVM_REG_ARM64_SYSREG_OP1_SHIFT);
2157                 params->CRn = ((id & KVM_REG_ARM64_SYSREG_CRN_MASK)
2158                                >> KVM_REG_ARM64_SYSREG_CRN_SHIFT);
2159                 params->CRm = ((id & KVM_REG_ARM64_SYSREG_CRM_MASK)
2160                                >> KVM_REG_ARM64_SYSREG_CRM_SHIFT);
2161                 params->Op2 = ((id & KVM_REG_ARM64_SYSREG_OP2_MASK)
2162                                >> KVM_REG_ARM64_SYSREG_OP2_SHIFT);
2163                 return true;
2164         default:
2165                 return false;
2166         }
2167 }
2168
2169 const struct sys_reg_desc *find_reg_by_id(u64 id,
2170                                           struct sys_reg_params *params,
2171                                           const struct sys_reg_desc table[],
2172                                           unsigned int num)
2173 {
2174         if (!index_to_params(id, params))
2175                 return NULL;
2176
2177         return find_reg(params, table, num);
2178 }
2179
2180 /* Decode an index value, and find the sys_reg_desc entry. */
2181 static const struct sys_reg_desc *index_to_sys_reg_desc(struct kvm_vcpu *vcpu,
2182                                                     u64 id)
2183 {
2184         size_t num;
2185         const struct sys_reg_desc *table, *r;
2186         struct sys_reg_params params;
2187
2188         /* We only do sys_reg for now. */
2189         if ((id & KVM_REG_ARM_COPROC_MASK) != KVM_REG_ARM64_SYSREG)
2190                 return NULL;
2191
2192         if (!index_to_params(id, &params))
2193                 return NULL;
2194
2195         table = get_target_table(vcpu->arch.target, true, &num);
2196         r = find_reg(&params, table, num);
2197         if (!r)
2198                 r = find_reg(&params, sys_reg_descs, ARRAY_SIZE(sys_reg_descs));
2199
2200         /* Not saved in the sys_reg array and not otherwise accessible? */
2201         if (r && !(r->reg || r->get_user))
2202                 r = NULL;
2203
2204         return r;
2205 }
2206
2207 /*
2208  * These are the invariant sys_reg registers: we let the guest see the
2209  * host versions of these, so they're part of the guest state.
2210  *
2211  * A future CPU may provide a mechanism to present different values to
2212  * the guest, or a future kvm may trap them.
2213  */
2214
2215 #define FUNCTION_INVARIANT(reg)                                         \
2216         static void get_##reg(struct kvm_vcpu *v,                       \
2217                               const struct sys_reg_desc *r)             \
2218         {                                                               \
2219                 ((struct sys_reg_desc *)r)->val = read_sysreg(reg);     \
2220         }
2221
2222 FUNCTION_INVARIANT(midr_el1)
2223 FUNCTION_INVARIANT(ctr_el0)
2224 FUNCTION_INVARIANT(revidr_el1)
2225 FUNCTION_INVARIANT(clidr_el1)
2226 FUNCTION_INVARIANT(aidr_el1)
2227
2228 /* ->val is filled in by kvm_sys_reg_table_init() */
2229 static struct sys_reg_desc invariant_sys_regs[] = {
2230         { SYS_DESC(SYS_MIDR_EL1), NULL, get_midr_el1 },
2231         { SYS_DESC(SYS_REVIDR_EL1), NULL, get_revidr_el1 },
2232         { SYS_DESC(SYS_CLIDR_EL1), NULL, get_clidr_el1 },
2233         { SYS_DESC(SYS_AIDR_EL1), NULL, get_aidr_el1 },
2234         { SYS_DESC(SYS_CTR_EL0), NULL, get_ctr_el0 },
2235 };
2236
2237 static int reg_from_user(u64 *val, const void __user *uaddr, u64 id)
2238 {
2239         if (copy_from_user(val, uaddr, KVM_REG_SIZE(id)) != 0)
2240                 return -EFAULT;
2241         return 0;
2242 }
2243
2244 static int reg_to_user(void __user *uaddr, const u64 *val, u64 id)
2245 {
2246         if (copy_to_user(uaddr, val, KVM_REG_SIZE(id)) != 0)
2247                 return -EFAULT;
2248         return 0;
2249 }
2250
2251 static int get_invariant_sys_reg(u64 id, void __user *uaddr)
2252 {
2253         struct sys_reg_params params;
2254         const struct sys_reg_desc *r;
2255
2256         r = find_reg_by_id(id, &params, invariant_sys_regs,
2257                            ARRAY_SIZE(invariant_sys_regs));
2258         if (!r)
2259                 return -ENOENT;
2260
2261         return reg_to_user(uaddr, &r->val, id);
2262 }
2263
2264 static int set_invariant_sys_reg(u64 id, void __user *uaddr)
2265 {
2266         struct sys_reg_params params;
2267         const struct sys_reg_desc *r;
2268         int err;
2269         u64 val = 0; /* Make sure high bits are 0 for 32-bit regs */
2270
2271         r = find_reg_by_id(id, &params, invariant_sys_regs,
2272                            ARRAY_SIZE(invariant_sys_regs));
2273         if (!r)
2274                 return -ENOENT;
2275
2276         err = reg_from_user(&val, uaddr, id);
2277         if (err)
2278                 return err;
2279
2280         /* This is what we mean by invariant: you can't change it. */
2281         if (r->val != val)
2282                 return -EINVAL;
2283
2284         return 0;
2285 }
2286
2287 static bool is_valid_cache(u32 val)
2288 {
2289         u32 level, ctype;
2290
2291         if (val >= CSSELR_MAX)
2292                 return false;
2293
2294         /* Bottom bit is Instruction or Data bit.  Next 3 bits are level. */
2295         level = (val >> 1);
2296         ctype = (cache_levels >> (level * 3)) & 7;
2297
2298         switch (ctype) {
2299         case 0: /* No cache */
2300                 return false;
2301         case 1: /* Instruction cache only */
2302                 return (val & 1);
2303         case 2: /* Data cache only */
2304         case 4: /* Unified cache */
2305                 return !(val & 1);
2306         case 3: /* Separate instruction and data caches */
2307                 return true;
2308         default: /* Reserved: we can't know instruction or data. */
2309                 return false;
2310         }
2311 }
2312
2313 static int demux_c15_get(u64 id, void __user *uaddr)
2314 {
2315         u32 val;
2316         u32 __user *uval = uaddr;
2317
2318         /* Fail if we have unknown bits set. */
2319         if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK
2320                    | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1)))
2321                 return -ENOENT;
2322
2323         switch (id & KVM_REG_ARM_DEMUX_ID_MASK) {
2324         case KVM_REG_ARM_DEMUX_ID_CCSIDR:
2325                 if (KVM_REG_SIZE(id) != 4)
2326                         return -ENOENT;
2327                 val = (id & KVM_REG_ARM_DEMUX_VAL_MASK)
2328                         >> KVM_REG_ARM_DEMUX_VAL_SHIFT;
2329                 if (!is_valid_cache(val))
2330                         return -ENOENT;
2331
2332                 return put_user(get_ccsidr(val), uval);
2333         default:
2334                 return -ENOENT;
2335         }
2336 }
2337
2338 static int demux_c15_set(u64 id, void __user *uaddr)
2339 {
2340         u32 val, newval;
2341         u32 __user *uval = uaddr;
2342
2343         /* Fail if we have unknown bits set. */
2344         if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK
2345                    | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1)))
2346                 return -ENOENT;
2347
2348         switch (id & KVM_REG_ARM_DEMUX_ID_MASK) {
2349         case KVM_REG_ARM_DEMUX_ID_CCSIDR:
2350                 if (KVM_REG_SIZE(id) != 4)
2351                         return -ENOENT;
2352                 val = (id & KVM_REG_ARM_DEMUX_VAL_MASK)
2353                         >> KVM_REG_ARM_DEMUX_VAL_SHIFT;
2354                 if (!is_valid_cache(val))
2355                         return -ENOENT;
2356
2357                 if (get_user(newval, uval))
2358                         return -EFAULT;
2359
2360                 /* This is also invariant: you can't change it. */
2361                 if (newval != get_ccsidr(val))
2362                         return -EINVAL;
2363                 return 0;
2364         default:
2365                 return -ENOENT;
2366         }
2367 }
2368
2369 int kvm_arm_sys_reg_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
2370 {
2371         const struct sys_reg_desc *r;
2372         void __user *uaddr = (void __user *)(unsigned long)reg->addr;
2373
2374         if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_DEMUX)
2375                 return demux_c15_get(reg->id, uaddr);
2376
2377         if (KVM_REG_SIZE(reg->id) != sizeof(__u64))
2378                 return -ENOENT;
2379
2380         r = index_to_sys_reg_desc(vcpu, reg->id);
2381         if (!r)
2382                 return get_invariant_sys_reg(reg->id, uaddr);
2383
2384         if (r->get_user)
2385                 return (r->get_user)(vcpu, r, reg, uaddr);
2386
2387         return reg_to_user(uaddr, &__vcpu_sys_reg(vcpu, r->reg), reg->id);
2388 }
2389
2390 int kvm_arm_sys_reg_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
2391 {
2392         const struct sys_reg_desc *r;
2393         void __user *uaddr = (void __user *)(unsigned long)reg->addr;
2394
2395         if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_DEMUX)
2396                 return demux_c15_set(reg->id, uaddr);
2397
2398         if (KVM_REG_SIZE(reg->id) != sizeof(__u64))
2399                 return -ENOENT;
2400
2401         r = index_to_sys_reg_desc(vcpu, reg->id);
2402         if (!r)
2403                 return set_invariant_sys_reg(reg->id, uaddr);
2404
2405         if (r->set_user)
2406                 return (r->set_user)(vcpu, r, reg, uaddr);
2407
2408         return reg_from_user(&__vcpu_sys_reg(vcpu, r->reg), uaddr, reg->id);
2409 }
2410
2411 static unsigned int num_demux_regs(void)
2412 {
2413         unsigned int i, count = 0;
2414
2415         for (i = 0; i < CSSELR_MAX; i++)
2416                 if (is_valid_cache(i))
2417                         count++;
2418
2419         return count;
2420 }
2421
2422 static int write_demux_regids(u64 __user *uindices)
2423 {
2424         u64 val = KVM_REG_ARM64 | KVM_REG_SIZE_U32 | KVM_REG_ARM_DEMUX;
2425         unsigned int i;
2426
2427         val |= KVM_REG_ARM_DEMUX_ID_CCSIDR;
2428         for (i = 0; i < CSSELR_MAX; i++) {
2429                 if (!is_valid_cache(i))
2430                         continue;
2431                 if (put_user(val | i, uindices))
2432                         return -EFAULT;
2433                 uindices++;
2434         }
2435         return 0;
2436 }
2437
2438 static u64 sys_reg_to_index(const struct sys_reg_desc *reg)
2439 {
2440         return (KVM_REG_ARM64 | KVM_REG_SIZE_U64 |
2441                 KVM_REG_ARM64_SYSREG |
2442                 (reg->Op0 << KVM_REG_ARM64_SYSREG_OP0_SHIFT) |
2443                 (reg->Op1 << KVM_REG_ARM64_SYSREG_OP1_SHIFT) |
2444                 (reg->CRn << KVM_REG_ARM64_SYSREG_CRN_SHIFT) |
2445                 (reg->CRm << KVM_REG_ARM64_SYSREG_CRM_SHIFT) |
2446                 (reg->Op2 << KVM_REG_ARM64_SYSREG_OP2_SHIFT));
2447 }
2448
2449 static bool copy_reg_to_user(const struct sys_reg_desc *reg, u64 __user **uind)
2450 {
2451         if (!*uind)
2452                 return true;
2453
2454         if (put_user(sys_reg_to_index(reg), *uind))
2455                 return false;
2456
2457         (*uind)++;
2458         return true;
2459 }
2460
2461 static int walk_one_sys_reg(const struct sys_reg_desc *rd,
2462                             u64 __user **uind,
2463                             unsigned int *total)
2464 {
2465         /*
2466          * Ignore registers we trap but don't save,
2467          * and for which no custom user accessor is provided.
2468          */
2469         if (!(rd->reg || rd->get_user))
2470                 return 0;
2471
2472         if (!copy_reg_to_user(rd, uind))
2473                 return -EFAULT;
2474
2475         (*total)++;
2476         return 0;
2477 }
2478
2479 /* Assumed ordered tables, see kvm_sys_reg_table_init. */
2480 static int walk_sys_regs(struct kvm_vcpu *vcpu, u64 __user *uind)
2481 {
2482         const struct sys_reg_desc *i1, *i2, *end1, *end2;
2483         unsigned int total = 0;
2484         size_t num;
2485         int err;
2486
2487         /* We check for duplicates here, to allow arch-specific overrides. */
2488         i1 = get_target_table(vcpu->arch.target, true, &num);
2489         end1 = i1 + num;
2490         i2 = sys_reg_descs;
2491         end2 = sys_reg_descs + ARRAY_SIZE(sys_reg_descs);
2492
2493         BUG_ON(i1 == end1 || i2 == end2);
2494
2495         /* Walk carefully, as both tables may refer to the same register. */
2496         while (i1 || i2) {
2497                 int cmp = cmp_sys_reg(i1, i2);
2498                 /* target-specific overrides generic entry. */
2499                 if (cmp <= 0)
2500                         err = walk_one_sys_reg(i1, &uind, &total);
2501                 else
2502                         err = walk_one_sys_reg(i2, &uind, &total);
2503
2504                 if (err)
2505                         return err;
2506
2507                 if (cmp <= 0 && ++i1 == end1)
2508                         i1 = NULL;
2509                 if (cmp >= 0 && ++i2 == end2)
2510                         i2 = NULL;
2511         }
2512         return total;
2513 }
2514
2515 unsigned long kvm_arm_num_sys_reg_descs(struct kvm_vcpu *vcpu)
2516 {
2517         return ARRAY_SIZE(invariant_sys_regs)
2518                 + num_demux_regs()
2519                 + walk_sys_regs(vcpu, (u64 __user *)NULL);
2520 }
2521
2522 int kvm_arm_copy_sys_reg_indices(struct kvm_vcpu *vcpu, u64 __user *uindices)
2523 {
2524         unsigned int i;
2525         int err;
2526
2527         /* Then give them all the invariant registers' indices. */
2528         for (i = 0; i < ARRAY_SIZE(invariant_sys_regs); i++) {
2529                 if (put_user(sys_reg_to_index(&invariant_sys_regs[i]), uindices))
2530                         return -EFAULT;
2531                 uindices++;
2532         }
2533
2534         err = walk_sys_regs(vcpu, uindices);
2535         if (err < 0)
2536                 return err;
2537         uindices += err;
2538
2539         return write_demux_regids(uindices);
2540 }
2541
2542 static int check_sysreg_table(const struct sys_reg_desc *table, unsigned int n)
2543 {
2544         unsigned int i;
2545
2546         for (i = 1; i < n; i++) {
2547                 if (cmp_sys_reg(&table[i-1], &table[i]) >= 0) {
2548                         kvm_err("sys_reg table %p out of order (%d)\n", table, i - 1);
2549                         return 1;
2550                 }
2551         }
2552
2553         return 0;
2554 }
2555
2556 void kvm_sys_reg_table_init(void)
2557 {
2558         unsigned int i;
2559         struct sys_reg_desc clidr;
2560
2561         /* Make sure tables are unique and in order. */
2562         BUG_ON(check_sysreg_table(sys_reg_descs, ARRAY_SIZE(sys_reg_descs)));
2563         BUG_ON(check_sysreg_table(cp14_regs, ARRAY_SIZE(cp14_regs)));
2564         BUG_ON(check_sysreg_table(cp14_64_regs, ARRAY_SIZE(cp14_64_regs)));
2565         BUG_ON(check_sysreg_table(cp15_regs, ARRAY_SIZE(cp15_regs)));
2566         BUG_ON(check_sysreg_table(cp15_64_regs, ARRAY_SIZE(cp15_64_regs)));
2567         BUG_ON(check_sysreg_table(invariant_sys_regs, ARRAY_SIZE(invariant_sys_regs)));
2568
2569         /* We abuse the reset function to overwrite the table itself. */
2570         for (i = 0; i < ARRAY_SIZE(invariant_sys_regs); i++)
2571                 invariant_sys_regs[i].reset(NULL, &invariant_sys_regs[i]);
2572
2573         /*
2574          * CLIDR format is awkward, so clean it up.  See ARM B4.1.20:
2575          *
2576          *   If software reads the Cache Type fields from Ctype1
2577          *   upwards, once it has seen a value of 0b000, no caches
2578          *   exist at further-out levels of the hierarchy. So, for
2579          *   example, if Ctype3 is the first Cache Type field with a
2580          *   value of 0b000, the values of Ctype4 to Ctype7 must be
2581          *   ignored.
2582          */
2583         get_clidr_el1(NULL, &clidr); /* Ugly... */
2584         cache_levels = clidr.val;
2585         for (i = 0; i < 7; i++)
2586                 if (((cache_levels >> (i*3)) & 7) == 0)
2587                         break;
2588         /* Clear all higher bits. */
2589         cache_levels &= (1 << (i*3))-1;
2590 }
2591
2592 /**
2593  * kvm_reset_sys_regs - sets system registers to reset value
2594  * @vcpu: The VCPU pointer
2595  *
2596  * This function finds the right table above and sets the registers on the
2597  * virtual CPU struct to their architecturally defined reset values.
2598  */
2599 void kvm_reset_sys_regs(struct kvm_vcpu *vcpu)
2600 {
2601         size_t num;
2602         const struct sys_reg_desc *table;
2603         DECLARE_BITMAP(bmap, NR_SYS_REGS) = { 0, };
2604
2605         /* Generic chip reset first (so target could override). */
2606         reset_sys_reg_descs(vcpu, sys_reg_descs, ARRAY_SIZE(sys_reg_descs), bmap);
2607
2608         table = get_target_table(vcpu->arch.target, true, &num);
2609         reset_sys_reg_descs(vcpu, table, num, bmap);
2610
2611         for (num = 1; num < NR_SYS_REGS; num++) {
2612                 if (WARN(!test_bit(num, bmap),
2613                          "Didn't reset __vcpu_sys_reg(%zi)\n", num))
2614                         break;
2615         }
2616 }