arch/arm64/kvm/sys_regs.c

   1 /*
   2  * Copyright (C) 2012,2013 - ARM Ltd
   3  * Author: Marc Zyngier <marc.zyngier@arm.com>
   4  *
   5  * Derived from arch/arm/kvm/coproc.c:
   6  * Copyright (C) 2012 - Virtual Open Systems and Columbia University
   7  * Authors: Rusty Russell <rusty@rustcorp.com.au>
   8  *          Christoffer Dall <c.dall@virtualopensystems.com>
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License, version 2, as
  12  * published by the Free Software Foundation.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  21  */
  22
  23 #include <linux/bsearch.h>
  24 #include <linux/kvm_host.h>
  25 #include <linux/mm.h>
  26 #include <linux/uaccess.h>
  27
  28 #include <asm/cacheflush.h>
  29 #include <asm/cputype.h>
  30 #include <asm/debug-monitors.h>
  31 #include <asm/esr.h>
  32 #include <asm/kvm_arm.h>
  33 #include <asm/kvm_asm.h>
  34 #include <asm/kvm_coproc.h>
  35 #include <asm/kvm_emulate.h>
  36 #include <asm/kvm_host.h>
  37 #include <asm/kvm_mmu.h>
  38 #include <asm/perf_event.h>
  39 #include <asm/sysreg.h>
  40
  41 #include <trace/events/kvm.h>
  42
  43 #include "sys_regs.h"
  44
  45 #include "trace.h"
  46
  47 /*
  48  * All of this file is extremly similar to the ARM coproc.c, but the
  49  * types are different. My gut feeling is that it should be pretty
  50  * easy to merge, but that would be an ABI breakage -- again. VFP
  51  * would also need to be abstracted.
  52  *
  53  * For AArch32, we only take care of what is being trapped. Anything
  54  * that has to do with init and userspace access has to go via the
  55  * 64bit interface.
  56  */
  57
  58 static bool read_from_write_only(struct kvm_vcpu *vcpu,
  59                                  struct sys_reg_params *params,
  60                                  const struct sys_reg_desc *r)
  61 {
  62         WARN_ONCE(1, "Unexpected sys_reg read to write-only register\n");
  63         print_sys_reg_instr(params);
  64         kvm_inject_undefined(vcpu);
  65         return false;
  66 }
  67
  68 static bool write_to_read_only(struct kvm_vcpu *vcpu,
  69                                struct sys_reg_params *params,
  70                                const struct sys_reg_desc *r)
  71 {
  72         WARN_ONCE(1, "Unexpected sys_reg write to read-only register\n");
  73         print_sys_reg_instr(params);
  74         kvm_inject_undefined(vcpu);
  75         return false;
  76 }
  77
  78 /* 3 bits per cache level, as per CLIDR, but non-existent caches always 0 */
  79 static u32 cache_levels;
  80
  81 /* CSSELR values; used to index KVM_REG_ARM_DEMUX_ID_CCSIDR */
  82 #define CSSELR_MAX 12
  83
  84 /* Which cache CCSIDR represents depends on CSSELR value. */
  85 static u32 get_ccsidr(u32 csselr)
  86 {
  87         u32 ccsidr;
  88
  89         /* Make sure noone else changes CSSELR during this! */
  90         local_irq_disable();
  91         write_sysreg(csselr, csselr_el1);
  92         isb();
  93         ccsidr = read_sysreg(ccsidr_el1);
  94         local_irq_enable();
  95
  96         return ccsidr;
  97 }
  98
  99 /*
 100  * See note at ARMv7 ARM B1.14.4 (TL;DR: S/W ops are not easily virtualized).
 101  */
 102 static bool access_dcsw(struct kvm_vcpu *vcpu,
 103                         struct sys_reg_params *p,
 104                         const struct sys_reg_desc *r)
 105 {
 106         if (!p->is_write)
 107                 return read_from_write_only(vcpu, p, r);
 108
 109         kvm_set_way_flush(vcpu);
 110         return true;
 111 }
 112
 113 /*
 114  * Generic accessor for VM registers. Only called as long as HCR_TVM
 115  * is set. If the guest enables the MMU, we stop trapping the VM
 116  * sys_regs and leave it in complete control of the caches.
 117  */
 118 static bool access_vm_reg(struct kvm_vcpu *vcpu,
 119                           struct sys_reg_params *p,
 120                           const struct sys_reg_desc *r)
 121 {
 122         bool was_enabled = vcpu_has_cache_enabled(vcpu);
 123
 124         BUG_ON(!p->is_write);
 125
 126         if (!p->is_aarch32) {
 127                 vcpu_sys_reg(vcpu, r->reg) = p->regval;
 128         } else {
 129                 if (!p->is_32bit)
 130                         vcpu_cp15_64_high(vcpu, r->reg) = upper_32_bits(p->regval);
 131                 vcpu_cp15_64_low(vcpu, r->reg) = lower_32_bits(p->regval);
 132         }
 133
 134         kvm_toggle_cache(vcpu, was_enabled);
 135         return true;
 136 }
 137
 138 /*
 139  * Trap handler for the GICv3 SGI generation system register.
 140  * Forward the request to the VGIC emulation.
 141  * The cp15_64 code makes sure this automatically works
 142  * for both AArch64 and AArch32 accesses.
 143  */
 144 static bool access_gic_sgi(struct kvm_vcpu *vcpu,
 145                            struct sys_reg_params *p,
 146                            const struct sys_reg_desc *r)
 147 {
 148         if (!p->is_write)
 149                 return read_from_write_only(vcpu, p, r);
 150
 151         vgic_v3_dispatch_sgi(vcpu, p->regval);
 152
 153         return true;
 154 }
 155
 156 static bool access_gic_sre(struct kvm_vcpu *vcpu,
 157                            struct sys_reg_params *p,
 158                            const struct sys_reg_desc *r)
 159 {
 160         if (p->is_write)
 161                 return ignore_write(vcpu, p);
 162
 163         p->regval = vcpu->arch.vgic_cpu.vgic_v3.vgic_sre;
 164         return true;
 165 }
 166
 167 static bool trap_raz_wi(struct kvm_vcpu *vcpu,
 168                         struct sys_reg_params *p,
 169                         const struct sys_reg_desc *r)
 170 {
 171         if (p->is_write)
 172                 return ignore_write(vcpu, p);
 173         else
 174                 return read_zero(vcpu, p);
 175 }
 176
 177 static bool trap_oslsr_el1(struct kvm_vcpu *vcpu,
 178                            struct sys_reg_params *p,
 179                            const struct sys_reg_desc *r)
 180 {
 181         if (p->is_write) {
 182                 return ignore_write(vcpu, p);
 183         } else {
 184                 p->regval = (1 << 3);
 185                 return true;
 186         }
 187 }
 188
 189 static bool trap_dbgauthstatus_el1(struct kvm_vcpu *vcpu,
 190                                    struct sys_reg_params *p,
 191                                    const struct sys_reg_desc *r)
 192 {
 193         if (p->is_write) {
 194                 return ignore_write(vcpu, p);
 195         } else {
 196                 p->regval = read_sysreg(dbgauthstatus_el1);
 197                 return true;
 198         }
 199 }
 200
 201 /*
 202  * We want to avoid world-switching all the DBG registers all the
 203  * time:
 204  *
 205  * - If we've touched any debug register, it is likely that we're
 206  *   going to touch more of them. It then makes sense to disable the
 207  *   traps and start doing the save/restore dance
 208  * - If debug is active (DBG_MDSCR_KDE or DBG_MDSCR_MDE set), it is
 209  *   then mandatory to save/restore the registers, as the guest
 210  *   depends on them.
 211  *
 212  * For this, we use a DIRTY bit, indicating the guest has modified the
 213  * debug registers, used as follow:
 214  *
 215  * On guest entry:
 216  * - If the dirty bit is set (because we're coming back from trapping),
 217  *   disable the traps, save host registers, restore guest registers.
 218  * - If debug is actively in use (DBG_MDSCR_KDE or DBG_MDSCR_MDE set),
 219  *   set the dirty bit, disable the traps, save host registers,
 220  *   restore guest registers.
 221  * - Otherwise, enable the traps
 222  *
 223  * On guest exit:
 224  * - If the dirty bit is set, save guest registers, restore host
 225  *   registers and clear the dirty bit. This ensure that the host can
 226  *   now use the debug registers.
 227  */
 228 static bool trap_debug_regs(struct kvm_vcpu *vcpu,
 229                             struct sys_reg_params *p,
 230                             const struct sys_reg_desc *r)
 231 {
 232         if (p->is_write) {
 233                 vcpu_sys_reg(vcpu, r->reg) = p->regval;
 234                 vcpu->arch.debug_flags |= KVM_ARM64_DEBUG_DIRTY;
 235         } else {
 236                 p->regval = vcpu_sys_reg(vcpu, r->reg);
 237         }
 238
 239         trace_trap_reg(__func__, r->reg, p->is_write, p->regval);
 240
 241         return true;
 242 }
 243
 244 /*
 245  * reg_to_dbg/dbg_to_reg
 246  *
 247  * A 32 bit write to a debug register leave top bits alone
 248  * A 32 bit read from a debug register only returns the bottom bits
 249  *
 250  * All writes will set the KVM_ARM64_DEBUG_DIRTY flag to ensure the
 251  * hyp.S code switches between host and guest values in future.
 252  */
 253 static void reg_to_dbg(struct kvm_vcpu *vcpu,
 254                        struct sys_reg_params *p,
 255                        u64 *dbg_reg)
 256 {
 257         u64 val = p->regval;
 258
 259         if (p->is_32bit) {
 260                 val &= 0xffffffffUL;
 261                 val |= ((*dbg_reg >> 32) << 32);
 262         }
 263
 264         *dbg_reg = val;
 265         vcpu->arch.debug_flags |= KVM_ARM64_DEBUG_DIRTY;
 266 }
 267
 268 static void dbg_to_reg(struct kvm_vcpu *vcpu,
 269                        struct sys_reg_params *p,
 270                        u64 *dbg_reg)
 271 {
 272         p->regval = *dbg_reg;
 273         if (p->is_32bit)
 274                 p->regval &= 0xffffffffUL;
 275 }
 276
 277 static bool trap_bvr(struct kvm_vcpu *vcpu,
 278                      struct sys_reg_params *p,
 279                      const struct sys_reg_desc *rd)
 280 {
 281         u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_bvr[rd->reg];
 282
 283         if (p->is_write)
 284                 reg_to_dbg(vcpu, p, dbg_reg);
 285         else
 286                 dbg_to_reg(vcpu, p, dbg_reg);
 287
 288         trace_trap_reg(__func__, rd->reg, p->is_write, *dbg_reg);
 289
 290         return true;
 291 }
 292
 293 static int set_bvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
 294                 const struct kvm_one_reg *reg, void __user *uaddr)
 295 {
 296         __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_bvr[rd->reg];
 297
 298         if (copy_from_user(r, uaddr, KVM_REG_SIZE(reg->id)) != 0)
 299                 return -EFAULT;
 300         return 0;
 301 }
 302
 303 static int get_bvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
 304         const struct kvm_one_reg *reg, void __user *uaddr)
 305 {
 306         __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_bvr[rd->reg];
 307
 308         if (copy_to_user(uaddr, r, KVM_REG_SIZE(reg->id)) != 0)
 309                 return -EFAULT;
 310         return 0;
 311 }
 312
 313 static void reset_bvr(struct kvm_vcpu *vcpu,
 314                       const struct sys_reg_desc *rd)
 315 {
 316         vcpu->arch.vcpu_debug_state.dbg_bvr[rd->reg] = rd->val;
 317 }
 318
 319 static bool trap_bcr(struct kvm_vcpu *vcpu,
 320                      struct sys_reg_params *p,
 321                      const struct sys_reg_desc *rd)
 322 {
 323         u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_bcr[rd->reg];
 324
 325         if (p->is_write)
 326                 reg_to_dbg(vcpu, p, dbg_reg);
 327         else
 328                 dbg_to_reg(vcpu, p, dbg_reg);
 329
 330         trace_trap_reg(__func__, rd->reg, p->is_write, *dbg_reg);
 331
 332         return true;
 333 }
 334
 335 static int set_bcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
 336                 const struct kvm_one_reg *reg, void __user *uaddr)
 337 {
 338         __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_bcr[rd->reg];
 339
 340         if (copy_from_user(r, uaddr, KVM_REG_SIZE(reg->id)) != 0)
 341                 return -EFAULT;
 342
 343         return 0;
 344 }
 345
 346 static int get_bcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
 347         const struct kvm_one_reg *reg, void __user *uaddr)
 348 {
 349         __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_bcr[rd->reg];
 350
 351         if (copy_to_user(uaddr, r, KVM_REG_SIZE(reg->id)) != 0)
 352                 return -EFAULT;
 353         return 0;
 354 }
 355
 356 static void reset_bcr(struct kvm_vcpu *vcpu,
 357                       const struct sys_reg_desc *rd)
 358 {
 359         vcpu->arch.vcpu_debug_state.dbg_bcr[rd->reg] = rd->val;
 360 }
 361
 362 static bool trap_wvr(struct kvm_vcpu *vcpu,
 363                      struct sys_reg_params *p,
 364                      const struct sys_reg_desc *rd)
 365 {
 366         u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_wvr[rd->reg];
 367
 368         if (p->is_write)
 369                 reg_to_dbg(vcpu, p, dbg_reg);
 370         else
 371                 dbg_to_reg(vcpu, p, dbg_reg);
 372
 373         trace_trap_reg(__func__, rd->reg, p->is_write,
 374                 vcpu->arch.vcpu_debug_state.dbg_wvr[rd->reg]);
 375
 376         return true;
 377 }
 378
 379 static int set_wvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
 380                 const struct kvm_one_reg *reg, void __user *uaddr)
 381 {
 382         __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_wvr[rd->reg];
 383
 384         if (copy_from_user(r, uaddr, KVM_REG_SIZE(reg->id)) != 0)
 385                 return -EFAULT;
 386         return 0;
 387 }
 388
 389 static int get_wvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
 390         const struct kvm_one_reg *reg, void __user *uaddr)
 391 {
 392         __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_wvr[rd->reg];
 393
 394         if (copy_to_user(uaddr, r, KVM_REG_SIZE(reg->id)) != 0)
 395                 return -EFAULT;
 396         return 0;
 397 }
 398
 399 static void reset_wvr(struct kvm_vcpu *vcpu,
 400                       const struct sys_reg_desc *rd)
 401 {
 402         vcpu->arch.vcpu_debug_state.dbg_wvr[rd->reg] = rd->val;
 403 }
 404
 405 static bool trap_wcr(struct kvm_vcpu *vcpu,
 406                      struct sys_reg_params *p,
 407                      const struct sys_reg_desc *rd)
 408 {
 409         u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_wcr[rd->reg];
 410
 411         if (p->is_write)
 412                 reg_to_dbg(vcpu, p, dbg_reg);
 413         else
 414                 dbg_to_reg(vcpu, p, dbg_reg);
 415
 416         trace_trap_reg(__func__, rd->reg, p->is_write, *dbg_reg);
 417
 418         return true;
 419 }
 420
 421 static int set_wcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
 422                 const struct kvm_one_reg *reg, void __user *uaddr)
 423 {
 424         __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_wcr[rd->reg];
 425
 426         if (copy_from_user(r, uaddr, KVM_REG_SIZE(reg->id)) != 0)
 427                 return -EFAULT;
 428         return 0;
 429 }
 430
 431 static int get_wcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
 432         const struct kvm_one_reg *reg, void __user *uaddr)
 433 {
 434         __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_wcr[rd->reg];
 435
 436         if (copy_to_user(uaddr, r, KVM_REG_SIZE(reg->id)) != 0)
 437                 return -EFAULT;
 438         return 0;
 439 }
 440
 441 static void reset_wcr(struct kvm_vcpu *vcpu,
 442                       const struct sys_reg_desc *rd)
 443 {
 444         vcpu->arch.vcpu_debug_state.dbg_wcr[rd->reg] = rd->val;
 445 }
 446
 447 static void reset_amair_el1(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
 448 {
 449         vcpu_sys_reg(vcpu, AMAIR_EL1) = read_sysreg(amair_el1);
 450 }
 451
 452 static void reset_mpidr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
 453 {
 454         u64 mpidr;
 455
 456         /*
 457          * Map the vcpu_id into the first three affinity level fields of
 458          * the MPIDR. We limit the number of VCPUs in level 0 due to a
 459          * limitation to 16 CPUs in that level in the ICC_SGIxR registers
 460          * of the GICv3 to be able to address each CPU directly when
 461          * sending IPIs.
 462          */
 463         mpidr = (vcpu->vcpu_id & 0x0f) << MPIDR_LEVEL_SHIFT(0);
 464         mpidr |= ((vcpu->vcpu_id >> 4) & 0xff) << MPIDR_LEVEL_SHIFT(1);
 465         mpidr |= ((vcpu->vcpu_id >> 12) & 0xff) << MPIDR_LEVEL_SHIFT(2);
 466         vcpu_sys_reg(vcpu, MPIDR_EL1) = (1ULL << 31) | mpidr;
 467 }
 468
 469 static void reset_pmcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
 470 {
 471         u64 pmcr, val;
 472
 473         /* No PMU available, PMCR_EL0 may UNDEF... */
 474         if (!kvm_arm_support_pmu_v3())
 475                 return;
 476
 477         pmcr = read_sysreg(pmcr_el0);
 478         /*
 479          * Writable bits of PMCR_EL0 (ARMV8_PMU_PMCR_MASK) are reset to UNKNOWN
 480          * except PMCR.E resetting to zero.
 481          */
 482         val = ((pmcr & ~ARMV8_PMU_PMCR_MASK)
 483                | (ARMV8_PMU_PMCR_MASK & 0xdecafbad)) & (~ARMV8_PMU_PMCR_E);
 484         vcpu_sys_reg(vcpu, PMCR_EL0) = val;
 485 }
 486
 487 static bool check_pmu_access_disabled(struct kvm_vcpu *vcpu, u64 flags)
 488 {
 489         u64 reg = vcpu_sys_reg(vcpu, PMUSERENR_EL0);
 490         bool enabled = (reg & flags) || vcpu_mode_priv(vcpu);
 491
 492         if (!enabled)
 493                 kvm_inject_undefined(vcpu);
 494
 495         return !enabled;
 496 }
 497
 498 static bool pmu_access_el0_disabled(struct kvm_vcpu *vcpu)
 499 {
 500         return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_EN);
 501 }
 502
 503 static bool pmu_write_swinc_el0_disabled(struct kvm_vcpu *vcpu)
 504 {
 505         return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_SW | ARMV8_PMU_USERENR_EN);
 506 }
 507
 508 static bool pmu_access_cycle_counter_el0_disabled(struct kvm_vcpu *vcpu)
 509 {
 510         return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_CR | ARMV8_PMU_USERENR_EN);
 511 }
 512
 513 static bool pmu_access_event_counter_el0_disabled(struct kvm_vcpu *vcpu)
 514 {
 515         return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_ER | ARMV8_PMU_USERENR_EN);
 516 }
 517
 518 static bool access_pmcr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
 519                         const struct sys_reg_desc *r)
 520 {
 521         u64 val;
 522
 523         if (!kvm_arm_pmu_v3_ready(vcpu))
 524                 return trap_raz_wi(vcpu, p, r);
 525
 526         if (pmu_access_el0_disabled(vcpu))
 527                 return false;
 528
 529         if (p->is_write) {
 530                 /* Only update writeable bits of PMCR */
 531                 val = vcpu_sys_reg(vcpu, PMCR_EL0);
 532                 val &= ~ARMV8_PMU_PMCR_MASK;
 533                 val |= p->regval & ARMV8_PMU_PMCR_MASK;
 534                 vcpu_sys_reg(vcpu, PMCR_EL0) = val;
 535                 kvm_pmu_handle_pmcr(vcpu, val);
 536         } else {
 537                 /* PMCR.P & PMCR.C are RAZ */
 538                 val = vcpu_sys_reg(vcpu, PMCR_EL0)
 539                       & ~(ARMV8_PMU_PMCR_P | ARMV8_PMU_PMCR_C);
 540                 p->regval = val;
 541         }
 542
 543         return true;
 544 }
 545
 546 static bool access_pmselr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
 547                           const struct sys_reg_desc *r)
 548 {
 549         if (!kvm_arm_pmu_v3_ready(vcpu))
 550                 return trap_raz_wi(vcpu, p, r);
 551
 552         if (pmu_access_event_counter_el0_disabled(vcpu))
 553                 return false;
 554
 555         if (p->is_write)
 556                 vcpu_sys_reg(vcpu, PMSELR_EL0) = p->regval;
 557         else
 558                 /* return PMSELR.SEL field */
 559                 p->regval = vcpu_sys_reg(vcpu, PMSELR_EL0)
 560                             & ARMV8_PMU_COUNTER_MASK;
 561
 562         return true;
 563 }
 564
 565 static bool access_pmceid(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
 566                           const struct sys_reg_desc *r)
 567 {
 568         u64 pmceid;
 569
 570         if (!kvm_arm_pmu_v3_ready(vcpu))
 571                 return trap_raz_wi(vcpu, p, r);
 572
 573         BUG_ON(p->is_write);
 574
 575         if (pmu_access_el0_disabled(vcpu))
 576                 return false;
 577
 578         if (!(p->Op2 & 1))
 579                 pmceid = read_sysreg(pmceid0_el0);
 580         else
 581                 pmceid = read_sysreg(pmceid1_el0);
 582
 583         p->regval = pmceid;
 584
 585         return true;
 586 }
 587
 588 static bool pmu_counter_idx_valid(struct kvm_vcpu *vcpu, u64 idx)
 589 {
 590         u64 pmcr, val;
 591
 592         pmcr = vcpu_sys_reg(vcpu, PMCR_EL0);
 593         val = (pmcr >> ARMV8_PMU_PMCR_N_SHIFT) & ARMV8_PMU_PMCR_N_MASK;
 594         if (idx >= val && idx != ARMV8_PMU_CYCLE_IDX) {
 595                 kvm_inject_undefined(vcpu);
 596                 return false;
 597         }
 598
 599         return true;
 600 }
 601
 602 static bool access_pmu_evcntr(struct kvm_vcpu *vcpu,
 603                               struct sys_reg_params *p,
 604                               const struct sys_reg_desc *r)
 605 {
 606         u64 idx;
 607
 608         if (!kvm_arm_pmu_v3_ready(vcpu))
 609                 return trap_raz_wi(vcpu, p, r);
 610
 611         if (r->CRn == 9 && r->CRm == 13) {
 612                 if (r->Op2 == 2) {
 613                         /* PMXEVCNTR_EL0 */
 614                         if (pmu_access_event_counter_el0_disabled(vcpu))
 615                                 return false;
 616
 617                         idx = vcpu_sys_reg(vcpu, PMSELR_EL0)
 618                               & ARMV8_PMU_COUNTER_MASK;
 619                 } else if (r->Op2 == 0) {
 620                         /* PMCCNTR_EL0 */
 621                         if (pmu_access_cycle_counter_el0_disabled(vcpu))
 622                                 return false;
 623
 624                         idx = ARMV8_PMU_CYCLE_IDX;
 625                 } else {
 626                         return false;
 627                 }
 628         } else if (r->CRn == 0 && r->CRm == 9) {
 629                 /* PMCCNTR */
 630                 if (pmu_access_event_counter_el0_disabled(vcpu))
 631                         return false;
 632
 633                 idx = ARMV8_PMU_CYCLE_IDX;
 634         } else if (r->CRn == 14 && (r->CRm & 12) == 8) {
 635                 /* PMEVCNTRn_EL0 */
 636                 if (pmu_access_event_counter_el0_disabled(vcpu))
 637                         return false;
 638
 639                 idx = ((r->CRm & 3) << 3) | (r->Op2 & 7);
 640         } else {
 641                 return false;
 642         }
 643
 644         if (!pmu_counter_idx_valid(vcpu, idx))
 645                 return false;
 646
 647         if (p->is_write) {
 648                 if (pmu_access_el0_disabled(vcpu))
 649                         return false;
 650
 651                 kvm_pmu_set_counter_value(vcpu, idx, p->regval);
 652         } else {
 653                 p->regval = kvm_pmu_get_counter_value(vcpu, idx);
 654         }
 655
 656         return true;
 657 }
 658
 659 static bool access_pmu_evtyper(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
 660                                const struct sys_reg_desc *r)
 661 {
 662         u64 idx, reg;
 663
 664         if (!kvm_arm_pmu_v3_ready(vcpu))
 665                 return trap_raz_wi(vcpu, p, r);
 666
 667         if (pmu_access_el0_disabled(vcpu))
 668                 return false;
 669
 670         if (r->CRn == 9 && r->CRm == 13 && r->Op2 == 1) {
 671                 /* PMXEVTYPER_EL0 */
 672                 idx = vcpu_sys_reg(vcpu, PMSELR_EL0) & ARMV8_PMU_COUNTER_MASK;
 673                 reg = PMEVTYPER0_EL0 + idx;
 674         } else if (r->CRn == 14 && (r->CRm & 12) == 12) {
 675                 idx = ((r->CRm & 3) << 3) | (r->Op2 & 7);
 676                 if (idx == ARMV8_PMU_CYCLE_IDX)
 677                         reg = PMCCFILTR_EL0;
 678                 else
 679                         /* PMEVTYPERn_EL0 */
 680                         reg = PMEVTYPER0_EL0 + idx;
 681         } else {
 682                 BUG();
 683         }
 684
 685         if (!pmu_counter_idx_valid(vcpu, idx))
 686                 return false;
 687
 688         if (p->is_write) {
 689                 kvm_pmu_set_counter_event_type(vcpu, p->regval, idx);
 690                 vcpu_sys_reg(vcpu, reg) = p->regval & ARMV8_PMU_EVTYPE_MASK;
 691         } else {
 692                 p->regval = vcpu_sys_reg(vcpu, reg) & ARMV8_PMU_EVTYPE_MASK;
 693         }
 694
 695         return true;
 696 }
 697
 698 static bool access_pmcnten(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
 699                            const struct sys_reg_desc *r)
 700 {
 701         u64 val, mask;
 702
 703         if (!kvm_arm_pmu_v3_ready(vcpu))
 704                 return trap_raz_wi(vcpu, p, r);
 705
 706         if (pmu_access_el0_disabled(vcpu))
 707                 return false;
 708
 709         mask = kvm_pmu_valid_counter_mask(vcpu);
 710         if (p->is_write) {
 711                 val = p->regval & mask;
 712                 if (r->Op2 & 0x1) {
 713                         /* accessing PMCNTENSET_EL0 */
 714                         vcpu_sys_reg(vcpu, PMCNTENSET_EL0) |= val;
 715                         kvm_pmu_enable_counter(vcpu, val);
 716                 } else {
 717                         /* accessing PMCNTENCLR_EL0 */
 718                         vcpu_sys_reg(vcpu, PMCNTENSET_EL0) &= ~val;
 719                         kvm_pmu_disable_counter(vcpu, val);
 720                 }
 721         } else {
 722                 p->regval = vcpu_sys_reg(vcpu, PMCNTENSET_EL0) & mask;
 723         }
 724
 725         return true;
 726 }
 727
 728 static bool access_pminten(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
 729                            const struct sys_reg_desc *r)
 730 {
 731         u64 mask = kvm_pmu_valid_counter_mask(vcpu);
 732
 733         if (!kvm_arm_pmu_v3_ready(vcpu))
 734                 return trap_raz_wi(vcpu, p, r);
 735
 736         if (!vcpu_mode_priv(vcpu)) {
 737                 kvm_inject_undefined(vcpu);
 738                 return false;
 739         }
 740
 741         if (p->is_write) {
 742                 u64 val = p->regval & mask;
 743
 744                 if (r->Op2 & 0x1)
 745                         /* accessing PMINTENSET_EL1 */
 746                         vcpu_sys_reg(vcpu, PMINTENSET_EL1) |= val;
 747                 else
 748                         /* accessing PMINTENCLR_EL1 */
 749                         vcpu_sys_reg(vcpu, PMINTENSET_EL1) &= ~val;
 750         } else {
 751                 p->regval = vcpu_sys_reg(vcpu, PMINTENSET_EL1) & mask;
 752         }
 753
 754         return true;
 755 }
 756
 757 static bool access_pmovs(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
 758                          const struct sys_reg_desc *r)
 759 {
 760         u64 mask = kvm_pmu_valid_counter_mask(vcpu);
 761
 762         if (!kvm_arm_pmu_v3_ready(vcpu))
 763                 return trap_raz_wi(vcpu, p, r);
 764
 765         if (pmu_access_el0_disabled(vcpu))
 766                 return false;
 767
 768         if (p->is_write) {
 769                 if (r->CRm & 0x2)
 770                         /* accessing PMOVSSET_EL0 */
 771                         vcpu_sys_reg(vcpu, PMOVSSET_EL0) |= (p->regval & mask);
 772                 else
 773                         /* accessing PMOVSCLR_EL0 */
 774                         vcpu_sys_reg(vcpu, PMOVSSET_EL0) &= ~(p->regval & mask);
 775         } else {
 776                 p->regval = vcpu_sys_reg(vcpu, PMOVSSET_EL0) & mask;
 777         }
 778
 779         return true;
 780 }
 781
 782 static bool access_pmswinc(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
 783                            const struct sys_reg_desc *r)
 784 {
 785         u64 mask;
 786
 787         if (!kvm_arm_pmu_v3_ready(vcpu))
 788                 return trap_raz_wi(vcpu, p, r);
 789
 790         if (!p->is_write)
 791                 return read_from_write_only(vcpu, p, r);
 792
 793         if (pmu_write_swinc_el0_disabled(vcpu))
 794                 return false;
 795
 796         mask = kvm_pmu_valid_counter_mask(vcpu);
 797         kvm_pmu_software_increment(vcpu, p->regval & mask);
 798         return true;
 799 }
 800
 801 static bool access_pmuserenr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
 802                              const struct sys_reg_desc *r)
 803 {
 804         if (!kvm_arm_pmu_v3_ready(vcpu))
 805                 return trap_raz_wi(vcpu, p, r);
 806
 807         if (p->is_write) {
 808                 if (!vcpu_mode_priv(vcpu)) {
 809                         kvm_inject_undefined(vcpu);
 810                         return false;
 811                 }
 812
 813                 vcpu_sys_reg(vcpu, PMUSERENR_EL0) = p->regval
 814                                                     & ARMV8_PMU_USERENR_MASK;
 815         } else {
 816                 p->regval = vcpu_sys_reg(vcpu, PMUSERENR_EL0)
 817                             & ARMV8_PMU_USERENR_MASK;
 818         }
 819
 820         return true;
 821 }
 822
 823 /* Silly macro to expand the DBG{BCR,BVR,WVR,WCR}n_EL1 registers in one go */
 824 #define DBG_BCR_BVR_WCR_WVR_EL1(n)                                      \
 825         { SYS_DESC(SYS_DBGBVRn_EL1(n)),                                 \
 826           trap_bvr, reset_bvr, n, 0, get_bvr, set_bvr },                \
 827         { SYS_DESC(SYS_DBGBCRn_EL1(n)),                                 \
 828           trap_bcr, reset_bcr, n, 0, get_bcr, set_bcr },                \
 829         { SYS_DESC(SYS_DBGWVRn_EL1(n)),                                 \
 830           trap_wvr, reset_wvr, n, 0,  get_wvr, set_wvr },               \
 831         { SYS_DESC(SYS_DBGWCRn_EL1(n)),                                 \
 832           trap_wcr, reset_wcr, n, 0,  get_wcr, set_wcr }
 833
 834 /* Macro to expand the PMEVCNTRn_EL0 register */
 835 #define PMU_PMEVCNTR_EL0(n)                                             \
 836         { SYS_DESC(SYS_PMEVCNTRn_EL0(n)),                                       \
 837           access_pmu_evcntr, reset_unknown, (PMEVCNTR0_EL0 + n), }
 838
 839 /* Macro to expand the PMEVTYPERn_EL0 register */
 840 #define PMU_PMEVTYPER_EL0(n)                                            \
 841         { SYS_DESC(SYS_PMEVTYPERn_EL0(n)),                                      \
 842           access_pmu_evtyper, reset_unknown, (PMEVTYPER0_EL0 + n), }
 843
 844 static bool access_cntp_tval(struct kvm_vcpu *vcpu,
 845                 struct sys_reg_params *p,
 846                 const struct sys_reg_desc *r)
 847 {
 848         struct arch_timer_context *ptimer = vcpu_ptimer(vcpu);
 849         u64 now = kvm_phys_timer_read();
 850
 851         if (p->is_write)
 852                 ptimer->cnt_cval = p->regval + now;
 853         else
 854                 p->regval = ptimer->cnt_cval - now;
 855
 856         return true;
 857 }
 858
 859 static bool access_cntp_ctl(struct kvm_vcpu *vcpu,
 860                 struct sys_reg_params *p,
 861                 const struct sys_reg_desc *r)
 862 {
 863         struct arch_timer_context *ptimer = vcpu_ptimer(vcpu);
 864
 865         if (p->is_write) {
 866                 /* ISTATUS bit is read-only */
 867                 ptimer->cnt_ctl = p->regval & ~ARCH_TIMER_CTRL_IT_STAT;
 868         } else {
 869                 u64 now = kvm_phys_timer_read();
 870
 871                 p->regval = ptimer->cnt_ctl;
 872                 /*
 873                  * Set ISTATUS bit if it's expired.
 874                  * Note that according to ARMv8 ARM Issue A.k, ISTATUS bit is
 875                  * UNKNOWN when ENABLE bit is 0, so we chose to set ISTATUS bit
 876                  * regardless of ENABLE bit for our implementation convenience.
 877                  */
 878                 if (ptimer->cnt_cval <= now)
 879                         p->regval |= ARCH_TIMER_CTRL_IT_STAT;
 880         }
 881
 882         return true;
 883 }
 884
 885 static bool access_cntp_cval(struct kvm_vcpu *vcpu,
 886                 struct sys_reg_params *p,
 887                 const struct sys_reg_desc *r)
 888 {
 889         struct arch_timer_context *ptimer = vcpu_ptimer(vcpu);
 890
 891         if (p->is_write)
 892                 ptimer->cnt_cval = p->regval;
 893         else
 894                 p->regval = ptimer->cnt_cval;
 895
 896         return true;
 897 }
 898
 899 /*
 900  * Architected system registers.
 901  * Important: Must be sorted ascending by Op0, Op1, CRn, CRm, Op2
 902  *
 903  * Debug handling: We do trap most, if not all debug related system
 904  * registers. The implementation is good enough to ensure that a guest
 905  * can use these with minimal performance degradation. The drawback is
 906  * that we don't implement any of the external debug, none of the
 907  * OSlock protocol. This should be revisited if we ever encounter a
 908  * more demanding guest...
 909  */
 910 static const struct sys_reg_desc sys_reg_descs[] = {
 911         { SYS_DESC(SYS_DC_ISW), access_dcsw },
 912         { SYS_DESC(SYS_DC_CSW), access_dcsw },
 913         { SYS_DESC(SYS_DC_CISW), access_dcsw },
 914
 915         DBG_BCR_BVR_WCR_WVR_EL1(0),
 916         DBG_BCR_BVR_WCR_WVR_EL1(1),
 917         { SYS_DESC(SYS_MDCCINT_EL1), trap_debug_regs, reset_val, MDCCINT_EL1, 0 },
 918         { SYS_DESC(SYS_MDSCR_EL1), trap_debug_regs, reset_val, MDSCR_EL1, 0 },
 919         DBG_BCR_BVR_WCR_WVR_EL1(2),
 920         DBG_BCR_BVR_WCR_WVR_EL1(3),
 921         DBG_BCR_BVR_WCR_WVR_EL1(4),
 922         DBG_BCR_BVR_WCR_WVR_EL1(5),
 923         DBG_BCR_BVR_WCR_WVR_EL1(6),
 924         DBG_BCR_BVR_WCR_WVR_EL1(7),
 925         DBG_BCR_BVR_WCR_WVR_EL1(8),
 926         DBG_BCR_BVR_WCR_WVR_EL1(9),
 927         DBG_BCR_BVR_WCR_WVR_EL1(10),
 928         DBG_BCR_BVR_WCR_WVR_EL1(11),
 929         DBG_BCR_BVR_WCR_WVR_EL1(12),
 930         DBG_BCR_BVR_WCR_WVR_EL1(13),
 931         DBG_BCR_BVR_WCR_WVR_EL1(14),
 932         DBG_BCR_BVR_WCR_WVR_EL1(15),
 933
 934         { SYS_DESC(SYS_MDRAR_EL1), trap_raz_wi },
 935         { SYS_DESC(SYS_OSLAR_EL1), trap_raz_wi },
 936         { SYS_DESC(SYS_OSLSR_EL1), trap_oslsr_el1 },
 937         { SYS_DESC(SYS_OSDLR_EL1), trap_raz_wi },
 938         { SYS_DESC(SYS_DBGPRCR_EL1), trap_raz_wi },
 939         { SYS_DESC(SYS_DBGCLAIMSET_EL1), trap_raz_wi },
 940         { SYS_DESC(SYS_DBGCLAIMCLR_EL1), trap_raz_wi },
 941         { SYS_DESC(SYS_DBGAUTHSTATUS_EL1), trap_dbgauthstatus_el1 },
 942
 943         { SYS_DESC(SYS_MDCCSR_EL0), trap_raz_wi },
 944         { SYS_DESC(SYS_DBGDTR_EL0), trap_raz_wi },
 945         // DBGDTR[TR]X_EL0 share the same encoding
 946         { SYS_DESC(SYS_DBGDTRTX_EL0), trap_raz_wi },
 947
 948         { SYS_DESC(SYS_DBGVCR32_EL2), NULL, reset_val, DBGVCR32_EL2, 0 },
 949
 950         { SYS_DESC(SYS_MPIDR_EL1), NULL, reset_mpidr, MPIDR_EL1 },
 951         { SYS_DESC(SYS_SCTLR_EL1), access_vm_reg, reset_val, SCTLR_EL1, 0x00C50078 },
 952         { SYS_DESC(SYS_CPACR_EL1), NULL, reset_val, CPACR_EL1, 0 },
 953         { SYS_DESC(SYS_TTBR0_EL1), access_vm_reg, reset_unknown, TTBR0_EL1 },
 954         { SYS_DESC(SYS_TTBR1_EL1), access_vm_reg, reset_unknown, TTBR1_EL1 },
 955         { SYS_DESC(SYS_TCR_EL1), access_vm_reg, reset_val, TCR_EL1, 0 },
 956
 957         { SYS_DESC(SYS_AFSR0_EL1), access_vm_reg, reset_unknown, AFSR0_EL1 },
 958         { SYS_DESC(SYS_AFSR1_EL1), access_vm_reg, reset_unknown, AFSR1_EL1 },
 959         { SYS_DESC(SYS_ESR_EL1), access_vm_reg, reset_unknown, ESR_EL1 },
 960         { SYS_DESC(SYS_FAR_EL1), access_vm_reg, reset_unknown, FAR_EL1 },
 961         { SYS_DESC(SYS_PAR_EL1), NULL, reset_unknown, PAR_EL1 },
 962
 963         { SYS_DESC(SYS_PMINTENSET_EL1), access_pminten, reset_unknown, PMINTENSET_EL1 },
 964         { SYS_DESC(SYS_PMINTENCLR_EL1), access_pminten, NULL, PMINTENSET_EL1 },
 965
 966         { SYS_DESC(SYS_MAIR_EL1), access_vm_reg, reset_unknown, MAIR_EL1 },
 967         { SYS_DESC(SYS_AMAIR_EL1), access_vm_reg, reset_amair_el1, AMAIR_EL1 },
 968
 969         { SYS_DESC(SYS_VBAR_EL1), NULL, reset_val, VBAR_EL1, 0 },
 970
 971         { SYS_DESC(SYS_ICC_IAR0_EL1), write_to_read_only },
 972         { SYS_DESC(SYS_ICC_EOIR0_EL1), read_from_write_only },
 973         { SYS_DESC(SYS_ICC_HPPIR0_EL1), write_to_read_only },
 974         { SYS_DESC(SYS_ICC_DIR_EL1), read_from_write_only },
 975         { SYS_DESC(SYS_ICC_RPR_EL1), write_to_read_only },
 976         { SYS_DESC(SYS_ICC_SGI1R_EL1), access_gic_sgi },
 977         { SYS_DESC(SYS_ICC_IAR1_EL1), write_to_read_only },
 978         { SYS_DESC(SYS_ICC_EOIR1_EL1), read_from_write_only },
 979         { SYS_DESC(SYS_ICC_HPPIR1_EL1), write_to_read_only },
 980         { SYS_DESC(SYS_ICC_SRE_EL1), access_gic_sre },
 981
 982         { SYS_DESC(SYS_CONTEXTIDR_EL1), access_vm_reg, reset_val, CONTEXTIDR_EL1, 0 },
 983         { SYS_DESC(SYS_TPIDR_EL1), NULL, reset_unknown, TPIDR_EL1 },
 984
 985         { SYS_DESC(SYS_CNTKCTL_EL1), NULL, reset_val, CNTKCTL_EL1, 0},
 986
 987         { SYS_DESC(SYS_CSSELR_EL1), NULL, reset_unknown, CSSELR_EL1 },
 988
 989         { SYS_DESC(SYS_PMCR_EL0), access_pmcr, reset_pmcr, },
 990         { SYS_DESC(SYS_PMCNTENSET_EL0), access_pmcnten, reset_unknown, PMCNTENSET_EL0 },
 991         { SYS_DESC(SYS_PMCNTENCLR_EL0), access_pmcnten, NULL, PMCNTENSET_EL0 },
 992         { SYS_DESC(SYS_PMOVSCLR_EL0), access_pmovs, NULL, PMOVSSET_EL0 },
 993         { SYS_DESC(SYS_PMSWINC_EL0), access_pmswinc, reset_unknown, PMSWINC_EL0 },
 994         { SYS_DESC(SYS_PMSELR_EL0), access_pmselr, reset_unknown, PMSELR_EL0 },
 995         { SYS_DESC(SYS_PMCEID0_EL0), access_pmceid },
 996         { SYS_DESC(SYS_PMCEID1_EL0), access_pmceid },
 997         { SYS_DESC(SYS_PMCCNTR_EL0), access_pmu_evcntr, reset_unknown, PMCCNTR_EL0 },
 998         { SYS_DESC(SYS_PMXEVTYPER_EL0), access_pmu_evtyper },
 999         { SYS_DESC(SYS_PMXEVCNTR_EL0), access_pmu_evcntr },
1000         /*
1001          * PMUSERENR_EL0 resets as unknown in 64bit mode while it resets as zero
1002          * in 32bit mode. Here we choose to reset it as zero for consistency.
1003          */
1004         { SYS_DESC(SYS_PMUSERENR_EL0), access_pmuserenr, reset_val, PMUSERENR_EL0, 0 },
1005         { SYS_DESC(SYS_PMOVSSET_EL0), access_pmovs, reset_unknown, PMOVSSET_EL0 },
1006
1007         { SYS_DESC(SYS_TPIDR_EL0), NULL, reset_unknown, TPIDR_EL0 },
1008         { SYS_DESC(SYS_TPIDRRO_EL0), NULL, reset_unknown, TPIDRRO_EL0 },
1009
1010         { SYS_DESC(SYS_CNTP_TVAL_EL0), access_cntp_tval },
1011         { SYS_DESC(SYS_CNTP_CTL_EL0), access_cntp_ctl },
1012         { SYS_DESC(SYS_CNTP_CVAL_EL0), access_cntp_cval },
1013
1014         /* PMEVCNTRn_EL0 */
1015         PMU_PMEVCNTR_EL0(0),
1016         PMU_PMEVCNTR_EL0(1),
1017         PMU_PMEVCNTR_EL0(2),
1018         PMU_PMEVCNTR_EL0(3),
1019         PMU_PMEVCNTR_EL0(4),
1020         PMU_PMEVCNTR_EL0(5),
1021         PMU_PMEVCNTR_EL0(6),
1022         PMU_PMEVCNTR_EL0(7),
1023         PMU_PMEVCNTR_EL0(8),
1024         PMU_PMEVCNTR_EL0(9),
1025         PMU_PMEVCNTR_EL0(10),
1026         PMU_PMEVCNTR_EL0(11),
1027         PMU_PMEVCNTR_EL0(12),
1028         PMU_PMEVCNTR_EL0(13),
1029         PMU_PMEVCNTR_EL0(14),
1030         PMU_PMEVCNTR_EL0(15),
1031         PMU_PMEVCNTR_EL0(16),
1032         PMU_PMEVCNTR_EL0(17),
1033         PMU_PMEVCNTR_EL0(18),
1034         PMU_PMEVCNTR_EL0(19),
1035         PMU_PMEVCNTR_EL0(20),
1036         PMU_PMEVCNTR_EL0(21),
1037         PMU_PMEVCNTR_EL0(22),
1038         PMU_PMEVCNTR_EL0(23),
1039         PMU_PMEVCNTR_EL0(24),
1040         PMU_PMEVCNTR_EL0(25),
1041         PMU_PMEVCNTR_EL0(26),
1042         PMU_PMEVCNTR_EL0(27),
1043         PMU_PMEVCNTR_EL0(28),
1044         PMU_PMEVCNTR_EL0(29),
1045         PMU_PMEVCNTR_EL0(30),
1046         /* PMEVTYPERn_EL0 */
1047         PMU_PMEVTYPER_EL0(0),
1048         PMU_PMEVTYPER_EL0(1),
1049         PMU_PMEVTYPER_EL0(2),
1050         PMU_PMEVTYPER_EL0(3),
1051         PMU_PMEVTYPER_EL0(4),
1052         PMU_PMEVTYPER_EL0(5),
1053         PMU_PMEVTYPER_EL0(6),
1054         PMU_PMEVTYPER_EL0(7),
1055         PMU_PMEVTYPER_EL0(8),
1056         PMU_PMEVTYPER_EL0(9),
1057         PMU_PMEVTYPER_EL0(10),
1058         PMU_PMEVTYPER_EL0(11),
1059         PMU_PMEVTYPER_EL0(12),
1060         PMU_PMEVTYPER_EL0(13),
1061         PMU_PMEVTYPER_EL0(14),
1062         PMU_PMEVTYPER_EL0(15),
1063         PMU_PMEVTYPER_EL0(16),
1064         PMU_PMEVTYPER_EL0(17),
1065         PMU_PMEVTYPER_EL0(18),
1066         PMU_PMEVTYPER_EL0(19),
1067         PMU_PMEVTYPER_EL0(20),
1068         PMU_PMEVTYPER_EL0(21),
1069         PMU_PMEVTYPER_EL0(22),
1070         PMU_PMEVTYPER_EL0(23),
1071         PMU_PMEVTYPER_EL0(24),
1072         PMU_PMEVTYPER_EL0(25),
1073         PMU_PMEVTYPER_EL0(26),
1074         PMU_PMEVTYPER_EL0(27),
1075         PMU_PMEVTYPER_EL0(28),
1076         PMU_PMEVTYPER_EL0(29),
1077         PMU_PMEVTYPER_EL0(30),
1078         /*
1079          * PMCCFILTR_EL0 resets as unknown in 64bit mode while it resets as zero
1080          * in 32bit mode. Here we choose to reset it as zero for consistency.
1081          */
1082         { SYS_DESC(SYS_PMCCFILTR_EL0), access_pmu_evtyper, reset_val, PMCCFILTR_EL0, 0 },
1083
1084         { SYS_DESC(SYS_DACR32_EL2), NULL, reset_unknown, DACR32_EL2 },
1085         { SYS_DESC(SYS_IFSR32_EL2), NULL, reset_unknown, IFSR32_EL2 },
1086         { SYS_DESC(SYS_FPEXC32_EL2), NULL, reset_val, FPEXC32_EL2, 0x700 },
1087 };
1088
1089 static bool trap_dbgidr(struct kvm_vcpu *vcpu,
1090                         struct sys_reg_params *p,
1091                         const struct sys_reg_desc *r)
1092 {
1093         if (p->is_write) {
1094                 return ignore_write(vcpu, p);
1095         } else {
1096                 u64 dfr = read_sanitised_ftr_reg(SYS_ID_AA64DFR0_EL1);
1097                 u64 pfr = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1);
1098                 u32 el3 = !!cpuid_feature_extract_unsigned_field(pfr, ID_AA64PFR0_EL3_SHIFT);
1099
1100                 p->regval = ((((dfr >> ID_AA64DFR0_WRPS_SHIFT) & 0xf) << 28) |
1101                              (((dfr >> ID_AA64DFR0_BRPS_SHIFT) & 0xf) << 24) |
1102                              (((dfr >> ID_AA64DFR0_CTX_CMPS_SHIFT) & 0xf) << 20)
1103                              | (6 << 16) | (el3 << 14) | (el3 << 12));
1104                 return true;
1105         }
1106 }
1107
1108 static bool trap_debug32(struct kvm_vcpu *vcpu,
1109                          struct sys_reg_params *p,
1110                          const struct sys_reg_desc *r)
1111 {
1112         if (p->is_write) {
1113                 vcpu_cp14(vcpu, r->reg) = p->regval;
1114                 vcpu->arch.debug_flags |= KVM_ARM64_DEBUG_DIRTY;
1115         } else {
1116                 p->regval = vcpu_cp14(vcpu, r->reg);
1117         }
1118
1119         return true;
1120 }
1121
1122 /* AArch32 debug register mappings
1123  *
1124  * AArch32 DBGBVRn is mapped to DBGBVRn_EL1[31:0]
1125  * AArch32 DBGBXVRn is mapped to DBGBVRn_EL1[63:32]
1126  *
1127  * All control registers and watchpoint value registers are mapped to
1128  * the lower 32 bits of their AArch64 equivalents. We share the trap
1129  * handlers with the above AArch64 code which checks what mode the
1130  * system is in.
1131  */
1132
1133 static bool trap_xvr(struct kvm_vcpu *vcpu,
1134                      struct sys_reg_params *p,
1135                      const struct sys_reg_desc *rd)
1136 {
1137         u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_bvr[rd->reg];
1138
1139         if (p->is_write) {
1140                 u64 val = *dbg_reg;
1141
1142                 val &= 0xffffffffUL;
1143                 val |= p->regval << 32;
1144                 *dbg_reg = val;
1145
1146                 vcpu->arch.debug_flags |= KVM_ARM64_DEBUG_DIRTY;
1147         } else {
1148                 p->regval = *dbg_reg >> 32;
1149         }
1150
1151         trace_trap_reg(__func__, rd->reg, p->is_write, *dbg_reg);
1152
1153         return true;
1154 }
1155
1156 #define DBG_BCR_BVR_WCR_WVR(n)                                          \
1157         /* DBGBVRn */                                                   \
1158         { Op1( 0), CRn( 0), CRm((n)), Op2( 4), trap_bvr, NULL, n },     \
1159         /* DBGBCRn */                                                   \
1160         { Op1( 0), CRn( 0), CRm((n)), Op2( 5), trap_bcr, NULL, n },     \
1161         /* DBGWVRn */                                                   \
1162         { Op1( 0), CRn( 0), CRm((n)), Op2( 6), trap_wvr, NULL, n },     \
1163         /* DBGWCRn */                                                   \
1164         { Op1( 0), CRn( 0), CRm((n)), Op2( 7), trap_wcr, NULL, n }
1165
1166 #define DBGBXVR(n)                                                      \
1167         { Op1( 0), CRn( 1), CRm((n)), Op2( 1), trap_xvr, NULL, n }
1168
1169 /*
1170  * Trapped cp14 registers. We generally ignore most of the external
1171  * debug, on the principle that they don't really make sense to a
1172  * guest. Revisit this one day, would this principle change.
1173  */
1174 static const struct sys_reg_desc cp14_regs[] = {
1175         /* DBGIDR */
1176         { Op1( 0), CRn( 0), CRm( 0), Op2( 0), trap_dbgidr },
1177         /* DBGDTRRXext */
1178         { Op1( 0), CRn( 0), CRm( 0), Op2( 2), trap_raz_wi },
1179
1180         DBG_BCR_BVR_WCR_WVR(0),
1181         /* DBGDSCRint */
1182         { Op1( 0), CRn( 0), CRm( 1), Op2( 0), trap_raz_wi },
1183         DBG_BCR_BVR_WCR_WVR(1),
1184         /* DBGDCCINT */
1185         { Op1( 0), CRn( 0), CRm( 2), Op2( 0), trap_debug32, NULL, cp14_DBGDCCINT },
1186         /* DBGDSCRext */
1187         { Op1( 0), CRn( 0), CRm( 2), Op2( 2), trap_debug32, NULL, cp14_DBGDSCRext },
1188         DBG_BCR_BVR_WCR_WVR(2),
1189         /* DBGDTR[RT]Xint */
1190         { Op1( 0), CRn( 0), CRm( 3), Op2( 0), trap_raz_wi },
1191         /* DBGDTR[RT]Xext */
1192         { Op1( 0), CRn( 0), CRm( 3), Op2( 2), trap_raz_wi },
1193         DBG_BCR_BVR_WCR_WVR(3),
1194         DBG_BCR_BVR_WCR_WVR(4),
1195         DBG_BCR_BVR_WCR_WVR(5),
1196         /* DBGWFAR */
1197         { Op1( 0), CRn( 0), CRm( 6), Op2( 0), trap_raz_wi },
1198         /* DBGOSECCR */
1199         { Op1( 0), CRn( 0), CRm( 6), Op2( 2), trap_raz_wi },
1200         DBG_BCR_BVR_WCR_WVR(6),
1201         /* DBGVCR */
1202         { Op1( 0), CRn( 0), CRm( 7), Op2( 0), trap_debug32, NULL, cp14_DBGVCR },
1203         DBG_BCR_BVR_WCR_WVR(7),
1204         DBG_BCR_BVR_WCR_WVR(8),
1205         DBG_BCR_BVR_WCR_WVR(9),
1206         DBG_BCR_BVR_WCR_WVR(10),
1207         DBG_BCR_BVR_WCR_WVR(11),
1208         DBG_BCR_BVR_WCR_WVR(12),
1209         DBG_BCR_BVR_WCR_WVR(13),
1210         DBG_BCR_BVR_WCR_WVR(14),
1211         DBG_BCR_BVR_WCR_WVR(15),
1212
1213         /* DBGDRAR (32bit) */
1214         { Op1( 0), CRn( 1), CRm( 0), Op2( 0), trap_raz_wi },
1215
1216         DBGBXVR(0),
1217         /* DBGOSLAR */
1218         { Op1( 0), CRn( 1), CRm( 0), Op2( 4), trap_raz_wi },
1219         DBGBXVR(1),
1220         /* DBGOSLSR */
1221         { Op1( 0), CRn( 1), CRm( 1), Op2( 4), trap_oslsr_el1 },
1222         DBGBXVR(2),
1223         DBGBXVR(3),
1224         /* DBGOSDLR */
1225         { Op1( 0), CRn( 1), CRm( 3), Op2( 4), trap_raz_wi },
1226         DBGBXVR(4),
1227         /* DBGPRCR */
1228         { Op1( 0), CRn( 1), CRm( 4), Op2( 4), trap_raz_wi },
1229         DBGBXVR(5),
1230         DBGBXVR(6),
1231         DBGBXVR(7),
1232         DBGBXVR(8),
1233         DBGBXVR(9),
1234         DBGBXVR(10),
1235         DBGBXVR(11),
1236         DBGBXVR(12),
1237         DBGBXVR(13),
1238         DBGBXVR(14),
1239         DBGBXVR(15),
1240
1241         /* DBGDSAR (32bit) */
1242         { Op1( 0), CRn( 2), CRm( 0), Op2( 0), trap_raz_wi },
1243
1244         /* DBGDEVID2 */
1245         { Op1( 0), CRn( 7), CRm( 0), Op2( 7), trap_raz_wi },
1246         /* DBGDEVID1 */
1247         { Op1( 0), CRn( 7), CRm( 1), Op2( 7), trap_raz_wi },
1248         /* DBGDEVID */
1249         { Op1( 0), CRn( 7), CRm( 2), Op2( 7), trap_raz_wi },
1250         /* DBGCLAIMSET */
1251         { Op1( 0), CRn( 7), CRm( 8), Op2( 6), trap_raz_wi },
1252         /* DBGCLAIMCLR */
1253         { Op1( 0), CRn( 7), CRm( 9), Op2( 6), trap_raz_wi },
1254         /* DBGAUTHSTATUS */
1255         { Op1( 0), CRn( 7), CRm(14), Op2( 6), trap_dbgauthstatus_el1 },
1256 };
1257
1258 /* Trapped cp14 64bit registers */
1259 static const struct sys_reg_desc cp14_64_regs[] = {
1260         /* DBGDRAR (64bit) */
1261         { Op1( 0), CRm( 1), .access = trap_raz_wi },
1262
1263         /* DBGDSAR (64bit) */
1264         { Op1( 0), CRm( 2), .access = trap_raz_wi },
1265 };
1266
1267 /* Macro to expand the PMEVCNTRn register */
1268 #define PMU_PMEVCNTR(n)                                                 \
1269         /* PMEVCNTRn */                                                 \
1270         { Op1(0), CRn(0b1110),                                          \
1271           CRm((0b1000 | (((n) >> 3) & 0x3))), Op2(((n) & 0x7)),         \
1272           access_pmu_evcntr }
1273
1274 /* Macro to expand the PMEVTYPERn register */
1275 #define PMU_PMEVTYPER(n)                                                \
1276         /* PMEVTYPERn */                                                \
1277         { Op1(0), CRn(0b1110),                                          \
1278           CRm((0b1100 | (((n) >> 3) & 0x3))), Op2(((n) & 0x7)),         \
1279           access_pmu_evtyper }
1280
1281 /*
1282  * Trapped cp15 registers. TTBR0/TTBR1 get a double encoding,
1283  * depending on the way they are accessed (as a 32bit or a 64bit
1284  * register).
1285  */
1286 static const struct sys_reg_desc cp15_regs[] = {
1287         { Op1( 0), CRn( 0), CRm(12), Op2( 0), access_gic_sgi },
1288
1289         { Op1( 0), CRn( 1), CRm( 0), Op2( 0), access_vm_reg, NULL, c1_SCTLR },
1290         { Op1( 0), CRn( 2), CRm( 0), Op2( 0), access_vm_reg, NULL, c2_TTBR0 },
1291         { Op1( 0), CRn( 2), CRm( 0), Op2( 1), access_vm_reg, NULL, c2_TTBR1 },
1292         { Op1( 0), CRn( 2), CRm( 0), Op2( 2), access_vm_reg, NULL, c2_TTBCR },
1293         { Op1( 0), CRn( 2), CRm( 0), Op2( 3), access_vm_reg, NULL, c2_TTBCR2 },
1294         { Op1( 0), CRn( 3), CRm( 0), Op2( 0), access_vm_reg, NULL, c3_DACR },
1295         { Op1( 0), CRn( 5), CRm( 0), Op2( 0), access_vm_reg, NULL, c5_DFSR },
1296         { Op1( 0), CRn( 5), CRm( 0), Op2( 1), access_vm_reg, NULL, c5_IFSR },
1297         { Op1( 0), CRn( 5), CRm( 1), Op2( 0), access_vm_reg, NULL, c5_ADFSR },
1298         { Op1( 0), CRn( 5), CRm( 1), Op2( 1), access_vm_reg, NULL, c5_AIFSR },
1299         { Op1( 0), CRn( 6), CRm( 0), Op2( 0), access_vm_reg, NULL, c6_DFAR },
1300         { Op1( 0), CRn( 6), CRm( 0), Op2( 2), access_vm_reg, NULL, c6_IFAR },
1301
1302         /*
1303          * DC{C,I,CI}SW operations:
1304          */
1305         { Op1( 0), CRn( 7), CRm( 6), Op2( 2), access_dcsw },
1306         { Op1( 0), CRn( 7), CRm(10), Op2( 2), access_dcsw },
1307         { Op1( 0), CRn( 7), CRm(14), Op2( 2), access_dcsw },
1308
1309         /* PMU */
1310         { Op1( 0), CRn( 9), CRm(12), Op2( 0), access_pmcr },
1311         { Op1( 0), CRn( 9), CRm(12), Op2( 1), access_pmcnten },
1312         { Op1( 0), CRn( 9), CRm(12), Op2( 2), access_pmcnten },
1313         { Op1( 0), CRn( 9), CRm(12), Op2( 3), access_pmovs },
1314         { Op1( 0), CRn( 9), CRm(12), Op2( 4), access_pmswinc },
1315         { Op1( 0), CRn( 9), CRm(12), Op2( 5), access_pmselr },
1316         { Op1( 0), CRn( 9), CRm(12), Op2( 6), access_pmceid },
1317         { Op1( 0), CRn( 9), CRm(12), Op2( 7), access_pmceid },
1318         { Op1( 0), CRn( 9), CRm(13), Op2( 0), access_pmu_evcntr },
1319         { Op1( 0), CRn( 9), CRm(13), Op2( 1), access_pmu_evtyper },
1320         { Op1( 0), CRn( 9), CRm(13), Op2( 2), access_pmu_evcntr },
1321         { Op1( 0), CRn( 9), CRm(14), Op2( 0), access_pmuserenr },
1322         { Op1( 0), CRn( 9), CRm(14), Op2( 1), access_pminten },
1323         { Op1( 0), CRn( 9), CRm(14), Op2( 2), access_pminten },
1324         { Op1( 0), CRn( 9), CRm(14), Op2( 3), access_pmovs },
1325
1326         { Op1( 0), CRn(10), CRm( 2), Op2( 0), access_vm_reg, NULL, c10_PRRR },
1327         { Op1( 0), CRn(10), CRm( 2), Op2( 1), access_vm_reg, NULL, c10_NMRR },
1328         { Op1( 0), CRn(10), CRm( 3), Op2( 0), access_vm_reg, NULL, c10_AMAIR0 },
1329         { Op1( 0), CRn(10), CRm( 3), Op2( 1), access_vm_reg, NULL, c10_AMAIR1 },
1330
1331         /* ICC_SRE */
1332         { Op1( 0), CRn(12), CRm(12), Op2( 5), access_gic_sre },
1333
1334         { Op1( 0), CRn(13), CRm( 0), Op2( 1), access_vm_reg, NULL, c13_CID },
1335
1336         /* PMEVCNTRn */
1337         PMU_PMEVCNTR(0),
1338         PMU_PMEVCNTR(1),
1339         PMU_PMEVCNTR(2),
1340         PMU_PMEVCNTR(3),
1341         PMU_PMEVCNTR(4),
1342         PMU_PMEVCNTR(5),
1343         PMU_PMEVCNTR(6),
1344         PMU_PMEVCNTR(7),
1345         PMU_PMEVCNTR(8),
1346         PMU_PMEVCNTR(9),
1347         PMU_PMEVCNTR(10),
1348         PMU_PMEVCNTR(11),
1349         PMU_PMEVCNTR(12),
1350         PMU_PMEVCNTR(13),
1351         PMU_PMEVCNTR(14),
1352         PMU_PMEVCNTR(15),
1353         PMU_PMEVCNTR(16),
1354         PMU_PMEVCNTR(17),
1355         PMU_PMEVCNTR(18),
1356         PMU_PMEVCNTR(19),
1357         PMU_PMEVCNTR(20),
1358         PMU_PMEVCNTR(21),
1359         PMU_PMEVCNTR(22),
1360         PMU_PMEVCNTR(23),
1361         PMU_PMEVCNTR(24),
1362         PMU_PMEVCNTR(25),
1363         PMU_PMEVCNTR(26),
1364         PMU_PMEVCNTR(27),
1365         PMU_PMEVCNTR(28),
1366         PMU_PMEVCNTR(29),
1367         PMU_PMEVCNTR(30),
1368         /* PMEVTYPERn */
1369         PMU_PMEVTYPER(0),
1370         PMU_PMEVTYPER(1),
1371         PMU_PMEVTYPER(2),
1372         PMU_PMEVTYPER(3),
1373         PMU_PMEVTYPER(4),
1374         PMU_PMEVTYPER(5),
1375         PMU_PMEVTYPER(6),
1376         PMU_PMEVTYPER(7),
1377         PMU_PMEVTYPER(8),
1378         PMU_PMEVTYPER(9),
1379         PMU_PMEVTYPER(10),
1380         PMU_PMEVTYPER(11),
1381         PMU_PMEVTYPER(12),
1382         PMU_PMEVTYPER(13),
1383         PMU_PMEVTYPER(14),
1384         PMU_PMEVTYPER(15),
1385         PMU_PMEVTYPER(16),
1386         PMU_PMEVTYPER(17),
1387         PMU_PMEVTYPER(18),
1388         PMU_PMEVTYPER(19),
1389         PMU_PMEVTYPER(20),
1390         PMU_PMEVTYPER(21),
1391         PMU_PMEVTYPER(22),
1392         PMU_PMEVTYPER(23),
1393         PMU_PMEVTYPER(24),
1394         PMU_PMEVTYPER(25),
1395         PMU_PMEVTYPER(26),
1396         PMU_PMEVTYPER(27),
1397         PMU_PMEVTYPER(28),
1398         PMU_PMEVTYPER(29),
1399         PMU_PMEVTYPER(30),
1400         /* PMCCFILTR */
1401         { Op1(0), CRn(14), CRm(15), Op2(7), access_pmu_evtyper },
1402 };
1403
1404 static const struct sys_reg_desc cp15_64_regs[] = {
1405         { Op1( 0), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, c2_TTBR0 },
1406         { Op1( 0), CRn( 0), CRm( 9), Op2( 0), access_pmu_evcntr },
1407         { Op1( 0), CRn( 0), CRm(12), Op2( 0), access_gic_sgi },
1408         { Op1( 1), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, c2_TTBR1 },
1409 };
1410
1411 /* Target specific emulation tables */
1412 static struct kvm_sys_reg_target_table *target_tables[KVM_ARM_NUM_TARGETS];
1413
1414 void kvm_register_target_sys_reg_table(unsigned int target,
1415                                        struct kvm_sys_reg_target_table *table)
1416 {
1417         target_tables[target] = table;
1418 }
1419
1420 /* Get specific register table for this target. */
1421 static const struct sys_reg_desc *get_target_table(unsigned target,
1422                                                    bool mode_is_64,
1423                                                    size_t *num)
1424 {
1425         struct kvm_sys_reg_target_table *table;
1426
1427         table = target_tables[target];
1428         if (mode_is_64) {
1429                 *num = table->table64.num;
1430                 return table->table64.table;
1431         } else {
1432                 *num = table->table32.num;
1433                 return table->table32.table;
1434         }
1435 }
1436
1437 #define reg_to_match_value(x)                                           \
1438         ({                                                              \
1439                 unsigned long val;                                      \
1440                 val  = (x)->Op0 << 14;                                  \
1441                 val |= (x)->Op1 << 11;                                  \
1442                 val |= (x)->CRn << 7;                                   \
1443                 val |= (x)->CRm << 3;                                   \
1444                 val |= (x)->Op2;                                        \
1445                 val;                                                    \
1446          })
1447
1448 static int match_sys_reg(const void *key, const void *elt)
1449 {
1450         const unsigned long pval = (unsigned long)key;
1451         const struct sys_reg_desc *r = elt;
1452
1453         return pval - reg_to_match_value(r);
1454 }
1455
1456 static const struct sys_reg_desc *find_reg(const struct sys_reg_params *params,
1457                                          const struct sys_reg_desc table[],
1458                                          unsigned int num)
1459 {
1460         unsigned long pval = reg_to_match_value(params);
1461
1462         return bsearch((void *)pval, table, num, sizeof(table[0]), match_sys_reg);
1463 }
1464
1465 int kvm_handle_cp14_load_store(struct kvm_vcpu *vcpu, struct kvm_run *run)
1466 {
1467         kvm_inject_undefined(vcpu);
1468         return 1;
1469 }
1470
1471 static void perform_access(struct kvm_vcpu *vcpu,
1472                            struct sys_reg_params *params,
1473                            const struct sys_reg_desc *r)
1474 {
1475         /*
1476          * Not having an accessor means that we have configured a trap
1477          * that we don't know how to handle. This certainly qualifies
1478          * as a gross bug that should be fixed right away.
1479          */
1480         BUG_ON(!r->access);
1481
1482         /* Skip instruction if instructed so */
1483         if (likely(r->access(vcpu, params, r)))
1484                 kvm_skip_instr(vcpu, kvm_vcpu_trap_il_is32bit(vcpu));
1485 }
1486
1487 /*
1488  * emulate_cp --  tries to match a sys_reg access in a handling table, and
1489  *                call the corresponding trap handler.
1490  *
1491  * @params: pointer to the descriptor of the access
1492  * @table: array of trap descriptors
1493  * @num: size of the trap descriptor array
1494  *
1495  * Return 0 if the access has been handled, and -1 if not.
1496  */
1497 static int emulate_cp(struct kvm_vcpu *vcpu,
1498                       struct sys_reg_params *params,
1499                       const struct sys_reg_desc *table,
1500                       size_t num)
1501 {
1502         const struct sys_reg_desc *r;
1503
1504         if (!table)
1505                 return -1;      /* Not handled */
1506
1507         r = find_reg(params, table, num);
1508
1509         if (r) {
1510                 perform_access(vcpu, params, r);
1511                 return 0;
1512         }
1513
1514         /* Not handled */
1515         return -1;
1516 }
1517
1518 static void unhandled_cp_access(struct kvm_vcpu *vcpu,
1519                                 struct sys_reg_params *params)
1520 {
1521         u8 hsr_ec = kvm_vcpu_trap_get_class(vcpu);
1522         int cp = -1;
1523
1524         switch(hsr_ec) {
1525         case ESR_ELx_EC_CP15_32:
1526         case ESR_ELx_EC_CP15_64:
1527                 cp = 15;
1528                 break;
1529         case ESR_ELx_EC_CP14_MR:
1530         case ESR_ELx_EC_CP14_64:
1531                 cp = 14;
1532                 break;
1533         default:
1534                 WARN_ON(1);
1535         }
1536
1537         kvm_err("Unsupported guest CP%d access at: %08lx\n",
1538                 cp, *vcpu_pc(vcpu));
1539         print_sys_reg_instr(params);
1540         kvm_inject_undefined(vcpu);
1541 }
1542
1543 /**
1544  * kvm_handle_cp_64 -- handles a mrrc/mcrr trap on a guest CP14/CP15 access
1545  * @vcpu: The VCPU pointer
1546  * @run:  The kvm_run struct
1547  */
1548 static int kvm_handle_cp_64(struct kvm_vcpu *vcpu,
1549                             const struct sys_reg_desc *global,
1550                             size_t nr_global,
1551                             const struct sys_reg_desc *target_specific,
1552                             size_t nr_specific)
1553 {
1554         struct sys_reg_params params;
1555         u32 hsr = kvm_vcpu_get_hsr(vcpu);
1556         int Rt = kvm_vcpu_sys_get_rt(vcpu);
1557         int Rt2 = (hsr >> 10) & 0x1f;
1558
1559         params.is_aarch32 = true;
1560         params.is_32bit = false;
1561         params.CRm = (hsr >> 1) & 0xf;
1562         params.is_write = ((hsr & 1) == 0);
1563
1564         params.Op0 = 0;
1565         params.Op1 = (hsr >> 16) & 0xf;
1566         params.Op2 = 0;
1567         params.CRn = 0;
1568
1569         /*
1570          * Make a 64-bit value out of Rt and Rt2. As we use the same trap
1571          * backends between AArch32 and AArch64, we get away with it.
1572          */
1573         if (params.is_write) {
1574                 params.regval = vcpu_get_reg(vcpu, Rt) & 0xffffffff;
1575                 params.regval |= vcpu_get_reg(vcpu, Rt2) << 32;
1576         }
1577
1578         /*
1579          * Try to emulate the coprocessor access using the target
1580          * specific table first, and using the global table afterwards.
1581          * If either of the tables contains a handler, handle the
1582          * potential register operation in the case of a read and return
1583          * with success.
1584          */
1585         if (!emulate_cp(vcpu, &params, target_specific, nr_specific) ||
1586             !emulate_cp(vcpu, &params, global, nr_global)) {
1587                 /* Split up the value between registers for the read side */
1588                 if (!params.is_write) {
1589                         vcpu_set_reg(vcpu, Rt, lower_32_bits(params.regval));
1590                         vcpu_set_reg(vcpu, Rt2, upper_32_bits(params.regval));
1591                 }
1592
1593                 return 1;
1594         }
1595
1596         unhandled_cp_access(vcpu, &params);
1597         return 1;
1598 }
1599
1600 /**
1601  * kvm_handle_cp_32 -- handles a mrc/mcr trap on a guest CP14/CP15 access
1602  * @vcpu: The VCPU pointer
1603  * @run:  The kvm_run struct
1604  */
1605 static int kvm_handle_cp_32(struct kvm_vcpu *vcpu,
1606                             const struct sys_reg_desc *global,
1607                             size_t nr_global,
1608                             const struct sys_reg_desc *target_specific,
1609                             size_t nr_specific)
1610 {
1611         struct sys_reg_params params;
1612         u32 hsr = kvm_vcpu_get_hsr(vcpu);
1613         int Rt  = kvm_vcpu_sys_get_rt(vcpu);
1614
1615         params.is_aarch32 = true;
1616         params.is_32bit = true;
1617         params.CRm = (hsr >> 1) & 0xf;
1618         params.regval = vcpu_get_reg(vcpu, Rt);
1619         params.is_write = ((hsr & 1) == 0);
1620         params.CRn = (hsr >> 10) & 0xf;
1621         params.Op0 = 0;
1622         params.Op1 = (hsr >> 14) & 0x7;
1623         params.Op2 = (hsr >> 17) & 0x7;
1624
1625         if (!emulate_cp(vcpu, &params, target_specific, nr_specific) ||
1626             !emulate_cp(vcpu, &params, global, nr_global)) {
1627                 if (!params.is_write)
1628                         vcpu_set_reg(vcpu, Rt, params.regval);
1629                 return 1;
1630         }
1631
1632         unhandled_cp_access(vcpu, &params);
1633         return 1;
1634 }
1635
1636 int kvm_handle_cp15_64(struct kvm_vcpu *vcpu, struct kvm_run *run)
1637 {
1638         const struct sys_reg_desc *target_specific;
1639         size_t num;
1640
1641         target_specific = get_target_table(vcpu->arch.target, false, &num);
1642         return kvm_handle_cp_64(vcpu,
1643                                 cp15_64_regs, ARRAY_SIZE(cp15_64_regs),
1644                                 target_specific, num);
1645 }
1646
1647 int kvm_handle_cp15_32(struct kvm_vcpu *vcpu, struct kvm_run *run)
1648 {
1649         const struct sys_reg_desc *target_specific;
1650         size_t num;
1651
1652         target_specific = get_target_table(vcpu->arch.target, false, &num);
1653         return kvm_handle_cp_32(vcpu,
1654                                 cp15_regs, ARRAY_SIZE(cp15_regs),
1655                                 target_specific, num);
1656 }
1657
1658 int kvm_handle_cp14_64(struct kvm_vcpu *vcpu, struct kvm_run *run)
1659 {
1660         return kvm_handle_cp_64(vcpu,
1661                                 cp14_64_regs, ARRAY_SIZE(cp14_64_regs),
1662                                 NULL, 0);
1663 }
1664
1665 int kvm_handle_cp14_32(struct kvm_vcpu *vcpu, struct kvm_run *run)
1666 {
1667         return kvm_handle_cp_32(vcpu,
1668                                 cp14_regs, ARRAY_SIZE(cp14_regs),
1669                                 NULL, 0);
1670 }
1671
1672 static int emulate_sys_reg(struct kvm_vcpu *vcpu,
1673                            struct sys_reg_params *params)
1674 {
1675         size_t num;
1676         const struct sys_reg_desc *table, *r;
1677
1678         table = get_target_table(vcpu->arch.target, true, &num);
1679
1680         /* Search target-specific then generic table. */
1681         r = find_reg(params, table, num);
1682         if (!r)
1683                 r = find_reg(params, sys_reg_descs, ARRAY_SIZE(sys_reg_descs));
1684
1685         if (likely(r)) {
1686                 perform_access(vcpu, params, r);
1687         } else {
1688                 kvm_err("Unsupported guest sys_reg access at: %lx\n",
1689                         *vcpu_pc(vcpu));
1690                 print_sys_reg_instr(params);
1691                 kvm_inject_undefined(vcpu);
1692         }
1693         return 1;
1694 }
1695
1696 static void reset_sys_reg_descs(struct kvm_vcpu *vcpu,
1697                               const struct sys_reg_desc *table, size_t num)
1698 {
1699         unsigned long i;
1700
1701         for (i = 0; i < num; i++)
1702                 if (table[i].reset)
1703                         table[i].reset(vcpu, &table[i]);
1704 }
1705
1706 /**
1707  * kvm_handle_sys_reg -- handles a mrs/msr trap on a guest sys_reg access
1708  * @vcpu: The VCPU pointer
1709  * @run:  The kvm_run struct
1710  */
1711 int kvm_handle_sys_reg(struct kvm_vcpu *vcpu, struct kvm_run *run)
1712 {
1713         struct sys_reg_params params;
1714         unsigned long esr = kvm_vcpu_get_hsr(vcpu);
1715         int Rt = kvm_vcpu_sys_get_rt(vcpu);
1716         int ret;
1717
1718         trace_kvm_handle_sys_reg(esr);
1719
1720         params.is_aarch32 = false;
1721         params.is_32bit = false;
1722         params.Op0 = (esr >> 20) & 3;
1723         params.Op1 = (esr >> 14) & 0x7;
1724         params.CRn = (esr >> 10) & 0xf;
1725         params.CRm = (esr >> 1) & 0xf;
1726         params.Op2 = (esr >> 17) & 0x7;
1727         params.regval = vcpu_get_reg(vcpu, Rt);
1728         params.is_write = !(esr & 1);
1729
1730         ret = emulate_sys_reg(vcpu, &params);
1731
1732         if (!params.is_write)
1733                 vcpu_set_reg(vcpu, Rt, params.regval);
1734         return ret;
1735 }
1736
1737 /******************************************************************************
1738  * Userspace API
1739  *****************************************************************************/
1740
1741 static bool index_to_params(u64 id, struct sys_reg_params *params)
1742 {
1743         switch (id & KVM_REG_SIZE_MASK) {
1744         case KVM_REG_SIZE_U64:
1745                 /* Any unused index bits means it's not valid. */
1746                 if (id & ~(KVM_REG_ARCH_MASK | KVM_REG_SIZE_MASK
1747                               | KVM_REG_ARM_COPROC_MASK
1748                               | KVM_REG_ARM64_SYSREG_OP0_MASK
1749                               | KVM_REG_ARM64_SYSREG_OP1_MASK
1750                               | KVM_REG_ARM64_SYSREG_CRN_MASK
1751                               | KVM_REG_ARM64_SYSREG_CRM_MASK
1752                               | KVM_REG_ARM64_SYSREG_OP2_MASK))
1753                         return false;
1754                 params->Op0 = ((id & KVM_REG_ARM64_SYSREG_OP0_MASK)
1755                                >> KVM_REG_ARM64_SYSREG_OP0_SHIFT);
1756                 params->Op1 = ((id & KVM_REG_ARM64_SYSREG_OP1_MASK)
1757                                >> KVM_REG_ARM64_SYSREG_OP1_SHIFT);
1758                 params->CRn = ((id & KVM_REG_ARM64_SYSREG_CRN_MASK)
1759                                >> KVM_REG_ARM64_SYSREG_CRN_SHIFT);
1760                 params->CRm = ((id & KVM_REG_ARM64_SYSREG_CRM_MASK)
1761                                >> KVM_REG_ARM64_SYSREG_CRM_SHIFT);
1762                 params->Op2 = ((id & KVM_REG_ARM64_SYSREG_OP2_MASK)
1763                                >> KVM_REG_ARM64_SYSREG_OP2_SHIFT);
1764                 return true;
1765         default:
1766                 return false;
1767         }
1768 }
1769
1770 const struct sys_reg_desc *find_reg_by_id(u64 id,
1771                                           struct sys_reg_params *params,
1772                                           const struct sys_reg_desc table[],
1773                                           unsigned int num)
1774 {
1775         if (!index_to_params(id, params))
1776                 return NULL;
1777
1778         return find_reg(params, table, num);
1779 }
1780
1781 /* Decode an index value, and find the sys_reg_desc entry. */
1782 static const struct sys_reg_desc *index_to_sys_reg_desc(struct kvm_vcpu *vcpu,
1783                                                     u64 id)
1784 {
1785         size_t num;
1786         const struct sys_reg_desc *table, *r;
1787         struct sys_reg_params params;
1788
1789         /* We only do sys_reg for now. */
1790         if ((id & KVM_REG_ARM_COPROC_MASK) != KVM_REG_ARM64_SYSREG)
1791                 return NULL;
1792
1793         if (!index_to_params(id, &params))
1794                 return NULL;
1795
1796         table = get_target_table(vcpu->arch.target, true, &num);
1797         r = find_reg(&params, table, num);
1798         if (!r)
1799                 r = find_reg(&params, sys_reg_descs, ARRAY_SIZE(sys_reg_descs));
1800
1801         /* Not saved in the sys_reg array? */
1802         if (r && !r->reg)
1803                 r = NULL;
1804
1805         return r;
1806 }
1807
1808 /*
1809  * These are the invariant sys_reg registers: we let the guest see the
1810  * host versions of these, so they're part of the guest state.
1811  *
1812  * A future CPU may provide a mechanism to present different values to
1813  * the guest, or a future kvm may trap them.
1814  */
1815
1816 #define FUNCTION_INVARIANT(reg)                                         \
1817         static void get_##reg(struct kvm_vcpu *v,                       \
1818                               const struct sys_reg_desc *r)             \
1819         {                                                               \
1820                 ((struct sys_reg_desc *)r)->val = read_sysreg(reg);     \
1821         }
1822
1823 FUNCTION_INVARIANT(midr_el1)
1824 FUNCTION_INVARIANT(ctr_el0)
1825 FUNCTION_INVARIANT(revidr_el1)
1826 FUNCTION_INVARIANT(id_pfr0_el1)
1827 FUNCTION_INVARIANT(id_pfr1_el1)
1828 FUNCTION_INVARIANT(id_dfr0_el1)
1829 FUNCTION_INVARIANT(id_afr0_el1)
1830 FUNCTION_INVARIANT(id_mmfr0_el1)
1831 FUNCTION_INVARIANT(id_mmfr1_el1)
1832 FUNCTION_INVARIANT(id_mmfr2_el1)
1833 FUNCTION_INVARIANT(id_mmfr3_el1)
1834 FUNCTION_INVARIANT(id_isar0_el1)
1835 FUNCTION_INVARIANT(id_isar1_el1)
1836 FUNCTION_INVARIANT(id_isar2_el1)
1837 FUNCTION_INVARIANT(id_isar3_el1)
1838 FUNCTION_INVARIANT(id_isar4_el1)
1839 FUNCTION_INVARIANT(id_isar5_el1)
1840 FUNCTION_INVARIANT(clidr_el1)
1841 FUNCTION_INVARIANT(aidr_el1)
1842
1843 /* ->val is filled in by kvm_sys_reg_table_init() */
1844 static struct sys_reg_desc invariant_sys_regs[] = {
1845         { SYS_DESC(SYS_MIDR_EL1), NULL, get_midr_el1 },
1846         { SYS_DESC(SYS_REVIDR_EL1), NULL, get_revidr_el1 },
1847         { SYS_DESC(SYS_ID_PFR0_EL1), NULL, get_id_pfr0_el1 },
1848         { SYS_DESC(SYS_ID_PFR1_EL1), NULL, get_id_pfr1_el1 },
1849         { SYS_DESC(SYS_ID_DFR0_EL1), NULL, get_id_dfr0_el1 },
1850         { SYS_DESC(SYS_ID_AFR0_EL1), NULL, get_id_afr0_el1 },
1851         { SYS_DESC(SYS_ID_MMFR0_EL1), NULL, get_id_mmfr0_el1 },
1852         { SYS_DESC(SYS_ID_MMFR1_EL1), NULL, get_id_mmfr1_el1 },
1853         { SYS_DESC(SYS_ID_MMFR2_EL1), NULL, get_id_mmfr2_el1 },
1854         { SYS_DESC(SYS_ID_MMFR3_EL1), NULL, get_id_mmfr3_el1 },
1855         { SYS_DESC(SYS_ID_ISAR0_EL1), NULL, get_id_isar0_el1 },
1856         { SYS_DESC(SYS_ID_ISAR1_EL1), NULL, get_id_isar1_el1 },
1857         { SYS_DESC(SYS_ID_ISAR2_EL1), NULL, get_id_isar2_el1 },
1858         { SYS_DESC(SYS_ID_ISAR3_EL1), NULL, get_id_isar3_el1 },
1859         { SYS_DESC(SYS_ID_ISAR4_EL1), NULL, get_id_isar4_el1 },
1860         { SYS_DESC(SYS_ID_ISAR5_EL1), NULL, get_id_isar5_el1 },
1861         { SYS_DESC(SYS_CLIDR_EL1), NULL, get_clidr_el1 },
1862         { SYS_DESC(SYS_AIDR_EL1), NULL, get_aidr_el1 },
1863         { SYS_DESC(SYS_CTR_EL0), NULL, get_ctr_el0 },
1864 };
1865
1866 static int reg_from_user(u64 *val, const void __user *uaddr, u64 id)
1867 {
1868         if (copy_from_user(val, uaddr, KVM_REG_SIZE(id)) != 0)
1869                 return -EFAULT;
1870         return 0;
1871 }
1872
1873 static int reg_to_user(void __user *uaddr, const u64 *val, u64 id)
1874 {
1875         if (copy_to_user(uaddr, val, KVM_REG_SIZE(id)) != 0)
1876                 return -EFAULT;
1877         return 0;
1878 }
1879
1880 static int get_invariant_sys_reg(u64 id, void __user *uaddr)
1881 {
1882         struct sys_reg_params params;
1883         const struct sys_reg_desc *r;
1884
1885         r = find_reg_by_id(id, &params, invariant_sys_regs,
1886                            ARRAY_SIZE(invariant_sys_regs));
1887         if (!r)
1888                 return -ENOENT;
1889
1890         return reg_to_user(uaddr, &r->val, id);
1891 }
1892
1893 static int set_invariant_sys_reg(u64 id, void __user *uaddr)
1894 {
1895         struct sys_reg_params params;
1896         const struct sys_reg_desc *r;
1897         int err;
1898         u64 val = 0; /* Make sure high bits are 0 for 32-bit regs */
1899
1900         r = find_reg_by_id(id, &params, invariant_sys_regs,
1901                            ARRAY_SIZE(invariant_sys_regs));
1902         if (!r)
1903                 return -ENOENT;
1904
1905         err = reg_from_user(&val, uaddr, id);
1906         if (err)
1907                 return err;
1908
1909         /* This is what we mean by invariant: you can't change it. */
1910         if (r->val != val)
1911                 return -EINVAL;
1912
1913         return 0;
1914 }
1915
1916 static bool is_valid_cache(u32 val)
1917 {
1918         u32 level, ctype;
1919
1920         if (val >= CSSELR_MAX)
1921                 return false;
1922
1923         /* Bottom bit is Instruction or Data bit.  Next 3 bits are level. */
1924         level = (val >> 1);
1925         ctype = (cache_levels >> (level * 3)) & 7;
1926
1927         switch (ctype) {
1928         case 0: /* No cache */
1929                 return false;
1930         case 1: /* Instruction cache only */
1931                 return (val & 1);
1932         case 2: /* Data cache only */
1933         case 4: /* Unified cache */
1934                 return !(val & 1);
1935         case 3: /* Separate instruction and data caches */
1936                 return true;
1937         default: /* Reserved: we can't know instruction or data. */
1938                 return false;
1939         }
1940 }
1941
1942 static int demux_c15_get(u64 id, void __user *uaddr)
1943 {
1944         u32 val;
1945         u32 __user *uval = uaddr;
1946
1947         /* Fail if we have unknown bits set. */
1948         if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK
1949                    | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1)))
1950                 return -ENOENT;
1951
1952         switch (id & KVM_REG_ARM_DEMUX_ID_MASK) {
1953         case KVM_REG_ARM_DEMUX_ID_CCSIDR:
1954                 if (KVM_REG_SIZE(id) != 4)
1955                         return -ENOENT;
1956                 val = (id & KVM_REG_ARM_DEMUX_VAL_MASK)
1957                         >> KVM_REG_ARM_DEMUX_VAL_SHIFT;
1958                 if (!is_valid_cache(val))
1959                         return -ENOENT;
1960
1961                 return put_user(get_ccsidr(val), uval);
1962         default:
1963                 return -ENOENT;
1964         }
1965 }
1966
1967 static int demux_c15_set(u64 id, void __user *uaddr)
1968 {
1969         u32 val, newval;
1970         u32 __user *uval = uaddr;
1971
1972         /* Fail if we have unknown bits set. */
1973         if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK
1974                    | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1)))
1975                 return -ENOENT;
1976
1977         switch (id & KVM_REG_ARM_DEMUX_ID_MASK) {
1978         case KVM_REG_ARM_DEMUX_ID_CCSIDR:
1979                 if (KVM_REG_SIZE(id) != 4)
1980                         return -ENOENT;
1981                 val = (id & KVM_REG_ARM_DEMUX_VAL_MASK)
1982                         >> KVM_REG_ARM_DEMUX_VAL_SHIFT;
1983                 if (!is_valid_cache(val))
1984                         return -ENOENT;
1985
1986                 if (get_user(newval, uval))
1987                         return -EFAULT;
1988
1989                 /* This is also invariant: you can't change it. */
1990                 if (newval != get_ccsidr(val))
1991                         return -EINVAL;
1992                 return 0;
1993         default:
1994                 return -ENOENT;
1995         }
1996 }
1997
1998 int kvm_arm_sys_reg_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
1999 {
2000         const struct sys_reg_desc *r;
2001         void __user *uaddr = (void __user *)(unsigned long)reg->addr;
2002
2003         if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_DEMUX)
2004                 return demux_c15_get(reg->id, uaddr);
2005
2006         if (KVM_REG_SIZE(reg->id) != sizeof(__u64))
2007                 return -ENOENT;
2008
2009         r = index_to_sys_reg_desc(vcpu, reg->id);
2010         if (!r)
2011                 return get_invariant_sys_reg(reg->id, uaddr);
2012
2013         if (r->get_user)
2014                 return (r->get_user)(vcpu, r, reg, uaddr);
2015
2016         return reg_to_user(uaddr, &vcpu_sys_reg(vcpu, r->reg), reg->id);
2017 }
2018
2019 int kvm_arm_sys_reg_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
2020 {
2021         const struct sys_reg_desc *r;
2022         void __user *uaddr = (void __user *)(unsigned long)reg->addr;
2023
2024         if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_DEMUX)
2025                 return demux_c15_set(reg->id, uaddr);
2026
2027         if (KVM_REG_SIZE(reg->id) != sizeof(__u64))
2028                 return -ENOENT;
2029
2030         r = index_to_sys_reg_desc(vcpu, reg->id);
2031         if (!r)
2032                 return set_invariant_sys_reg(reg->id, uaddr);
2033
2034         if (r->set_user)
2035                 return (r->set_user)(vcpu, r, reg, uaddr);
2036
2037         return reg_from_user(&vcpu_sys_reg(vcpu, r->reg), uaddr, reg->id);
2038 }
2039
2040 static unsigned int num_demux_regs(void)
2041 {
2042         unsigned int i, count = 0;
2043
2044         for (i = 0; i < CSSELR_MAX; i++)
2045                 if (is_valid_cache(i))
2046                         count++;
2047
2048         return count;
2049 }
2050
2051 static int write_demux_regids(u64 __user *uindices)
2052 {
2053         u64 val = KVM_REG_ARM64 | KVM_REG_SIZE_U32 | KVM_REG_ARM_DEMUX;
2054         unsigned int i;
2055
2056         val |= KVM_REG_ARM_DEMUX_ID_CCSIDR;
2057         for (i = 0; i < CSSELR_MAX; i++) {
2058                 if (!is_valid_cache(i))
2059                         continue;
2060                 if (put_user(val | i, uindices))
2061                         return -EFAULT;
2062                 uindices++;
2063         }
2064         return 0;
2065 }
2066
2067 static u64 sys_reg_to_index(const struct sys_reg_desc *reg)
2068 {
2069         return (KVM_REG_ARM64 | KVM_REG_SIZE_U64 |
2070                 KVM_REG_ARM64_SYSREG |
2071                 (reg->Op0 << KVM_REG_ARM64_SYSREG_OP0_SHIFT) |
2072                 (reg->Op1 << KVM_REG_ARM64_SYSREG_OP1_SHIFT) |
2073                 (reg->CRn << KVM_REG_ARM64_SYSREG_CRN_SHIFT) |
2074                 (reg->CRm << KVM_REG_ARM64_SYSREG_CRM_SHIFT) |
2075                 (reg->Op2 << KVM_REG_ARM64_SYSREG_OP2_SHIFT));
2076 }
2077
2078 static bool copy_reg_to_user(const struct sys_reg_desc *reg, u64 __user **uind)
2079 {
2080         if (!*uind)
2081                 return true;
2082
2083         if (put_user(sys_reg_to_index(reg), *uind))
2084                 return false;
2085
2086         (*uind)++;
2087         return true;
2088 }
2089
2090 /* Assumed ordered tables, see kvm_sys_reg_table_init. */
2091 static int walk_sys_regs(struct kvm_vcpu *vcpu, u64 __user *uind)
2092 {
2093         const struct sys_reg_desc *i1, *i2, *end1, *end2;
2094         unsigned int total = 0;
2095         size_t num;
2096
2097         /* We check for duplicates here, to allow arch-specific overrides. */
2098         i1 = get_target_table(vcpu->arch.target, true, &num);
2099         end1 = i1 + num;
2100         i2 = sys_reg_descs;
2101         end2 = sys_reg_descs + ARRAY_SIZE(sys_reg_descs);
2102
2103         BUG_ON(i1 == end1 || i2 == end2);
2104
2105         /* Walk carefully, as both tables may refer to the same register. */
2106         while (i1 || i2) {
2107                 int cmp = cmp_sys_reg(i1, i2);
2108                 /* target-specific overrides generic entry. */
2109                 if (cmp <= 0) {
2110                         /* Ignore registers we trap but don't save. */
2111                         if (i1->reg) {
2112                                 if (!copy_reg_to_user(i1, &uind))
2113                                         return -EFAULT;
2114                                 total++;
2115                         }
2116                 } else {
2117                         /* Ignore registers we trap but don't save. */
2118                         if (i2->reg) {
2119                                 if (!copy_reg_to_user(i2, &uind))
2120                                         return -EFAULT;
2121                                 total++;
2122                         }
2123                 }
2124
2125                 if (cmp <= 0 && ++i1 == end1)
2126                         i1 = NULL;
2127                 if (cmp >= 0 && ++i2 == end2)
2128                         i2 = NULL;
2129         }
2130         return total;
2131 }
2132
2133 unsigned long kvm_arm_num_sys_reg_descs(struct kvm_vcpu *vcpu)
2134 {
2135         return ARRAY_SIZE(invariant_sys_regs)
2136                 + num_demux_regs()
2137                 + walk_sys_regs(vcpu, (u64 __user *)NULL);
2138 }
2139
2140 int kvm_arm_copy_sys_reg_indices(struct kvm_vcpu *vcpu, u64 __user *uindices)
2141 {
2142         unsigned int i;
2143         int err;
2144
2145         /* Then give them all the invariant registers' indices. */
2146         for (i = 0; i < ARRAY_SIZE(invariant_sys_regs); i++) {
2147                 if (put_user(sys_reg_to_index(&invariant_sys_regs[i]), uindices))
2148                         return -EFAULT;
2149                 uindices++;
2150         }
2151
2152         err = walk_sys_regs(vcpu, uindices);
2153         if (err < 0)
2154                 return err;
2155         uindices += err;
2156
2157         return write_demux_regids(uindices);
2158 }
2159
2160 static int check_sysreg_table(const struct sys_reg_desc *table, unsigned int n)
2161 {
2162         unsigned int i;
2163
2164         for (i = 1; i < n; i++) {
2165                 if (cmp_sys_reg(&table[i-1], &table[i]) >= 0) {
2166                         kvm_err("sys_reg table %p out of order (%d)\n", table, i - 1);
2167                         return 1;
2168                 }
2169         }
2170
2171         return 0;
2172 }
2173
2174 void kvm_sys_reg_table_init(void)
2175 {
2176         unsigned int i;
2177         struct sys_reg_desc clidr;
2178
2179         /* Make sure tables are unique and in order. */
2180         BUG_ON(check_sysreg_table(sys_reg_descs, ARRAY_SIZE(sys_reg_descs)));
2181         BUG_ON(check_sysreg_table(cp14_regs, ARRAY_SIZE(cp14_regs)));
2182         BUG_ON(check_sysreg_table(cp14_64_regs, ARRAY_SIZE(cp14_64_regs)));
2183         BUG_ON(check_sysreg_table(cp15_regs, ARRAY_SIZE(cp15_regs)));
2184         BUG_ON(check_sysreg_table(cp15_64_regs, ARRAY_SIZE(cp15_64_regs)));
2185         BUG_ON(check_sysreg_table(invariant_sys_regs, ARRAY_SIZE(invariant_sys_regs)));
2186
2187         /* We abuse the reset function to overwrite the table itself. */
2188         for (i = 0; i < ARRAY_SIZE(invariant_sys_regs); i++)
2189                 invariant_sys_regs[i].reset(NULL, &invariant_sys_regs[i]);
2190
2191         /*
2192          * CLIDR format is awkward, so clean it up.  See ARM B4.1.20:
2193          *
2194          *   If software reads the Cache Type fields from Ctype1
2195          *   upwards, once it has seen a value of 0b000, no caches
2196          *   exist at further-out levels of the hierarchy. So, for
2197          *   example, if Ctype3 is the first Cache Type field with a
2198          *   value of 0b000, the values of Ctype4 to Ctype7 must be
2199          *   ignored.
2200          */
2201         get_clidr_el1(NULL, &clidr); /* Ugly... */
2202         cache_levels = clidr.val;
2203         for (i = 0; i < 7; i++)
2204                 if (((cache_levels >> (i*3)) & 7) == 0)
2205                         break;
2206         /* Clear all higher bits. */
2207         cache_levels &= (1 << (i*3))-1;
2208 }
2209
2210 /**
2211  * kvm_reset_sys_regs - sets system registers to reset value
2212  * @vcpu: The VCPU pointer
2213  *
2214  * This function finds the right table above and sets the registers on the
2215  * virtual CPU struct to their architecturally defined reset values.
2216  */
2217 void kvm_reset_sys_regs(struct kvm_vcpu *vcpu)
2218 {
2219         size_t num;
2220         const struct sys_reg_desc *table;
2221
2222         /* Catch someone adding a register without putting in reset entry. */
2223         memset(&vcpu->arch.ctxt.sys_regs, 0x42, sizeof(vcpu->arch.ctxt.sys_regs));
2224
2225         /* Generic chip reset first (so target could override). */
2226         reset_sys_reg_descs(vcpu, sys_reg_descs, ARRAY_SIZE(sys_reg_descs));
2227
2228         table = get_target_table(vcpu->arch.target, true, &num);
2229         reset_sys_reg_descs(vcpu, table, num);
2230
2231         for (num = 1; num < NR_SYS_REGS; num++)
2232                 if (vcpu_sys_reg(vcpu, num) == 0x4242424242424242)
2233                         panic("Didn't reset vcpu_sys_reg(%zi)", num);
2234 }