arch/arm64/kvm/sys_regs.c

   1 /*
   2  * Copyright (C) 2012,2013 - ARM Ltd
   3  * Author: Marc Zyngier <marc.zyngier@arm.com>
   4  *
   5  * Derived from arch/arm/kvm/coproc.c:
   6  * Copyright (C) 2012 - Virtual Open Systems and Columbia University
   7  * Authors: Rusty Russell <rusty@rustcorp.com.au>
   8  *          Christoffer Dall <c.dall@virtualopensystems.com>
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License, version 2, as
  12  * published by the Free Software Foundation.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  21  */
  22
  23 #include <linux/bsearch.h>
  24 #include <linux/kvm_host.h>
  25 #include <linux/mm.h>
  26 #include <linux/uaccess.h>
  27
  28 #include <asm/cacheflush.h>
  29 #include <asm/cputype.h>
  30 #include <asm/debug-monitors.h>
  31 #include <asm/esr.h>
  32 #include <asm/kvm_arm.h>
  33 #include <asm/kvm_asm.h>
  34 #include <asm/kvm_coproc.h>
  35 #include <asm/kvm_emulate.h>
  36 #include <asm/kvm_host.h>
  37 #include <asm/kvm_mmu.h>
  38 #include <asm/perf_event.h>
  39 #include <asm/sysreg.h>
  40
  41 #include <trace/events/kvm.h>
  42
  43 #include "sys_regs.h"
  44
  45 #include "trace.h"
  46
  47 /*
  48  * All of this file is extremly similar to the ARM coproc.c, but the
  49  * types are different. My gut feeling is that it should be pretty
  50  * easy to merge, but that would be an ABI breakage -- again. VFP
  51  * would also need to be abstracted.
  52  *
  53  * For AArch32, we only take care of what is being trapped. Anything
  54  * that has to do with init and userspace access has to go via the
  55  * 64bit interface.
  56  */
  57
  58 /* 3 bits per cache level, as per CLIDR, but non-existent caches always 0 */
  59 static u32 cache_levels;
  60
  61 /* CSSELR values; used to index KVM_REG_ARM_DEMUX_ID_CCSIDR */
  62 #define CSSELR_MAX 12
  63
  64 /* Which cache CCSIDR represents depends on CSSELR value. */
  65 static u32 get_ccsidr(u32 csselr)
  66 {
  67         u32 ccsidr;
  68
  69         /* Make sure noone else changes CSSELR during this! */
  70         local_irq_disable();
  71         write_sysreg(csselr, csselr_el1);
  72         isb();
  73         ccsidr = read_sysreg(ccsidr_el1);
  74         local_irq_enable();
  75
  76         return ccsidr;
  77 }
  78
  79 /*
  80  * See note at ARMv7 ARM B1.14.4 (TL;DR: S/W ops are not easily virtualized).
  81  */
  82 static bool access_dcsw(struct kvm_vcpu *vcpu,
  83                         struct sys_reg_params *p,
  84                         const struct sys_reg_desc *r)
  85 {
  86         if (!p->is_write)
  87                 return read_from_write_only(vcpu, p);
  88
  89         kvm_set_way_flush(vcpu);
  90         return true;
  91 }
  92
  93 /*
  94  * Generic accessor for VM registers. Only called as long as HCR_TVM
  95  * is set. If the guest enables the MMU, we stop trapping the VM
  96  * sys_regs and leave it in complete control of the caches.
  97  */
  98 static bool access_vm_reg(struct kvm_vcpu *vcpu,
  99                           struct sys_reg_params *p,
 100                           const struct sys_reg_desc *r)
 101 {
 102         bool was_enabled = vcpu_has_cache_enabled(vcpu);
 103
 104         BUG_ON(!p->is_write);
 105
 106         if (!p->is_aarch32) {
 107                 vcpu_sys_reg(vcpu, r->reg) = p->regval;
 108         } else {
 109                 if (!p->is_32bit)
 110                         vcpu_cp15_64_high(vcpu, r->reg) = upper_32_bits(p->regval);
 111                 vcpu_cp15_64_low(vcpu, r->reg) = lower_32_bits(p->regval);
 112         }
 113
 114         kvm_toggle_cache(vcpu, was_enabled);
 115         return true;
 116 }
 117
 118 /*
 119  * Trap handler for the GICv3 SGI generation system register.
 120  * Forward the request to the VGIC emulation.
 121  * The cp15_64 code makes sure this automatically works
 122  * for both AArch64 and AArch32 accesses.
 123  */
 124 static bool access_gic_sgi(struct kvm_vcpu *vcpu,
 125                            struct sys_reg_params *p,
 126                            const struct sys_reg_desc *r)
 127 {
 128         if (!p->is_write)
 129                 return read_from_write_only(vcpu, p);
 130
 131         vgic_v3_dispatch_sgi(vcpu, p->regval);
 132
 133         return true;
 134 }
 135
 136 static bool access_gic_sre(struct kvm_vcpu *vcpu,
 137                            struct sys_reg_params *p,
 138                            const struct sys_reg_desc *r)
 139 {
 140         if (p->is_write)
 141                 return ignore_write(vcpu, p);
 142
 143         p->regval = vcpu->arch.vgic_cpu.vgic_v3.vgic_sre;
 144         return true;
 145 }
 146
 147 static bool trap_raz_wi(struct kvm_vcpu *vcpu,
 148                         struct sys_reg_params *p,
 149                         const struct sys_reg_desc *r)
 150 {
 151         if (p->is_write)
 152                 return ignore_write(vcpu, p);
 153         else
 154                 return read_zero(vcpu, p);
 155 }
 156
 157 static bool trap_oslsr_el1(struct kvm_vcpu *vcpu,
 158                            struct sys_reg_params *p,
 159                            const struct sys_reg_desc *r)
 160 {
 161         if (p->is_write) {
 162                 return ignore_write(vcpu, p);
 163         } else {
 164                 p->regval = (1 << 3);
 165                 return true;
 166         }
 167 }
 168
 169 static bool trap_dbgauthstatus_el1(struct kvm_vcpu *vcpu,
 170                                    struct sys_reg_params *p,
 171                                    const struct sys_reg_desc *r)
 172 {
 173         if (p->is_write) {
 174                 return ignore_write(vcpu, p);
 175         } else {
 176                 p->regval = read_sysreg(dbgauthstatus_el1);
 177                 return true;
 178         }
 179 }
 180
 181 /*
 182  * We want to avoid world-switching all the DBG registers all the
 183  * time:
 184  *
 185  * - If we've touched any debug register, it is likely that we're
 186  *   going to touch more of them. It then makes sense to disable the
 187  *   traps and start doing the save/restore dance
 188  * - If debug is active (DBG_MDSCR_KDE or DBG_MDSCR_MDE set), it is
 189  *   then mandatory to save/restore the registers, as the guest
 190  *   depends on them.
 191  *
 192  * For this, we use a DIRTY bit, indicating the guest has modified the
 193  * debug registers, used as follow:
 194  *
 195  * On guest entry:
 196  * - If the dirty bit is set (because we're coming back from trapping),
 197  *   disable the traps, save host registers, restore guest registers.
 198  * - If debug is actively in use (DBG_MDSCR_KDE or DBG_MDSCR_MDE set),
 199  *   set the dirty bit, disable the traps, save host registers,
 200  *   restore guest registers.
 201  * - Otherwise, enable the traps
 202  *
 203  * On guest exit:
 204  * - If the dirty bit is set, save guest registers, restore host
 205  *   registers and clear the dirty bit. This ensure that the host can
 206  *   now use the debug registers.
 207  */
 208 static bool trap_debug_regs(struct kvm_vcpu *vcpu,
 209                             struct sys_reg_params *p,
 210                             const struct sys_reg_desc *r)
 211 {
 212         if (p->is_write) {
 213                 vcpu_sys_reg(vcpu, r->reg) = p->regval;
 214                 vcpu->arch.debug_flags |= KVM_ARM64_DEBUG_DIRTY;
 215         } else {
 216                 p->regval = vcpu_sys_reg(vcpu, r->reg);
 217         }
 218
 219         trace_trap_reg(__func__, r->reg, p->is_write, p->regval);
 220
 221         return true;
 222 }
 223
 224 /*
 225  * reg_to_dbg/dbg_to_reg
 226  *
 227  * A 32 bit write to a debug register leave top bits alone
 228  * A 32 bit read from a debug register only returns the bottom bits
 229  *
 230  * All writes will set the KVM_ARM64_DEBUG_DIRTY flag to ensure the
 231  * hyp.S code switches between host and guest values in future.
 232  */
 233 static void reg_to_dbg(struct kvm_vcpu *vcpu,
 234                        struct sys_reg_params *p,
 235                        u64 *dbg_reg)
 236 {
 237         u64 val = p->regval;
 238
 239         if (p->is_32bit) {
 240                 val &= 0xffffffffUL;
 241                 val |= ((*dbg_reg >> 32) << 32);
 242         }
 243
 244         *dbg_reg = val;
 245         vcpu->arch.debug_flags |= KVM_ARM64_DEBUG_DIRTY;
 246 }
 247
 248 static void dbg_to_reg(struct kvm_vcpu *vcpu,
 249                        struct sys_reg_params *p,
 250                        u64 *dbg_reg)
 251 {
 252         p->regval = *dbg_reg;
 253         if (p->is_32bit)
 254                 p->regval &= 0xffffffffUL;
 255 }
 256
 257 static bool trap_bvr(struct kvm_vcpu *vcpu,
 258                      struct sys_reg_params *p,
 259                      const struct sys_reg_desc *rd)
 260 {
 261         u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_bvr[rd->reg];
 262
 263         if (p->is_write)
 264                 reg_to_dbg(vcpu, p, dbg_reg);
 265         else
 266                 dbg_to_reg(vcpu, p, dbg_reg);
 267
 268         trace_trap_reg(__func__, rd->reg, p->is_write, *dbg_reg);
 269
 270         return true;
 271 }
 272
 273 static int set_bvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
 274                 const struct kvm_one_reg *reg, void __user *uaddr)
 275 {
 276         __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_bvr[rd->reg];
 277
 278         if (copy_from_user(r, uaddr, KVM_REG_SIZE(reg->id)) != 0)
 279                 return -EFAULT;
 280         return 0;
 281 }
 282
 283 static int get_bvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
 284         const struct kvm_one_reg *reg, void __user *uaddr)
 285 {
 286         __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_bvr[rd->reg];
 287
 288         if (copy_to_user(uaddr, r, KVM_REG_SIZE(reg->id)) != 0)
 289                 return -EFAULT;
 290         return 0;
 291 }
 292
 293 static void reset_bvr(struct kvm_vcpu *vcpu,
 294                       const struct sys_reg_desc *rd)
 295 {
 296         vcpu->arch.vcpu_debug_state.dbg_bvr[rd->reg] = rd->val;
 297 }
 298
 299 static bool trap_bcr(struct kvm_vcpu *vcpu,
 300                      struct sys_reg_params *p,
 301                      const struct sys_reg_desc *rd)
 302 {
 303         u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_bcr[rd->reg];
 304
 305         if (p->is_write)
 306                 reg_to_dbg(vcpu, p, dbg_reg);
 307         else
 308                 dbg_to_reg(vcpu, p, dbg_reg);
 309
 310         trace_trap_reg(__func__, rd->reg, p->is_write, *dbg_reg);
 311
 312         return true;
 313 }
 314
 315 static int set_bcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
 316                 const struct kvm_one_reg *reg, void __user *uaddr)
 317 {
 318         __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_bcr[rd->reg];
 319
 320         if (copy_from_user(r, uaddr, KVM_REG_SIZE(reg->id)) != 0)
 321                 return -EFAULT;
 322
 323         return 0;
 324 }
 325
 326 static int get_bcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
 327         const struct kvm_one_reg *reg, void __user *uaddr)
 328 {
 329         __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_bcr[rd->reg];
 330
 331         if (copy_to_user(uaddr, r, KVM_REG_SIZE(reg->id)) != 0)
 332                 return -EFAULT;
 333         return 0;
 334 }
 335
 336 static void reset_bcr(struct kvm_vcpu *vcpu,
 337                       const struct sys_reg_desc *rd)
 338 {
 339         vcpu->arch.vcpu_debug_state.dbg_bcr[rd->reg] = rd->val;
 340 }
 341
 342 static bool trap_wvr(struct kvm_vcpu *vcpu,
 343                      struct sys_reg_params *p,
 344                      const struct sys_reg_desc *rd)
 345 {
 346         u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_wvr[rd->reg];
 347
 348         if (p->is_write)
 349                 reg_to_dbg(vcpu, p, dbg_reg);
 350         else
 351                 dbg_to_reg(vcpu, p, dbg_reg);
 352
 353         trace_trap_reg(__func__, rd->reg, p->is_write,
 354                 vcpu->arch.vcpu_debug_state.dbg_wvr[rd->reg]);
 355
 356         return true;
 357 }
 358
 359 static int set_wvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
 360                 const struct kvm_one_reg *reg, void __user *uaddr)
 361 {
 362         __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_wvr[rd->reg];
 363
 364         if (copy_from_user(r, uaddr, KVM_REG_SIZE(reg->id)) != 0)
 365                 return -EFAULT;
 366         return 0;
 367 }
 368
 369 static int get_wvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
 370         const struct kvm_one_reg *reg, void __user *uaddr)
 371 {
 372         __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_wvr[rd->reg];
 373
 374         if (copy_to_user(uaddr, r, KVM_REG_SIZE(reg->id)) != 0)
 375                 return -EFAULT;
 376         return 0;
 377 }
 378
 379 static void reset_wvr(struct kvm_vcpu *vcpu,
 380                       const struct sys_reg_desc *rd)
 381 {
 382         vcpu->arch.vcpu_debug_state.dbg_wvr[rd->reg] = rd->val;
 383 }
 384
 385 static bool trap_wcr(struct kvm_vcpu *vcpu,
 386                      struct sys_reg_params *p,
 387                      const struct sys_reg_desc *rd)
 388 {
 389         u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_wcr[rd->reg];
 390
 391         if (p->is_write)
 392                 reg_to_dbg(vcpu, p, dbg_reg);
 393         else
 394                 dbg_to_reg(vcpu, p, dbg_reg);
 395
 396         trace_trap_reg(__func__, rd->reg, p->is_write, *dbg_reg);
 397
 398         return true;
 399 }
 400
 401 static int set_wcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
 402                 const struct kvm_one_reg *reg, void __user *uaddr)
 403 {
 404         __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_wcr[rd->reg];
 405
 406         if (copy_from_user(r, uaddr, KVM_REG_SIZE(reg->id)) != 0)
 407                 return -EFAULT;
 408         return 0;
 409 }
 410
 411 static int get_wcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
 412         const struct kvm_one_reg *reg, void __user *uaddr)
 413 {
 414         __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_wcr[rd->reg];
 415
 416         if (copy_to_user(uaddr, r, KVM_REG_SIZE(reg->id)) != 0)
 417                 return -EFAULT;
 418         return 0;
 419 }
 420
 421 static void reset_wcr(struct kvm_vcpu *vcpu,
 422                       const struct sys_reg_desc *rd)
 423 {
 424         vcpu->arch.vcpu_debug_state.dbg_wcr[rd->reg] = rd->val;
 425 }
 426
 427 static void reset_amair_el1(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
 428 {
 429         vcpu_sys_reg(vcpu, AMAIR_EL1) = read_sysreg(amair_el1);
 430 }
 431
 432 static void reset_mpidr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
 433 {
 434         u64 mpidr;
 435
 436         /*
 437          * Map the vcpu_id into the first three affinity level fields of
 438          * the MPIDR. We limit the number of VCPUs in level 0 due to a
 439          * limitation to 16 CPUs in that level in the ICC_SGIxR registers
 440          * of the GICv3 to be able to address each CPU directly when
 441          * sending IPIs.
 442          */
 443         mpidr = (vcpu->vcpu_id & 0x0f) << MPIDR_LEVEL_SHIFT(0);
 444         mpidr |= ((vcpu->vcpu_id >> 4) & 0xff) << MPIDR_LEVEL_SHIFT(1);
 445         mpidr |= ((vcpu->vcpu_id >> 12) & 0xff) << MPIDR_LEVEL_SHIFT(2);
 446         vcpu_sys_reg(vcpu, MPIDR_EL1) = (1ULL << 31) | mpidr;
 447 }
 448
 449 static void reset_pmcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
 450 {
 451         u64 pmcr, val;
 452
 453         /* No PMU available, PMCR_EL0 may UNDEF... */
 454         if (!kvm_arm_support_pmu_v3())
 455                 return;
 456
 457         pmcr = read_sysreg(pmcr_el0);
 458         /*
 459          * Writable bits of PMCR_EL0 (ARMV8_PMU_PMCR_MASK) are reset to UNKNOWN
 460          * except PMCR.E resetting to zero.
 461          */
 462         val = ((pmcr & ~ARMV8_PMU_PMCR_MASK)
 463                | (ARMV8_PMU_PMCR_MASK & 0xdecafbad)) & (~ARMV8_PMU_PMCR_E);
 464         vcpu_sys_reg(vcpu, PMCR_EL0) = val;
 465 }
 466
 467 static bool pmu_access_el0_disabled(struct kvm_vcpu *vcpu)
 468 {
 469         u64 reg = vcpu_sys_reg(vcpu, PMUSERENR_EL0);
 470
 471         return !((reg & ARMV8_PMU_USERENR_EN) || vcpu_mode_priv(vcpu));
 472 }
 473
 474 static bool pmu_write_swinc_el0_disabled(struct kvm_vcpu *vcpu)
 475 {
 476         u64 reg = vcpu_sys_reg(vcpu, PMUSERENR_EL0);
 477
 478         return !((reg & (ARMV8_PMU_USERENR_SW | ARMV8_PMU_USERENR_EN))
 479                  || vcpu_mode_priv(vcpu));
 480 }
 481
 482 static bool pmu_access_cycle_counter_el0_disabled(struct kvm_vcpu *vcpu)
 483 {
 484         u64 reg = vcpu_sys_reg(vcpu, PMUSERENR_EL0);
 485
 486         return !((reg & (ARMV8_PMU_USERENR_CR | ARMV8_PMU_USERENR_EN))
 487                  || vcpu_mode_priv(vcpu));
 488 }
 489
 490 static bool pmu_access_event_counter_el0_disabled(struct kvm_vcpu *vcpu)
 491 {
 492         u64 reg = vcpu_sys_reg(vcpu, PMUSERENR_EL0);
 493
 494         return !((reg & (ARMV8_PMU_USERENR_ER | ARMV8_PMU_USERENR_EN))
 495                  || vcpu_mode_priv(vcpu));
 496 }
 497
 498 static bool access_pmcr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
 499                         const struct sys_reg_desc *r)
 500 {
 501         u64 val;
 502
 503         if (!kvm_arm_pmu_v3_ready(vcpu))
 504                 return trap_raz_wi(vcpu, p, r);
 505
 506         if (pmu_access_el0_disabled(vcpu))
 507                 return false;
 508
 509         if (p->is_write) {
 510                 /* Only update writeable bits of PMCR */
 511                 val = vcpu_sys_reg(vcpu, PMCR_EL0);
 512                 val &= ~ARMV8_PMU_PMCR_MASK;
 513                 val |= p->regval & ARMV8_PMU_PMCR_MASK;
 514                 vcpu_sys_reg(vcpu, PMCR_EL0) = val;
 515                 kvm_pmu_handle_pmcr(vcpu, val);
 516         } else {
 517                 /* PMCR.P & PMCR.C are RAZ */
 518                 val = vcpu_sys_reg(vcpu, PMCR_EL0)
 519                       & ~(ARMV8_PMU_PMCR_P | ARMV8_PMU_PMCR_C);
 520                 p->regval = val;
 521         }
 522
 523         return true;
 524 }
 525
 526 static bool access_pmselr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
 527                           const struct sys_reg_desc *r)
 528 {
 529         if (!kvm_arm_pmu_v3_ready(vcpu))
 530                 return trap_raz_wi(vcpu, p, r);
 531
 532         if (pmu_access_event_counter_el0_disabled(vcpu))
 533                 return false;
 534
 535         if (p->is_write)
 536                 vcpu_sys_reg(vcpu, PMSELR_EL0) = p->regval;
 537         else
 538                 /* return PMSELR.SEL field */
 539                 p->regval = vcpu_sys_reg(vcpu, PMSELR_EL0)
 540                             & ARMV8_PMU_COUNTER_MASK;
 541
 542         return true;
 543 }
 544
 545 static bool access_pmceid(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
 546                           const struct sys_reg_desc *r)
 547 {
 548         u64 pmceid;
 549
 550         if (!kvm_arm_pmu_v3_ready(vcpu))
 551                 return trap_raz_wi(vcpu, p, r);
 552
 553         BUG_ON(p->is_write);
 554
 555         if (pmu_access_el0_disabled(vcpu))
 556                 return false;
 557
 558         if (!(p->Op2 & 1))
 559                 pmceid = read_sysreg(pmceid0_el0);
 560         else
 561                 pmceid = read_sysreg(pmceid1_el0);
 562
 563         p->regval = pmceid;
 564
 565         return true;
 566 }
 567
 568 static bool pmu_counter_idx_valid(struct kvm_vcpu *vcpu, u64 idx)
 569 {
 570         u64 pmcr, val;
 571
 572         pmcr = vcpu_sys_reg(vcpu, PMCR_EL0);
 573         val = (pmcr >> ARMV8_PMU_PMCR_N_SHIFT) & ARMV8_PMU_PMCR_N_MASK;
 574         if (idx >= val && idx != ARMV8_PMU_CYCLE_IDX)
 575                 return false;
 576
 577         return true;
 578 }
 579
 580 static bool access_pmu_evcntr(struct kvm_vcpu *vcpu,
 581                               struct sys_reg_params *p,
 582                               const struct sys_reg_desc *r)
 583 {
 584         u64 idx;
 585
 586         if (!kvm_arm_pmu_v3_ready(vcpu))
 587                 return trap_raz_wi(vcpu, p, r);
 588
 589         if (r->CRn == 9 && r->CRm == 13) {
 590                 if (r->Op2 == 2) {
 591                         /* PMXEVCNTR_EL0 */
 592                         if (pmu_access_event_counter_el0_disabled(vcpu))
 593                                 return false;
 594
 595                         idx = vcpu_sys_reg(vcpu, PMSELR_EL0)
 596                               & ARMV8_PMU_COUNTER_MASK;
 597                 } else if (r->Op2 == 0) {
 598                         /* PMCCNTR_EL0 */
 599                         if (pmu_access_cycle_counter_el0_disabled(vcpu))
 600                                 return false;
 601
 602                         idx = ARMV8_PMU_CYCLE_IDX;
 603                 } else {
 604                         return false;
 605                 }
 606         } else if (r->CRn == 0 && r->CRm == 9) {
 607                 /* PMCCNTR */
 608                 if (pmu_access_event_counter_el0_disabled(vcpu))
 609                         return false;
 610
 611                 idx = ARMV8_PMU_CYCLE_IDX;
 612         } else if (r->CRn == 14 && (r->CRm & 12) == 8) {
 613                 /* PMEVCNTRn_EL0 */
 614                 if (pmu_access_event_counter_el0_disabled(vcpu))
 615                         return false;
 616
 617                 idx = ((r->CRm & 3) << 3) | (r->Op2 & 7);
 618         } else {
 619                 return false;
 620         }
 621
 622         if (!pmu_counter_idx_valid(vcpu, idx))
 623                 return false;
 624
 625         if (p->is_write) {
 626                 if (pmu_access_el0_disabled(vcpu))
 627                         return false;
 628
 629                 kvm_pmu_set_counter_value(vcpu, idx, p->regval);
 630         } else {
 631                 p->regval = kvm_pmu_get_counter_value(vcpu, idx);
 632         }
 633
 634         return true;
 635 }
 636
 637 static bool access_pmu_evtyper(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
 638                                const struct sys_reg_desc *r)
 639 {
 640         u64 idx, reg;
 641
 642         if (!kvm_arm_pmu_v3_ready(vcpu))
 643                 return trap_raz_wi(vcpu, p, r);
 644
 645         if (pmu_access_el0_disabled(vcpu))
 646                 return false;
 647
 648         if (r->CRn == 9 && r->CRm == 13 && r->Op2 == 1) {
 649                 /* PMXEVTYPER_EL0 */
 650                 idx = vcpu_sys_reg(vcpu, PMSELR_EL0) & ARMV8_PMU_COUNTER_MASK;
 651                 reg = PMEVTYPER0_EL0 + idx;
 652         } else if (r->CRn == 14 && (r->CRm & 12) == 12) {
 653                 idx = ((r->CRm & 3) << 3) | (r->Op2 & 7);
 654                 if (idx == ARMV8_PMU_CYCLE_IDX)
 655                         reg = PMCCFILTR_EL0;
 656                 else
 657                         /* PMEVTYPERn_EL0 */
 658                         reg = PMEVTYPER0_EL0 + idx;
 659         } else {
 660                 BUG();
 661         }
 662
 663         if (!pmu_counter_idx_valid(vcpu, idx))
 664                 return false;
 665
 666         if (p->is_write) {
 667                 kvm_pmu_set_counter_event_type(vcpu, p->regval, idx);
 668                 vcpu_sys_reg(vcpu, reg) = p->regval & ARMV8_PMU_EVTYPE_MASK;
 669         } else {
 670                 p->regval = vcpu_sys_reg(vcpu, reg) & ARMV8_PMU_EVTYPE_MASK;
 671         }
 672
 673         return true;
 674 }
 675
 676 static bool access_pmcnten(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
 677                            const struct sys_reg_desc *r)
 678 {
 679         u64 val, mask;
 680
 681         if (!kvm_arm_pmu_v3_ready(vcpu))
 682                 return trap_raz_wi(vcpu, p, r);
 683
 684         if (pmu_access_el0_disabled(vcpu))
 685                 return false;
 686
 687         mask = kvm_pmu_valid_counter_mask(vcpu);
 688         if (p->is_write) {
 689                 val = p->regval & mask;
 690                 if (r->Op2 & 0x1) {
 691                         /* accessing PMCNTENSET_EL0 */
 692                         vcpu_sys_reg(vcpu, PMCNTENSET_EL0) |= val;
 693                         kvm_pmu_enable_counter(vcpu, val);
 694                 } else {
 695                         /* accessing PMCNTENCLR_EL0 */
 696                         vcpu_sys_reg(vcpu, PMCNTENSET_EL0) &= ~val;
 697                         kvm_pmu_disable_counter(vcpu, val);
 698                 }
 699         } else {
 700                 p->regval = vcpu_sys_reg(vcpu, PMCNTENSET_EL0) & mask;
 701         }
 702
 703         return true;
 704 }
 705
 706 static bool access_pminten(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
 707                            const struct sys_reg_desc *r)
 708 {
 709         u64 mask = kvm_pmu_valid_counter_mask(vcpu);
 710
 711         if (!kvm_arm_pmu_v3_ready(vcpu))
 712                 return trap_raz_wi(vcpu, p, r);
 713
 714         if (!vcpu_mode_priv(vcpu))
 715                 return false;
 716
 717         if (p->is_write) {
 718                 u64 val = p->regval & mask;
 719
 720                 if (r->Op2 & 0x1)
 721                         /* accessing PMINTENSET_EL1 */
 722                         vcpu_sys_reg(vcpu, PMINTENSET_EL1) |= val;
 723                 else
 724                         /* accessing PMINTENCLR_EL1 */
 725                         vcpu_sys_reg(vcpu, PMINTENSET_EL1) &= ~val;
 726         } else {
 727                 p->regval = vcpu_sys_reg(vcpu, PMINTENSET_EL1) & mask;
 728         }
 729
 730         return true;
 731 }
 732
 733 static bool access_pmovs(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
 734                          const struct sys_reg_desc *r)
 735 {
 736         u64 mask = kvm_pmu_valid_counter_mask(vcpu);
 737
 738         if (!kvm_arm_pmu_v3_ready(vcpu))
 739                 return trap_raz_wi(vcpu, p, r);
 740
 741         if (pmu_access_el0_disabled(vcpu))
 742                 return false;
 743
 744         if (p->is_write) {
 745                 if (r->CRm & 0x2)
 746                         /* accessing PMOVSSET_EL0 */
 747                         kvm_pmu_overflow_set(vcpu, p->regval & mask);
 748                 else
 749                         /* accessing PMOVSCLR_EL0 */
 750                         vcpu_sys_reg(vcpu, PMOVSSET_EL0) &= ~(p->regval & mask);
 751         } else {
 752                 p->regval = vcpu_sys_reg(vcpu, PMOVSSET_EL0) & mask;
 753         }
 754
 755         return true;
 756 }
 757
 758 static bool access_pmswinc(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
 759                            const struct sys_reg_desc *r)
 760 {
 761         u64 mask;
 762
 763         if (!kvm_arm_pmu_v3_ready(vcpu))
 764                 return trap_raz_wi(vcpu, p, r);
 765
 766         if (pmu_write_swinc_el0_disabled(vcpu))
 767                 return false;
 768
 769         if (p->is_write) {
 770                 mask = kvm_pmu_valid_counter_mask(vcpu);
 771                 kvm_pmu_software_increment(vcpu, p->regval & mask);
 772                 return true;
 773         }
 774
 775         return false;
 776 }
 777
 778 static bool access_pmuserenr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
 779                              const struct sys_reg_desc *r)
 780 {
 781         if (!kvm_arm_pmu_v3_ready(vcpu))
 782                 return trap_raz_wi(vcpu, p, r);
 783
 784         if (p->is_write) {
 785                 if (!vcpu_mode_priv(vcpu))
 786                         return false;
 787
 788                 vcpu_sys_reg(vcpu, PMUSERENR_EL0) = p->regval
 789                                                     & ARMV8_PMU_USERENR_MASK;
 790         } else {
 791                 p->regval = vcpu_sys_reg(vcpu, PMUSERENR_EL0)
 792                             & ARMV8_PMU_USERENR_MASK;
 793         }
 794
 795         return true;
 796 }
 797
 798 /* Silly macro to expand the DBG{BCR,BVR,WVR,WCR}n_EL1 registers in one go */
 799 #define DBG_BCR_BVR_WCR_WVR_EL1(n)                                      \
 800         /* DBGBVRn_EL1 */                                               \
 801         { Op0(0b10), Op1(0b000), CRn(0b0000), CRm((n)), Op2(0b100),     \
 802           trap_bvr, reset_bvr, n, 0, get_bvr, set_bvr },                \
 803         /* DBGBCRn_EL1 */                                               \
 804         { Op0(0b10), Op1(0b000), CRn(0b0000), CRm((n)), Op2(0b101),     \
 805           trap_bcr, reset_bcr, n, 0, get_bcr, set_bcr },                \
 806         /* DBGWVRn_EL1 */                                               \
 807         { Op0(0b10), Op1(0b000), CRn(0b0000), CRm((n)), Op2(0b110),     \
 808           trap_wvr, reset_wvr, n, 0,  get_wvr, set_wvr },               \
 809         /* DBGWCRn_EL1 */                                               \
 810         { Op0(0b10), Op1(0b000), CRn(0b0000), CRm((n)), Op2(0b111),     \
 811           trap_wcr, reset_wcr, n, 0,  get_wcr, set_wcr }
 812
 813 /* Macro to expand the PMEVCNTRn_EL0 register */
 814 #define PMU_PMEVCNTR_EL0(n)                                             \
 815         /* PMEVCNTRn_EL0 */                                             \
 816         { Op0(0b11), Op1(0b011), CRn(0b1110),                           \
 817           CRm((0b1000 | (((n) >> 3) & 0x3))), Op2(((n) & 0x7)),         \
 818           access_pmu_evcntr, reset_unknown, (PMEVCNTR0_EL0 + n), }
 819
 820 /* Macro to expand the PMEVTYPERn_EL0 register */
 821 #define PMU_PMEVTYPER_EL0(n)                                            \
 822         /* PMEVTYPERn_EL0 */                                            \
 823         { Op0(0b11), Op1(0b011), CRn(0b1110),                           \
 824           CRm((0b1100 | (((n) >> 3) & 0x3))), Op2(((n) & 0x7)),         \
 825           access_pmu_evtyper, reset_unknown, (PMEVTYPER0_EL0 + n), }
 826
 827 /*
 828  * Architected system registers.
 829  * Important: Must be sorted ascending by Op0, Op1, CRn, CRm, Op2
 830  *
 831  * Debug handling: We do trap most, if not all debug related system
 832  * registers. The implementation is good enough to ensure that a guest
 833  * can use these with minimal performance degradation. The drawback is
 834  * that we don't implement any of the external debug, none of the
 835  * OSlock protocol. This should be revisited if we ever encounter a
 836  * more demanding guest...
 837  */
 838 static const struct sys_reg_desc sys_reg_descs[] = {
 839         /* DC ISW */
 840         { Op0(0b01), Op1(0b000), CRn(0b0111), CRm(0b0110), Op2(0b010),
 841           access_dcsw },
 842         /* DC CSW */
 843         { Op0(0b01), Op1(0b000), CRn(0b0111), CRm(0b1010), Op2(0b010),
 844           access_dcsw },
 845         /* DC CISW */
 846         { Op0(0b01), Op1(0b000), CRn(0b0111), CRm(0b1110), Op2(0b010),
 847           access_dcsw },
 848
 849         DBG_BCR_BVR_WCR_WVR_EL1(0),
 850         DBG_BCR_BVR_WCR_WVR_EL1(1),
 851         /* MDCCINT_EL1 */
 852         { Op0(0b10), Op1(0b000), CRn(0b0000), CRm(0b0010), Op2(0b000),
 853           trap_debug_regs, reset_val, MDCCINT_EL1, 0 },
 854         /* MDSCR_EL1 */
 855         { Op0(0b10), Op1(0b000), CRn(0b0000), CRm(0b0010), Op2(0b010),
 856           trap_debug_regs, reset_val, MDSCR_EL1, 0 },
 857         DBG_BCR_BVR_WCR_WVR_EL1(2),
 858         DBG_BCR_BVR_WCR_WVR_EL1(3),
 859         DBG_BCR_BVR_WCR_WVR_EL1(4),
 860         DBG_BCR_BVR_WCR_WVR_EL1(5),
 861         DBG_BCR_BVR_WCR_WVR_EL1(6),
 862         DBG_BCR_BVR_WCR_WVR_EL1(7),
 863         DBG_BCR_BVR_WCR_WVR_EL1(8),
 864         DBG_BCR_BVR_WCR_WVR_EL1(9),
 865         DBG_BCR_BVR_WCR_WVR_EL1(10),
 866         DBG_BCR_BVR_WCR_WVR_EL1(11),
 867         DBG_BCR_BVR_WCR_WVR_EL1(12),
 868         DBG_BCR_BVR_WCR_WVR_EL1(13),
 869         DBG_BCR_BVR_WCR_WVR_EL1(14),
 870         DBG_BCR_BVR_WCR_WVR_EL1(15),
 871
 872         /* MDRAR_EL1 */
 873         { Op0(0b10), Op1(0b000), CRn(0b0001), CRm(0b0000), Op2(0b000),
 874           trap_raz_wi },
 875         /* OSLAR_EL1 */
 876         { Op0(0b10), Op1(0b000), CRn(0b0001), CRm(0b0000), Op2(0b100),
 877           trap_raz_wi },
 878         /* OSLSR_EL1 */
 879         { Op0(0b10), Op1(0b000), CRn(0b0001), CRm(0b0001), Op2(0b100),
 880           trap_oslsr_el1 },
 881         /* OSDLR_EL1 */
 882         { Op0(0b10), Op1(0b000), CRn(0b0001), CRm(0b0011), Op2(0b100),
 883           trap_raz_wi },
 884         /* DBGPRCR_EL1 */
 885         { Op0(0b10), Op1(0b000), CRn(0b0001), CRm(0b0100), Op2(0b100),
 886           trap_raz_wi },
 887         /* DBGCLAIMSET_EL1 */
 888         { Op0(0b10), Op1(0b000), CRn(0b0111), CRm(0b1000), Op2(0b110),
 889           trap_raz_wi },
 890         /* DBGCLAIMCLR_EL1 */
 891         { Op0(0b10), Op1(0b000), CRn(0b0111), CRm(0b1001), Op2(0b110),
 892           trap_raz_wi },
 893         /* DBGAUTHSTATUS_EL1 */
 894         { Op0(0b10), Op1(0b000), CRn(0b0111), CRm(0b1110), Op2(0b110),
 895           trap_dbgauthstatus_el1 },
 896
 897         /* MDCCSR_EL1 */
 898         { Op0(0b10), Op1(0b011), CRn(0b0000), CRm(0b0001), Op2(0b000),
 899           trap_raz_wi },
 900         /* DBGDTR_EL0 */
 901         { Op0(0b10), Op1(0b011), CRn(0b0000), CRm(0b0100), Op2(0b000),
 902           trap_raz_wi },
 903         /* DBGDTR[TR]X_EL0 */
 904         { Op0(0b10), Op1(0b011), CRn(0b0000), CRm(0b0101), Op2(0b000),
 905           trap_raz_wi },
 906
 907         /* DBGVCR32_EL2 */
 908         { Op0(0b10), Op1(0b100), CRn(0b0000), CRm(0b0111), Op2(0b000),
 909           NULL, reset_val, DBGVCR32_EL2, 0 },
 910
 911         /* MPIDR_EL1 */
 912         { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0000), Op2(0b101),
 913           NULL, reset_mpidr, MPIDR_EL1 },
 914         /* SCTLR_EL1 */
 915         { Op0(0b11), Op1(0b000), CRn(0b0001), CRm(0b0000), Op2(0b000),
 916           access_vm_reg, reset_val, SCTLR_EL1, 0x00C50078 },
 917         /* CPACR_EL1 */
 918         { Op0(0b11), Op1(0b000), CRn(0b0001), CRm(0b0000), Op2(0b010),
 919           NULL, reset_val, CPACR_EL1, 0 },
 920         /* TTBR0_EL1 */
 921         { Op0(0b11), Op1(0b000), CRn(0b0010), CRm(0b0000), Op2(0b000),
 922           access_vm_reg, reset_unknown, TTBR0_EL1 },
 923         /* TTBR1_EL1 */
 924         { Op0(0b11), Op1(0b000), CRn(0b0010), CRm(0b0000), Op2(0b001),
 925           access_vm_reg, reset_unknown, TTBR1_EL1 },
 926         /* TCR_EL1 */
 927         { Op0(0b11), Op1(0b000), CRn(0b0010), CRm(0b0000), Op2(0b010),
 928           access_vm_reg, reset_val, TCR_EL1, 0 },
 929
 930         /* AFSR0_EL1 */
 931         { Op0(0b11), Op1(0b000), CRn(0b0101), CRm(0b0001), Op2(0b000),
 932           access_vm_reg, reset_unknown, AFSR0_EL1 },
 933         /* AFSR1_EL1 */
 934         { Op0(0b11), Op1(0b000), CRn(0b0101), CRm(0b0001), Op2(0b001),
 935           access_vm_reg, reset_unknown, AFSR1_EL1 },
 936         /* ESR_EL1 */
 937         { Op0(0b11), Op1(0b000), CRn(0b0101), CRm(0b0010), Op2(0b000),
 938           access_vm_reg, reset_unknown, ESR_EL1 },
 939         /* FAR_EL1 */
 940         { Op0(0b11), Op1(0b000), CRn(0b0110), CRm(0b0000), Op2(0b000),
 941           access_vm_reg, reset_unknown, FAR_EL1 },
 942         /* PAR_EL1 */
 943         { Op0(0b11), Op1(0b000), CRn(0b0111), CRm(0b0100), Op2(0b000),
 944           NULL, reset_unknown, PAR_EL1 },
 945
 946         /* PMINTENSET_EL1 */
 947         { Op0(0b11), Op1(0b000), CRn(0b1001), CRm(0b1110), Op2(0b001),
 948           access_pminten, reset_unknown, PMINTENSET_EL1 },
 949         /* PMINTENCLR_EL1 */
 950         { Op0(0b11), Op1(0b000), CRn(0b1001), CRm(0b1110), Op2(0b010),
 951           access_pminten, NULL, PMINTENSET_EL1 },
 952
 953         /* MAIR_EL1 */
 954         { Op0(0b11), Op1(0b000), CRn(0b1010), CRm(0b0010), Op2(0b000),
 955           access_vm_reg, reset_unknown, MAIR_EL1 },
 956         /* AMAIR_EL1 */
 957         { Op0(0b11), Op1(0b000), CRn(0b1010), CRm(0b0011), Op2(0b000),
 958           access_vm_reg, reset_amair_el1, AMAIR_EL1 },
 959
 960         /* VBAR_EL1 */
 961         { Op0(0b11), Op1(0b000), CRn(0b1100), CRm(0b0000), Op2(0b000),
 962           NULL, reset_val, VBAR_EL1, 0 },
 963
 964         /* ICC_SGI1R_EL1 */
 965         { Op0(0b11), Op1(0b000), CRn(0b1100), CRm(0b1011), Op2(0b101),
 966           access_gic_sgi },
 967         /* ICC_SRE_EL1 */
 968         { Op0(0b11), Op1(0b000), CRn(0b1100), CRm(0b1100), Op2(0b101),
 969           access_gic_sre },
 970
 971         /* CONTEXTIDR_EL1 */
 972         { Op0(0b11), Op1(0b000), CRn(0b1101), CRm(0b0000), Op2(0b001),
 973           access_vm_reg, reset_val, CONTEXTIDR_EL1, 0 },
 974         /* TPIDR_EL1 */
 975         { Op0(0b11), Op1(0b000), CRn(0b1101), CRm(0b0000), Op2(0b100),
 976           NULL, reset_unknown, TPIDR_EL1 },
 977
 978         /* CNTKCTL_EL1 */
 979         { Op0(0b11), Op1(0b000), CRn(0b1110), CRm(0b0001), Op2(0b000),
 980           NULL, reset_val, CNTKCTL_EL1, 0},
 981
 982         /* CSSELR_EL1 */
 983         { Op0(0b11), Op1(0b010), CRn(0b0000), CRm(0b0000), Op2(0b000),
 984           NULL, reset_unknown, CSSELR_EL1 },
 985
 986         /* PMCR_EL0 */
 987         { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b000),
 988           access_pmcr, reset_pmcr, },
 989         /* PMCNTENSET_EL0 */
 990         { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b001),
 991           access_pmcnten, reset_unknown, PMCNTENSET_EL0 },
 992         /* PMCNTENCLR_EL0 */
 993         { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b010),
 994           access_pmcnten, NULL, PMCNTENSET_EL0 },
 995         /* PMOVSCLR_EL0 */
 996         { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b011),
 997           access_pmovs, NULL, PMOVSSET_EL0 },
 998         /* PMSWINC_EL0 */
 999         { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b100),
1000           access_pmswinc, reset_unknown, PMSWINC_EL0 },
1001         /* PMSELR_EL0 */
1002         { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b101),
1003           access_pmselr, reset_unknown, PMSELR_EL0 },
1004         /* PMCEID0_EL0 */
1005         { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b110),
1006           access_pmceid },
1007         /* PMCEID1_EL0 */
1008         { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b111),
1009           access_pmceid },
1010         /* PMCCNTR_EL0 */
1011         { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1101), Op2(0b000),
1012           access_pmu_evcntr, reset_unknown, PMCCNTR_EL0 },
1013         /* PMXEVTYPER_EL0 */
1014         { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1101), Op2(0b001),
1015           access_pmu_evtyper },
1016         /* PMXEVCNTR_EL0 */
1017         { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1101), Op2(0b010),
1018           access_pmu_evcntr },
1019         /* PMUSERENR_EL0
1020          * This register resets as unknown in 64bit mode while it resets as zero
1021          * in 32bit mode. Here we choose to reset it as zero for consistency.
1022          */
1023         { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1110), Op2(0b000),
1024           access_pmuserenr, reset_val, PMUSERENR_EL0, 0 },
1025         /* PMOVSSET_EL0 */
1026         { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1110), Op2(0b011),
1027           access_pmovs, reset_unknown, PMOVSSET_EL0 },
1028
1029         /* TPIDR_EL0 */
1030         { Op0(0b11), Op1(0b011), CRn(0b1101), CRm(0b0000), Op2(0b010),
1031           NULL, reset_unknown, TPIDR_EL0 },
1032         /* TPIDRRO_EL0 */
1033         { Op0(0b11), Op1(0b011), CRn(0b1101), CRm(0b0000), Op2(0b011),
1034           NULL, reset_unknown, TPIDRRO_EL0 },
1035
1036         /* PMEVCNTRn_EL0 */
1037         PMU_PMEVCNTR_EL0(0),
1038         PMU_PMEVCNTR_EL0(1),
1039         PMU_PMEVCNTR_EL0(2),
1040         PMU_PMEVCNTR_EL0(3),
1041         PMU_PMEVCNTR_EL0(4),
1042         PMU_PMEVCNTR_EL0(5),
1043         PMU_PMEVCNTR_EL0(6),
1044         PMU_PMEVCNTR_EL0(7),
1045         PMU_PMEVCNTR_EL0(8),
1046         PMU_PMEVCNTR_EL0(9),
1047         PMU_PMEVCNTR_EL0(10),
1048         PMU_PMEVCNTR_EL0(11),
1049         PMU_PMEVCNTR_EL0(12),
1050         PMU_PMEVCNTR_EL0(13),
1051         PMU_PMEVCNTR_EL0(14),
1052         PMU_PMEVCNTR_EL0(15),
1053         PMU_PMEVCNTR_EL0(16),
1054         PMU_PMEVCNTR_EL0(17),
1055         PMU_PMEVCNTR_EL0(18),
1056         PMU_PMEVCNTR_EL0(19),
1057         PMU_PMEVCNTR_EL0(20),
1058         PMU_PMEVCNTR_EL0(21),
1059         PMU_PMEVCNTR_EL0(22),
1060         PMU_PMEVCNTR_EL0(23),
1061         PMU_PMEVCNTR_EL0(24),
1062         PMU_PMEVCNTR_EL0(25),
1063         PMU_PMEVCNTR_EL0(26),
1064         PMU_PMEVCNTR_EL0(27),
1065         PMU_PMEVCNTR_EL0(28),
1066         PMU_PMEVCNTR_EL0(29),
1067         PMU_PMEVCNTR_EL0(30),
1068         /* PMEVTYPERn_EL0 */
1069         PMU_PMEVTYPER_EL0(0),
1070         PMU_PMEVTYPER_EL0(1),
1071         PMU_PMEVTYPER_EL0(2),
1072         PMU_PMEVTYPER_EL0(3),
1073         PMU_PMEVTYPER_EL0(4),
1074         PMU_PMEVTYPER_EL0(5),
1075         PMU_PMEVTYPER_EL0(6),
1076         PMU_PMEVTYPER_EL0(7),
1077         PMU_PMEVTYPER_EL0(8),
1078         PMU_PMEVTYPER_EL0(9),
1079         PMU_PMEVTYPER_EL0(10),
1080         PMU_PMEVTYPER_EL0(11),
1081         PMU_PMEVTYPER_EL0(12),
1082         PMU_PMEVTYPER_EL0(13),
1083         PMU_PMEVTYPER_EL0(14),
1084         PMU_PMEVTYPER_EL0(15),
1085         PMU_PMEVTYPER_EL0(16),
1086         PMU_PMEVTYPER_EL0(17),
1087         PMU_PMEVTYPER_EL0(18),
1088         PMU_PMEVTYPER_EL0(19),
1089         PMU_PMEVTYPER_EL0(20),
1090         PMU_PMEVTYPER_EL0(21),
1091         PMU_PMEVTYPER_EL0(22),
1092         PMU_PMEVTYPER_EL0(23),
1093         PMU_PMEVTYPER_EL0(24),
1094         PMU_PMEVTYPER_EL0(25),
1095         PMU_PMEVTYPER_EL0(26),
1096         PMU_PMEVTYPER_EL0(27),
1097         PMU_PMEVTYPER_EL0(28),
1098         PMU_PMEVTYPER_EL0(29),
1099         PMU_PMEVTYPER_EL0(30),
1100         /* PMCCFILTR_EL0
1101          * This register resets as unknown in 64bit mode while it resets as zero
1102          * in 32bit mode. Here we choose to reset it as zero for consistency.
1103          */
1104         { Op0(0b11), Op1(0b011), CRn(0b1110), CRm(0b1111), Op2(0b111),
1105           access_pmu_evtyper, reset_val, PMCCFILTR_EL0, 0 },
1106
1107         /* DACR32_EL2 */
1108         { Op0(0b11), Op1(0b100), CRn(0b0011), CRm(0b0000), Op2(0b000),
1109           NULL, reset_unknown, DACR32_EL2 },
1110         /* IFSR32_EL2 */
1111         { Op0(0b11), Op1(0b100), CRn(0b0101), CRm(0b0000), Op2(0b001),
1112           NULL, reset_unknown, IFSR32_EL2 },
1113         /* FPEXC32_EL2 */
1114         { Op0(0b11), Op1(0b100), CRn(0b0101), CRm(0b0011), Op2(0b000),
1115           NULL, reset_val, FPEXC32_EL2, 0x70 },
1116 };
1117
1118 static bool trap_dbgidr(struct kvm_vcpu *vcpu,
1119                         struct sys_reg_params *p,
1120                         const struct sys_reg_desc *r)
1121 {
1122         if (p->is_write) {
1123                 return ignore_write(vcpu, p);
1124         } else {
1125                 u64 dfr = read_system_reg(SYS_ID_AA64DFR0_EL1);
1126                 u64 pfr = read_system_reg(SYS_ID_AA64PFR0_EL1);
1127                 u32 el3 = !!cpuid_feature_extract_unsigned_field(pfr, ID_AA64PFR0_EL3_SHIFT);
1128
1129                 p->regval = ((((dfr >> ID_AA64DFR0_WRPS_SHIFT) & 0xf) << 28) |
1130                              (((dfr >> ID_AA64DFR0_BRPS_SHIFT) & 0xf) << 24) |
1131                              (((dfr >> ID_AA64DFR0_CTX_CMPS_SHIFT) & 0xf) << 20)
1132                              | (6 << 16) | (el3 << 14) | (el3 << 12));
1133                 return true;
1134         }
1135 }
1136
1137 static bool trap_debug32(struct kvm_vcpu *vcpu,
1138                          struct sys_reg_params *p,
1139                          const struct sys_reg_desc *r)
1140 {
1141         if (p->is_write) {
1142                 vcpu_cp14(vcpu, r->reg) = p->regval;
1143                 vcpu->arch.debug_flags |= KVM_ARM64_DEBUG_DIRTY;
1144         } else {
1145                 p->regval = vcpu_cp14(vcpu, r->reg);
1146         }
1147
1148         return true;
1149 }
1150
1151 /* AArch32 debug register mappings
1152  *
1153  * AArch32 DBGBVRn is mapped to DBGBVRn_EL1[31:0]
1154  * AArch32 DBGBXVRn is mapped to DBGBVRn_EL1[63:32]
1155  *
1156  * All control registers and watchpoint value registers are mapped to
1157  * the lower 32 bits of their AArch64 equivalents. We share the trap
1158  * handlers with the above AArch64 code which checks what mode the
1159  * system is in.
1160  */
1161
1162 static bool trap_xvr(struct kvm_vcpu *vcpu,
1163                      struct sys_reg_params *p,
1164                      const struct sys_reg_desc *rd)
1165 {
1166         u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_bvr[rd->reg];
1167
1168         if (p->is_write) {
1169                 u64 val = *dbg_reg;
1170
1171                 val &= 0xffffffffUL;
1172                 val |= p->regval << 32;
1173                 *dbg_reg = val;
1174
1175                 vcpu->arch.debug_flags |= KVM_ARM64_DEBUG_DIRTY;
1176         } else {
1177                 p->regval = *dbg_reg >> 32;
1178         }
1179
1180         trace_trap_reg(__func__, rd->reg, p->is_write, *dbg_reg);
1181
1182         return true;
1183 }
1184
1185 #define DBG_BCR_BVR_WCR_WVR(n)                                          \
1186         /* DBGBVRn */                                                   \
1187         { Op1( 0), CRn( 0), CRm((n)), Op2( 4), trap_bvr, NULL, n },     \
1188         /* DBGBCRn */                                                   \
1189         { Op1( 0), CRn( 0), CRm((n)), Op2( 5), trap_bcr, NULL, n },     \
1190         /* DBGWVRn */                                                   \
1191         { Op1( 0), CRn( 0), CRm((n)), Op2( 6), trap_wvr, NULL, n },     \
1192         /* DBGWCRn */                                                   \
1193         { Op1( 0), CRn( 0), CRm((n)), Op2( 7), trap_wcr, NULL, n }
1194
1195 #define DBGBXVR(n)                                                      \
1196         { Op1( 0), CRn( 1), CRm((n)), Op2( 1), trap_xvr, NULL, n }
1197
1198 /*
1199  * Trapped cp14 registers. We generally ignore most of the external
1200  * debug, on the principle that they don't really make sense to a
1201  * guest. Revisit this one day, would this principle change.
1202  */
1203 static const struct sys_reg_desc cp14_regs[] = {
1204         /* DBGIDR */
1205         { Op1( 0), CRn( 0), CRm( 0), Op2( 0), trap_dbgidr },
1206         /* DBGDTRRXext */
1207         { Op1( 0), CRn( 0), CRm( 0), Op2( 2), trap_raz_wi },
1208
1209         DBG_BCR_BVR_WCR_WVR(0),
1210         /* DBGDSCRint */
1211         { Op1( 0), CRn( 0), CRm( 1), Op2( 0), trap_raz_wi },
1212         DBG_BCR_BVR_WCR_WVR(1),
1213         /* DBGDCCINT */
1214         { Op1( 0), CRn( 0), CRm( 2), Op2( 0), trap_debug32, NULL, cp14_DBGDCCINT },
1215         /* DBGDSCRext */
1216         { Op1( 0), CRn( 0), CRm( 2), Op2( 2), trap_debug32, NULL, cp14_DBGDSCRext },
1217         DBG_BCR_BVR_WCR_WVR(2),
1218         /* DBGDTR[RT]Xint */
1219         { Op1( 0), CRn( 0), CRm( 3), Op2( 0), trap_raz_wi },
1220         /* DBGDTR[RT]Xext */
1221         { Op1( 0), CRn( 0), CRm( 3), Op2( 2), trap_raz_wi },
1222         DBG_BCR_BVR_WCR_WVR(3),
1223         DBG_BCR_BVR_WCR_WVR(4),
1224         DBG_BCR_BVR_WCR_WVR(5),
1225         /* DBGWFAR */
1226         { Op1( 0), CRn( 0), CRm( 6), Op2( 0), trap_raz_wi },
1227         /* DBGOSECCR */
1228         { Op1( 0), CRn( 0), CRm( 6), Op2( 2), trap_raz_wi },
1229         DBG_BCR_BVR_WCR_WVR(6),
1230         /* DBGVCR */
1231         { Op1( 0), CRn( 0), CRm( 7), Op2( 0), trap_debug32, NULL, cp14_DBGVCR },
1232         DBG_BCR_BVR_WCR_WVR(7),
1233         DBG_BCR_BVR_WCR_WVR(8),
1234         DBG_BCR_BVR_WCR_WVR(9),
1235         DBG_BCR_BVR_WCR_WVR(10),
1236         DBG_BCR_BVR_WCR_WVR(11),
1237         DBG_BCR_BVR_WCR_WVR(12),
1238         DBG_BCR_BVR_WCR_WVR(13),
1239         DBG_BCR_BVR_WCR_WVR(14),
1240         DBG_BCR_BVR_WCR_WVR(15),
1241
1242         /* DBGDRAR (32bit) */
1243         { Op1( 0), CRn( 1), CRm( 0), Op2( 0), trap_raz_wi },
1244
1245         DBGBXVR(0),
1246         /* DBGOSLAR */
1247         { Op1( 0), CRn( 1), CRm( 0), Op2( 4), trap_raz_wi },
1248         DBGBXVR(1),
1249         /* DBGOSLSR */
1250         { Op1( 0), CRn( 1), CRm( 1), Op2( 4), trap_oslsr_el1 },
1251         DBGBXVR(2),
1252         DBGBXVR(3),
1253         /* DBGOSDLR */
1254         { Op1( 0), CRn( 1), CRm( 3), Op2( 4), trap_raz_wi },
1255         DBGBXVR(4),
1256         /* DBGPRCR */
1257         { Op1( 0), CRn( 1), CRm( 4), Op2( 4), trap_raz_wi },
1258         DBGBXVR(5),
1259         DBGBXVR(6),
1260         DBGBXVR(7),
1261         DBGBXVR(8),
1262         DBGBXVR(9),
1263         DBGBXVR(10),
1264         DBGBXVR(11),
1265         DBGBXVR(12),
1266         DBGBXVR(13),
1267         DBGBXVR(14),
1268         DBGBXVR(15),
1269
1270         /* DBGDSAR (32bit) */
1271         { Op1( 0), CRn( 2), CRm( 0), Op2( 0), trap_raz_wi },
1272
1273         /* DBGDEVID2 */
1274         { Op1( 0), CRn( 7), CRm( 0), Op2( 7), trap_raz_wi },
1275         /* DBGDEVID1 */
1276         { Op1( 0), CRn( 7), CRm( 1), Op2( 7), trap_raz_wi },
1277         /* DBGDEVID */
1278         { Op1( 0), CRn( 7), CRm( 2), Op2( 7), trap_raz_wi },
1279         /* DBGCLAIMSET */
1280         { Op1( 0), CRn( 7), CRm( 8), Op2( 6), trap_raz_wi },
1281         /* DBGCLAIMCLR */
1282         { Op1( 0), CRn( 7), CRm( 9), Op2( 6), trap_raz_wi },
1283         /* DBGAUTHSTATUS */
1284         { Op1( 0), CRn( 7), CRm(14), Op2( 6), trap_dbgauthstatus_el1 },
1285 };
1286
1287 /* Trapped cp14 64bit registers */
1288 static const struct sys_reg_desc cp14_64_regs[] = {
1289         /* DBGDRAR (64bit) */
1290         { Op1( 0), CRm( 1), .access = trap_raz_wi },
1291
1292         /* DBGDSAR (64bit) */
1293         { Op1( 0), CRm( 2), .access = trap_raz_wi },
1294 };
1295
1296 /* Macro to expand the PMEVCNTRn register */
1297 #define PMU_PMEVCNTR(n)                                                 \
1298         /* PMEVCNTRn */                                                 \
1299         { Op1(0), CRn(0b1110),                                          \
1300           CRm((0b1000 | (((n) >> 3) & 0x3))), Op2(((n) & 0x7)),         \
1301           access_pmu_evcntr }
1302
1303 /* Macro to expand the PMEVTYPERn register */
1304 #define PMU_PMEVTYPER(n)                                                \
1305         /* PMEVTYPERn */                                                \
1306         { Op1(0), CRn(0b1110),                                          \
1307           CRm((0b1100 | (((n) >> 3) & 0x3))), Op2(((n) & 0x7)),         \
1308           access_pmu_evtyper }
1309
1310 /*
1311  * Trapped cp15 registers. TTBR0/TTBR1 get a double encoding,
1312  * depending on the way they are accessed (as a 32bit or a 64bit
1313  * register).
1314  */
1315 static const struct sys_reg_desc cp15_regs[] = {
1316         { Op1( 0), CRn( 0), CRm(12), Op2( 0), access_gic_sgi },
1317
1318         { Op1( 0), CRn( 1), CRm( 0), Op2( 0), access_vm_reg, NULL, c1_SCTLR },
1319         { Op1( 0), CRn( 2), CRm( 0), Op2( 0), access_vm_reg, NULL, c2_TTBR0 },
1320         { Op1( 0), CRn( 2), CRm( 0), Op2( 1), access_vm_reg, NULL, c2_TTBR1 },
1321         { Op1( 0), CRn( 2), CRm( 0), Op2( 2), access_vm_reg, NULL, c2_TTBCR },
1322         { Op1( 0), CRn( 2), CRm( 0), Op2( 3), access_vm_reg, NULL, c2_TTBCR2 },
1323         { Op1( 0), CRn( 3), CRm( 0), Op2( 0), access_vm_reg, NULL, c3_DACR },
1324         { Op1( 0), CRn( 5), CRm( 0), Op2( 0), access_vm_reg, NULL, c5_DFSR },
1325         { Op1( 0), CRn( 5), CRm( 0), Op2( 1), access_vm_reg, NULL, c5_IFSR },
1326         { Op1( 0), CRn( 5), CRm( 1), Op2( 0), access_vm_reg, NULL, c5_ADFSR },
1327         { Op1( 0), CRn( 5), CRm( 1), Op2( 1), access_vm_reg, NULL, c5_AIFSR },
1328         { Op1( 0), CRn( 6), CRm( 0), Op2( 0), access_vm_reg, NULL, c6_DFAR },
1329         { Op1( 0), CRn( 6), CRm( 0), Op2( 2), access_vm_reg, NULL, c6_IFAR },
1330
1331         /*
1332          * DC{C,I,CI}SW operations:
1333          */
1334         { Op1( 0), CRn( 7), CRm( 6), Op2( 2), access_dcsw },
1335         { Op1( 0), CRn( 7), CRm(10), Op2( 2), access_dcsw },
1336         { Op1( 0), CRn( 7), CRm(14), Op2( 2), access_dcsw },
1337
1338         /* PMU */
1339         { Op1( 0), CRn( 9), CRm(12), Op2( 0), access_pmcr },
1340         { Op1( 0), CRn( 9), CRm(12), Op2( 1), access_pmcnten },
1341         { Op1( 0), CRn( 9), CRm(12), Op2( 2), access_pmcnten },
1342         { Op1( 0), CRn( 9), CRm(12), Op2( 3), access_pmovs },
1343         { Op1( 0), CRn( 9), CRm(12), Op2( 4), access_pmswinc },
1344         { Op1( 0), CRn( 9), CRm(12), Op2( 5), access_pmselr },
1345         { Op1( 0), CRn( 9), CRm(12), Op2( 6), access_pmceid },
1346         { Op1( 0), CRn( 9), CRm(12), Op2( 7), access_pmceid },
1347         { Op1( 0), CRn( 9), CRm(13), Op2( 0), access_pmu_evcntr },
1348         { Op1( 0), CRn( 9), CRm(13), Op2( 1), access_pmu_evtyper },
1349         { Op1( 0), CRn( 9), CRm(13), Op2( 2), access_pmu_evcntr },
1350         { Op1( 0), CRn( 9), CRm(14), Op2( 0), access_pmuserenr },
1351         { Op1( 0), CRn( 9), CRm(14), Op2( 1), access_pminten },
1352         { Op1( 0), CRn( 9), CRm(14), Op2( 2), access_pminten },
1353         { Op1( 0), CRn( 9), CRm(14), Op2( 3), access_pmovs },
1354
1355         { Op1( 0), CRn(10), CRm( 2), Op2( 0), access_vm_reg, NULL, c10_PRRR },
1356         { Op1( 0), CRn(10), CRm( 2), Op2( 1), access_vm_reg, NULL, c10_NMRR },
1357         { Op1( 0), CRn(10), CRm( 3), Op2( 0), access_vm_reg, NULL, c10_AMAIR0 },
1358         { Op1( 0), CRn(10), CRm( 3), Op2( 1), access_vm_reg, NULL, c10_AMAIR1 },
1359
1360         /* ICC_SRE */
1361         { Op1( 0), CRn(12), CRm(12), Op2( 5), access_gic_sre },
1362
1363         { Op1( 0), CRn(13), CRm( 0), Op2( 1), access_vm_reg, NULL, c13_CID },
1364
1365         /* PMEVCNTRn */
1366         PMU_PMEVCNTR(0),
1367         PMU_PMEVCNTR(1),
1368         PMU_PMEVCNTR(2),
1369         PMU_PMEVCNTR(3),
1370         PMU_PMEVCNTR(4),
1371         PMU_PMEVCNTR(5),
1372         PMU_PMEVCNTR(6),
1373         PMU_PMEVCNTR(7),
1374         PMU_PMEVCNTR(8),
1375         PMU_PMEVCNTR(9),
1376         PMU_PMEVCNTR(10),
1377         PMU_PMEVCNTR(11),
1378         PMU_PMEVCNTR(12),
1379         PMU_PMEVCNTR(13),
1380         PMU_PMEVCNTR(14),
1381         PMU_PMEVCNTR(15),
1382         PMU_PMEVCNTR(16),
1383         PMU_PMEVCNTR(17),
1384         PMU_PMEVCNTR(18),
1385         PMU_PMEVCNTR(19),
1386         PMU_PMEVCNTR(20),
1387         PMU_PMEVCNTR(21),
1388         PMU_PMEVCNTR(22),
1389         PMU_PMEVCNTR(23),
1390         PMU_PMEVCNTR(24),
1391         PMU_PMEVCNTR(25),
1392         PMU_PMEVCNTR(26),
1393         PMU_PMEVCNTR(27),
1394         PMU_PMEVCNTR(28),
1395         PMU_PMEVCNTR(29),
1396         PMU_PMEVCNTR(30),
1397         /* PMEVTYPERn */
1398         PMU_PMEVTYPER(0),
1399         PMU_PMEVTYPER(1),
1400         PMU_PMEVTYPER(2),
1401         PMU_PMEVTYPER(3),
1402         PMU_PMEVTYPER(4),
1403         PMU_PMEVTYPER(5),
1404         PMU_PMEVTYPER(6),
1405         PMU_PMEVTYPER(7),
1406         PMU_PMEVTYPER(8),
1407         PMU_PMEVTYPER(9),
1408         PMU_PMEVTYPER(10),
1409         PMU_PMEVTYPER(11),
1410         PMU_PMEVTYPER(12),
1411         PMU_PMEVTYPER(13),
1412         PMU_PMEVTYPER(14),
1413         PMU_PMEVTYPER(15),
1414         PMU_PMEVTYPER(16),
1415         PMU_PMEVTYPER(17),
1416         PMU_PMEVTYPER(18),
1417         PMU_PMEVTYPER(19),
1418         PMU_PMEVTYPER(20),
1419         PMU_PMEVTYPER(21),
1420         PMU_PMEVTYPER(22),
1421         PMU_PMEVTYPER(23),
1422         PMU_PMEVTYPER(24),
1423         PMU_PMEVTYPER(25),
1424         PMU_PMEVTYPER(26),
1425         PMU_PMEVTYPER(27),
1426         PMU_PMEVTYPER(28),
1427         PMU_PMEVTYPER(29),
1428         PMU_PMEVTYPER(30),
1429         /* PMCCFILTR */
1430         { Op1(0), CRn(14), CRm(15), Op2(7), access_pmu_evtyper },
1431 };
1432
1433 static const struct sys_reg_desc cp15_64_regs[] = {
1434         { Op1( 0), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, c2_TTBR0 },
1435         { Op1( 0), CRn( 0), CRm( 9), Op2( 0), access_pmu_evcntr },
1436         { Op1( 0), CRn( 0), CRm(12), Op2( 0), access_gic_sgi },
1437         { Op1( 1), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, c2_TTBR1 },
1438 };
1439
1440 /* Target specific emulation tables */
1441 static struct kvm_sys_reg_target_table *target_tables[KVM_ARM_NUM_TARGETS];
1442
1443 void kvm_register_target_sys_reg_table(unsigned int target,
1444                                        struct kvm_sys_reg_target_table *table)
1445 {
1446         target_tables[target] = table;
1447 }
1448
1449 /* Get specific register table for this target. */
1450 static const struct sys_reg_desc *get_target_table(unsigned target,
1451                                                    bool mode_is_64,
1452                                                    size_t *num)
1453 {
1454         struct kvm_sys_reg_target_table *table;
1455
1456         table = target_tables[target];
1457         if (mode_is_64) {
1458                 *num = table->table64.num;
1459                 return table->table64.table;
1460         } else {
1461                 *num = table->table32.num;
1462                 return table->table32.table;
1463         }
1464 }
1465
1466 #define reg_to_match_value(x)                                           \
1467         ({                                                              \
1468                 unsigned long val;                                      \
1469                 val  = (x)->Op0 << 14;                                  \
1470                 val |= (x)->Op1 << 11;                                  \
1471                 val |= (x)->CRn << 7;                                   \
1472                 val |= (x)->CRm << 3;                                   \
1473                 val |= (x)->Op2;                                        \
1474                 val;                                                    \
1475          })
1476
1477 static int match_sys_reg(const void *key, const void *elt)
1478 {
1479         const unsigned long pval = (unsigned long)key;
1480         const struct sys_reg_desc *r = elt;
1481
1482         return pval - reg_to_match_value(r);
1483 }
1484
1485 static const struct sys_reg_desc *find_reg(const struct sys_reg_params *params,
1486                                          const struct sys_reg_desc table[],
1487                                          unsigned int num)
1488 {
1489         unsigned long pval = reg_to_match_value(params);
1490
1491         return bsearch((void *)pval, table, num, sizeof(table[0]), match_sys_reg);
1492 }
1493
1494 int kvm_handle_cp14_load_store(struct kvm_vcpu *vcpu, struct kvm_run *run)
1495 {
1496         kvm_inject_undefined(vcpu);
1497         return 1;
1498 }
1499
1500 /*
1501  * emulate_cp --  tries to match a sys_reg access in a handling table, and
1502  *                call the corresponding trap handler.
1503  *
1504  * @params: pointer to the descriptor of the access
1505  * @table: array of trap descriptors
1506  * @num: size of the trap descriptor array
1507  *
1508  * Return 0 if the access has been handled, and -1 if not.
1509  */
1510 static int emulate_cp(struct kvm_vcpu *vcpu,
1511                       struct sys_reg_params *params,
1512                       const struct sys_reg_desc *table,
1513                       size_t num)
1514 {
1515         const struct sys_reg_desc *r;
1516
1517         if (!table)
1518                 return -1;      /* Not handled */
1519
1520         r = find_reg(params, table, num);
1521
1522         if (r) {
1523                 /*
1524                  * Not having an accessor means that we have
1525                  * configured a trap that we don't know how to
1526                  * handle. This certainly qualifies as a gross bug
1527                  * that should be fixed right away.
1528                  */
1529                 BUG_ON(!r->access);
1530
1531                 if (likely(r->access(vcpu, params, r))) {
1532                         /* Skip instruction, since it was emulated */
1533                         kvm_skip_instr(vcpu, kvm_vcpu_trap_il_is32bit(vcpu));
1534                         /* Handled */
1535                         return 0;
1536                 }
1537         }
1538
1539         /* Not handled */
1540         return -1;
1541 }
1542
1543 static void unhandled_cp_access(struct kvm_vcpu *vcpu,
1544                                 struct sys_reg_params *params)
1545 {
1546         u8 hsr_ec = kvm_vcpu_trap_get_class(vcpu);
1547         int cp = -1;
1548
1549         switch(hsr_ec) {
1550         case ESR_ELx_EC_CP15_32:
1551         case ESR_ELx_EC_CP15_64:
1552                 cp = 15;
1553                 break;
1554         case ESR_ELx_EC_CP14_MR:
1555         case ESR_ELx_EC_CP14_64:
1556                 cp = 14;
1557                 break;
1558         default:
1559                 WARN_ON(1);
1560         }
1561
1562         kvm_err("Unsupported guest CP%d access at: %08lx\n",
1563                 cp, *vcpu_pc(vcpu));
1564         print_sys_reg_instr(params);
1565         kvm_inject_undefined(vcpu);
1566 }
1567
1568 /**
1569  * kvm_handle_cp_64 -- handles a mrrc/mcrr trap on a guest CP14/CP15 access
1570  * @vcpu: The VCPU pointer
1571  * @run:  The kvm_run struct
1572  */
1573 static int kvm_handle_cp_64(struct kvm_vcpu *vcpu,
1574                             const struct sys_reg_desc *global,
1575                             size_t nr_global,
1576                             const struct sys_reg_desc *target_specific,
1577                             size_t nr_specific)
1578 {
1579         struct sys_reg_params params;
1580         u32 hsr = kvm_vcpu_get_hsr(vcpu);
1581         int Rt = kvm_vcpu_sys_get_rt(vcpu);
1582         int Rt2 = (hsr >> 10) & 0x1f;
1583
1584         params.is_aarch32 = true;
1585         params.is_32bit = false;
1586         params.CRm = (hsr >> 1) & 0xf;
1587         params.is_write = ((hsr & 1) == 0);
1588
1589         params.Op0 = 0;
1590         params.Op1 = (hsr >> 16) & 0xf;
1591         params.Op2 = 0;
1592         params.CRn = 0;
1593
1594         /*
1595          * Make a 64-bit value out of Rt and Rt2. As we use the same trap
1596          * backends between AArch32 and AArch64, we get away with it.
1597          */
1598         if (params.is_write) {
1599                 params.regval = vcpu_get_reg(vcpu, Rt) & 0xffffffff;
1600                 params.regval |= vcpu_get_reg(vcpu, Rt2) << 32;
1601         }
1602
1603         if (!emulate_cp(vcpu, &params, target_specific, nr_specific))
1604                 goto out;
1605         if (!emulate_cp(vcpu, &params, global, nr_global))
1606                 goto out;
1607
1608         unhandled_cp_access(vcpu, &params);
1609
1610 out:
1611         /* Split up the value between registers for the read side */
1612         if (!params.is_write) {
1613                 vcpu_set_reg(vcpu, Rt, lower_32_bits(params.regval));
1614                 vcpu_set_reg(vcpu, Rt2, upper_32_bits(params.regval));
1615         }
1616
1617         return 1;
1618 }
1619
1620 /**
1621  * kvm_handle_cp_32 -- handles a mrc/mcr trap on a guest CP14/CP15 access
1622  * @vcpu: The VCPU pointer
1623  * @run:  The kvm_run struct
1624  */
1625 static int kvm_handle_cp_32(struct kvm_vcpu *vcpu,
1626                             const struct sys_reg_desc *global,
1627                             size_t nr_global,
1628                             const struct sys_reg_desc *target_specific,
1629                             size_t nr_specific)
1630 {
1631         struct sys_reg_params params;
1632         u32 hsr = kvm_vcpu_get_hsr(vcpu);
1633         int Rt  = kvm_vcpu_sys_get_rt(vcpu);
1634
1635         params.is_aarch32 = true;
1636         params.is_32bit = true;
1637         params.CRm = (hsr >> 1) & 0xf;
1638         params.regval = vcpu_get_reg(vcpu, Rt);
1639         params.is_write = ((hsr & 1) == 0);
1640         params.CRn = (hsr >> 10) & 0xf;
1641         params.Op0 = 0;
1642         params.Op1 = (hsr >> 14) & 0x7;
1643         params.Op2 = (hsr >> 17) & 0x7;
1644
1645         if (!emulate_cp(vcpu, &params, target_specific, nr_specific) ||
1646             !emulate_cp(vcpu, &params, global, nr_global)) {
1647                 if (!params.is_write)
1648                         vcpu_set_reg(vcpu, Rt, params.regval);
1649                 return 1;
1650         }
1651
1652         unhandled_cp_access(vcpu, &params);
1653         return 1;
1654 }
1655
1656 int kvm_handle_cp15_64(struct kvm_vcpu *vcpu, struct kvm_run *run)
1657 {
1658         const struct sys_reg_desc *target_specific;
1659         size_t num;
1660
1661         target_specific = get_target_table(vcpu->arch.target, false, &num);
1662         return kvm_handle_cp_64(vcpu,
1663                                 cp15_64_regs, ARRAY_SIZE(cp15_64_regs),
1664                                 target_specific, num);
1665 }
1666
1667 int kvm_handle_cp15_32(struct kvm_vcpu *vcpu, struct kvm_run *run)
1668 {
1669         const struct sys_reg_desc *target_specific;
1670         size_t num;
1671
1672         target_specific = get_target_table(vcpu->arch.target, false, &num);
1673         return kvm_handle_cp_32(vcpu,
1674                                 cp15_regs, ARRAY_SIZE(cp15_regs),
1675                                 target_specific, num);
1676 }
1677
1678 int kvm_handle_cp14_64(struct kvm_vcpu *vcpu, struct kvm_run *run)
1679 {
1680         return kvm_handle_cp_64(vcpu,
1681                                 cp14_64_regs, ARRAY_SIZE(cp14_64_regs),
1682                                 NULL, 0);
1683 }
1684
1685 int kvm_handle_cp14_32(struct kvm_vcpu *vcpu, struct kvm_run *run)
1686 {
1687         return kvm_handle_cp_32(vcpu,
1688                                 cp14_regs, ARRAY_SIZE(cp14_regs),
1689                                 NULL, 0);
1690 }
1691
1692 static int emulate_sys_reg(struct kvm_vcpu *vcpu,
1693                            struct sys_reg_params *params)
1694 {
1695         size_t num;
1696         const struct sys_reg_desc *table, *r;
1697
1698         table = get_target_table(vcpu->arch.target, true, &num);
1699
1700         /* Search target-specific then generic table. */
1701         r = find_reg(params, table, num);
1702         if (!r)
1703                 r = find_reg(params, sys_reg_descs, ARRAY_SIZE(sys_reg_descs));
1704
1705         if (likely(r)) {
1706                 /*
1707                  * Not having an accessor means that we have
1708                  * configured a trap that we don't know how to
1709                  * handle. This certainly qualifies as a gross bug
1710                  * that should be fixed right away.
1711                  */
1712                 BUG_ON(!r->access);
1713
1714                 if (likely(r->access(vcpu, params, r))) {
1715                         /* Skip instruction, since it was emulated */
1716                         kvm_skip_instr(vcpu, kvm_vcpu_trap_il_is32bit(vcpu));
1717                         return 1;
1718                 }
1719                 /* If access function fails, it should complain. */
1720         } else {
1721                 kvm_err("Unsupported guest sys_reg access at: %lx\n",
1722                         *vcpu_pc(vcpu));
1723                 print_sys_reg_instr(params);
1724         }
1725         kvm_inject_undefined(vcpu);
1726         return 1;
1727 }
1728
1729 static void reset_sys_reg_descs(struct kvm_vcpu *vcpu,
1730                               const struct sys_reg_desc *table, size_t num)
1731 {
1732         unsigned long i;
1733
1734         for (i = 0; i < num; i++)
1735                 if (table[i].reset)
1736                         table[i].reset(vcpu, &table[i]);
1737 }
1738
1739 /**
1740  * kvm_handle_sys_reg -- handles a mrs/msr trap on a guest sys_reg access
1741  * @vcpu: The VCPU pointer
1742  * @run:  The kvm_run struct
1743  */
1744 int kvm_handle_sys_reg(struct kvm_vcpu *vcpu, struct kvm_run *run)
1745 {
1746         struct sys_reg_params params;
1747         unsigned long esr = kvm_vcpu_get_hsr(vcpu);
1748         int Rt = kvm_vcpu_sys_get_rt(vcpu);
1749         int ret;
1750
1751         trace_kvm_handle_sys_reg(esr);
1752
1753         params.is_aarch32 = false;
1754         params.is_32bit = false;
1755         params.Op0 = (esr >> 20) & 3;
1756         params.Op1 = (esr >> 14) & 0x7;
1757         params.CRn = (esr >> 10) & 0xf;
1758         params.CRm = (esr >> 1) & 0xf;
1759         params.Op2 = (esr >> 17) & 0x7;
1760         params.regval = vcpu_get_reg(vcpu, Rt);
1761         params.is_write = !(esr & 1);
1762
1763         ret = emulate_sys_reg(vcpu, &params);
1764
1765         if (!params.is_write)
1766                 vcpu_set_reg(vcpu, Rt, params.regval);
1767         return ret;
1768 }
1769
1770 /******************************************************************************
1771  * Userspace API
1772  *****************************************************************************/
1773
1774 static bool index_to_params(u64 id, struct sys_reg_params *params)
1775 {
1776         switch (id & KVM_REG_SIZE_MASK) {
1777         case KVM_REG_SIZE_U64:
1778                 /* Any unused index bits means it's not valid. */
1779                 if (id & ~(KVM_REG_ARCH_MASK | KVM_REG_SIZE_MASK
1780                               | KVM_REG_ARM_COPROC_MASK
1781                               | KVM_REG_ARM64_SYSREG_OP0_MASK
1782                               | KVM_REG_ARM64_SYSREG_OP1_MASK
1783                               | KVM_REG_ARM64_SYSREG_CRN_MASK
1784                               | KVM_REG_ARM64_SYSREG_CRM_MASK
1785                               | KVM_REG_ARM64_SYSREG_OP2_MASK))
1786                         return false;
1787                 params->Op0 = ((id & KVM_REG_ARM64_SYSREG_OP0_MASK)
1788                                >> KVM_REG_ARM64_SYSREG_OP0_SHIFT);
1789                 params->Op1 = ((id & KVM_REG_ARM64_SYSREG_OP1_MASK)
1790                                >> KVM_REG_ARM64_SYSREG_OP1_SHIFT);
1791                 params->CRn = ((id & KVM_REG_ARM64_SYSREG_CRN_MASK)
1792                                >> KVM_REG_ARM64_SYSREG_CRN_SHIFT);
1793                 params->CRm = ((id & KVM_REG_ARM64_SYSREG_CRM_MASK)
1794                                >> KVM_REG_ARM64_SYSREG_CRM_SHIFT);
1795                 params->Op2 = ((id & KVM_REG_ARM64_SYSREG_OP2_MASK)
1796                                >> KVM_REG_ARM64_SYSREG_OP2_SHIFT);
1797                 return true;
1798         default:
1799                 return false;
1800         }
1801 }
1802
1803 /* Decode an index value, and find the sys_reg_desc entry. */
1804 static const struct sys_reg_desc *index_to_sys_reg_desc(struct kvm_vcpu *vcpu,
1805                                                     u64 id)
1806 {
1807         size_t num;
1808         const struct sys_reg_desc *table, *r;
1809         struct sys_reg_params params;
1810
1811         /* We only do sys_reg for now. */
1812         if ((id & KVM_REG_ARM_COPROC_MASK) != KVM_REG_ARM64_SYSREG)
1813                 return NULL;
1814
1815         if (!index_to_params(id, &params))
1816                 return NULL;
1817
1818         table = get_target_table(vcpu->arch.target, true, &num);
1819         r = find_reg(&params, table, num);
1820         if (!r)
1821                 r = find_reg(&params, sys_reg_descs, ARRAY_SIZE(sys_reg_descs));
1822
1823         /* Not saved in the sys_reg array? */
1824         if (r && !r->reg)
1825                 r = NULL;
1826
1827         return r;
1828 }
1829
1830 /*
1831  * These are the invariant sys_reg registers: we let the guest see the
1832  * host versions of these, so they're part of the guest state.
1833  *
1834  * A future CPU may provide a mechanism to present different values to
1835  * the guest, or a future kvm may trap them.
1836  */
1837
1838 #define FUNCTION_INVARIANT(reg)                                         \
1839         static void get_##reg(struct kvm_vcpu *v,                       \
1840                               const struct sys_reg_desc *r)             \
1841         {                                                               \
1842                 ((struct sys_reg_desc *)r)->val = read_sysreg(reg);     \
1843         }
1844
1845 FUNCTION_INVARIANT(midr_el1)
1846 FUNCTION_INVARIANT(ctr_el0)
1847 FUNCTION_INVARIANT(revidr_el1)
1848 FUNCTION_INVARIANT(id_pfr0_el1)
1849 FUNCTION_INVARIANT(id_pfr1_el1)
1850 FUNCTION_INVARIANT(id_dfr0_el1)
1851 FUNCTION_INVARIANT(id_afr0_el1)
1852 FUNCTION_INVARIANT(id_mmfr0_el1)
1853 FUNCTION_INVARIANT(id_mmfr1_el1)
1854 FUNCTION_INVARIANT(id_mmfr2_el1)
1855 FUNCTION_INVARIANT(id_mmfr3_el1)
1856 FUNCTION_INVARIANT(id_isar0_el1)
1857 FUNCTION_INVARIANT(id_isar1_el1)
1858 FUNCTION_INVARIANT(id_isar2_el1)
1859 FUNCTION_INVARIANT(id_isar3_el1)
1860 FUNCTION_INVARIANT(id_isar4_el1)
1861 FUNCTION_INVARIANT(id_isar5_el1)
1862 FUNCTION_INVARIANT(clidr_el1)
1863 FUNCTION_INVARIANT(aidr_el1)
1864
1865 /* ->val is filled in by kvm_sys_reg_table_init() */
1866 static struct sys_reg_desc invariant_sys_regs[] = {
1867         { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0000), Op2(0b000),
1868           NULL, get_midr_el1 },
1869         { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0000), Op2(0b110),
1870           NULL, get_revidr_el1 },
1871         { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b000),
1872           NULL, get_id_pfr0_el1 },
1873         { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b001),
1874           NULL, get_id_pfr1_el1 },
1875         { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b010),
1876           NULL, get_id_dfr0_el1 },
1877         { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b011),
1878           NULL, get_id_afr0_el1 },
1879         { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b100),
1880           NULL, get_id_mmfr0_el1 },
1881         { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b101),
1882           NULL, get_id_mmfr1_el1 },
1883         { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b110),
1884           NULL, get_id_mmfr2_el1 },
1885         { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b111),
1886           NULL, get_id_mmfr3_el1 },
1887         { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0010), Op2(0b000),
1888           NULL, get_id_isar0_el1 },
1889         { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0010), Op2(0b001),
1890           NULL, get_id_isar1_el1 },
1891         { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0010), Op2(0b010),
1892           NULL, get_id_isar2_el1 },
1893         { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0010), Op2(0b011),
1894           NULL, get_id_isar3_el1 },
1895         { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0010), Op2(0b100),
1896           NULL, get_id_isar4_el1 },
1897         { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0010), Op2(0b101),
1898           NULL, get_id_isar5_el1 },
1899         { Op0(0b11), Op1(0b001), CRn(0b0000), CRm(0b0000), Op2(0b001),
1900           NULL, get_clidr_el1 },
1901         { Op0(0b11), Op1(0b001), CRn(0b0000), CRm(0b0000), Op2(0b111),
1902           NULL, get_aidr_el1 },
1903         { Op0(0b11), Op1(0b011), CRn(0b0000), CRm(0b0000), Op2(0b001),
1904           NULL, get_ctr_el0 },
1905 };
1906
1907 static int reg_from_user(u64 *val, const void __user *uaddr, u64 id)
1908 {
1909         if (copy_from_user(val, uaddr, KVM_REG_SIZE(id)) != 0)
1910                 return -EFAULT;
1911         return 0;
1912 }
1913
1914 static int reg_to_user(void __user *uaddr, const u64 *val, u64 id)
1915 {
1916         if (copy_to_user(uaddr, val, KVM_REG_SIZE(id)) != 0)
1917                 return -EFAULT;
1918         return 0;
1919 }
1920
1921 static int get_invariant_sys_reg(u64 id, void __user *uaddr)
1922 {
1923         struct sys_reg_params params;
1924         const struct sys_reg_desc *r;
1925
1926         if (!index_to_params(id, &params))
1927                 return -ENOENT;
1928
1929         r = find_reg(&params, invariant_sys_regs, ARRAY_SIZE(invariant_sys_regs));
1930         if (!r)
1931                 return -ENOENT;
1932
1933         return reg_to_user(uaddr, &r->val, id);
1934 }
1935
1936 static int set_invariant_sys_reg(u64 id, void __user *uaddr)
1937 {
1938         struct sys_reg_params params;
1939         const struct sys_reg_desc *r;
1940         int err;
1941         u64 val = 0; /* Make sure high bits are 0 for 32-bit regs */
1942
1943         if (!index_to_params(id, &params))
1944                 return -ENOENT;
1945         r = find_reg(&params, invariant_sys_regs, ARRAY_SIZE(invariant_sys_regs));
1946         if (!r)
1947                 return -ENOENT;
1948
1949         err = reg_from_user(&val, uaddr, id);
1950         if (err)
1951                 return err;
1952
1953         /* This is what we mean by invariant: you can't change it. */
1954         if (r->val != val)
1955                 return -EINVAL;
1956
1957         return 0;
1958 }
1959
1960 static bool is_valid_cache(u32 val)
1961 {
1962         u32 level, ctype;
1963
1964         if (val >= CSSELR_MAX)
1965                 return false;
1966
1967         /* Bottom bit is Instruction or Data bit.  Next 3 bits are level. */
1968         level = (val >> 1);
1969         ctype = (cache_levels >> (level * 3)) & 7;
1970
1971         switch (ctype) {
1972         case 0: /* No cache */
1973                 return false;
1974         case 1: /* Instruction cache only */
1975                 return (val & 1);
1976         case 2: /* Data cache only */
1977         case 4: /* Unified cache */
1978                 return !(val & 1);
1979         case 3: /* Separate instruction and data caches */
1980                 return true;
1981         default: /* Reserved: we can't know instruction or data. */
1982                 return false;
1983         }
1984 }
1985
1986 static int demux_c15_get(u64 id, void __user *uaddr)
1987 {
1988         u32 val;
1989         u32 __user *uval = uaddr;
1990
1991         /* Fail if we have unknown bits set. */
1992         if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK
1993                    | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1)))
1994                 return -ENOENT;
1995
1996         switch (id & KVM_REG_ARM_DEMUX_ID_MASK) {
1997         case KVM_REG_ARM_DEMUX_ID_CCSIDR:
1998                 if (KVM_REG_SIZE(id) != 4)
1999                         return -ENOENT;
2000                 val = (id & KVM_REG_ARM_DEMUX_VAL_MASK)
2001                         >> KVM_REG_ARM_DEMUX_VAL_SHIFT;
2002                 if (!is_valid_cache(val))
2003                         return -ENOENT;
2004
2005                 return put_user(get_ccsidr(val), uval);
2006         default:
2007                 return -ENOENT;
2008         }
2009 }
2010
2011 static int demux_c15_set(u64 id, void __user *uaddr)
2012 {
2013         u32 val, newval;
2014         u32 __user *uval = uaddr;
2015
2016         /* Fail if we have unknown bits set. */
2017         if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK
2018                    | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1)))
2019                 return -ENOENT;
2020
2021         switch (id & KVM_REG_ARM_DEMUX_ID_MASK) {
2022         case KVM_REG_ARM_DEMUX_ID_CCSIDR:
2023                 if (KVM_REG_SIZE(id) != 4)
2024                         return -ENOENT;
2025                 val = (id & KVM_REG_ARM_DEMUX_VAL_MASK)
2026                         >> KVM_REG_ARM_DEMUX_VAL_SHIFT;
2027                 if (!is_valid_cache(val))
2028                         return -ENOENT;
2029
2030                 if (get_user(newval, uval))
2031                         return -EFAULT;
2032
2033                 /* This is also invariant: you can't change it. */
2034                 if (newval != get_ccsidr(val))
2035                         return -EINVAL;
2036                 return 0;
2037         default:
2038                 return -ENOENT;
2039         }
2040 }
2041
2042 int kvm_arm_sys_reg_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
2043 {
2044         const struct sys_reg_desc *r;
2045         void __user *uaddr = (void __user *)(unsigned long)reg->addr;
2046
2047         if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_DEMUX)
2048                 return demux_c15_get(reg->id, uaddr);
2049
2050         if (KVM_REG_SIZE(reg->id) != sizeof(__u64))
2051                 return -ENOENT;
2052
2053         r = index_to_sys_reg_desc(vcpu, reg->id);
2054         if (!r)
2055                 return get_invariant_sys_reg(reg->id, uaddr);
2056
2057         if (r->get_user)
2058                 return (r->get_user)(vcpu, r, reg, uaddr);
2059
2060         return reg_to_user(uaddr, &vcpu_sys_reg(vcpu, r->reg), reg->id);
2061 }
2062
2063 int kvm_arm_sys_reg_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
2064 {
2065         const struct sys_reg_desc *r;
2066         void __user *uaddr = (void __user *)(unsigned long)reg->addr;
2067
2068         if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_DEMUX)
2069                 return demux_c15_set(reg->id, uaddr);
2070
2071         if (KVM_REG_SIZE(reg->id) != sizeof(__u64))
2072                 return -ENOENT;
2073
2074         r = index_to_sys_reg_desc(vcpu, reg->id);
2075         if (!r)
2076                 return set_invariant_sys_reg(reg->id, uaddr);
2077
2078         if (r->set_user)
2079                 return (r->set_user)(vcpu, r, reg, uaddr);
2080
2081         return reg_from_user(&vcpu_sys_reg(vcpu, r->reg), uaddr, reg->id);
2082 }
2083
2084 static unsigned int num_demux_regs(void)
2085 {
2086         unsigned int i, count = 0;
2087
2088         for (i = 0; i < CSSELR_MAX; i++)
2089                 if (is_valid_cache(i))
2090                         count++;
2091
2092         return count;
2093 }
2094
2095 static int write_demux_regids(u64 __user *uindices)
2096 {
2097         u64 val = KVM_REG_ARM64 | KVM_REG_SIZE_U32 | KVM_REG_ARM_DEMUX;
2098         unsigned int i;
2099
2100         val |= KVM_REG_ARM_DEMUX_ID_CCSIDR;
2101         for (i = 0; i < CSSELR_MAX; i++) {
2102                 if (!is_valid_cache(i))
2103                         continue;
2104                 if (put_user(val | i, uindices))
2105                         return -EFAULT;
2106                 uindices++;
2107         }
2108         return 0;
2109 }
2110
2111 static u64 sys_reg_to_index(const struct sys_reg_desc *reg)
2112 {
2113         return (KVM_REG_ARM64 | KVM_REG_SIZE_U64 |
2114                 KVM_REG_ARM64_SYSREG |
2115                 (reg->Op0 << KVM_REG_ARM64_SYSREG_OP0_SHIFT) |
2116                 (reg->Op1 << KVM_REG_ARM64_SYSREG_OP1_SHIFT) |
2117                 (reg->CRn << KVM_REG_ARM64_SYSREG_CRN_SHIFT) |
2118                 (reg->CRm << KVM_REG_ARM64_SYSREG_CRM_SHIFT) |
2119                 (reg->Op2 << KVM_REG_ARM64_SYSREG_OP2_SHIFT));
2120 }
2121
2122 static bool copy_reg_to_user(const struct sys_reg_desc *reg, u64 __user **uind)
2123 {
2124         if (!*uind)
2125                 return true;
2126
2127         if (put_user(sys_reg_to_index(reg), *uind))
2128                 return false;
2129
2130         (*uind)++;
2131         return true;
2132 }
2133
2134 /* Assumed ordered tables, see kvm_sys_reg_table_init. */
2135 static int walk_sys_regs(struct kvm_vcpu *vcpu, u64 __user *uind)
2136 {
2137         const struct sys_reg_desc *i1, *i2, *end1, *end2;
2138         unsigned int total = 0;
2139         size_t num;
2140
2141         /* We check for duplicates here, to allow arch-specific overrides. */
2142         i1 = get_target_table(vcpu->arch.target, true, &num);
2143         end1 = i1 + num;
2144         i2 = sys_reg_descs;
2145         end2 = sys_reg_descs + ARRAY_SIZE(sys_reg_descs);
2146
2147         BUG_ON(i1 == end1 || i2 == end2);
2148
2149         /* Walk carefully, as both tables may refer to the same register. */
2150         while (i1 || i2) {
2151                 int cmp = cmp_sys_reg(i1, i2);
2152                 /* target-specific overrides generic entry. */
2153                 if (cmp <= 0) {
2154                         /* Ignore registers we trap but don't save. */
2155                         if (i1->reg) {
2156                                 if (!copy_reg_to_user(i1, &uind))
2157                                         return -EFAULT;
2158                                 total++;
2159                         }
2160                 } else {
2161                         /* Ignore registers we trap but don't save. */
2162                         if (i2->reg) {
2163                                 if (!copy_reg_to_user(i2, &uind))
2164                                         return -EFAULT;
2165                                 total++;
2166                         }
2167                 }
2168
2169                 if (cmp <= 0 && ++i1 == end1)
2170                         i1 = NULL;
2171                 if (cmp >= 0 && ++i2 == end2)
2172                         i2 = NULL;
2173         }
2174         return total;
2175 }
2176
2177 unsigned long kvm_arm_num_sys_reg_descs(struct kvm_vcpu *vcpu)
2178 {
2179         return ARRAY_SIZE(invariant_sys_regs)
2180                 + num_demux_regs()
2181                 + walk_sys_regs(vcpu, (u64 __user *)NULL);
2182 }
2183
2184 int kvm_arm_copy_sys_reg_indices(struct kvm_vcpu *vcpu, u64 __user *uindices)
2185 {
2186         unsigned int i;
2187         int err;
2188
2189         /* Then give them all the invariant registers' indices. */
2190         for (i = 0; i < ARRAY_SIZE(invariant_sys_regs); i++) {
2191                 if (put_user(sys_reg_to_index(&invariant_sys_regs[i]), uindices))
2192                         return -EFAULT;
2193                 uindices++;
2194         }
2195
2196         err = walk_sys_regs(vcpu, uindices);
2197         if (err < 0)
2198                 return err;
2199         uindices += err;
2200
2201         return write_demux_regids(uindices);
2202 }
2203
2204 static int check_sysreg_table(const struct sys_reg_desc *table, unsigned int n)
2205 {
2206         unsigned int i;
2207
2208         for (i = 1; i < n; i++) {
2209                 if (cmp_sys_reg(&table[i-1], &table[i]) >= 0) {
2210                         kvm_err("sys_reg table %p out of order (%d)\n", table, i - 1);
2211                         return 1;
2212                 }
2213         }
2214
2215         return 0;
2216 }
2217
2218 void kvm_sys_reg_table_init(void)
2219 {
2220         unsigned int i;
2221         struct sys_reg_desc clidr;
2222
2223         /* Make sure tables are unique and in order. */
2224         BUG_ON(check_sysreg_table(sys_reg_descs, ARRAY_SIZE(sys_reg_descs)));
2225         BUG_ON(check_sysreg_table(cp14_regs, ARRAY_SIZE(cp14_regs)));
2226         BUG_ON(check_sysreg_table(cp14_64_regs, ARRAY_SIZE(cp14_64_regs)));
2227         BUG_ON(check_sysreg_table(cp15_regs, ARRAY_SIZE(cp15_regs)));
2228         BUG_ON(check_sysreg_table(cp15_64_regs, ARRAY_SIZE(cp15_64_regs)));
2229         BUG_ON(check_sysreg_table(invariant_sys_regs, ARRAY_SIZE(invariant_sys_regs)));
2230
2231         /* We abuse the reset function to overwrite the table itself. */
2232         for (i = 0; i < ARRAY_SIZE(invariant_sys_regs); i++)
2233                 invariant_sys_regs[i].reset(NULL, &invariant_sys_regs[i]);
2234
2235         /*
2236          * CLIDR format is awkward, so clean it up.  See ARM B4.1.20:
2237          *
2238          *   If software reads the Cache Type fields from Ctype1
2239          *   upwards, once it has seen a value of 0b000, no caches
2240          *   exist at further-out levels of the hierarchy. So, for
2241          *   example, if Ctype3 is the first Cache Type field with a
2242          *   value of 0b000, the values of Ctype4 to Ctype7 must be
2243          *   ignored.
2244          */
2245         get_clidr_el1(NULL, &clidr); /* Ugly... */
2246         cache_levels = clidr.val;
2247         for (i = 0; i < 7; i++)
2248                 if (((cache_levels >> (i*3)) & 7) == 0)
2249                         break;
2250         /* Clear all higher bits. */
2251         cache_levels &= (1 << (i*3))-1;
2252 }
2253
2254 /**
2255  * kvm_reset_sys_regs - sets system registers to reset value
2256  * @vcpu: The VCPU pointer
2257  *
2258  * This function finds the right table above and sets the registers on the
2259  * virtual CPU struct to their architecturally defined reset values.
2260  */
2261 void kvm_reset_sys_regs(struct kvm_vcpu *vcpu)
2262 {
2263         size_t num;
2264         const struct sys_reg_desc *table;
2265
2266         /* Catch someone adding a register without putting in reset entry. */
2267         memset(&vcpu->arch.ctxt.sys_regs, 0x42, sizeof(vcpu->arch.ctxt.sys_regs));
2268
2269         /* Generic chip reset first (so target could override). */
2270         reset_sys_reg_descs(vcpu, sys_reg_descs, ARRAY_SIZE(sys_reg_descs));
2271
2272         table = get_target_table(vcpu->arch.target, true, &num);
2273         reset_sys_reg_descs(vcpu, table, num);
2274
2275         for (num = 1; num < NR_SYS_REGS; num++)
2276                 if (vcpu_sys_reg(vcpu, num) == 0x4242424242424242)
2277                         panic("Didn't reset vcpu_sys_reg(%zi)", num);
2278 }