arch/arm64/kvm/hyp/vhe/switch.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 2015 - ARM Ltd
   4  * Author: Marc Zyngier <marc.zyngier@arm.com>
   5  */
   6
   7 #include <hyp/switch.h>
   8
   9 #include <linux/arm-smccc.h>
  10 #include <linux/kvm_host.h>
  11 #include <linux/types.h>
  12 #include <linux/jump_label.h>
  13 #include <linux/percpu.h>
  14 #include <uapi/linux/psci.h>
  15
  16 #include <kvm/arm_psci.h>
  17
  18 #include <asm/barrier.h>
  19 #include <asm/cpufeature.h>
  20 #include <asm/kprobes.h>
  21 #include <asm/kvm_asm.h>
  22 #include <asm/kvm_emulate.h>
  23 #include <asm/kvm_hyp.h>
  24 #include <asm/kvm_mmu.h>
  25 #include <asm/fpsimd.h>
  26 #include <asm/debug-monitors.h>
  27 #include <asm/processor.h>
  28 #include <asm/thread_info.h>
  29 #include <asm/vectors.h>
  30
  31 /* VHE specific context */
  32 DEFINE_PER_CPU(struct kvm_host_data, kvm_host_data);
  33 DEFINE_PER_CPU(struct kvm_cpu_context, kvm_hyp_ctxt);
  34 DEFINE_PER_CPU(unsigned long, kvm_hyp_vector);
  35
  36 static void __activate_traps(struct kvm_vcpu *vcpu)
  37 {
  38         u64 val;
  39
  40         ___activate_traps(vcpu);
  41
  42         if (has_cntpoff()) {
  43                 struct timer_map map;
  44
  45                 get_timer_map(vcpu, &map);
  46
  47                 /*
  48                  * We're entrering the guest. Reload the correct
  49                  * values from memory now that TGE is clear.
  50                  */
  51                 if (map.direct_ptimer == vcpu_ptimer(vcpu))
  52                         val = __vcpu_sys_reg(vcpu, CNTP_CVAL_EL0);
  53                 if (map.direct_ptimer == vcpu_hptimer(vcpu))
  54                         val = __vcpu_sys_reg(vcpu, CNTHP_CVAL_EL2);
  55
  56                 if (map.direct_ptimer) {
  57                         write_sysreg_el0(val, SYS_CNTP_CVAL);
  58                         isb();
  59                 }
  60         }
  61
  62         val = read_sysreg(cpacr_el1);
  63         val |= CPACR_ELx_TTA;
  64         val &= ~(CPACR_EL1_ZEN_EL0EN | CPACR_EL1_ZEN_EL1EN |
  65                  CPACR_EL1_SMEN_EL0EN | CPACR_EL1_SMEN_EL1EN);
  66
  67         /*
  68          * With VHE (HCR.E2H == 1), accesses to CPACR_EL1 are routed to
  69          * CPTR_EL2. In general, CPACR_EL1 has the same layout as CPTR_EL2,
  70          * except for some missing controls, such as TAM.
  71          * In this case, CPTR_EL2.TAM has the same position with or without
  72          * VHE (HCR.E2H == 1) which allows us to use here the CPTR_EL2.TAM
  73          * shift value for trapping the AMU accesses.
  74          */
  75
  76         val |= CPTR_EL2_TAM;
  77
  78         if (guest_owns_fp_regs(vcpu)) {
  79                 if (vcpu_has_sve(vcpu))
  80                         val |= CPACR_EL1_ZEN_EL0EN | CPACR_EL1_ZEN_EL1EN;
  81         } else {
  82                 val &= ~(CPACR_EL1_FPEN_EL0EN | CPACR_EL1_FPEN_EL1EN);
  83                 __activate_traps_fpsimd32(vcpu);
  84         }
  85
  86         write_sysreg(val, cpacr_el1);
  87
  88         write_sysreg(__this_cpu_read(kvm_hyp_vector), vbar_el1);
  89 }
  90 NOKPROBE_SYMBOL(__activate_traps);
  91
  92 static void __deactivate_traps(struct kvm_vcpu *vcpu)
  93 {
  94         const char *host_vectors = vectors;
  95
  96         ___deactivate_traps(vcpu);
  97
  98         write_sysreg(HCR_HOST_VHE_FLAGS, hcr_el2);
  99
 100         if (has_cntpoff()) {
 101                 struct timer_map map;
 102                 u64 val, offset;
 103
 104                 get_timer_map(vcpu, &map);
 105
 106                 /*
 107                  * We're exiting the guest. Save the latest CVAL value
 108                  * to memory and apply the offset now that TGE is set.
 109                  */
 110                 val = read_sysreg_el0(SYS_CNTP_CVAL);
 111                 if (map.direct_ptimer == vcpu_ptimer(vcpu))
 112                         __vcpu_sys_reg(vcpu, CNTP_CVAL_EL0) = val;
 113                 if (map.direct_ptimer == vcpu_hptimer(vcpu))
 114                         __vcpu_sys_reg(vcpu, CNTHP_CVAL_EL2) = val;
 115
 116                 offset = read_sysreg_s(SYS_CNTPOFF_EL2);
 117
 118                 if (map.direct_ptimer && offset) {
 119                         write_sysreg_el0(val + offset, SYS_CNTP_CVAL);
 120                         isb();
 121                 }
 122         }
 123
 124         /*
 125          * ARM errata 1165522 and 1530923 require the actual execution of the
 126          * above before we can switch to the EL2/EL0 translation regime used by
 127          * the host.
 128          */
 129         asm(ALTERNATIVE("nop", "isb", ARM64_WORKAROUND_SPECULATIVE_AT));
 130
 131         kvm_reset_cptr_el2(vcpu);
 132
 133         if (!arm64_kernel_unmapped_at_el0())
 134                 host_vectors = __this_cpu_read(this_cpu_vector);
 135         write_sysreg(host_vectors, vbar_el1);
 136 }
 137 NOKPROBE_SYMBOL(__deactivate_traps);
 138
 139 /*
 140  * Disable IRQs in __vcpu_{load,put}_{activate,deactivate}_traps() to
 141  * prevent a race condition between context switching of PMUSERENR_EL0
 142  * in __{activate,deactivate}_traps_common() and IPIs that attempts to
 143  * update PMUSERENR_EL0. See also kvm_set_pmuserenr().
 144  */
 145 static void __vcpu_load_activate_traps(struct kvm_vcpu *vcpu)
 146 {
 147         unsigned long flags;
 148
 149         local_irq_save(flags);
 150         __activate_traps_common(vcpu);
 151         local_irq_restore(flags);
 152 }
 153
 154 static void __vcpu_put_deactivate_traps(struct kvm_vcpu *vcpu)
 155 {
 156         unsigned long flags;
 157
 158         local_irq_save(flags);
 159         __deactivate_traps_common(vcpu);
 160         local_irq_restore(flags);
 161 }
 162
 163 void kvm_vcpu_load_vhe(struct kvm_vcpu *vcpu)
 164 {
 165         __vcpu_load_switch_sysregs(vcpu);
 166         __vcpu_load_activate_traps(vcpu);
 167         __load_stage2(vcpu->arch.hw_mmu, vcpu->arch.hw_mmu->arch);
 168 }
 169
 170 void kvm_vcpu_put_vhe(struct kvm_vcpu *vcpu)
 171 {
 172         __vcpu_put_deactivate_traps(vcpu);
 173         __vcpu_put_switch_sysregs(vcpu);
 174 }
 175
 176 static const exit_handler_fn hyp_exit_handlers[] = {
 177         [0 ... ESR_ELx_EC_MAX]          = NULL,
 178         [ESR_ELx_EC_CP15_32]            = kvm_hyp_handle_cp15_32,
 179         [ESR_ELx_EC_SYS64]              = kvm_hyp_handle_sysreg,
 180         [ESR_ELx_EC_SVE]                = kvm_hyp_handle_fpsimd,
 181         [ESR_ELx_EC_FP_ASIMD]           = kvm_hyp_handle_fpsimd,
 182         [ESR_ELx_EC_IABT_LOW]           = kvm_hyp_handle_iabt_low,
 183         [ESR_ELx_EC_DABT_LOW]           = kvm_hyp_handle_dabt_low,
 184         [ESR_ELx_EC_WATCHPT_LOW]        = kvm_hyp_handle_watchpt_low,
 185         [ESR_ELx_EC_PAC]                = kvm_hyp_handle_ptrauth,
 186         [ESR_ELx_EC_MOPS]               = kvm_hyp_handle_mops,
 187 };
 188
 189 static const exit_handler_fn *kvm_get_exit_handler_array(struct kvm_vcpu *vcpu)
 190 {
 191         return hyp_exit_handlers;
 192 }
 193
 194 static void early_exit_filter(struct kvm_vcpu *vcpu, u64 *exit_code)
 195 {
 196         /*
 197          * If we were in HYP context on entry, adjust the PSTATE view
 198          * so that the usual helpers work correctly.
 199          */
 200         if (unlikely(vcpu_get_flag(vcpu, VCPU_HYP_CONTEXT))) {
 201                 u64 mode = *vcpu_cpsr(vcpu) & (PSR_MODE_MASK | PSR_MODE32_BIT);
 202
 203                 switch (mode) {
 204                 case PSR_MODE_EL1t:
 205                         mode = PSR_MODE_EL2t;
 206                         break;
 207                 case PSR_MODE_EL1h:
 208                         mode = PSR_MODE_EL2h;
 209                         break;
 210                 }
 211
 212                 *vcpu_cpsr(vcpu) &= ~(PSR_MODE_MASK | PSR_MODE32_BIT);
 213                 *vcpu_cpsr(vcpu) |= mode;
 214         }
 215 }
 216
 217 /* Switch to the guest for VHE systems running in EL2 */
 218 static int __kvm_vcpu_run_vhe(struct kvm_vcpu *vcpu)
 219 {
 220         struct kvm_cpu_context *host_ctxt;
 221         struct kvm_cpu_context *guest_ctxt;
 222         u64 exit_code;
 223
 224         host_ctxt = &this_cpu_ptr(&kvm_host_data)->host_ctxt;
 225         host_ctxt->__hyp_running_vcpu = vcpu;
 226         guest_ctxt = &vcpu->arch.ctxt;
 227
 228         sysreg_save_host_state_vhe(host_ctxt);
 229
 230         /*
 231          * Note that ARM erratum 1165522 requires us to configure both stage 1
 232          * and stage 2 translation for the guest context before we clear
 233          * HCR_EL2.TGE. The stage 1 and stage 2 guest context has already been
 234          * loaded on the CPU in kvm_vcpu_load_vhe().
 235          */
 236         __activate_traps(vcpu);
 237
 238         __kvm_adjust_pc(vcpu);
 239
 240         sysreg_restore_guest_state_vhe(guest_ctxt);
 241         __debug_switch_to_guest(vcpu);
 242
 243         if (is_hyp_ctxt(vcpu))
 244                 vcpu_set_flag(vcpu, VCPU_HYP_CONTEXT);
 245         else
 246                 vcpu_clear_flag(vcpu, VCPU_HYP_CONTEXT);
 247
 248         do {
 249                 /* Jump in the fire! */
 250                 exit_code = __guest_enter(vcpu);
 251
 252                 /* And we're baaack! */
 253         } while (fixup_guest_exit(vcpu, &exit_code));
 254
 255         sysreg_save_guest_state_vhe(guest_ctxt);
 256
 257         __deactivate_traps(vcpu);
 258
 259         sysreg_restore_host_state_vhe(host_ctxt);
 260
 261         if (vcpu->arch.fp_state == FP_STATE_GUEST_OWNED)
 262                 __fpsimd_save_fpexc32(vcpu);
 263
 264         __debug_switch_to_host(vcpu);
 265
 266         return exit_code;
 267 }
 268 NOKPROBE_SYMBOL(__kvm_vcpu_run_vhe);
 269
 270 int __kvm_vcpu_run(struct kvm_vcpu *vcpu)
 271 {
 272         int ret;
 273
 274         local_daif_mask();
 275
 276         /*
 277          * Having IRQs masked via PMR when entering the guest means the GIC
 278          * will not signal the CPU of interrupts of lower priority, and the
 279          * only way to get out will be via guest exceptions.
 280          * Naturally, we want to avoid this.
 281          *
 282          * local_daif_mask() already sets GIC_PRIO_PSR_I_SET, we just need a
 283          * dsb to ensure the redistributor is forwards EL2 IRQs to the CPU.
 284          */
 285         pmr_sync();
 286
 287         ret = __kvm_vcpu_run_vhe(vcpu);
 288
 289         /*
 290          * local_daif_restore() takes care to properly restore PSTATE.DAIF
 291          * and the GIC PMR if the host is using IRQ priorities.
 292          */
 293         local_daif_restore(DAIF_PROCCTX_NOIRQ);
 294
 295         /*
 296          * When we exit from the guest we change a number of CPU configuration
 297          * parameters, such as traps.  We rely on the isb() in kvm_call_hyp*()
 298          * to make sure these changes take effect before running the host or
 299          * additional guests.
 300          */
 301         return ret;
 302 }
 303
 304 static void __hyp_call_panic(u64 spsr, u64 elr, u64 par)
 305 {
 306         struct kvm_cpu_context *host_ctxt;
 307         struct kvm_vcpu *vcpu;
 308
 309         host_ctxt = &this_cpu_ptr(&kvm_host_data)->host_ctxt;
 310         vcpu = host_ctxt->__hyp_running_vcpu;
 311
 312         __deactivate_traps(vcpu);
 313         sysreg_restore_host_state_vhe(host_ctxt);
 314
 315         panic("HYP panic:\nPS:%08llx PC:%016llx ESR:%08llx\nFAR:%016llx HPFAR:%016llx PAR:%016llx\nVCPU:%p\n",
 316               spsr, elr,
 317               read_sysreg_el2(SYS_ESR), read_sysreg_el2(SYS_FAR),
 318               read_sysreg(hpfar_el2), par, vcpu);
 319 }
 320 NOKPROBE_SYMBOL(__hyp_call_panic);
 321
 322 void __noreturn hyp_panic(void)
 323 {
 324         u64 spsr = read_sysreg_el2(SYS_SPSR);
 325         u64 elr = read_sysreg_el2(SYS_ELR);
 326         u64 par = read_sysreg_par();
 327
 328         __hyp_call_panic(spsr, elr, par);
 329         unreachable();
 330 }
 331
 332 asmlinkage void kvm_unexpected_el2_exception(void)
 333 {
 334         __kvm_unexpected_el2_exception();
 335 }