arch/arm64/kvm/hyp/switch.c

   1 /*
   2  * Copyright (C) 2015 - ARM Ltd
   3  * Author: Marc Zyngier <marc.zyngier@arm.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  16  */
  17
  18 #include <linux/arm-smccc.h>
  19 #include <linux/types.h>
  20 #include <linux/jump_label.h>
  21 #include <uapi/linux/psci.h>
  22
  23 #include <kvm/arm_psci.h>
  24
  25 #include <asm/cpufeature.h>
  26 #include <asm/extable.h>
  27 #include <asm/kprobes.h>
  28 #include <asm/kvm_asm.h>
  29 #include <asm/kvm_emulate.h>
  30 #include <asm/kvm_host.h>
  31 #include <asm/kvm_hyp.h>
  32 #include <asm/kvm_mmu.h>
  33 #include <asm/fpsimd.h>
  34 #include <asm/debug-monitors.h>
  35 #include <asm/processor.h>
  36 #include <asm/thread_info.h>
  37
  38 extern struct exception_table_entry __start___kvm_ex_table;
  39 extern struct exception_table_entry __stop___kvm_ex_table;
  40
  41 /* Check whether the FP regs were dirtied while in the host-side run loop: */
  42 static bool __hyp_text update_fp_enabled(struct kvm_vcpu *vcpu)
  43 {
  44         /*
  45          * When the system doesn't support FP/SIMD, we cannot rely on
  46          * the _TIF_FOREIGN_FPSTATE flag. However, we always inject an
  47          * abort on the very first access to FP and thus we should never
  48          * see KVM_ARM64_FP_ENABLED. For added safety, make sure we always
  49          * trap the accesses.
  50          */
  51         if (!system_supports_fpsimd() ||
  52             vcpu->arch.host_thread_info->flags & _TIF_FOREIGN_FPSTATE)
  53                 vcpu->arch.flags &= ~(KVM_ARM64_FP_ENABLED |
  54                                       KVM_ARM64_FP_HOST);
  55
  56         return !!(vcpu->arch.flags & KVM_ARM64_FP_ENABLED);
  57 }
  58
  59 /* Save the 32-bit only FPSIMD system register state */
  60 static void __hyp_text __fpsimd_save_fpexc32(struct kvm_vcpu *vcpu)
  61 {
  62         if (!vcpu_el1_is_32bit(vcpu))
  63                 return;
  64
  65         vcpu->arch.ctxt.sys_regs[FPEXC32_EL2] = read_sysreg(fpexc32_el2);
  66 }
  67
  68 static void __hyp_text __activate_traps_fpsimd32(struct kvm_vcpu *vcpu)
  69 {
  70         /*
  71          * We are about to set CPTR_EL2.TFP to trap all floating point
  72          * register accesses to EL2, however, the ARM ARM clearly states that
  73          * traps are only taken to EL2 if the operation would not otherwise
  74          * trap to EL1.  Therefore, always make sure that for 32-bit guests,
  75          * we set FPEXC.EN to prevent traps to EL1, when setting the TFP bit.
  76          * If FP/ASIMD is not implemented, FPEXC is UNDEFINED and any access to
  77          * it will cause an exception.
  78          */
  79         if (vcpu_el1_is_32bit(vcpu) && system_supports_fpsimd()) {
  80                 write_sysreg(1 << 30, fpexc32_el2);
  81                 isb();
  82         }
  83 }
  84
  85 static void __hyp_text __activate_traps_common(struct kvm_vcpu *vcpu)
  86 {
  87         /* Trap on AArch32 cp15 c15 (impdef sysregs) accesses (EL1 or EL0) */
  88         write_sysreg(1 << 15, hstr_el2);
  89
  90         /*
  91          * Make sure we trap PMU access from EL0 to EL2. Also sanitize
  92          * PMSELR_EL0 to make sure it never contains the cycle
  93          * counter, which could make a PMXEVCNTR_EL0 access UNDEF at
  94          * EL1 instead of being trapped to EL2.
  95          */
  96         write_sysreg(0, pmselr_el0);
  97         write_sysreg(ARMV8_PMU_USERENR_MASK, pmuserenr_el0);
  98         write_sysreg(vcpu->arch.mdcr_el2, mdcr_el2);
  99 }
 100
 101 static void __hyp_text __deactivate_traps_common(void)
 102 {
 103         write_sysreg(0, hstr_el2);
 104         write_sysreg(0, pmuserenr_el0);
 105 }
 106
 107 static void activate_traps_vhe(struct kvm_vcpu *vcpu)
 108 {
 109         u64 val;
 110
 111         val = read_sysreg(cpacr_el1);
 112         val |= CPACR_EL1_TTA;
 113         val &= ~CPACR_EL1_ZEN;
 114         if (!update_fp_enabled(vcpu)) {
 115                 val &= ~CPACR_EL1_FPEN;
 116                 __activate_traps_fpsimd32(vcpu);
 117         }
 118
 119         write_sysreg(val, cpacr_el1);
 120
 121         write_sysreg(kvm_get_hyp_vector(), vbar_el1);
 122 }
 123 NOKPROBE_SYMBOL(activate_traps_vhe);
 124
 125 static void __hyp_text __activate_traps_nvhe(struct kvm_vcpu *vcpu)
 126 {
 127         u64 val;
 128
 129         __activate_traps_common(vcpu);
 130
 131         val = CPTR_EL2_DEFAULT;
 132         val |= CPTR_EL2_TTA | CPTR_EL2_TZ;
 133         if (!update_fp_enabled(vcpu)) {
 134                 val |= CPTR_EL2_TFP;
 135                 __activate_traps_fpsimd32(vcpu);
 136         }
 137
 138         write_sysreg(val, cptr_el2);
 139 }
 140
 141 static void __hyp_text __activate_traps(struct kvm_vcpu *vcpu)
 142 {
 143         u64 hcr = vcpu->arch.hcr_el2;
 144
 145         write_sysreg(hcr, hcr_el2);
 146
 147         if (cpus_have_const_cap(ARM64_HAS_RAS_EXTN) && (hcr & HCR_VSE))
 148                 write_sysreg_s(vcpu->arch.vsesr_el2, SYS_VSESR_EL2);
 149
 150         if (has_vhe())
 151                 activate_traps_vhe(vcpu);
 152         else
 153                 __activate_traps_nvhe(vcpu);
 154 }
 155
 156 static void deactivate_traps_vhe(void)
 157 {
 158         extern char vectors[];  /* kernel exception vectors */
 159         write_sysreg(HCR_HOST_VHE_FLAGS, hcr_el2);
 160         write_sysreg(CPACR_EL1_DEFAULT, cpacr_el1);
 161         write_sysreg(vectors, vbar_el1);
 162 }
 163 NOKPROBE_SYMBOL(deactivate_traps_vhe);
 164
 165 static void __hyp_text __deactivate_traps_nvhe(void)
 166 {
 167         u64 mdcr_el2 = read_sysreg(mdcr_el2);
 168
 169         __deactivate_traps_common();
 170
 171         mdcr_el2 &= MDCR_EL2_HPMN_MASK;
 172         mdcr_el2 |= MDCR_EL2_E2PB_MASK << MDCR_EL2_E2PB_SHIFT;
 173
 174         write_sysreg(mdcr_el2, mdcr_el2);
 175         write_sysreg(HCR_HOST_NVHE_FLAGS, hcr_el2);
 176         write_sysreg(CPTR_EL2_DEFAULT, cptr_el2);
 177 }
 178
 179 static void __hyp_text __deactivate_traps(struct kvm_vcpu *vcpu)
 180 {
 181         /*
 182          * If we pended a virtual abort, preserve it until it gets
 183          * cleared. See D1.14.3 (Virtual Interrupts) for details, but
 184          * the crucial bit is "On taking a vSError interrupt,
 185          * HCR_EL2.VSE is cleared to 0."
 186          */
 187         if (vcpu->arch.hcr_el2 & HCR_VSE)
 188                 vcpu->arch.hcr_el2 = read_sysreg(hcr_el2);
 189
 190         if (has_vhe())
 191                 deactivate_traps_vhe();
 192         else
 193                 __deactivate_traps_nvhe();
 194 }
 195
 196 void activate_traps_vhe_load(struct kvm_vcpu *vcpu)
 197 {
 198         __activate_traps_common(vcpu);
 199 }
 200
 201 void deactivate_traps_vhe_put(void)
 202 {
 203         u64 mdcr_el2 = read_sysreg(mdcr_el2);
 204
 205         mdcr_el2 &= MDCR_EL2_HPMN_MASK |
 206                     MDCR_EL2_E2PB_MASK << MDCR_EL2_E2PB_SHIFT |
 207                     MDCR_EL2_TPMS;
 208
 209         write_sysreg(mdcr_el2, mdcr_el2);
 210
 211         __deactivate_traps_common();
 212 }
 213
 214 static void __hyp_text __activate_vm(struct kvm *kvm)
 215 {
 216         write_sysreg(kvm->arch.vttbr, vttbr_el2);
 217 }
 218
 219 static void __hyp_text __deactivate_vm(struct kvm_vcpu *vcpu)
 220 {
 221         write_sysreg(0, vttbr_el2);
 222 }
 223
 224 /* Save VGICv3 state on non-VHE systems */
 225 static void __hyp_text __hyp_vgic_save_state(struct kvm_vcpu *vcpu)
 226 {
 227         if (static_branch_unlikely(&kvm_vgic_global_state.gicv3_cpuif)) {
 228                 __vgic_v3_save_state(vcpu);
 229                 __vgic_v3_deactivate_traps(vcpu);
 230         }
 231 }
 232
 233 /* Restore VGICv3 state on non_VEH systems */
 234 static void __hyp_text __hyp_vgic_restore_state(struct kvm_vcpu *vcpu)
 235 {
 236         if (static_branch_unlikely(&kvm_vgic_global_state.gicv3_cpuif)) {
 237                 __vgic_v3_activate_traps(vcpu);
 238                 __vgic_v3_restore_state(vcpu);
 239         }
 240 }
 241
 242 static bool __hyp_text __true_value(void)
 243 {
 244         return true;
 245 }
 246
 247 static bool __hyp_text __false_value(void)
 248 {
 249         return false;
 250 }
 251
 252 static hyp_alternate_select(__check_arm_834220,
 253                             __false_value, __true_value,
 254                             ARM64_WORKAROUND_834220);
 255
 256 static bool __hyp_text __translate_far_to_hpfar(u64 far, u64 *hpfar)
 257 {
 258         u64 par, tmp;
 259
 260         /*
 261          * Resolve the IPA the hard way using the guest VA.
 262          *
 263          * Stage-1 translation already validated the memory access
 264          * rights. As such, we can use the EL1 translation regime, and
 265          * don't have to distinguish between EL0 and EL1 access.
 266          *
 267          * We do need to save/restore PAR_EL1 though, as we haven't
 268          * saved the guest context yet, and we may return early...
 269          */
 270         par = read_sysreg(par_el1);
 271         if (!__kvm_at("s1e1r", far))
 272                 tmp = read_sysreg(par_el1);
 273         else
 274                 tmp = 1; /* back to the guest */
 275         write_sysreg(par, par_el1);
 276
 277         if (unlikely(tmp & 1))
 278                 return false; /* Translation failed, back to guest */
 279
 280         /* Convert PAR to HPFAR format */
 281         *hpfar = ((tmp >> 12) & ((1UL << 36) - 1)) << 4;
 282         return true;
 283 }
 284
 285 static bool __hyp_text __populate_fault_info(struct kvm_vcpu *vcpu)
 286 {
 287         u8 ec;
 288         u64 esr;
 289         u64 hpfar, far;
 290
 291         esr = vcpu->arch.fault.esr_el2;
 292         ec = ESR_ELx_EC(esr);
 293
 294         if (ec != ESR_ELx_EC_DABT_LOW && ec != ESR_ELx_EC_IABT_LOW)
 295                 return true;
 296
 297         far = read_sysreg_el2(far);
 298
 299         /*
 300          * The HPFAR can be invalid if the stage 2 fault did not
 301          * happen during a stage 1 page table walk (the ESR_EL2.S1PTW
 302          * bit is clear) and one of the two following cases are true:
 303          *   1. The fault was due to a permission fault
 304          *   2. The processor carries errata 834220
 305          *
 306          * Therefore, for all non S1PTW faults where we either have a
 307          * permission fault or the errata workaround is enabled, we
 308          * resolve the IPA using the AT instruction.
 309          */
 310         if (!(esr & ESR_ELx_S1PTW) &&
 311             (__check_arm_834220()() || (esr & ESR_ELx_FSC_TYPE) == FSC_PERM)) {
 312                 if (!__translate_far_to_hpfar(far, &hpfar))
 313                         return false;
 314         } else {
 315                 hpfar = read_sysreg(hpfar_el2);
 316         }
 317
 318         vcpu->arch.fault.far_el2 = far;
 319         vcpu->arch.fault.hpfar_el2 = hpfar;
 320         return true;
 321 }
 322
 323 /* Skip an instruction which has been emulated. Returns true if
 324  * execution can continue or false if we need to exit hyp mode because
 325  * single-step was in effect.
 326  */
 327 static bool __hyp_text __skip_instr(struct kvm_vcpu *vcpu)
 328 {
 329         *vcpu_pc(vcpu) = read_sysreg_el2(elr);
 330
 331         if (vcpu_mode_is_32bit(vcpu)) {
 332                 vcpu->arch.ctxt.gp_regs.regs.pstate = read_sysreg_el2(spsr);
 333                 kvm_skip_instr32(vcpu, kvm_vcpu_trap_il_is32bit(vcpu));
 334                 write_sysreg_el2(vcpu->arch.ctxt.gp_regs.regs.pstate, spsr);
 335         } else {
 336                 *vcpu_pc(vcpu) += 4;
 337         }
 338
 339         write_sysreg_el2(*vcpu_pc(vcpu), elr);
 340
 341         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
 342                 vcpu->arch.fault.esr_el2 =
 343                         (ESR_ELx_EC_SOFTSTP_LOW << ESR_ELx_EC_SHIFT) | 0x22;
 344                 return false;
 345         } else {
 346                 return true;
 347         }
 348 }
 349
 350 static bool __hyp_text __hyp_switch_fpsimd(struct kvm_vcpu *vcpu)
 351 {
 352         struct user_fpsimd_state *host_fpsimd = vcpu->arch.host_fpsimd_state;
 353
 354         if (has_vhe())
 355                 write_sysreg(read_sysreg(cpacr_el1) | CPACR_EL1_FPEN,
 356                              cpacr_el1);
 357         else
 358                 write_sysreg(read_sysreg(cptr_el2) & ~(u64)CPTR_EL2_TFP,
 359                              cptr_el2);
 360
 361         isb();
 362
 363         if (vcpu->arch.flags & KVM_ARM64_FP_HOST) {
 364                 /*
 365                  * In the SVE case, VHE is assumed: it is enforced by
 366                  * Kconfig and kvm_arch_init().
 367                  */
 368                 if (system_supports_sve() &&
 369                     (vcpu->arch.flags & KVM_ARM64_HOST_SVE_IN_USE)) {
 370                         struct thread_struct *thread = container_of(
 371                                 host_fpsimd,
 372                                 struct thread_struct, uw.fpsimd_state);
 373
 374                         sve_save_state(sve_pffr(thread), &host_fpsimd->fpsr);
 375                 } else {
 376                         __fpsimd_save_state(host_fpsimd);
 377                 }
 378
 379                 vcpu->arch.flags &= ~KVM_ARM64_FP_HOST;
 380         }
 381
 382         __fpsimd_restore_state(&vcpu->arch.ctxt.gp_regs.fp_regs);
 383
 384         /* Skip restoring fpexc32 for AArch64 guests */
 385         if (!(read_sysreg(hcr_el2) & HCR_RW))
 386                 write_sysreg(vcpu->arch.ctxt.sys_regs[FPEXC32_EL2],
 387                              fpexc32_el2);
 388
 389         vcpu->arch.flags |= KVM_ARM64_FP_ENABLED;
 390
 391         return true;
 392 }
 393
 394 /*
 395  * Return true when we were able to fixup the guest exit and should return to
 396  * the guest, false when we should restore the host state and return to the
 397  * main run loop.
 398  */
 399 static bool __hyp_text fixup_guest_exit(struct kvm_vcpu *vcpu, u64 *exit_code)
 400 {
 401         if (ARM_EXCEPTION_CODE(*exit_code) != ARM_EXCEPTION_IRQ)
 402                 vcpu->arch.fault.esr_el2 = read_sysreg_el2(esr);
 403
 404         /*
 405          * We're using the raw exception code in order to only process
 406          * the trap if no SError is pending. We will come back to the
 407          * same PC once the SError has been injected, and replay the
 408          * trapping instruction.
 409          */
 410         if (*exit_code != ARM_EXCEPTION_TRAP)
 411                 goto exit;
 412
 413         /*
 414          * We trap the first access to the FP/SIMD to save the host context
 415          * and restore the guest context lazily.
 416          * If FP/SIMD is not implemented, handle the trap and inject an
 417          * undefined instruction exception to the guest.
 418          */
 419         if (system_supports_fpsimd() &&
 420             kvm_vcpu_trap_get_class(vcpu) == ESR_ELx_EC_FP_ASIMD)
 421                 return __hyp_switch_fpsimd(vcpu);
 422
 423         if (!__populate_fault_info(vcpu))
 424                 return true;
 425
 426         if (static_branch_unlikely(&vgic_v2_cpuif_trap)) {
 427                 bool valid;
 428
 429                 valid = kvm_vcpu_trap_get_class(vcpu) == ESR_ELx_EC_DABT_LOW &&
 430                         kvm_vcpu_trap_get_fault_type(vcpu) == FSC_FAULT &&
 431                         kvm_vcpu_dabt_isvalid(vcpu) &&
 432                         !kvm_vcpu_dabt_isextabt(vcpu) &&
 433                         !kvm_vcpu_abt_iss1tw(vcpu);
 434
 435                 if (valid) {
 436                         int ret = __vgic_v2_perform_cpuif_access(vcpu);
 437
 438                         if (ret ==  1 && __skip_instr(vcpu))
 439                                 return true;
 440
 441                         if (ret == -1) {
 442                                 /* Promote an illegal access to an
 443                                  * SError. If we would be returning
 444                                  * due to single-step clear the SS
 445                                  * bit so handle_exit knows what to
 446                                  * do after dealing with the error.
 447                                  */
 448                                 if (!__skip_instr(vcpu))
 449                                         *vcpu_cpsr(vcpu) &= ~DBG_SPSR_SS;
 450                                 *exit_code = ARM_EXCEPTION_EL1_SERROR;
 451                         }
 452
 453                         goto exit;
 454                 }
 455         }
 456
 457         if (static_branch_unlikely(&vgic_v3_cpuif_trap) &&
 458             (kvm_vcpu_trap_get_class(vcpu) == ESR_ELx_EC_SYS64 ||
 459              kvm_vcpu_trap_get_class(vcpu) == ESR_ELx_EC_CP15_32)) {
 460                 int ret = __vgic_v3_perform_cpuif_access(vcpu);
 461
 462                 if (ret == 1 && __skip_instr(vcpu))
 463                         return true;
 464         }
 465
 466 exit:
 467         /* Return to the host kernel and handle the exit */
 468         return false;
 469 }
 470
 471 static inline bool __hyp_text __needs_ssbd_off(struct kvm_vcpu *vcpu)
 472 {
 473         if (!cpus_have_const_cap(ARM64_SSBD))
 474                 return false;
 475
 476         return !(vcpu->arch.workaround_flags & VCPU_WORKAROUND_2_FLAG);
 477 }
 478
 479 static void __hyp_text __set_guest_arch_workaround_state(struct kvm_vcpu *vcpu)
 480 {
 481 #ifdef CONFIG_ARM64_SSBD
 482         /*
 483          * The host runs with the workaround always present. If the
 484          * guest wants it disabled, so be it...
 485          */
 486         if (__needs_ssbd_off(vcpu) &&
 487             __hyp_this_cpu_read(arm64_ssbd_callback_required))
 488                 arm_smccc_1_1_smc(ARM_SMCCC_ARCH_WORKAROUND_2, 0, NULL);
 489 #endif
 490 }
 491
 492 static void __hyp_text __set_host_arch_workaround_state(struct kvm_vcpu *vcpu)
 493 {
 494 #ifdef CONFIG_ARM64_SSBD
 495         /*
 496          * If the guest has disabled the workaround, bring it back on.
 497          */
 498         if (__needs_ssbd_off(vcpu) &&
 499             __hyp_this_cpu_read(arm64_ssbd_callback_required))
 500                 arm_smccc_1_1_smc(ARM_SMCCC_ARCH_WORKAROUND_2, 1, NULL);
 501 #endif
 502 }
 503
 504 /* Switch to the guest for VHE systems running in EL2 */
 505 int kvm_vcpu_run_vhe(struct kvm_vcpu *vcpu)
 506 {
 507         struct kvm_cpu_context *host_ctxt;
 508         struct kvm_cpu_context *guest_ctxt;
 509         u64 exit_code;
 510
 511         host_ctxt = vcpu->arch.host_cpu_context;
 512         host_ctxt->__hyp_running_vcpu = vcpu;
 513         guest_ctxt = &vcpu->arch.ctxt;
 514
 515         sysreg_save_host_state_vhe(host_ctxt);
 516
 517         __activate_traps(vcpu);
 518         __activate_vm(vcpu->kvm);
 519
 520         sysreg_restore_guest_state_vhe(guest_ctxt);
 521         __debug_switch_to_guest(vcpu);
 522
 523         __set_guest_arch_workaround_state(vcpu);
 524
 525         do {
 526                 /* Jump in the fire! */
 527                 exit_code = __guest_enter(vcpu, host_ctxt);
 528
 529                 /* And we're baaack! */
 530         } while (fixup_guest_exit(vcpu, &exit_code));
 531
 532         __set_host_arch_workaround_state(vcpu);
 533
 534         sysreg_save_guest_state_vhe(guest_ctxt);
 535
 536         __deactivate_traps(vcpu);
 537
 538         sysreg_restore_host_state_vhe(host_ctxt);
 539
 540         if (vcpu->arch.flags & KVM_ARM64_FP_ENABLED)
 541                 __fpsimd_save_fpexc32(vcpu);
 542
 543         __debug_switch_to_host(vcpu);
 544
 545         return exit_code;
 546 }
 547 NOKPROBE_SYMBOL(kvm_vcpu_run_vhe);
 548
 549 /* Switch to the guest for legacy non-VHE systems */
 550 int __hyp_text __kvm_vcpu_run_nvhe(struct kvm_vcpu *vcpu)
 551 {
 552         struct kvm_cpu_context *host_ctxt;
 553         struct kvm_cpu_context *guest_ctxt;
 554         u64 exit_code;
 555
 556         vcpu = kern_hyp_va(vcpu);
 557
 558         host_ctxt = kern_hyp_va(vcpu->arch.host_cpu_context);
 559         host_ctxt->__hyp_running_vcpu = vcpu;
 560         guest_ctxt = &vcpu->arch.ctxt;
 561
 562         __sysreg_save_state_nvhe(host_ctxt);
 563         __debug_save_host_buffers_nvhe(vcpu);
 564
 565         __activate_traps(vcpu);
 566         __activate_vm(kern_hyp_va(vcpu->kvm));
 567
 568         __hyp_vgic_restore_state(vcpu);
 569         __timer_enable_traps(vcpu);
 570
 571         /*
 572          * We must restore the 32-bit state before the sysregs, thanks
 573          * to erratum #852523 (Cortex-A57) or #853709 (Cortex-A72).
 574          */
 575         __sysreg32_restore_state(vcpu);
 576         __sysreg_restore_state_nvhe(guest_ctxt);
 577         __debug_switch_to_guest(vcpu);
 578
 579         __set_guest_arch_workaround_state(vcpu);
 580
 581         do {
 582                 /* Jump in the fire! */
 583                 exit_code = __guest_enter(vcpu, host_ctxt);
 584
 585                 /* And we're baaack! */
 586         } while (fixup_guest_exit(vcpu, &exit_code));
 587
 588         __set_host_arch_workaround_state(vcpu);
 589
 590         __sysreg_save_state_nvhe(guest_ctxt);
 591         __sysreg32_save_state(vcpu);
 592         __timer_disable_traps(vcpu);
 593         __hyp_vgic_save_state(vcpu);
 594
 595         __deactivate_traps(vcpu);
 596         __deactivate_vm(vcpu);
 597
 598         __sysreg_restore_state_nvhe(host_ctxt);
 599
 600         if (vcpu->arch.flags & KVM_ARM64_FP_ENABLED)
 601                 __fpsimd_save_fpexc32(vcpu);
 602
 603         __debug_switch_to_host(vcpu);
 604         /*
 605          * This must come after restoring the host sysregs, since a non-VHE
 606          * system may enable SPE here and make use of the TTBRs.
 607          */
 608         __debug_restore_host_buffers_nvhe(vcpu);
 609
 610         return exit_code;
 611 }
 612
 613 static const char __hyp_panic_string[] = "HYP panic:\nPS:%08llx PC:%016llx ESR:%08llx\nFAR:%016llx HPFAR:%016llx PAR:%016llx\nVCPU:%p\n";
 614
 615 static void __hyp_text __hyp_call_panic_nvhe(u64 spsr, u64 elr, u64 par,
 616                                              struct kvm_cpu_context *__host_ctxt)
 617 {
 618         struct kvm_vcpu *vcpu;
 619         unsigned long str_va;
 620
 621         vcpu = __host_ctxt->__hyp_running_vcpu;
 622
 623         if (read_sysreg(vttbr_el2)) {
 624                 __timer_disable_traps(vcpu);
 625                 __deactivate_traps(vcpu);
 626                 __deactivate_vm(vcpu);
 627                 __sysreg_restore_state_nvhe(__host_ctxt);
 628         }
 629
 630         /*
 631          * Force the panic string to be loaded from the literal pool,
 632          * making sure it is a kernel address and not a PC-relative
 633          * reference.
 634          */
 635         asm volatile("ldr %0, =%1" : "=r" (str_va) : "S" (__hyp_panic_string));
 636
 637         __hyp_do_panic(str_va,
 638                        spsr,  elr,
 639                        read_sysreg(esr_el2),   read_sysreg_el2(far),
 640                        read_sysreg(hpfar_el2), par, vcpu);
 641 }
 642
 643 static void __hyp_call_panic_vhe(u64 spsr, u64 elr, u64 par,
 644                                  struct kvm_cpu_context *host_ctxt)
 645 {
 646         struct kvm_vcpu *vcpu;
 647         vcpu = host_ctxt->__hyp_running_vcpu;
 648
 649         __deactivate_traps(vcpu);
 650         sysreg_restore_host_state_vhe(host_ctxt);
 651
 652         panic(__hyp_panic_string,
 653               spsr,  elr,
 654               read_sysreg_el2(esr),   read_sysreg_el2(far),
 655               read_sysreg(hpfar_el2), par, vcpu);
 656 }
 657 NOKPROBE_SYMBOL(__hyp_call_panic_vhe);
 658
 659 void __hyp_text __noreturn hyp_panic(struct kvm_cpu_context *host_ctxt)
 660 {
 661         u64 spsr = read_sysreg_el2(spsr);
 662         u64 elr = read_sysreg_el2(elr);
 663         u64 par = read_sysreg(par_el1);
 664
 665         if (!has_vhe())
 666                 __hyp_call_panic_nvhe(spsr, elr, par, host_ctxt);
 667         else
 668                 __hyp_call_panic_vhe(spsr, elr, par, host_ctxt);
 669
 670         unreachable();
 671 }
 672
 673 asmlinkage void __hyp_text kvm_unexpected_el2_exception(void)
 674 {
 675         unsigned long addr, fixup;
 676         struct kvm_cpu_context *host_ctxt;
 677         struct exception_table_entry *entry, *end;
 678         unsigned long elr_el2 = read_sysreg(elr_el2);
 679
 680         entry = hyp_symbol_addr(__start___kvm_ex_table);
 681         end = hyp_symbol_addr(__stop___kvm_ex_table);
 682         host_ctxt = __hyp_this_cpu_ptr(kvm_host_cpu_state);
 683
 684         while (entry < end) {
 685                 addr = (unsigned long)&entry->insn + entry->insn;
 686                 fixup = (unsigned long)&entry->fixup + entry->fixup;
 687
 688                 if (addr != elr_el2) {
 689                         entry++;
 690                         continue;
 691                 }
 692
 693                 write_sysreg(fixup, elr_el2);
 694                 return;
 695         }
 696
 697         hyp_panic(host_ctxt);
 698 }