arch/arm64/kvm/hyp/switch.c

   1 /*
   2  * Copyright (C) 2015 - ARM Ltd
   3  * Author: Marc Zyngier <marc.zyngier@arm.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  16  */
  17
  18 #include <linux/arm-smccc.h>
  19 #include <linux/types.h>
  20 #include <linux/jump_label.h>
  21 #include <uapi/linux/psci.h>
  22
  23 #include <kvm/arm_psci.h>
  24
  25 #include <asm/kvm_asm.h>
  26 #include <asm/kvm_emulate.h>
  27 #include <asm/kvm_hyp.h>
  28 #include <asm/uaccess.h>
  29
  30 extern struct exception_table_entry __start___kvm_ex_table;
  31 extern struct exception_table_entry __stop___kvm_ex_table;
  32
  33 static bool __hyp_text __fpsimd_enabled_nvhe(void)
  34 {
  35         return !(read_sysreg(cptr_el2) & CPTR_EL2_TFP);
  36 }
  37
  38 static bool __hyp_text __fpsimd_enabled_vhe(void)
  39 {
  40         return !!(read_sysreg(cpacr_el1) & CPACR_EL1_FPEN);
  41 }
  42
  43 static hyp_alternate_select(__fpsimd_is_enabled,
  44                             __fpsimd_enabled_nvhe, __fpsimd_enabled_vhe,
  45                             ARM64_HAS_VIRT_HOST_EXTN);
  46
  47 bool __hyp_text __fpsimd_enabled(void)
  48 {
  49         return __fpsimd_is_enabled()();
  50 }
  51
  52 static void __hyp_text __activate_traps_vhe(void)
  53 {
  54         u64 val;
  55
  56         val = read_sysreg(cpacr_el1);
  57         val |= CPACR_EL1_TTA;
  58         val &= ~CPACR_EL1_FPEN;
  59         write_sysreg(val, cpacr_el1);
  60
  61         write_sysreg(kvm_get_hyp_vector(), vbar_el1);
  62 }
  63
  64 static void __hyp_text __activate_traps_nvhe(void)
  65 {
  66         u64 val;
  67
  68         val = CPTR_EL2_DEFAULT;
  69         val |= CPTR_EL2_TTA | CPTR_EL2_TFP;
  70         write_sysreg(val, cptr_el2);
  71 }
  72
  73 static hyp_alternate_select(__activate_traps_arch,
  74                             __activate_traps_nvhe, __activate_traps_vhe,
  75                             ARM64_HAS_VIRT_HOST_EXTN);
  76
  77 static void __hyp_text __activate_traps(struct kvm_vcpu *vcpu)
  78 {
  79         u64 val;
  80
  81         /*
  82          * We are about to set CPTR_EL2.TFP to trap all floating point
  83          * register accesses to EL2, however, the ARM ARM clearly states that
  84          * traps are only taken to EL2 if the operation would not otherwise
  85          * trap to EL1.  Therefore, always make sure that for 32-bit guests,
  86          * we set FPEXC.EN to prevent traps to EL1, when setting the TFP bit.
  87          */
  88         val = vcpu->arch.hcr_el2;
  89         if (!(val & HCR_RW)) {
  90                 write_sysreg(1 << 30, fpexc32_el2);
  91                 isb();
  92         }
  93         write_sysreg(val, hcr_el2);
  94         /* Trap on AArch32 cp15 c15 accesses (EL1 or EL0) */
  95         write_sysreg(1 << 15, hstr_el2);
  96         /*
  97          * Make sure we trap PMU access from EL0 to EL2. Also sanitize
  98          * PMSELR_EL0 to make sure it never contains the cycle
  99          * counter, which could make a PMXEVCNTR_EL0 access UNDEF at
 100          * EL1 instead of being trapped to EL2.
 101          */
 102         write_sysreg(0, pmselr_el0);
 103         write_sysreg(ARMV8_PMU_USERENR_MASK, pmuserenr_el0);
 104         write_sysreg(vcpu->arch.mdcr_el2, mdcr_el2);
 105         __activate_traps_arch()();
 106 }
 107
 108 static void __hyp_text __deactivate_traps_vhe(void)
 109 {
 110         extern char vectors[];  /* kernel exception vectors */
 111
 112         write_sysreg(HCR_HOST_VHE_FLAGS, hcr_el2);
 113         write_sysreg(CPACR_EL1_FPEN, cpacr_el1);
 114         write_sysreg(vectors, vbar_el1);
 115 }
 116
 117 static void __hyp_text __deactivate_traps_nvhe(void)
 118 {
 119         write_sysreg(HCR_HOST_NVHE_FLAGS, hcr_el2);
 120         write_sysreg(CPTR_EL2_DEFAULT, cptr_el2);
 121 }
 122
 123 static hyp_alternate_select(__deactivate_traps_arch,
 124                             __deactivate_traps_nvhe, __deactivate_traps_vhe,
 125                             ARM64_HAS_VIRT_HOST_EXTN);
 126
 127 static void __hyp_text __deactivate_traps(struct kvm_vcpu *vcpu)
 128 {
 129         /*
 130          * If we pended a virtual abort, preserve it until it gets
 131          * cleared. See D1.14.3 (Virtual Interrupts) for details, but
 132          * the crucial bit is "On taking a vSError interrupt,
 133          * HCR_EL2.VSE is cleared to 0."
 134          */
 135         if (vcpu->arch.hcr_el2 & HCR_VSE)
 136                 vcpu->arch.hcr_el2 = read_sysreg(hcr_el2);
 137
 138         __deactivate_traps_arch()();
 139         write_sysreg(0, hstr_el2);
 140         write_sysreg(read_sysreg(mdcr_el2) & MDCR_EL2_HPMN_MASK, mdcr_el2);
 141         write_sysreg(0, pmuserenr_el0);
 142 }
 143
 144 static void __hyp_text __activate_vm(struct kvm_vcpu *vcpu)
 145 {
 146         struct kvm *kvm = kern_hyp_va(vcpu->kvm);
 147         write_sysreg(kvm->arch.vttbr, vttbr_el2);
 148 }
 149
 150 static void __hyp_text __deactivate_vm(struct kvm_vcpu *vcpu)
 151 {
 152         write_sysreg(0, vttbr_el2);
 153 }
 154
 155 static void __hyp_text __vgic_save_state(struct kvm_vcpu *vcpu)
 156 {
 157         if (static_branch_unlikely(&kvm_vgic_global_state.gicv3_cpuif))
 158                 __vgic_v3_save_state(vcpu);
 159         else
 160                 __vgic_v2_save_state(vcpu);
 161
 162         write_sysreg(read_sysreg(hcr_el2) & ~HCR_INT_OVERRIDE, hcr_el2);
 163 }
 164
 165 static void __hyp_text __vgic_restore_state(struct kvm_vcpu *vcpu)
 166 {
 167         u64 val;
 168
 169         val = read_sysreg(hcr_el2);
 170         val |=  HCR_INT_OVERRIDE;
 171         val |= vcpu->arch.irq_lines;
 172         write_sysreg(val, hcr_el2);
 173
 174         if (static_branch_unlikely(&kvm_vgic_global_state.gicv3_cpuif))
 175                 __vgic_v3_restore_state(vcpu);
 176         else
 177                 __vgic_v2_restore_state(vcpu);
 178 }
 179
 180 static bool __hyp_text __true_value(void)
 181 {
 182         return true;
 183 }
 184
 185 static bool __hyp_text __false_value(void)
 186 {
 187         return false;
 188 }
 189
 190 static hyp_alternate_select(__check_arm_834220,
 191                             __false_value, __true_value,
 192                             ARM64_WORKAROUND_834220);
 193
 194 static bool __hyp_text __translate_far_to_hpfar(u64 far, u64 *hpfar)
 195 {
 196         u64 par, tmp;
 197
 198         /*
 199          * Resolve the IPA the hard way using the guest VA.
 200          *
 201          * Stage-1 translation already validated the memory access
 202          * rights. As such, we can use the EL1 translation regime, and
 203          * don't have to distinguish between EL0 and EL1 access.
 204          *
 205          * We do need to save/restore PAR_EL1 though, as we haven't
 206          * saved the guest context yet, and we may return early...
 207          */
 208         par = read_sysreg(par_el1);
 209         if (!__kvm_at("s1e1r", far))
 210                 tmp = read_sysreg(par_el1);
 211         else
 212                 tmp = 1; /* back to the guest */
 213         write_sysreg(par, par_el1);
 214
 215         if (unlikely(tmp & 1))
 216                 return false; /* Translation failed, back to guest */
 217
 218         /* Convert PAR to HPFAR format */
 219         *hpfar = ((tmp >> 12) & ((1UL << 36) - 1)) << 4;
 220         return true;
 221 }
 222
 223 static bool __hyp_text __populate_fault_info(struct kvm_vcpu *vcpu)
 224 {
 225         u64 esr = read_sysreg_el2(esr);
 226         u8 ec = ESR_ELx_EC(esr);
 227         u64 hpfar, far;
 228
 229         vcpu->arch.fault.esr_el2 = esr;
 230
 231         if (ec != ESR_ELx_EC_DABT_LOW && ec != ESR_ELx_EC_IABT_LOW)
 232                 return true;
 233
 234         far = read_sysreg_el2(far);
 235
 236         /*
 237          * The HPFAR can be invalid if the stage 2 fault did not
 238          * happen during a stage 1 page table walk (the ESR_EL2.S1PTW
 239          * bit is clear) and one of the two following cases are true:
 240          *   1. The fault was due to a permission fault
 241          *   2. The processor carries errata 834220
 242          *
 243          * Therefore, for all non S1PTW faults where we either have a
 244          * permission fault or the errata workaround is enabled, we
 245          * resolve the IPA using the AT instruction.
 246          */
 247         if (!(esr & ESR_ELx_S1PTW) &&
 248             (__check_arm_834220()() || (esr & ESR_ELx_FSC_TYPE) == FSC_PERM)) {
 249                 if (!__translate_far_to_hpfar(far, &hpfar))
 250                         return false;
 251         } else {
 252                 hpfar = read_sysreg(hpfar_el2);
 253         }
 254
 255         vcpu->arch.fault.far_el2 = far;
 256         vcpu->arch.fault.hpfar_el2 = hpfar;
 257         return true;
 258 }
 259
 260 static void __hyp_text __skip_instr(struct kvm_vcpu *vcpu)
 261 {
 262         *vcpu_pc(vcpu) = read_sysreg_el2(elr);
 263
 264         if (vcpu_mode_is_32bit(vcpu)) {
 265                 vcpu->arch.ctxt.gp_regs.regs.pstate = read_sysreg_el2(spsr);
 266                 kvm_skip_instr32(vcpu, kvm_vcpu_trap_il_is32bit(vcpu));
 267                 write_sysreg_el2(vcpu->arch.ctxt.gp_regs.regs.pstate, spsr);
 268         } else {
 269                 *vcpu_pc(vcpu) += 4;
 270         }
 271
 272         write_sysreg_el2(*vcpu_pc(vcpu), elr);
 273 }
 274
 275 static inline bool __hyp_text __needs_ssbd_off(struct kvm_vcpu *vcpu)
 276 {
 277         if (!cpus_have_cap(ARM64_SSBD))
 278                 return false;
 279
 280         return !(vcpu->arch.workaround_flags & VCPU_WORKAROUND_2_FLAG);
 281 }
 282
 283 static void __hyp_text __set_guest_arch_workaround_state(struct kvm_vcpu *vcpu)
 284 {
 285 #ifdef CONFIG_ARM64_SSBD
 286         /*
 287          * The host runs with the workaround always present. If the
 288          * guest wants it disabled, so be it...
 289          */
 290         if (__needs_ssbd_off(vcpu) &&
 291             __hyp_this_cpu_read(arm64_ssbd_callback_required))
 292                 arm_smccc_1_1_smc(ARM_SMCCC_ARCH_WORKAROUND_2, 0, NULL);
 293 #endif
 294 }
 295
 296 static void __hyp_text __set_host_arch_workaround_state(struct kvm_vcpu *vcpu)
 297 {
 298 #ifdef CONFIG_ARM64_SSBD
 299         /*
 300          * If the guest has disabled the workaround, bring it back on.
 301          */
 302         if (__needs_ssbd_off(vcpu) &&
 303             __hyp_this_cpu_read(arm64_ssbd_callback_required))
 304                 arm_smccc_1_1_smc(ARM_SMCCC_ARCH_WORKAROUND_2, 1, NULL);
 305 #endif
 306 }
 307
 308 int __hyp_text __kvm_vcpu_run(struct kvm_vcpu *vcpu)
 309 {
 310         struct kvm_cpu_context *host_ctxt;
 311         struct kvm_cpu_context *guest_ctxt;
 312         bool fp_enabled;
 313         u64 exit_code;
 314
 315         vcpu = kern_hyp_va(vcpu);
 316
 317         host_ctxt = kern_hyp_va(vcpu->arch.host_cpu_context);
 318         host_ctxt->__hyp_running_vcpu = vcpu;
 319         guest_ctxt = &vcpu->arch.ctxt;
 320
 321         __sysreg_save_host_state(host_ctxt);
 322         __debug_cond_save_host_state(vcpu);
 323
 324         __activate_traps(vcpu);
 325         __activate_vm(vcpu);
 326
 327         __vgic_restore_state(vcpu);
 328         __timer_restore_state(vcpu);
 329
 330         /*
 331          * We must restore the 32-bit state before the sysregs, thanks
 332          * to erratum #852523 (Cortex-A57) or #853709 (Cortex-A72).
 333          */
 334         __sysreg32_restore_state(vcpu);
 335         __sysreg_restore_guest_state(guest_ctxt);
 336         __debug_restore_state(vcpu, kern_hyp_va(vcpu->arch.debug_ptr), guest_ctxt);
 337
 338         __set_guest_arch_workaround_state(vcpu);
 339
 340         /* Jump in the fire! */
 341 again:
 342         exit_code = __guest_enter(vcpu, host_ctxt);
 343         /* And we're baaack! */
 344
 345         /*
 346          * We're using the raw exception code in order to only process
 347          * the trap if no SError is pending. We will come back to the
 348          * same PC once the SError has been injected, and replay the
 349          * trapping instruction.
 350          */
 351         if (exit_code == ARM_EXCEPTION_TRAP && !__populate_fault_info(vcpu))
 352                 goto again;
 353
 354         if (static_branch_unlikely(&vgic_v2_cpuif_trap) &&
 355             exit_code == ARM_EXCEPTION_TRAP) {
 356                 bool valid;
 357
 358                 valid = kvm_vcpu_trap_get_class(vcpu) == ESR_ELx_EC_DABT_LOW &&
 359                         kvm_vcpu_trap_get_fault_type(vcpu) == FSC_FAULT &&
 360                         kvm_vcpu_dabt_isvalid(vcpu) &&
 361                         !kvm_vcpu_dabt_isextabt(vcpu) &&
 362                         !kvm_vcpu_dabt_iss1tw(vcpu);
 363
 364                 if (valid) {
 365                         int ret = __vgic_v2_perform_cpuif_access(vcpu);
 366
 367                         if (ret == 1) {
 368                                 __skip_instr(vcpu);
 369                                 goto again;
 370                         }
 371
 372                         if (ret == -1) {
 373                                 /* Promote an illegal access to an SError */
 374                                 __skip_instr(vcpu);
 375                                 exit_code = ARM_EXCEPTION_EL1_SERROR;
 376                         }
 377
 378                         /* 0 falls through to be handler out of EL2 */
 379                 }
 380         }
 381
 382         __set_host_arch_workaround_state(vcpu);
 383
 384         fp_enabled = __fpsimd_enabled();
 385
 386         __sysreg_save_guest_state(guest_ctxt);
 387         __sysreg32_save_state(vcpu);
 388         __timer_save_state(vcpu);
 389         __vgic_save_state(vcpu);
 390
 391         __deactivate_traps(vcpu);
 392         __deactivate_vm(vcpu);
 393
 394         __sysreg_restore_host_state(host_ctxt);
 395
 396         if (fp_enabled) {
 397                 __fpsimd_save_state(&guest_ctxt->gp_regs.fp_regs);
 398                 __fpsimd_restore_state(&host_ctxt->gp_regs.fp_regs);
 399         }
 400
 401         __debug_save_state(vcpu, kern_hyp_va(vcpu->arch.debug_ptr), guest_ctxt);
 402         __debug_cond_restore_host_state(vcpu);
 403
 404         return exit_code;
 405 }
 406
 407 static const char __hyp_panic_string[] = "HYP panic:\nPS:%08llx PC:%016llx ESR:%08llx\nFAR:%016llx HPFAR:%016llx PAR:%016llx\nVCPU:%p\n";
 408
 409 static void __hyp_text __hyp_call_panic_nvhe(u64 spsr, u64 elr, u64 par,
 410                                              struct kvm_vcpu *vcpu)
 411 {
 412         unsigned long str_va;
 413
 414         /*
 415          * Force the panic string to be loaded from the literal pool,
 416          * making sure it is a kernel address and not a PC-relative
 417          * reference.
 418          */
 419         asm volatile("ldr %0, =%1" : "=r" (str_va) : "S" (__hyp_panic_string));
 420
 421         __hyp_do_panic(str_va,
 422                        spsr,  elr,
 423                        read_sysreg(esr_el2),   read_sysreg_el2(far),
 424                        read_sysreg(hpfar_el2), par, vcpu);
 425 }
 426
 427 static void __hyp_text __hyp_call_panic_vhe(u64 spsr, u64 elr, u64 par,
 428                                             struct kvm_vcpu *vcpu)
 429 {
 430         panic(__hyp_panic_string,
 431               spsr,  elr,
 432               read_sysreg_el2(esr),   read_sysreg_el2(far),
 433               read_sysreg(hpfar_el2), par, vcpu);
 434 }
 435
 436 static hyp_alternate_select(__hyp_call_panic,
 437                             __hyp_call_panic_nvhe, __hyp_call_panic_vhe,
 438                             ARM64_HAS_VIRT_HOST_EXTN);
 439
 440 void __hyp_text __noreturn hyp_panic(struct kvm_cpu_context *host_ctxt)
 441 {
 442         struct kvm_vcpu *vcpu = NULL;
 443
 444         u64 spsr = read_sysreg_el2(spsr);
 445         u64 elr = read_sysreg_el2(elr);
 446         u64 par = read_sysreg(par_el1);
 447
 448         if (read_sysreg(vttbr_el2)) {
 449                 vcpu = host_ctxt->__hyp_running_vcpu;
 450                 __timer_save_state(vcpu);
 451                 __deactivate_traps(vcpu);
 452                 __deactivate_vm(vcpu);
 453                 __sysreg_restore_host_state(host_ctxt);
 454         }
 455
 456         /* Call panic for real */
 457         __hyp_call_panic()(spsr, elr, par, vcpu);
 458
 459         unreachable();
 460 }
 461
 462 asmlinkage void __hyp_text kvm_unexpected_el2_exception(void)
 463 {
 464         unsigned long addr, fixup;
 465         struct kvm_cpu_context *host_ctxt;
 466         struct exception_table_entry *entry, *end;
 467         unsigned long elr_el2 = read_sysreg(elr_el2);
 468
 469         entry = hyp_symbol_addr(__start___kvm_ex_table);
 470         end = hyp_symbol_addr(__stop___kvm_ex_table);
 471         host_ctxt = __hyp_this_cpu_ptr(kvm_host_cpu_state);
 472
 473         while (entry < end) {
 474                 addr = (unsigned long)&entry->insn + entry->insn;
 475                 fixup = (unsigned long)&entry->fixup + entry->fixup;
 476
 477                 if (addr != elr_el2) {
 478                         entry++;
 479                         continue;
 480                 }
 481
 482                 write_sysreg(fixup, elr_el2);
 483                 return;
 484         }
 485
 486         hyp_panic(host_ctxt);
 487 }