arch/arm64/kernel/traps.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Based on arch/arm/kernel/traps.c
   4  *
   5  * Copyright (C) 1995-2009 Russell King
   6  * Copyright (C) 2012 ARM Ltd.
   7  */
   8
   9 #include <linux/bug.h>
  10 #include <linux/context_tracking.h>
  11 #include <linux/signal.h>
  12 #include <linux/personality.h>
  13 #include <linux/kallsyms.h>
  14 #include <linux/kprobes.h>
  15 #include <linux/spinlock.h>
  16 #include <linux/uaccess.h>
  17 #include <linux/hardirq.h>
  18 #include <linux/kdebug.h>
  19 #include <linux/module.h>
  20 #include <linux/kexec.h>
  21 #include <linux/delay.h>
  22 #include <linux/init.h>
  23 #include <linux/sched/signal.h>
  24 #include <linux/sched/debug.h>
  25 #include <linux/sched/task_stack.h>
  26 #include <linux/sizes.h>
  27 #include <linux/syscalls.h>
  28 #include <linux/mm_types.h>
  29 #include <linux/kasan.h>
  30
  31 #include <asm/atomic.h>
  32 #include <asm/bug.h>
  33 #include <asm/cpufeature.h>
  34 #include <asm/daifflags.h>
  35 #include <asm/debug-monitors.h>
  36 #include <asm/esr.h>
  37 #include <asm/exception.h>
  38 #include <asm/extable.h>
  39 #include <asm/insn.h>
  40 #include <asm/kprobes.h>
  41 #include <asm/patching.h>
  42 #include <asm/traps.h>
  43 #include <asm/smp.h>
  44 #include <asm/stack_pointer.h>
  45 #include <asm/stacktrace.h>
  46 #include <asm/system_misc.h>
  47 #include <asm/sysreg.h>
  48
  49 static bool __kprobes __check_eq(unsigned long pstate)
  50 {
  51         return (pstate & PSR_Z_BIT) != 0;
  52 }
  53
  54 static bool __kprobes __check_ne(unsigned long pstate)
  55 {
  56         return (pstate & PSR_Z_BIT) == 0;
  57 }
  58
  59 static bool __kprobes __check_cs(unsigned long pstate)
  60 {
  61         return (pstate & PSR_C_BIT) != 0;
  62 }
  63
  64 static bool __kprobes __check_cc(unsigned long pstate)
  65 {
  66         return (pstate & PSR_C_BIT) == 0;
  67 }
  68
  69 static bool __kprobes __check_mi(unsigned long pstate)
  70 {
  71         return (pstate & PSR_N_BIT) != 0;
  72 }
  73
  74 static bool __kprobes __check_pl(unsigned long pstate)
  75 {
  76         return (pstate & PSR_N_BIT) == 0;
  77 }
  78
  79 static bool __kprobes __check_vs(unsigned long pstate)
  80 {
  81         return (pstate & PSR_V_BIT) != 0;
  82 }
  83
  84 static bool __kprobes __check_vc(unsigned long pstate)
  85 {
  86         return (pstate & PSR_V_BIT) == 0;
  87 }
  88
  89 static bool __kprobes __check_hi(unsigned long pstate)
  90 {
  91         pstate &= ~(pstate >> 1);       /* PSR_C_BIT &= ~PSR_Z_BIT */
  92         return (pstate & PSR_C_BIT) != 0;
  93 }
  94
  95 static bool __kprobes __check_ls(unsigned long pstate)
  96 {
  97         pstate &= ~(pstate >> 1);       /* PSR_C_BIT &= ~PSR_Z_BIT */
  98         return (pstate & PSR_C_BIT) == 0;
  99 }
 100
 101 static bool __kprobes __check_ge(unsigned long pstate)
 102 {
 103         pstate ^= (pstate << 3);        /* PSR_N_BIT ^= PSR_V_BIT */
 104         return (pstate & PSR_N_BIT) == 0;
 105 }
 106
 107 static bool __kprobes __check_lt(unsigned long pstate)
 108 {
 109         pstate ^= (pstate << 3);        /* PSR_N_BIT ^= PSR_V_BIT */
 110         return (pstate & PSR_N_BIT) != 0;
 111 }
 112
 113 static bool __kprobes __check_gt(unsigned long pstate)
 114 {
 115         /*PSR_N_BIT ^= PSR_V_BIT */
 116         unsigned long temp = pstate ^ (pstate << 3);
 117
 118         temp |= (pstate << 1);  /*PSR_N_BIT |= PSR_Z_BIT */
 119         return (temp & PSR_N_BIT) == 0;
 120 }
 121
 122 static bool __kprobes __check_le(unsigned long pstate)
 123 {
 124         /*PSR_N_BIT ^= PSR_V_BIT */
 125         unsigned long temp = pstate ^ (pstate << 3);
 126
 127         temp |= (pstate << 1);  /*PSR_N_BIT |= PSR_Z_BIT */
 128         return (temp & PSR_N_BIT) != 0;
 129 }
 130
 131 static bool __kprobes __check_al(unsigned long pstate)
 132 {
 133         return true;
 134 }
 135
 136 /*
 137  * Note that the ARMv8 ARM calls condition code 0b1111 "nv", but states that
 138  * it behaves identically to 0b1110 ("al").
 139  */
 140 pstate_check_t * const aarch32_opcode_cond_checks[16] = {
 141         __check_eq, __check_ne, __check_cs, __check_cc,
 142         __check_mi, __check_pl, __check_vs, __check_vc,
 143         __check_hi, __check_ls, __check_ge, __check_lt,
 144         __check_gt, __check_le, __check_al, __check_al
 145 };
 146
 147 int show_unhandled_signals = 0;
 148
 149 static void dump_kernel_instr(const char *lvl, struct pt_regs *regs)
 150 {
 151         unsigned long addr = instruction_pointer(regs);
 152         char str[sizeof("00000000 ") * 5 + 2 + 1], *p = str;
 153         int i;
 154
 155         if (user_mode(regs))
 156                 return;
 157
 158         for (i = -4; i < 1; i++) {
 159                 unsigned int val, bad;
 160
 161                 bad = aarch64_insn_read(&((u32 *)addr)[i], &val);
 162
 163                 if (!bad)
 164                         p += sprintf(p, i == 0 ? "(%08x) " : "%08x ", val);
 165                 else {
 166                         p += sprintf(p, "bad PC value");
 167                         break;
 168                 }
 169         }
 170
 171         printk("%sCode: %s\n", lvl, str);
 172 }
 173
 174 #ifdef CONFIG_PREEMPT
 175 #define S_PREEMPT " PREEMPT"
 176 #elif defined(CONFIG_PREEMPT_RT)
 177 #define S_PREEMPT " PREEMPT_RT"
 178 #else
 179 #define S_PREEMPT ""
 180 #endif
 181
 182 #define S_SMP " SMP"
 183
 184 static int __die(const char *str, long err, struct pt_regs *regs)
 185 {
 186         static int die_counter;
 187         int ret;
 188
 189         pr_emerg("Internal error: %s: %016lx [#%d]" S_PREEMPT S_SMP "\n",
 190                  str, err, ++die_counter);
 191
 192         /* trap and error numbers are mostly meaningless on ARM */
 193         ret = notify_die(DIE_OOPS, str, regs, err, 0, SIGSEGV);
 194         if (ret == NOTIFY_STOP)
 195                 return ret;
 196
 197         print_modules();
 198         show_regs(regs);
 199
 200         dump_kernel_instr(KERN_EMERG, regs);
 201
 202         return ret;
 203 }
 204
 205 static DEFINE_RAW_SPINLOCK(die_lock);
 206
 207 /*
 208  * This function is protected against re-entrancy.
 209  */
 210 void die(const char *str, struct pt_regs *regs, long err)
 211 {
 212         int ret;
 213         unsigned long flags;
 214
 215         raw_spin_lock_irqsave(&die_lock, flags);
 216
 217         oops_enter();
 218
 219         console_verbose();
 220         bust_spinlocks(1);
 221         ret = __die(str, err, regs);
 222
 223         if (regs && kexec_should_crash(current))
 224                 crash_kexec(regs);
 225
 226         bust_spinlocks(0);
 227         add_taint(TAINT_DIE, LOCKDEP_NOW_UNRELIABLE);
 228         oops_exit();
 229
 230         if (in_interrupt())
 231                 panic("%s: Fatal exception in interrupt", str);
 232         if (panic_on_oops)
 233                 panic("%s: Fatal exception", str);
 234
 235         raw_spin_unlock_irqrestore(&die_lock, flags);
 236
 237         if (ret != NOTIFY_STOP)
 238                 make_task_dead(SIGSEGV);
 239 }
 240
 241 static void arm64_show_signal(int signo, const char *str)
 242 {
 243         static DEFINE_RATELIMIT_STATE(rs, DEFAULT_RATELIMIT_INTERVAL,
 244                                       DEFAULT_RATELIMIT_BURST);
 245         struct task_struct *tsk = current;
 246         unsigned long esr = tsk->thread.fault_code;
 247         struct pt_regs *regs = task_pt_regs(tsk);
 248
 249         /* Leave if the signal won't be shown */
 250         if (!show_unhandled_signals ||
 251             !unhandled_signal(tsk, signo) ||
 252             !__ratelimit(&rs))
 253                 return;
 254
 255         pr_info("%s[%d]: unhandled exception: ", tsk->comm, task_pid_nr(tsk));
 256         if (esr)
 257                 pr_cont("%s, ESR 0x%016lx, ", esr_get_class_string(esr), esr);
 258
 259         pr_cont("%s", str);
 260         print_vma_addr(KERN_CONT " in ", regs->pc);
 261         pr_cont("\n");
 262         __show_regs(regs);
 263 }
 264
 265 void arm64_force_sig_fault(int signo, int code, unsigned long far,
 266                            const char *str)
 267 {
 268         arm64_show_signal(signo, str);
 269         if (signo == SIGKILL)
 270                 force_sig(SIGKILL);
 271         else
 272                 force_sig_fault(signo, code, (void __user *)far);
 273 }
 274
 275 void arm64_force_sig_mceerr(int code, unsigned long far, short lsb,
 276                             const char *str)
 277 {
 278         arm64_show_signal(SIGBUS, str);
 279         force_sig_mceerr(code, (void __user *)far, lsb);
 280 }
 281
 282 void arm64_force_sig_ptrace_errno_trap(int errno, unsigned long far,
 283                                        const char *str)
 284 {
 285         arm64_show_signal(SIGTRAP, str);
 286         force_sig_ptrace_errno_trap(errno, (void __user *)far);
 287 }
 288
 289 void arm64_notify_die(const char *str, struct pt_regs *regs,
 290                       int signo, int sicode, unsigned long far,
 291                       unsigned long err)
 292 {
 293         if (user_mode(regs)) {
 294                 WARN_ON(regs != current_pt_regs());
 295                 current->thread.fault_address = 0;
 296                 current->thread.fault_code = err;
 297
 298                 arm64_force_sig_fault(signo, sicode, far, str);
 299         } else {
 300                 die(str, regs, err);
 301         }
 302 }
 303
 304 #ifdef CONFIG_COMPAT
 305 #define PSTATE_IT_1_0_SHIFT     25
 306 #define PSTATE_IT_1_0_MASK      (0x3 << PSTATE_IT_1_0_SHIFT)
 307 #define PSTATE_IT_7_2_SHIFT     10
 308 #define PSTATE_IT_7_2_MASK      (0x3f << PSTATE_IT_7_2_SHIFT)
 309
 310 static u32 compat_get_it_state(struct pt_regs *regs)
 311 {
 312         u32 it, pstate = regs->pstate;
 313
 314         it  = (pstate & PSTATE_IT_1_0_MASK) >> PSTATE_IT_1_0_SHIFT;
 315         it |= ((pstate & PSTATE_IT_7_2_MASK) >> PSTATE_IT_7_2_SHIFT) << 2;
 316
 317         return it;
 318 }
 319
 320 static void compat_set_it_state(struct pt_regs *regs, u32 it)
 321 {
 322         u32 pstate_it;
 323
 324         pstate_it  = (it << PSTATE_IT_1_0_SHIFT) & PSTATE_IT_1_0_MASK;
 325         pstate_it |= ((it >> 2) << PSTATE_IT_7_2_SHIFT) & PSTATE_IT_7_2_MASK;
 326
 327         regs->pstate &= ~PSR_AA32_IT_MASK;
 328         regs->pstate |= pstate_it;
 329 }
 330
 331 static void advance_itstate(struct pt_regs *regs)
 332 {
 333         u32 it;
 334
 335         /* ARM mode */
 336         if (!(regs->pstate & PSR_AA32_T_BIT) ||
 337             !(regs->pstate & PSR_AA32_IT_MASK))
 338                 return;
 339
 340         it  = compat_get_it_state(regs);
 341
 342         /*
 343          * If this is the last instruction of the block, wipe the IT
 344          * state. Otherwise advance it.
 345          */
 346         if (!(it & 7))
 347                 it = 0;
 348         else
 349                 it = (it & 0xe0) | ((it << 1) & 0x1f);
 350
 351         compat_set_it_state(regs, it);
 352 }
 353 #else
 354 static void advance_itstate(struct pt_regs *regs)
 355 {
 356 }
 357 #endif
 358
 359 void arm64_skip_faulting_instruction(struct pt_regs *regs, unsigned long size)
 360 {
 361         regs->pc += size;
 362
 363         /*
 364          * If we were single stepping, we want to get the step exception after
 365          * we return from the trap.
 366          */
 367         if (user_mode(regs))
 368                 user_fastforward_single_step(current);
 369
 370         if (compat_user_mode(regs))
 371                 advance_itstate(regs);
 372         else
 373                 regs->pstate &= ~PSR_BTYPE_MASK;
 374 }
 375
 376 static int user_insn_read(struct pt_regs *regs, u32 *insnp)
 377 {
 378         u32 instr;
 379         void __user *pc = (void __user *)instruction_pointer(regs);
 380
 381         if (compat_thumb_mode(regs)) {
 382                 /* 16-bit Thumb instruction */
 383                 __le16 instr_le;
 384                 if (get_user(instr_le, (__le16 __user *)pc))
 385                         return -EFAULT;
 386                 instr = le16_to_cpu(instr_le);
 387                 if (aarch32_insn_is_wide(instr)) {
 388                         u32 instr2;
 389
 390                         if (get_user(instr_le, (__le16 __user *)(pc + 2)))
 391                                 return -EFAULT;
 392                         instr2 = le16_to_cpu(instr_le);
 393                         instr = (instr << 16) | instr2;
 394                 }
 395         } else {
 396                 /* 32-bit ARM instruction */
 397                 __le32 instr_le;
 398                 if (get_user(instr_le, (__le32 __user *)pc))
 399                         return -EFAULT;
 400                 instr = le32_to_cpu(instr_le);
 401         }
 402
 403         *insnp = instr;
 404         return 0;
 405 }
 406
 407 void force_signal_inject(int signal, int code, unsigned long address, unsigned long err)
 408 {
 409         const char *desc;
 410         struct pt_regs *regs = current_pt_regs();
 411
 412         if (WARN_ON(!user_mode(regs)))
 413                 return;
 414
 415         switch (signal) {
 416         case SIGILL:
 417                 desc = "undefined instruction";
 418                 break;
 419         case SIGSEGV:
 420                 desc = "illegal memory access";
 421                 break;
 422         default:
 423                 desc = "unknown or unrecoverable error";
 424                 break;
 425         }
 426
 427         /* Force signals we don't understand to SIGKILL */
 428         if (WARN_ON(signal != SIGKILL &&
 429                     siginfo_layout(signal, code) != SIL_FAULT)) {
 430                 signal = SIGKILL;
 431         }
 432
 433         arm64_notify_die(desc, regs, signal, code, address, err);
 434 }
 435
 436 /*
 437  * Set up process info to signal segmentation fault - called on access error.
 438  */
 439 void arm64_notify_segfault(unsigned long addr)
 440 {
 441         int code;
 442
 443         mmap_read_lock(current->mm);
 444         if (find_vma(current->mm, untagged_addr(addr)) == NULL)
 445                 code = SEGV_MAPERR;
 446         else
 447                 code = SEGV_ACCERR;
 448         mmap_read_unlock(current->mm);
 449
 450         force_signal_inject(SIGSEGV, code, addr, 0);
 451 }
 452
 453 void do_el0_undef(struct pt_regs *regs, unsigned long esr)
 454 {
 455         u32 insn;
 456
 457         /* check for AArch32 breakpoint instructions */
 458         if (!aarch32_break_handler(regs))
 459                 return;
 460
 461         if (user_insn_read(regs, &insn))
 462                 goto out_err;
 463
 464         if (try_emulate_mrs(regs, insn))
 465                 return;
 466
 467         if (try_emulate_armv8_deprecated(regs, insn))
 468                 return;
 469
 470 out_err:
 471         force_signal_inject(SIGILL, ILL_ILLOPC, regs->pc, 0);
 472 }
 473
 474 void do_el1_undef(struct pt_regs *regs, unsigned long esr)
 475 {
 476         u32 insn;
 477
 478         if (aarch64_insn_read((void *)regs->pc, &insn))
 479                 goto out_err;
 480
 481         if (try_emulate_el1_ssbs(regs, insn))
 482                 return;
 483
 484 out_err:
 485         die("Oops - Undefined instruction", regs, esr);
 486 }
 487
 488 void do_el0_bti(struct pt_regs *regs)
 489 {
 490         force_signal_inject(SIGILL, ILL_ILLOPC, regs->pc, 0);
 491 }
 492
 493 void do_el1_bti(struct pt_regs *regs, unsigned long esr)
 494 {
 495         die("Oops - BTI", regs, esr);
 496 }
 497
 498 void do_el0_fpac(struct pt_regs *regs, unsigned long esr)
 499 {
 500         force_signal_inject(SIGILL, ILL_ILLOPN, regs->pc, esr);
 501 }
 502
 503 void do_el1_fpac(struct pt_regs *regs, unsigned long esr)
 504 {
 505         /*
 506          * Unexpected FPAC exception in the kernel: kill the task before it
 507          * does any more harm.
 508          */
 509         die("Oops - FPAC", regs, esr);
 510 }
 511
 512 #define __user_cache_maint(insn, address, res)                  \
 513         if (address >= user_addr_max()) {                       \
 514                 res = -EFAULT;                                  \
 515         } else {                                                \
 516                 uaccess_ttbr0_enable();                         \
 517                 asm volatile (                                  \
 518                         "1:     " insn ", %1\n"                 \
 519                         "       mov     %w0, #0\n"              \
 520                         "2:\n"                                  \
 521                         "       .pushsection .fixup,\"ax\"\n"   \
 522                         "       .align  2\n"                    \
 523                         "3:     mov     %w0, %w2\n"             \
 524                         "       b       2b\n"                   \
 525                         "       .popsection\n"                  \
 526                         _ASM_EXTABLE(1b, 3b)                    \
 527                         : "=r" (res)                            \
 528                         : "r" (address), "i" (-EFAULT));        \
 529                 uaccess_ttbr0_disable();                        \
 530         }
 531
 532 static void user_cache_maint_handler(unsigned long esr, struct pt_regs *regs)
 533 {
 534         unsigned long tagged_address, address;
 535         int rt = ESR_ELx_SYS64_ISS_RT(esr);
 536         int crm = (esr & ESR_ELx_SYS64_ISS_CRM_MASK) >> ESR_ELx_SYS64_ISS_CRM_SHIFT;
 537         int ret = 0;
 538
 539         tagged_address = pt_regs_read_reg(regs, rt);
 540         address = untagged_addr(tagged_address);
 541
 542         switch (crm) {
 543         case ESR_ELx_SYS64_ISS_CRM_DC_CVAU:     /* DC CVAU, gets promoted */
 544                 __user_cache_maint("dc civac", address, ret);
 545                 break;
 546         case ESR_ELx_SYS64_ISS_CRM_DC_CVAC:     /* DC CVAC, gets promoted */
 547                 __user_cache_maint("dc civac", address, ret);
 548                 break;
 549         case ESR_ELx_SYS64_ISS_CRM_DC_CVADP:    /* DC CVADP */
 550                 __user_cache_maint("sys 3, c7, c13, 1", address, ret);
 551                 break;
 552         case ESR_ELx_SYS64_ISS_CRM_DC_CVAP:     /* DC CVAP */
 553                 __user_cache_maint("sys 3, c7, c12, 1", address, ret);
 554                 break;
 555         case ESR_ELx_SYS64_ISS_CRM_DC_CIVAC:    /* DC CIVAC */
 556                 __user_cache_maint("dc civac", address, ret);
 557                 break;
 558         case ESR_ELx_SYS64_ISS_CRM_IC_IVAU:     /* IC IVAU */
 559                 __user_cache_maint("ic ivau", address, ret);
 560                 break;
 561         default:
 562                 force_signal_inject(SIGILL, ILL_ILLOPC, regs->pc, 0);
 563                 return;
 564         }
 565
 566         if (ret)
 567                 arm64_notify_segfault(tagged_address);
 568         else
 569                 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE);
 570 }
 571
 572 static void ctr_read_handler(unsigned long esr, struct pt_regs *regs)
 573 {
 574         int rt = ESR_ELx_SYS64_ISS_RT(esr);
 575         unsigned long val = arm64_ftr_reg_user_value(&arm64_ftr_reg_ctrel0);
 576
 577         if (cpus_have_const_cap(ARM64_WORKAROUND_1542419)) {
 578                 /* Hide DIC so that we can trap the unnecessary maintenance...*/
 579                 val &= ~BIT(CTR_DIC_SHIFT);
 580
 581                 /* ... and fake IminLine to reduce the number of traps. */
 582                 val &= ~CTR_IMINLINE_MASK;
 583                 val |= (PAGE_SHIFT - 2) & CTR_IMINLINE_MASK;
 584         }
 585
 586         pt_regs_write_reg(regs, rt, val);
 587
 588         arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE);
 589 }
 590
 591 static void cntvct_read_handler(unsigned long esr, struct pt_regs *regs)
 592 {
 593         int rt = ESR_ELx_SYS64_ISS_RT(esr);
 594
 595         pt_regs_write_reg(regs, rt, arch_timer_read_counter());
 596         arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE);
 597 }
 598
 599 static void cntfrq_read_handler(unsigned long esr, struct pt_regs *regs)
 600 {
 601         int rt = ESR_ELx_SYS64_ISS_RT(esr);
 602
 603         pt_regs_write_reg(regs, rt, arch_timer_get_rate());
 604         arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE);
 605 }
 606
 607 static void mrs_handler(unsigned long esr, struct pt_regs *regs)
 608 {
 609         u32 sysreg, rt;
 610
 611         rt = ESR_ELx_SYS64_ISS_RT(esr);
 612         sysreg = esr_sys64_to_sysreg(esr);
 613
 614         if (do_emulate_mrs(regs, sysreg, rt) != 0)
 615                 force_signal_inject(SIGILL, ILL_ILLOPC, regs->pc, 0);
 616 }
 617
 618 static void wfi_handler(unsigned long esr, struct pt_regs *regs)
 619 {
 620         arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE);
 621 }
 622
 623 struct sys64_hook {
 624         unsigned long esr_mask;
 625         unsigned long esr_val;
 626         void (*handler)(unsigned long esr, struct pt_regs *regs);
 627 };
 628
 629 static const struct sys64_hook sys64_hooks[] = {
 630         {
 631                 .esr_mask = ESR_ELx_SYS64_ISS_EL0_CACHE_OP_MASK,
 632                 .esr_val = ESR_ELx_SYS64_ISS_EL0_CACHE_OP_VAL,
 633                 .handler = user_cache_maint_handler,
 634         },
 635         {
 636                 /* Trap read access to CTR_EL0 */
 637                 .esr_mask = ESR_ELx_SYS64_ISS_SYS_OP_MASK,
 638                 .esr_val = ESR_ELx_SYS64_ISS_SYS_CTR_READ,
 639                 .handler = ctr_read_handler,
 640         },
 641         {
 642                 /* Trap read access to CNTVCT_EL0 */
 643                 .esr_mask = ESR_ELx_SYS64_ISS_SYS_OP_MASK,
 644                 .esr_val = ESR_ELx_SYS64_ISS_SYS_CNTVCT,
 645                 .handler = cntvct_read_handler,
 646         },
 647         {
 648                 /* Trap read access to CNTFRQ_EL0 */
 649                 .esr_mask = ESR_ELx_SYS64_ISS_SYS_OP_MASK,
 650                 .esr_val = ESR_ELx_SYS64_ISS_SYS_CNTFRQ,
 651                 .handler = cntfrq_read_handler,
 652         },
 653         {
 654                 /* Trap read access to CPUID registers */
 655                 .esr_mask = ESR_ELx_SYS64_ISS_SYS_MRS_OP_MASK,
 656                 .esr_val = ESR_ELx_SYS64_ISS_SYS_MRS_OP_VAL,
 657                 .handler = mrs_handler,
 658         },
 659         {
 660                 /* Trap WFI instructions executed in userspace */
 661                 .esr_mask = ESR_ELx_WFx_MASK,
 662                 .esr_val = ESR_ELx_WFx_WFI_VAL,
 663                 .handler = wfi_handler,
 664         },
 665         {},
 666 };
 667
 668 #ifdef CONFIG_COMPAT
 669 static bool cp15_cond_valid(unsigned long esr, struct pt_regs *regs)
 670 {
 671         int cond;
 672
 673         /* Only a T32 instruction can trap without CV being set */
 674         if (!(esr & ESR_ELx_CV)) {
 675                 u32 it;
 676
 677                 it = compat_get_it_state(regs);
 678                 if (!it)
 679                         return true;
 680
 681                 cond = it >> 4;
 682         } else {
 683                 cond = (esr & ESR_ELx_COND_MASK) >> ESR_ELx_COND_SHIFT;
 684         }
 685
 686         return aarch32_opcode_cond_checks[cond](regs->pstate);
 687 }
 688
 689 static void compat_cntfrq_read_handler(unsigned long esr, struct pt_regs *regs)
 690 {
 691         int reg = (esr & ESR_ELx_CP15_32_ISS_RT_MASK) >> ESR_ELx_CP15_32_ISS_RT_SHIFT;
 692
 693         pt_regs_write_reg(regs, reg, arch_timer_get_rate());
 694         arm64_skip_faulting_instruction(regs, 4);
 695 }
 696
 697 static const struct sys64_hook cp15_32_hooks[] = {
 698         {
 699                 .esr_mask = ESR_ELx_CP15_32_ISS_SYS_MASK,
 700                 .esr_val = ESR_ELx_CP15_32_ISS_SYS_CNTFRQ,
 701                 .handler = compat_cntfrq_read_handler,
 702         },
 703         {},
 704 };
 705
 706 static void compat_cntvct_read_handler(unsigned long esr, struct pt_regs *regs)
 707 {
 708         int rt = (esr & ESR_ELx_CP15_64_ISS_RT_MASK) >> ESR_ELx_CP15_64_ISS_RT_SHIFT;
 709         int rt2 = (esr & ESR_ELx_CP15_64_ISS_RT2_MASK) >> ESR_ELx_CP15_64_ISS_RT2_SHIFT;
 710         u64 val = arch_timer_read_counter();
 711
 712         pt_regs_write_reg(regs, rt, lower_32_bits(val));
 713         pt_regs_write_reg(regs, rt2, upper_32_bits(val));
 714         arm64_skip_faulting_instruction(regs, 4);
 715 }
 716
 717 static const struct sys64_hook cp15_64_hooks[] = {
 718         {
 719                 .esr_mask = ESR_ELx_CP15_64_ISS_SYS_MASK,
 720                 .esr_val = ESR_ELx_CP15_64_ISS_SYS_CNTVCT,
 721                 .handler = compat_cntvct_read_handler,
 722         },
 723         {},
 724 };
 725
 726 void do_el0_cp15(unsigned long esr, struct pt_regs *regs)
 727 {
 728         const struct sys64_hook *hook, *hook_base;
 729
 730         if (!cp15_cond_valid(esr, regs)) {
 731                 /*
 732                  * There is no T16 variant of a CP access, so we
 733                  * always advance PC by 4 bytes.
 734                  */
 735                 arm64_skip_faulting_instruction(regs, 4);
 736                 return;
 737         }
 738
 739         switch (ESR_ELx_EC(esr)) {
 740         case ESR_ELx_EC_CP15_32:
 741                 hook_base = cp15_32_hooks;
 742                 break;
 743         case ESR_ELx_EC_CP15_64:
 744                 hook_base = cp15_64_hooks;
 745                 break;
 746         default:
 747                 do_el0_undef(regs, esr);
 748                 return;
 749         }
 750
 751         for (hook = hook_base; hook->handler; hook++)
 752                 if ((hook->esr_mask & esr) == hook->esr_val) {
 753                         hook->handler(esr, regs);
 754                         return;
 755                 }
 756
 757         /*
 758          * New cp15 instructions may previously have been undefined at
 759          * EL0. Fall back to our usual undefined instruction handler
 760          * so that we handle these consistently.
 761          */
 762         do_el0_undef(regs, esr);
 763 }
 764 #endif
 765
 766 void do_el0_sys(unsigned long esr, struct pt_regs *regs)
 767 {
 768         const struct sys64_hook *hook;
 769
 770         for (hook = sys64_hooks; hook->handler; hook++)
 771                 if ((hook->esr_mask & esr) == hook->esr_val) {
 772                         hook->handler(esr, regs);
 773                         return;
 774                 }
 775
 776         /*
 777          * New SYS instructions may previously have been undefined at EL0. Fall
 778          * back to our usual undefined instruction handler so that we handle
 779          * these consistently.
 780          */
 781         do_el0_undef(regs, esr);
 782 }
 783
 784 static const char *esr_class_str[] = {
 785         [0 ... ESR_ELx_EC_MAX]          = "UNRECOGNIZED EC",
 786         [ESR_ELx_EC_UNKNOWN]            = "Unknown/Uncategorized",
 787         [ESR_ELx_EC_WFx]                = "WFI/WFE",
 788         [ESR_ELx_EC_CP15_32]            = "CP15 MCR/MRC",
 789         [ESR_ELx_EC_CP15_64]            = "CP15 MCRR/MRRC",
 790         [ESR_ELx_EC_CP14_MR]            = "CP14 MCR/MRC",
 791         [ESR_ELx_EC_CP14_LS]            = "CP14 LDC/STC",
 792         [ESR_ELx_EC_FP_ASIMD]           = "ASIMD",
 793         [ESR_ELx_EC_CP10_ID]            = "CP10 MRC/VMRS",
 794         [ESR_ELx_EC_PAC]                = "PAC",
 795         [ESR_ELx_EC_CP14_64]            = "CP14 MCRR/MRRC",
 796         [ESR_ELx_EC_BTI]                = "BTI",
 797         [ESR_ELx_EC_ILL]                = "PSTATE.IL",
 798         [ESR_ELx_EC_SVC32]              = "SVC (AArch32)",
 799         [ESR_ELx_EC_HVC32]              = "HVC (AArch32)",
 800         [ESR_ELx_EC_SMC32]              = "SMC (AArch32)",
 801         [ESR_ELx_EC_SVC64]              = "SVC (AArch64)",
 802         [ESR_ELx_EC_HVC64]              = "HVC (AArch64)",
 803         [ESR_ELx_EC_SMC64]              = "SMC (AArch64)",
 804         [ESR_ELx_EC_SYS64]              = "MSR/MRS (AArch64)",
 805         [ESR_ELx_EC_SVE]                = "SVE",
 806         [ESR_ELx_EC_ERET]               = "ERET/ERETAA/ERETAB",
 807         [ESR_ELx_EC_FPAC]               = "FPAC",
 808         [ESR_ELx_EC_IMP_DEF]            = "EL3 IMP DEF",
 809         [ESR_ELx_EC_IABT_LOW]           = "IABT (lower EL)",
 810         [ESR_ELx_EC_IABT_CUR]           = "IABT (current EL)",
 811         [ESR_ELx_EC_PC_ALIGN]           = "PC Alignment",
 812         [ESR_ELx_EC_DABT_LOW]           = "DABT (lower EL)",
 813         [ESR_ELx_EC_DABT_CUR]           = "DABT (current EL)",
 814         [ESR_ELx_EC_SP_ALIGN]           = "SP Alignment",
 815         [ESR_ELx_EC_FP_EXC32]           = "FP (AArch32)",
 816         [ESR_ELx_EC_FP_EXC64]           = "FP (AArch64)",
 817         [ESR_ELx_EC_SERROR]             = "SError",
 818         [ESR_ELx_EC_BREAKPT_LOW]        = "Breakpoint (lower EL)",
 819         [ESR_ELx_EC_BREAKPT_CUR]        = "Breakpoint (current EL)",
 820         [ESR_ELx_EC_SOFTSTP_LOW]        = "Software Step (lower EL)",
 821         [ESR_ELx_EC_SOFTSTP_CUR]        = "Software Step (current EL)",
 822         [ESR_ELx_EC_WATCHPT_LOW]        = "Watchpoint (lower EL)",
 823         [ESR_ELx_EC_WATCHPT_CUR]        = "Watchpoint (current EL)",
 824         [ESR_ELx_EC_BKPT32]             = "BKPT (AArch32)",
 825         [ESR_ELx_EC_VECTOR32]           = "Vector catch (AArch32)",
 826         [ESR_ELx_EC_BRK64]              = "BRK (AArch64)",
 827 };
 828
 829 const char *esr_get_class_string(unsigned long esr)
 830 {
 831         return esr_class_str[ESR_ELx_EC(esr)];
 832 }
 833
 834 /*
 835  * bad_el0_sync handles unexpected, but potentially recoverable synchronous
 836  * exceptions taken from EL0.
 837  */
 838 void bad_el0_sync(struct pt_regs *regs, int reason, unsigned long esr)
 839 {
 840         unsigned long pc = instruction_pointer(regs);
 841
 842         current->thread.fault_address = 0;
 843         current->thread.fault_code = esr;
 844
 845         arm64_force_sig_fault(SIGILL, ILL_ILLOPC, pc,
 846                               "Bad EL0 synchronous exception");
 847 }
 848
 849 #ifdef CONFIG_VMAP_STACK
 850
 851 DEFINE_PER_CPU(unsigned long [OVERFLOW_STACK_SIZE/sizeof(long)], overflow_stack)
 852         __aligned(16);
 853
 854 void panic_bad_stack(struct pt_regs *regs, unsigned long esr, unsigned long far)
 855 {
 856         unsigned long tsk_stk = (unsigned long)current->stack;
 857         unsigned long irq_stk = (unsigned long)this_cpu_read(irq_stack_ptr);
 858         unsigned long ovf_stk = (unsigned long)this_cpu_ptr(overflow_stack);
 859
 860         console_verbose();
 861         pr_emerg("Insufficient stack space to handle exception!");
 862
 863         pr_emerg("ESR: 0x%016lx -- %s\n", esr, esr_get_class_string(esr));
 864         pr_emerg("FAR: 0x%016lx\n", far);
 865
 866         pr_emerg("Task stack:     [0x%016lx..0x%016lx]\n",
 867                  tsk_stk, tsk_stk + THREAD_SIZE);
 868         pr_emerg("IRQ stack:      [0x%016lx..0x%016lx]\n",
 869                  irq_stk, irq_stk + IRQ_STACK_SIZE);
 870         pr_emerg("Overflow stack: [0x%016lx..0x%016lx]\n",
 871                  ovf_stk, ovf_stk + OVERFLOW_STACK_SIZE);
 872
 873         __show_regs(regs);
 874
 875         /*
 876          * We use nmi_panic to limit the potential for recusive overflows, and
 877          * to get a better stack trace.
 878          */
 879         nmi_panic(NULL, "kernel stack overflow");
 880         cpu_park_loop();
 881 }
 882 #endif
 883
 884 void __noreturn arm64_serror_panic(struct pt_regs *regs, unsigned long esr)
 885 {
 886         console_verbose();
 887
 888         pr_crit("SError Interrupt on CPU%d, code 0x%016lx -- %s\n",
 889                 smp_processor_id(), esr, esr_get_class_string(esr));
 890         if (regs)
 891                 __show_regs(regs);
 892
 893         nmi_panic(regs, "Asynchronous SError Interrupt");
 894
 895         cpu_park_loop();
 896         unreachable();
 897 }
 898
 899 bool arm64_is_fatal_ras_serror(struct pt_regs *regs, unsigned long esr)
 900 {
 901         unsigned long aet = arm64_ras_serror_get_severity(esr);
 902
 903         switch (aet) {
 904         case ESR_ELx_AET_CE:    /* corrected error */
 905         case ESR_ELx_AET_UEO:   /* restartable, not yet consumed */
 906                 /*
 907                  * The CPU can make progress. We may take UEO again as
 908                  * a more severe error.
 909                  */
 910                 return false;
 911
 912         case ESR_ELx_AET_UEU:   /* Uncorrected Unrecoverable */
 913         case ESR_ELx_AET_UER:   /* Uncorrected Recoverable */
 914                 /*
 915                  * The CPU can't make progress. The exception may have
 916                  * been imprecise.
 917                  *
 918                  * Neoverse-N1 #1349291 means a non-KVM SError reported as
 919                  * Unrecoverable should be treated as Uncontainable. We
 920                  * call arm64_serror_panic() in both cases.
 921                  */
 922                 return true;
 923
 924         case ESR_ELx_AET_UC:    /* Uncontainable or Uncategorized error */
 925         default:
 926                 /* Error has been silently propagated */
 927                 arm64_serror_panic(regs, esr);
 928         }
 929 }
 930
 931 void do_serror(struct pt_regs *regs, unsigned long esr)
 932 {
 933         /* non-RAS errors are not containable */
 934         if (!arm64_is_ras_serror(esr) || arm64_is_fatal_ras_serror(regs, esr))
 935                 arm64_serror_panic(regs, esr);
 936 }
 937
 938 /* GENERIC_BUG traps */
 939
 940 int is_valid_bugaddr(unsigned long addr)
 941 {
 942         /*
 943          * bug_handler() only called for BRK #BUG_BRK_IMM.
 944          * So the answer is trivial -- any spurious instances with no
 945          * bug table entry will be rejected by report_bug() and passed
 946          * back to the debug-monitors code and handled as a fatal
 947          * unexpected debug exception.
 948          */
 949         return 1;
 950 }
 951
 952 static int bug_handler(struct pt_regs *regs, unsigned long esr)
 953 {
 954         switch (report_bug(regs->pc, regs)) {
 955         case BUG_TRAP_TYPE_BUG:
 956                 die("Oops - BUG", regs, esr);
 957                 break;
 958
 959         case BUG_TRAP_TYPE_WARN:
 960                 break;
 961
 962         default:
 963                 /* unknown/unrecognised bug trap type */
 964                 return DBG_HOOK_ERROR;
 965         }
 966
 967         /* If thread survives, skip over the BUG instruction and continue: */
 968         arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE);
 969         return DBG_HOOK_HANDLED;
 970 }
 971
 972 static struct break_hook bug_break_hook = {
 973         .fn = bug_handler,
 974         .imm = BUG_BRK_IMM,
 975 };
 976
 977 static int reserved_fault_handler(struct pt_regs *regs, unsigned long esr)
 978 {
 979         pr_err("%s generated an invalid instruction at %pS!\n",
 980                 "Kernel text patching",
 981                 (void *)instruction_pointer(regs));
 982
 983         /* We cannot handle this */
 984         return DBG_HOOK_ERROR;
 985 }
 986
 987 static struct break_hook fault_break_hook = {
 988         .fn = reserved_fault_handler,
 989         .imm = FAULT_BRK_IMM,
 990 };
 991
 992 #ifdef CONFIG_KASAN_SW_TAGS
 993
 994 #define KASAN_ESR_RECOVER       0x20
 995 #define KASAN_ESR_WRITE 0x10
 996 #define KASAN_ESR_SIZE_MASK     0x0f
 997 #define KASAN_ESR_SIZE(esr)     (1 << ((esr) & KASAN_ESR_SIZE_MASK))
 998
 999 static int kasan_handler(struct pt_regs *regs, unsigned long esr)
1000 {
1001         bool recover = esr & KASAN_ESR_RECOVER;
1002         bool write = esr & KASAN_ESR_WRITE;
1003         size_t size = KASAN_ESR_SIZE(esr);
1004         u64 addr = regs->regs[0];
1005         u64 pc = regs->pc;
1006
1007         kasan_report(addr, size, write, pc);
1008
1009         /*
1010          * The instrumentation allows to control whether we can proceed after
1011          * a crash was detected. This is done by passing the -recover flag to
1012          * the compiler. Disabling recovery allows to generate more compact
1013          * code.
1014          *
1015          * Unfortunately disabling recovery doesn't work for the kernel right
1016          * now. KASAN reporting is disabled in some contexts (for example when
1017          * the allocator accesses slab object metadata; this is controlled by
1018          * current->kasan_depth). All these accesses are detected by the tool,
1019          * even though the reports for them are not printed.
1020          *
1021          * This is something that might be fixed at some point in the future.
1022          */
1023         if (!recover)
1024                 die("Oops - KASAN", regs, esr);
1025
1026         /* If thread survives, skip over the brk instruction and continue: */
1027         arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE);
1028         return DBG_HOOK_HANDLED;
1029 }
1030
1031 static struct break_hook kasan_break_hook = {
1032         .fn     = kasan_handler,
1033         .imm    = KASAN_BRK_IMM,
1034         .mask   = KASAN_BRK_MASK,
1035 };
1036 #endif
1037
1038 /*
1039  * Initial handler for AArch64 BRK exceptions
1040  * This handler only used until debug_traps_init().
1041  */
1042 int __init early_brk64(unsigned long addr, unsigned long esr,
1043                 struct pt_regs *regs)
1044 {
1045 #ifdef CONFIG_KASAN_SW_TAGS
1046         unsigned long comment = esr & ESR_ELx_BRK64_ISS_COMMENT_MASK;
1047
1048         if ((comment & ~KASAN_BRK_MASK) == KASAN_BRK_IMM)
1049                 return kasan_handler(regs, esr) != DBG_HOOK_HANDLED;
1050 #endif
1051         return bug_handler(regs, esr) != DBG_HOOK_HANDLED;
1052 }
1053
1054 void __init trap_init(void)
1055 {
1056         register_kernel_break_hook(&bug_break_hook);
1057         register_kernel_break_hook(&fault_break_hook);
1058 #ifdef CONFIG_KASAN_SW_TAGS
1059         register_kernel_break_hook(&kasan_break_hook);
1060 #endif
1061         debug_traps_init();
1062 }