arch/arm64/kernel/traps.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Based on arch/arm/kernel/traps.c
   4  *
   5  * Copyright (C) 1995-2009 Russell King
   6  * Copyright (C) 2012 ARM Ltd.
   7  */
   8
   9 #include <linux/bug.h>
  10 #include <linux/context_tracking.h>
  11 #include <linux/signal.h>
  12 #include <linux/personality.h>
  13 #include <linux/kallsyms.h>
  14 #include <linux/kprobes.h>
  15 #include <linux/spinlock.h>
  16 #include <linux/uaccess.h>
  17 #include <linux/hardirq.h>
  18 #include <linux/kdebug.h>
  19 #include <linux/module.h>
  20 #include <linux/kexec.h>
  21 #include <linux/delay.h>
  22 #include <linux/init.h>
  23 #include <linux/sched/signal.h>
  24 #include <linux/sched/debug.h>
  25 #include <linux/sched/task_stack.h>
  26 #include <linux/sizes.h>
  27 #include <linux/syscalls.h>
  28 #include <linux/mm_types.h>
  29 #include <linux/kasan.h>
  30
  31 #include <asm/atomic.h>
  32 #include <asm/bug.h>
  33 #include <asm/cpufeature.h>
  34 #include <asm/daifflags.h>
  35 #include <asm/debug-monitors.h>
  36 #include <asm/esr.h>
  37 #include <asm/insn.h>
  38 #include <asm/traps.h>
  39 #include <asm/smp.h>
  40 #include <asm/stack_pointer.h>
  41 #include <asm/stacktrace.h>
  42 #include <asm/exception.h>
  43 #include <asm/system_misc.h>
  44 #include <asm/sysreg.h>
  45
  46 static const char *handler[]= {
  47         "Synchronous Abort",
  48         "IRQ",
  49         "FIQ",
  50         "Error"
  51 };
  52
  53 int show_unhandled_signals = 0;
  54
  55 static void dump_backtrace_entry(unsigned long where)
  56 {
  57         printk(" %pS\n", (void *)where);
  58 }
  59
  60 static void dump_kernel_instr(const char *lvl, struct pt_regs *regs)
  61 {
  62         unsigned long addr = instruction_pointer(regs);
  63         char str[sizeof("00000000 ") * 5 + 2 + 1], *p = str;
  64         int i;
  65
  66         if (user_mode(regs))
  67                 return;
  68
  69         for (i = -4; i < 1; i++) {
  70                 unsigned int val, bad;
  71
  72                 bad = aarch64_insn_read(&((u32 *)addr)[i], &val);
  73
  74                 if (!bad)
  75                         p += sprintf(p, i == 0 ? "(%08x) " : "%08x ", val);
  76                 else {
  77                         p += sprintf(p, "bad PC value");
  78                         break;
  79                 }
  80         }
  81
  82         printk("%sCode: %s\n", lvl, str);
  83 }
  84
  85 void dump_backtrace(struct pt_regs *regs, struct task_struct *tsk)
  86 {
  87         struct stackframe frame;
  88         int skip = 0;
  89
  90         pr_debug("%s(regs = %p tsk = %p)\n", __func__, regs, tsk);
  91
  92         if (regs) {
  93                 if (user_mode(regs))
  94                         return;
  95                 skip = 1;
  96         }
  97
  98         if (!tsk)
  99                 tsk = current;
 100
 101         if (!try_get_task_stack(tsk))
 102                 return;
 103
 104         if (tsk == current) {
 105                 start_backtrace(&frame,
 106                                 (unsigned long)__builtin_frame_address(0),
 107                                 (unsigned long)dump_backtrace);
 108         } else {
 109                 /*
 110                  * task blocked in __switch_to
 111                  */
 112                 start_backtrace(&frame,
 113                                 thread_saved_fp(tsk),
 114                                 thread_saved_pc(tsk));
 115         }
 116
 117         printk("Call trace:\n");
 118         do {
 119                 /* skip until specified stack frame */
 120                 if (!skip) {
 121                         dump_backtrace_entry(frame.pc);
 122                 } else if (frame.fp == regs->regs[29]) {
 123                         skip = 0;
 124                         /*
 125                          * Mostly, this is the case where this function is
 126                          * called in panic/abort. As exception handler's
 127                          * stack frame does not contain the corresponding pc
 128                          * at which an exception has taken place, use regs->pc
 129                          * instead.
 130                          */
 131                         dump_backtrace_entry(regs->pc);
 132                 }
 133         } while (!unwind_frame(tsk, &frame));
 134
 135         put_task_stack(tsk);
 136 }
 137
 138 void show_stack(struct task_struct *tsk, unsigned long *sp)
 139 {
 140         dump_backtrace(NULL, tsk);
 141         barrier();
 142 }
 143
 144 #ifdef CONFIG_PREEMPT
 145 #define S_PREEMPT " PREEMPT"
 146 #else
 147 #define S_PREEMPT ""
 148 #endif
 149 #define S_SMP " SMP"
 150
 151 static int __die(const char *str, int err, struct pt_regs *regs)
 152 {
 153         static int die_counter;
 154         int ret;
 155
 156         pr_emerg("Internal error: %s: %x [#%d]" S_PREEMPT S_SMP "\n",
 157                  str, err, ++die_counter);
 158
 159         /* trap and error numbers are mostly meaningless on ARM */
 160         ret = notify_die(DIE_OOPS, str, regs, err, 0, SIGSEGV);
 161         if (ret == NOTIFY_STOP)
 162                 return ret;
 163
 164         print_modules();
 165         show_regs(regs);
 166
 167         dump_kernel_instr(KERN_EMERG, regs);
 168
 169         return ret;
 170 }
 171
 172 static DEFINE_RAW_SPINLOCK(die_lock);
 173
 174 /*
 175  * This function is protected against re-entrancy.
 176  */
 177 void die(const char *str, struct pt_regs *regs, int err)
 178 {
 179         int ret;
 180         unsigned long flags;
 181
 182         raw_spin_lock_irqsave(&die_lock, flags);
 183
 184         oops_enter();
 185
 186         console_verbose();
 187         bust_spinlocks(1);
 188         ret = __die(str, err, regs);
 189
 190         if (regs && kexec_should_crash(current))
 191                 crash_kexec(regs);
 192
 193         bust_spinlocks(0);
 194         add_taint(TAINT_DIE, LOCKDEP_NOW_UNRELIABLE);
 195         oops_exit();
 196
 197         if (in_interrupt())
 198                 panic("Fatal exception in interrupt");
 199         if (panic_on_oops)
 200                 panic("Fatal exception");
 201
 202         raw_spin_unlock_irqrestore(&die_lock, flags);
 203
 204         if (ret != NOTIFY_STOP)
 205                 make_task_dead(SIGSEGV);
 206 }
 207
 208 static void arm64_show_signal(int signo, const char *str)
 209 {
 210         static DEFINE_RATELIMIT_STATE(rs, DEFAULT_RATELIMIT_INTERVAL,
 211                                       DEFAULT_RATELIMIT_BURST);
 212         struct task_struct *tsk = current;
 213         unsigned int esr = tsk->thread.fault_code;
 214         struct pt_regs *regs = task_pt_regs(tsk);
 215
 216         /* Leave if the signal won't be shown */
 217         if (!show_unhandled_signals ||
 218             !unhandled_signal(tsk, signo) ||
 219             !__ratelimit(&rs))
 220                 return;
 221
 222         pr_info("%s[%d]: unhandled exception: ", tsk->comm, task_pid_nr(tsk));
 223         if (esr)
 224                 pr_cont("%s, ESR 0x%08x, ", esr_get_class_string(esr), esr);
 225
 226         pr_cont("%s", str);
 227         print_vma_addr(KERN_CONT " in ", regs->pc);
 228         pr_cont("\n");
 229         __show_regs(regs);
 230 }
 231
 232 void arm64_force_sig_fault(int signo, int code, void __user *addr,
 233                            const char *str)
 234 {
 235         arm64_show_signal(signo, str);
 236         if (signo == SIGKILL)
 237                 force_sig(SIGKILL);
 238         else
 239                 force_sig_fault(signo, code, addr);
 240 }
 241
 242 void arm64_force_sig_mceerr(int code, void __user *addr, short lsb,
 243                             const char *str)
 244 {
 245         arm64_show_signal(SIGBUS, str);
 246         force_sig_mceerr(code, addr, lsb);
 247 }
 248
 249 void arm64_force_sig_ptrace_errno_trap(int errno, void __user *addr,
 250                                        const char *str)
 251 {
 252         arm64_show_signal(SIGTRAP, str);
 253         force_sig_ptrace_errno_trap(errno, addr);
 254 }
 255
 256 void arm64_notify_die(const char *str, struct pt_regs *regs,
 257                       int signo, int sicode, void __user *addr,
 258                       int err)
 259 {
 260         if (user_mode(regs)) {
 261                 WARN_ON(regs != current_pt_regs());
 262                 current->thread.fault_address = 0;
 263                 current->thread.fault_code = err;
 264
 265                 arm64_force_sig_fault(signo, sicode, addr, str);
 266         } else {
 267                 die(str, regs, err);
 268         }
 269 }
 270
 271 void arm64_skip_faulting_instruction(struct pt_regs *regs, unsigned long size)
 272 {
 273         regs->pc += size;
 274
 275         /*
 276          * If we were single stepping, we want to get the step exception after
 277          * we return from the trap.
 278          */
 279         if (user_mode(regs))
 280                 user_fastforward_single_step(current);
 281 }
 282
 283 static LIST_HEAD(undef_hook);
 284 static DEFINE_RAW_SPINLOCK(undef_lock);
 285
 286 void register_undef_hook(struct undef_hook *hook)
 287 {
 288         unsigned long flags;
 289
 290         raw_spin_lock_irqsave(&undef_lock, flags);
 291         list_add(&hook->node, &undef_hook);
 292         raw_spin_unlock_irqrestore(&undef_lock, flags);
 293 }
 294
 295 void unregister_undef_hook(struct undef_hook *hook)
 296 {
 297         unsigned long flags;
 298
 299         raw_spin_lock_irqsave(&undef_lock, flags);
 300         list_del(&hook->node);
 301         raw_spin_unlock_irqrestore(&undef_lock, flags);
 302 }
 303
 304 static int call_undef_hook(struct pt_regs *regs)
 305 {
 306         struct undef_hook *hook;
 307         unsigned long flags;
 308         u32 instr;
 309         int (*fn)(struct pt_regs *regs, u32 instr) = NULL;
 310         void __user *pc = (void __user *)instruction_pointer(regs);
 311
 312         if (!user_mode(regs)) {
 313                 __le32 instr_le;
 314                 if (probe_kernel_address((__force __le32 *)pc, instr_le))
 315                         goto exit;
 316                 instr = le32_to_cpu(instr_le);
 317         } else if (compat_thumb_mode(regs)) {
 318                 /* 16-bit Thumb instruction */
 319                 __le16 instr_le;
 320                 if (get_user(instr_le, (__le16 __user *)pc))
 321                         goto exit;
 322                 instr = le16_to_cpu(instr_le);
 323                 if (aarch32_insn_is_wide(instr)) {
 324                         u32 instr2;
 325
 326                         if (get_user(instr_le, (__le16 __user *)(pc + 2)))
 327                                 goto exit;
 328                         instr2 = le16_to_cpu(instr_le);
 329                         instr = (instr << 16) | instr2;
 330                 }
 331         } else {
 332                 /* 32-bit ARM instruction */
 333                 __le32 instr_le;
 334                 if (get_user(instr_le, (__le32 __user *)pc))
 335                         goto exit;
 336                 instr = le32_to_cpu(instr_le);
 337         }
 338
 339         raw_spin_lock_irqsave(&undef_lock, flags);
 340         list_for_each_entry(hook, &undef_hook, node)
 341                 if ((instr & hook->instr_mask) == hook->instr_val &&
 342                         (regs->pstate & hook->pstate_mask) == hook->pstate_val)
 343                         fn = hook->fn;
 344
 345         raw_spin_unlock_irqrestore(&undef_lock, flags);
 346 exit:
 347         return fn ? fn(regs, instr) : 1;
 348 }
 349
 350 void force_signal_inject(int signal, int code, unsigned long address)
 351 {
 352         const char *desc;
 353         struct pt_regs *regs = current_pt_regs();
 354
 355         if (WARN_ON(!user_mode(regs)))
 356                 return;
 357
 358         switch (signal) {
 359         case SIGILL:
 360                 desc = "undefined instruction";
 361                 break;
 362         case SIGSEGV:
 363                 desc = "illegal memory access";
 364                 break;
 365         default:
 366                 desc = "unknown or unrecoverable error";
 367                 break;
 368         }
 369
 370         /* Force signals we don't understand to SIGKILL */
 371         if (WARN_ON(signal != SIGKILL &&
 372                     siginfo_layout(signal, code) != SIL_FAULT)) {
 373                 signal = SIGKILL;
 374         }
 375
 376         arm64_notify_die(desc, regs, signal, code, (void __user *)address, 0);
 377 }
 378
 379 /*
 380  * Set up process info to signal segmentation fault - called on access error.
 381  */
 382 void arm64_notify_segfault(unsigned long addr)
 383 {
 384         int code;
 385
 386         down_read(&current->mm->mmap_sem);
 387         if (find_vma(current->mm, addr) == NULL)
 388                 code = SEGV_MAPERR;
 389         else
 390                 code = SEGV_ACCERR;
 391         up_read(&current->mm->mmap_sem);
 392
 393         force_signal_inject(SIGSEGV, code, addr);
 394 }
 395
 396 asmlinkage void __exception do_undefinstr(struct pt_regs *regs)
 397 {
 398         /* check for AArch32 breakpoint instructions */
 399         if (!aarch32_break_handler(regs))
 400                 return;
 401
 402         if (call_undef_hook(regs) == 0)
 403                 return;
 404
 405         BUG_ON(!user_mode(regs));
 406         force_signal_inject(SIGILL, ILL_ILLOPC, regs->pc);
 407 }
 408
 409 #define __user_cache_maint(insn, address, res)                  \
 410         if (address >= user_addr_max()) {                       \
 411                 res = -EFAULT;                                  \
 412         } else {                                                \
 413                 uaccess_ttbr0_enable();                         \
 414                 asm volatile (                                  \
 415                         "1:     " insn ", %1\n"                 \
 416                         "       mov     %w0, #0\n"              \
 417                         "2:\n"                                  \
 418                         "       .pushsection .fixup,\"ax\"\n"   \
 419                         "       .align  2\n"                    \
 420                         "3:     mov     %w0, %w2\n"             \
 421                         "       b       2b\n"                   \
 422                         "       .popsection\n"                  \
 423                         _ASM_EXTABLE(1b, 3b)                    \
 424                         : "=r" (res)                            \
 425                         : "r" (address), "i" (-EFAULT));        \
 426                 uaccess_ttbr0_disable();                        \
 427         }
 428
 429 static void user_cache_maint_handler(unsigned int esr, struct pt_regs *regs)
 430 {
 431         unsigned long address;
 432         int rt = ESR_ELx_SYS64_ISS_RT(esr);
 433         int crm = (esr & ESR_ELx_SYS64_ISS_CRM_MASK) >> ESR_ELx_SYS64_ISS_CRM_SHIFT;
 434         int ret = 0;
 435
 436         address = untagged_addr(pt_regs_read_reg(regs, rt));
 437
 438         switch (crm) {
 439         case ESR_ELx_SYS64_ISS_CRM_DC_CVAU:     /* DC CVAU, gets promoted */
 440                 __user_cache_maint("dc civac", address, ret);
 441                 break;
 442         case ESR_ELx_SYS64_ISS_CRM_DC_CVAC:     /* DC CVAC, gets promoted */
 443                 __user_cache_maint("dc civac", address, ret);
 444                 break;
 445         case ESR_ELx_SYS64_ISS_CRM_DC_CVADP:    /* DC CVADP */
 446                 __user_cache_maint("sys 3, c7, c13, 1", address, ret);
 447                 break;
 448         case ESR_ELx_SYS64_ISS_CRM_DC_CVAP:     /* DC CVAP */
 449                 __user_cache_maint("sys 3, c7, c12, 1", address, ret);
 450                 break;
 451         case ESR_ELx_SYS64_ISS_CRM_DC_CIVAC:    /* DC CIVAC */
 452                 __user_cache_maint("dc civac", address, ret);
 453                 break;
 454         case ESR_ELx_SYS64_ISS_CRM_IC_IVAU:     /* IC IVAU */
 455                 __user_cache_maint("ic ivau", address, ret);
 456                 break;
 457         default:
 458                 force_signal_inject(SIGILL, ILL_ILLOPC, regs->pc);
 459                 return;
 460         }
 461
 462         if (ret)
 463                 arm64_notify_segfault(address);
 464         else
 465                 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE);
 466 }
 467
 468 static void ctr_read_handler(unsigned int esr, struct pt_regs *regs)
 469 {
 470         int rt = ESR_ELx_SYS64_ISS_RT(esr);
 471         unsigned long val = arm64_ftr_reg_user_value(&arm64_ftr_reg_ctrel0);
 472
 473         if (cpus_have_const_cap(ARM64_WORKAROUND_1542419)) {
 474                 /* Hide DIC so that we can trap the unnecessary maintenance...*/
 475                 val &= ~BIT(CTR_DIC_SHIFT);
 476
 477                 /* ... and fake IminLine to reduce the number of traps. */
 478                 val &= ~CTR_IMINLINE_MASK;
 479                 val |= (PAGE_SHIFT - 2) & CTR_IMINLINE_MASK;
 480         }
 481
 482         pt_regs_write_reg(regs, rt, val);
 483
 484         arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE);
 485 }
 486
 487 static void cntvct_read_handler(unsigned int esr, struct pt_regs *regs)
 488 {
 489         int rt = ESR_ELx_SYS64_ISS_RT(esr);
 490
 491         pt_regs_write_reg(regs, rt, arch_timer_read_counter());
 492         arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE);
 493 }
 494
 495 static void cntfrq_read_handler(unsigned int esr, struct pt_regs *regs)
 496 {
 497         int rt = ESR_ELx_SYS64_ISS_RT(esr);
 498
 499         pt_regs_write_reg(regs, rt, arch_timer_get_rate());
 500         arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE);
 501 }
 502
 503 static void mrs_handler(unsigned int esr, struct pt_regs *regs)
 504 {
 505         u32 sysreg, rt;
 506
 507         rt = ESR_ELx_SYS64_ISS_RT(esr);
 508         sysreg = esr_sys64_to_sysreg(esr);
 509
 510         if (do_emulate_mrs(regs, sysreg, rt) != 0)
 511                 force_signal_inject(SIGILL, ILL_ILLOPC, regs->pc);
 512 }
 513
 514 static void wfi_handler(unsigned int esr, struct pt_regs *regs)
 515 {
 516         arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE);
 517 }
 518
 519 struct sys64_hook {
 520         unsigned int esr_mask;
 521         unsigned int esr_val;
 522         void (*handler)(unsigned int esr, struct pt_regs *regs);
 523 };
 524
 525 static const struct sys64_hook sys64_hooks[] = {
 526         {
 527                 .esr_mask = ESR_ELx_SYS64_ISS_EL0_CACHE_OP_MASK,
 528                 .esr_val = ESR_ELx_SYS64_ISS_EL0_CACHE_OP_VAL,
 529                 .handler = user_cache_maint_handler,
 530         },
 531         {
 532                 /* Trap read access to CTR_EL0 */
 533                 .esr_mask = ESR_ELx_SYS64_ISS_SYS_OP_MASK,
 534                 .esr_val = ESR_ELx_SYS64_ISS_SYS_CTR_READ,
 535                 .handler = ctr_read_handler,
 536         },
 537         {
 538                 /* Trap read access to CNTVCT_EL0 */
 539                 .esr_mask = ESR_ELx_SYS64_ISS_SYS_OP_MASK,
 540                 .esr_val = ESR_ELx_SYS64_ISS_SYS_CNTVCT,
 541                 .handler = cntvct_read_handler,
 542         },
 543         {
 544                 /* Trap read access to CNTFRQ_EL0 */
 545                 .esr_mask = ESR_ELx_SYS64_ISS_SYS_OP_MASK,
 546                 .esr_val = ESR_ELx_SYS64_ISS_SYS_CNTFRQ,
 547                 .handler = cntfrq_read_handler,
 548         },
 549         {
 550                 /* Trap read access to CPUID registers */
 551                 .esr_mask = ESR_ELx_SYS64_ISS_SYS_MRS_OP_MASK,
 552                 .esr_val = ESR_ELx_SYS64_ISS_SYS_MRS_OP_VAL,
 553                 .handler = mrs_handler,
 554         },
 555         {
 556                 /* Trap WFI instructions executed in userspace */
 557                 .esr_mask = ESR_ELx_WFx_MASK,
 558                 .esr_val = ESR_ELx_WFx_WFI_VAL,
 559                 .handler = wfi_handler,
 560         },
 561         {},
 562 };
 563
 564
 565 #ifdef CONFIG_COMPAT
 566 #define PSTATE_IT_1_0_SHIFT     25
 567 #define PSTATE_IT_1_0_MASK      (0x3 << PSTATE_IT_1_0_SHIFT)
 568 #define PSTATE_IT_7_2_SHIFT     10
 569 #define PSTATE_IT_7_2_MASK      (0x3f << PSTATE_IT_7_2_SHIFT)
 570
 571 static u32 compat_get_it_state(struct pt_regs *regs)
 572 {
 573         u32 it, pstate = regs->pstate;
 574
 575         it  = (pstate & PSTATE_IT_1_0_MASK) >> PSTATE_IT_1_0_SHIFT;
 576         it |= ((pstate & PSTATE_IT_7_2_MASK) >> PSTATE_IT_7_2_SHIFT) << 2;
 577
 578         return it;
 579 }
 580
 581 static void compat_set_it_state(struct pt_regs *regs, u32 it)
 582 {
 583         u32 pstate_it;
 584
 585         pstate_it  = (it << PSTATE_IT_1_0_SHIFT) & PSTATE_IT_1_0_MASK;
 586         pstate_it |= ((it >> 2) << PSTATE_IT_7_2_SHIFT) & PSTATE_IT_7_2_MASK;
 587
 588         regs->pstate &= ~PSR_AA32_IT_MASK;
 589         regs->pstate |= pstate_it;
 590 }
 591
 592 static bool cp15_cond_valid(unsigned int esr, struct pt_regs *regs)
 593 {
 594         int cond;
 595
 596         /* Only a T32 instruction can trap without CV being set */
 597         if (!(esr & ESR_ELx_CV)) {
 598                 u32 it;
 599
 600                 it = compat_get_it_state(regs);
 601                 if (!it)
 602                         return true;
 603
 604                 cond = it >> 4;
 605         } else {
 606                 cond = (esr & ESR_ELx_COND_MASK) >> ESR_ELx_COND_SHIFT;
 607         }
 608
 609         return aarch32_opcode_cond_checks[cond](regs->pstate);
 610 }
 611
 612 static void advance_itstate(struct pt_regs *regs)
 613 {
 614         u32 it;
 615
 616         /* ARM mode */
 617         if (!(regs->pstate & PSR_AA32_T_BIT) ||
 618             !(regs->pstate & PSR_AA32_IT_MASK))
 619                 return;
 620
 621         it  = compat_get_it_state(regs);
 622
 623         /*
 624          * If this is the last instruction of the block, wipe the IT
 625          * state. Otherwise advance it.
 626          */
 627         if (!(it & 7))
 628                 it = 0;
 629         else
 630                 it = (it & 0xe0) | ((it << 1) & 0x1f);
 631
 632         compat_set_it_state(regs, it);
 633 }
 634
 635 static void arm64_compat_skip_faulting_instruction(struct pt_regs *regs,
 636                                                    unsigned int sz)
 637 {
 638         advance_itstate(regs);
 639         arm64_skip_faulting_instruction(regs, sz);
 640 }
 641
 642 static void compat_cntfrq_read_handler(unsigned int esr, struct pt_regs *regs)
 643 {
 644         int reg = (esr & ESR_ELx_CP15_32_ISS_RT_MASK) >> ESR_ELx_CP15_32_ISS_RT_SHIFT;
 645
 646         pt_regs_write_reg(regs, reg, arch_timer_get_rate());
 647         arm64_compat_skip_faulting_instruction(regs, 4);
 648 }
 649
 650 static const struct sys64_hook cp15_32_hooks[] = {
 651         {
 652                 .esr_mask = ESR_ELx_CP15_32_ISS_SYS_MASK,
 653                 .esr_val = ESR_ELx_CP15_32_ISS_SYS_CNTFRQ,
 654                 .handler = compat_cntfrq_read_handler,
 655         },
 656         {},
 657 };
 658
 659 static void compat_cntvct_read_handler(unsigned int esr, struct pt_regs *regs)
 660 {
 661         int rt = (esr & ESR_ELx_CP15_64_ISS_RT_MASK) >> ESR_ELx_CP15_64_ISS_RT_SHIFT;
 662         int rt2 = (esr & ESR_ELx_CP15_64_ISS_RT2_MASK) >> ESR_ELx_CP15_64_ISS_RT2_SHIFT;
 663         u64 val = arch_timer_read_counter();
 664
 665         pt_regs_write_reg(regs, rt, lower_32_bits(val));
 666         pt_regs_write_reg(regs, rt2, upper_32_bits(val));
 667         arm64_compat_skip_faulting_instruction(regs, 4);
 668 }
 669
 670 static const struct sys64_hook cp15_64_hooks[] = {
 671         {
 672                 .esr_mask = ESR_ELx_CP15_64_ISS_SYS_MASK,
 673                 .esr_val = ESR_ELx_CP15_64_ISS_SYS_CNTVCT,
 674                 .handler = compat_cntvct_read_handler,
 675         },
 676         {},
 677 };
 678
 679 asmlinkage void __exception do_cp15instr(unsigned int esr, struct pt_regs *regs)
 680 {
 681         const struct sys64_hook *hook, *hook_base;
 682
 683         if (!cp15_cond_valid(esr, regs)) {
 684                 /*
 685                  * There is no T16 variant of a CP access, so we
 686                  * always advance PC by 4 bytes.
 687                  */
 688                 arm64_compat_skip_faulting_instruction(regs, 4);
 689                 return;
 690         }
 691
 692         switch (ESR_ELx_EC(esr)) {
 693         case ESR_ELx_EC_CP15_32:
 694                 hook_base = cp15_32_hooks;
 695                 break;
 696         case ESR_ELx_EC_CP15_64:
 697                 hook_base = cp15_64_hooks;
 698                 break;
 699         default:
 700                 do_undefinstr(regs);
 701                 return;
 702         }
 703
 704         for (hook = hook_base; hook->handler; hook++)
 705                 if ((hook->esr_mask & esr) == hook->esr_val) {
 706                         hook->handler(esr, regs);
 707                         return;
 708                 }
 709
 710         /*
 711          * New cp15 instructions may previously have been undefined at
 712          * EL0. Fall back to our usual undefined instruction handler
 713          * so that we handle these consistently.
 714          */
 715         do_undefinstr(regs);
 716 }
 717 #endif
 718
 719 asmlinkage void __exception do_sysinstr(unsigned int esr, struct pt_regs *regs)
 720 {
 721         const struct sys64_hook *hook;
 722
 723         for (hook = sys64_hooks; hook->handler; hook++)
 724                 if ((hook->esr_mask & esr) == hook->esr_val) {
 725                         hook->handler(esr, regs);
 726                         return;
 727                 }
 728
 729         /*
 730          * New SYS instructions may previously have been undefined at EL0. Fall
 731          * back to our usual undefined instruction handler so that we handle
 732          * these consistently.
 733          */
 734         do_undefinstr(regs);
 735 }
 736
 737 static const char *esr_class_str[] = {
 738         [0 ... ESR_ELx_EC_MAX]          = "UNRECOGNIZED EC",
 739         [ESR_ELx_EC_UNKNOWN]            = "Unknown/Uncategorized",
 740         [ESR_ELx_EC_WFx]                = "WFI/WFE",
 741         [ESR_ELx_EC_CP15_32]            = "CP15 MCR/MRC",
 742         [ESR_ELx_EC_CP15_64]            = "CP15 MCRR/MRRC",
 743         [ESR_ELx_EC_CP14_MR]            = "CP14 MCR/MRC",
 744         [ESR_ELx_EC_CP14_LS]            = "CP14 LDC/STC",
 745         [ESR_ELx_EC_FP_ASIMD]           = "ASIMD",
 746         [ESR_ELx_EC_CP10_ID]            = "CP10 MRC/VMRS",
 747         [ESR_ELx_EC_PAC]                = "PAC",
 748         [ESR_ELx_EC_CP14_64]            = "CP14 MCRR/MRRC",
 749         [ESR_ELx_EC_ILL]                = "PSTATE.IL",
 750         [ESR_ELx_EC_SVC32]              = "SVC (AArch32)",
 751         [ESR_ELx_EC_HVC32]              = "HVC (AArch32)",
 752         [ESR_ELx_EC_SMC32]              = "SMC (AArch32)",
 753         [ESR_ELx_EC_SVC64]              = "SVC (AArch64)",
 754         [ESR_ELx_EC_HVC64]              = "HVC (AArch64)",
 755         [ESR_ELx_EC_SMC64]              = "SMC (AArch64)",
 756         [ESR_ELx_EC_SYS64]              = "MSR/MRS (AArch64)",
 757         [ESR_ELx_EC_SVE]                = "SVE",
 758         [ESR_ELx_EC_ERET]               = "ERET/ERETAA/ERETAB",
 759         [ESR_ELx_EC_IMP_DEF]            = "EL3 IMP DEF",
 760         [ESR_ELx_EC_IABT_LOW]           = "IABT (lower EL)",
 761         [ESR_ELx_EC_IABT_CUR]           = "IABT (current EL)",
 762         [ESR_ELx_EC_PC_ALIGN]           = "PC Alignment",
 763         [ESR_ELx_EC_DABT_LOW]           = "DABT (lower EL)",
 764         [ESR_ELx_EC_DABT_CUR]           = "DABT (current EL)",
 765         [ESR_ELx_EC_SP_ALIGN]           = "SP Alignment",
 766         [ESR_ELx_EC_FP_EXC32]           = "FP (AArch32)",
 767         [ESR_ELx_EC_FP_EXC64]           = "FP (AArch64)",
 768         [ESR_ELx_EC_SERROR]             = "SError",
 769         [ESR_ELx_EC_BREAKPT_LOW]        = "Breakpoint (lower EL)",
 770         [ESR_ELx_EC_BREAKPT_CUR]        = "Breakpoint (current EL)",
 771         [ESR_ELx_EC_SOFTSTP_LOW]        = "Software Step (lower EL)",
 772         [ESR_ELx_EC_SOFTSTP_CUR]        = "Software Step (current EL)",
 773         [ESR_ELx_EC_WATCHPT_LOW]        = "Watchpoint (lower EL)",
 774         [ESR_ELx_EC_WATCHPT_CUR]        = "Watchpoint (current EL)",
 775         [ESR_ELx_EC_BKPT32]             = "BKPT (AArch32)",
 776         [ESR_ELx_EC_VECTOR32]           = "Vector catch (AArch32)",
 777         [ESR_ELx_EC_BRK64]              = "BRK (AArch64)",
 778 };
 779
 780 const char *esr_get_class_string(u32 esr)
 781 {
 782         return esr_class_str[ESR_ELx_EC(esr)];
 783 }
 784
 785 /*
 786  * bad_mode handles the impossible case in the exception vector. This is always
 787  * fatal.
 788  */
 789 asmlinkage void bad_mode(struct pt_regs *regs, int reason, unsigned int esr)
 790 {
 791         console_verbose();
 792
 793         pr_crit("Bad mode in %s handler detected on CPU%d, code 0x%08x -- %s\n",
 794                 handler[reason], smp_processor_id(), esr,
 795                 esr_get_class_string(esr));
 796
 797         local_daif_mask();
 798         panic("bad mode");
 799 }
 800
 801 /*
 802  * bad_el0_sync handles unexpected, but potentially recoverable synchronous
 803  * exceptions taken from EL0. Unlike bad_mode, this returns.
 804  */
 805 asmlinkage void bad_el0_sync(struct pt_regs *regs, int reason, unsigned int esr)
 806 {
 807         void __user *pc = (void __user *)instruction_pointer(regs);
 808
 809         current->thread.fault_address = 0;
 810         current->thread.fault_code = esr;
 811
 812         arm64_force_sig_fault(SIGILL, ILL_ILLOPC, pc,
 813                               "Bad EL0 synchronous exception");
 814 }
 815
 816 #ifdef CONFIG_VMAP_STACK
 817
 818 DEFINE_PER_CPU(unsigned long [OVERFLOW_STACK_SIZE/sizeof(long)], overflow_stack)
 819         __aligned(16);
 820
 821 asmlinkage void handle_bad_stack(struct pt_regs *regs)
 822 {
 823         unsigned long tsk_stk = (unsigned long)current->stack;
 824         unsigned long irq_stk = (unsigned long)this_cpu_read(irq_stack_ptr);
 825         unsigned long ovf_stk = (unsigned long)this_cpu_ptr(overflow_stack);
 826         unsigned int esr = read_sysreg(esr_el1);
 827         unsigned long far = read_sysreg(far_el1);
 828
 829         console_verbose();
 830         pr_emerg("Insufficient stack space to handle exception!");
 831
 832         pr_emerg("ESR: 0x%08x -- %s\n", esr, esr_get_class_string(esr));
 833         pr_emerg("FAR: 0x%016lx\n", far);
 834
 835         pr_emerg("Task stack:     [0x%016lx..0x%016lx]\n",
 836                  tsk_stk, tsk_stk + THREAD_SIZE);
 837         pr_emerg("IRQ stack:      [0x%016lx..0x%016lx]\n",
 838                  irq_stk, irq_stk + THREAD_SIZE);
 839         pr_emerg("Overflow stack: [0x%016lx..0x%016lx]\n",
 840                  ovf_stk, ovf_stk + OVERFLOW_STACK_SIZE);
 841
 842         __show_regs(regs);
 843
 844         /*
 845          * We use nmi_panic to limit the potential for recusive overflows, and
 846          * to get a better stack trace.
 847          */
 848         nmi_panic(NULL, "kernel stack overflow");
 849         cpu_park_loop();
 850 }
 851 #endif
 852
 853 void __noreturn arm64_serror_panic(struct pt_regs *regs, u32 esr)
 854 {
 855         console_verbose();
 856
 857         pr_crit("SError Interrupt on CPU%d, code 0x%08x -- %s\n",
 858                 smp_processor_id(), esr, esr_get_class_string(esr));
 859         if (regs)
 860                 __show_regs(regs);
 861
 862         nmi_panic(regs, "Asynchronous SError Interrupt");
 863
 864         cpu_park_loop();
 865         unreachable();
 866 }
 867
 868 bool arm64_is_fatal_ras_serror(struct pt_regs *regs, unsigned int esr)
 869 {
 870         u32 aet = arm64_ras_serror_get_severity(esr);
 871
 872         switch (aet) {
 873         case ESR_ELx_AET_CE:    /* corrected error */
 874         case ESR_ELx_AET_UEO:   /* restartable, not yet consumed */
 875                 /*
 876                  * The CPU can make progress. We may take UEO again as
 877                  * a more severe error.
 878                  */
 879                 return false;
 880
 881         case ESR_ELx_AET_UEU:   /* Uncorrected Unrecoverable */
 882         case ESR_ELx_AET_UER:   /* Uncorrected Recoverable */
 883                 /*
 884                  * The CPU can't make progress. The exception may have
 885                  * been imprecise.
 886                  *
 887                  * Neoverse-N1 #1349291 means a non-KVM SError reported as
 888                  * Unrecoverable should be treated as Uncontainable. We
 889                  * call arm64_serror_panic() in both cases.
 890                  */
 891                 return true;
 892
 893         case ESR_ELx_AET_UC:    /* Uncontainable or Uncategorized error */
 894         default:
 895                 /* Error has been silently propagated */
 896                 arm64_serror_panic(regs, esr);
 897         }
 898 }
 899
 900 asmlinkage void do_serror(struct pt_regs *regs, unsigned int esr)
 901 {
 902         const bool was_in_nmi = in_nmi();
 903
 904         if (!was_in_nmi)
 905                 nmi_enter();
 906
 907         /* non-RAS errors are not containable */
 908         if (!arm64_is_ras_serror(esr) || arm64_is_fatal_ras_serror(regs, esr))
 909                 arm64_serror_panic(regs, esr);
 910
 911         if (!was_in_nmi)
 912                 nmi_exit();
 913 }
 914
 915 asmlinkage void enter_from_user_mode(void)
 916 {
 917         CT_WARN_ON(ct_state() != CONTEXT_USER);
 918         user_exit_irqoff();
 919 }
 920 NOKPROBE_SYMBOL(enter_from_user_mode);
 921
 922 void __pte_error(const char *file, int line, unsigned long val)
 923 {
 924         pr_err("%s:%d: bad pte %016lx.\n", file, line, val);
 925 }
 926
 927 void __pmd_error(const char *file, int line, unsigned long val)
 928 {
 929         pr_err("%s:%d: bad pmd %016lx.\n", file, line, val);
 930 }
 931
 932 void __pud_error(const char *file, int line, unsigned long val)
 933 {
 934         pr_err("%s:%d: bad pud %016lx.\n", file, line, val);
 935 }
 936
 937 void __pgd_error(const char *file, int line, unsigned long val)
 938 {
 939         pr_err("%s:%d: bad pgd %016lx.\n", file, line, val);
 940 }
 941
 942 /* GENERIC_BUG traps */
 943
 944 int is_valid_bugaddr(unsigned long addr)
 945 {
 946         /*
 947          * bug_handler() only called for BRK #BUG_BRK_IMM.
 948          * So the answer is trivial -- any spurious instances with no
 949          * bug table entry will be rejected by report_bug() and passed
 950          * back to the debug-monitors code and handled as a fatal
 951          * unexpected debug exception.
 952          */
 953         return 1;
 954 }
 955
 956 static int bug_handler(struct pt_regs *regs, unsigned int esr)
 957 {
 958         switch (report_bug(regs->pc, regs)) {
 959         case BUG_TRAP_TYPE_BUG:
 960                 die("Oops - BUG", regs, 0);
 961                 break;
 962
 963         case BUG_TRAP_TYPE_WARN:
 964                 break;
 965
 966         default:
 967                 /* unknown/unrecognised bug trap type */
 968                 return DBG_HOOK_ERROR;
 969         }
 970
 971         /* If thread survives, skip over the BUG instruction and continue: */
 972         arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE);
 973         return DBG_HOOK_HANDLED;
 974 }
 975
 976 static struct break_hook bug_break_hook = {
 977         .fn = bug_handler,
 978         .imm = BUG_BRK_IMM,
 979 };
 980
 981 #ifdef CONFIG_KASAN_SW_TAGS
 982
 983 #define KASAN_ESR_RECOVER       0x20
 984 #define KASAN_ESR_WRITE 0x10
 985 #define KASAN_ESR_SIZE_MASK     0x0f
 986 #define KASAN_ESR_SIZE(esr)     (1 << ((esr) & KASAN_ESR_SIZE_MASK))
 987
 988 static int kasan_handler(struct pt_regs *regs, unsigned int esr)
 989 {
 990         bool recover = esr & KASAN_ESR_RECOVER;
 991         bool write = esr & KASAN_ESR_WRITE;
 992         size_t size = KASAN_ESR_SIZE(esr);
 993         u64 addr = regs->regs[0];
 994         u64 pc = regs->pc;
 995
 996         kasan_report(addr, size, write, pc);
 997
 998         /*
 999          * The instrumentation allows to control whether we can proceed after
1000          * a crash was detected. This is done by passing the -recover flag to
1001          * the compiler. Disabling recovery allows to generate more compact
1002          * code.
1003          *
1004          * Unfortunately disabling recovery doesn't work for the kernel right
1005          * now. KASAN reporting is disabled in some contexts (for example when
1006          * the allocator accesses slab object metadata; this is controlled by
1007          * current->kasan_depth). All these accesses are detected by the tool,
1008          * even though the reports for them are not printed.
1009          *
1010          * This is something that might be fixed at some point in the future.
1011          */
1012         if (!recover)
1013                 die("Oops - KASAN", regs, 0);
1014
1015         /* If thread survives, skip over the brk instruction and continue: */
1016         arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE);
1017         return DBG_HOOK_HANDLED;
1018 }
1019
1020 static struct break_hook kasan_break_hook = {
1021         .fn     = kasan_handler,
1022         .imm    = KASAN_BRK_IMM,
1023         .mask   = KASAN_BRK_MASK,
1024 };
1025 #endif
1026
1027 /*
1028  * Initial handler for AArch64 BRK exceptions
1029  * This handler only used until debug_traps_init().
1030  */
1031 int __init early_brk64(unsigned long addr, unsigned int esr,
1032                 struct pt_regs *regs)
1033 {
1034 #ifdef CONFIG_KASAN_SW_TAGS
1035         unsigned int comment = esr & ESR_ELx_BRK64_ISS_COMMENT_MASK;
1036
1037         if ((comment & ~KASAN_BRK_MASK) == KASAN_BRK_IMM)
1038                 return kasan_handler(regs, esr) != DBG_HOOK_HANDLED;
1039 #endif
1040         return bug_handler(regs, esr) != DBG_HOOK_HANDLED;
1041 }
1042
1043 /* This registration must happen early, before debug_traps_init(). */
1044 void __init trap_init(void)
1045 {
1046         register_kernel_break_hook(&bug_break_hook);
1047 #ifdef CONFIG_KASAN_SW_TAGS
1048         register_kernel_break_hook(&kasan_break_hook);
1049 #endif
1050 }