arch/arm64/kernel/traps.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Based on arch/arm/kernel/traps.c
   4  *
   5  * Copyright (C) 1995-2009 Russell King
   6  * Copyright (C) 2012 ARM Ltd.
   7  */
   8
   9 #include <linux/bug.h>
  10 #include <linux/context_tracking.h>
  11 #include <linux/signal.h>
  12 #include <linux/kallsyms.h>
  13 #include <linux/kprobes.h>
  14 #include <linux/spinlock.h>
  15 #include <linux/uaccess.h>
  16 #include <linux/hardirq.h>
  17 #include <linux/kdebug.h>
  18 #include <linux/module.h>
  19 #include <linux/kexec.h>
  20 #include <linux/delay.h>
  21 #include <linux/init.h>
  22 #include <linux/sched/signal.h>
  23 #include <linux/sched/debug.h>
  24 #include <linux/sched/task_stack.h>
  25 #include <linux/sizes.h>
  26 #include <linux/syscalls.h>
  27 #include <linux/mm_types.h>
  28 #include <linux/kasan.h>
  29 #include <linux/cfi.h>
  30
  31 #include <asm/atomic.h>
  32 #include <asm/bug.h>
  33 #include <asm/cpufeature.h>
  34 #include <asm/daifflags.h>
  35 #include <asm/debug-monitors.h>
  36 #include <asm/esr.h>
  37 #include <asm/exception.h>
  38 #include <asm/extable.h>
  39 #include <asm/insn.h>
  40 #include <asm/kprobes.h>
  41 #include <asm/patching.h>
  42 #include <asm/traps.h>
  43 #include <asm/smp.h>
  44 #include <asm/stack_pointer.h>
  45 #include <asm/stacktrace.h>
  46 #include <asm/system_misc.h>
  47 #include <asm/sysreg.h>
  48
  49 static bool __kprobes __check_eq(unsigned long pstate)
  50 {
  51         return (pstate & PSR_Z_BIT) != 0;
  52 }
  53
  54 static bool __kprobes __check_ne(unsigned long pstate)
  55 {
  56         return (pstate & PSR_Z_BIT) == 0;
  57 }
  58
  59 static bool __kprobes __check_cs(unsigned long pstate)
  60 {
  61         return (pstate & PSR_C_BIT) != 0;
  62 }
  63
  64 static bool __kprobes __check_cc(unsigned long pstate)
  65 {
  66         return (pstate & PSR_C_BIT) == 0;
  67 }
  68
  69 static bool __kprobes __check_mi(unsigned long pstate)
  70 {
  71         return (pstate & PSR_N_BIT) != 0;
  72 }
  73
  74 static bool __kprobes __check_pl(unsigned long pstate)
  75 {
  76         return (pstate & PSR_N_BIT) == 0;
  77 }
  78
  79 static bool __kprobes __check_vs(unsigned long pstate)
  80 {
  81         return (pstate & PSR_V_BIT) != 0;
  82 }
  83
  84 static bool __kprobes __check_vc(unsigned long pstate)
  85 {
  86         return (pstate & PSR_V_BIT) == 0;
  87 }
  88
  89 static bool __kprobes __check_hi(unsigned long pstate)
  90 {
  91         pstate &= ~(pstate >> 1);       /* PSR_C_BIT &= ~PSR_Z_BIT */
  92         return (pstate & PSR_C_BIT) != 0;
  93 }
  94
  95 static bool __kprobes __check_ls(unsigned long pstate)
  96 {
  97         pstate &= ~(pstate >> 1);       /* PSR_C_BIT &= ~PSR_Z_BIT */
  98         return (pstate & PSR_C_BIT) == 0;
  99 }
 100
 101 static bool __kprobes __check_ge(unsigned long pstate)
 102 {
 103         pstate ^= (pstate << 3);        /* PSR_N_BIT ^= PSR_V_BIT */
 104         return (pstate & PSR_N_BIT) == 0;
 105 }
 106
 107 static bool __kprobes __check_lt(unsigned long pstate)
 108 {
 109         pstate ^= (pstate << 3);        /* PSR_N_BIT ^= PSR_V_BIT */
 110         return (pstate & PSR_N_BIT) != 0;
 111 }
 112
 113 static bool __kprobes __check_gt(unsigned long pstate)
 114 {
 115         /*PSR_N_BIT ^= PSR_V_BIT */
 116         unsigned long temp = pstate ^ (pstate << 3);
 117
 118         temp |= (pstate << 1);  /*PSR_N_BIT |= PSR_Z_BIT */
 119         return (temp & PSR_N_BIT) == 0;
 120 }
 121
 122 static bool __kprobes __check_le(unsigned long pstate)
 123 {
 124         /*PSR_N_BIT ^= PSR_V_BIT */
 125         unsigned long temp = pstate ^ (pstate << 3);
 126
 127         temp |= (pstate << 1);  /*PSR_N_BIT |= PSR_Z_BIT */
 128         return (temp & PSR_N_BIT) != 0;
 129 }
 130
 131 static bool __kprobes __check_al(unsigned long pstate)
 132 {
 133         return true;
 134 }
 135
 136 /*
 137  * Note that the ARMv8 ARM calls condition code 0b1111 "nv", but states that
 138  * it behaves identically to 0b1110 ("al").
 139  */
 140 pstate_check_t * const aarch32_opcode_cond_checks[16] = {
 141         __check_eq, __check_ne, __check_cs, __check_cc,
 142         __check_mi, __check_pl, __check_vs, __check_vc,
 143         __check_hi, __check_ls, __check_ge, __check_lt,
 144         __check_gt, __check_le, __check_al, __check_al
 145 };
 146
 147 int show_unhandled_signals = 0;
 148
 149 static void dump_kernel_instr(const char *lvl, struct pt_regs *regs)
 150 {
 151         unsigned long addr = instruction_pointer(regs);
 152         char str[sizeof("00000000 ") * 5 + 2 + 1], *p = str;
 153         int i;
 154
 155         if (user_mode(regs))
 156                 return;
 157
 158         for (i = -4; i < 1; i++) {
 159                 unsigned int val, bad;
 160
 161                 bad = aarch64_insn_read(&((u32 *)addr)[i], &val);
 162
 163                 if (!bad)
 164                         p += sprintf(p, i == 0 ? "(%08x) " : "%08x ", val);
 165                 else {
 166                         p += sprintf(p, "bad PC value");
 167                         break;
 168                 }
 169         }
 170
 171         printk("%sCode: %s\n", lvl, str);
 172 }
 173
 174 #ifdef CONFIG_PREEMPT
 175 #define S_PREEMPT " PREEMPT"
 176 #elif defined(CONFIG_PREEMPT_RT)
 177 #define S_PREEMPT " PREEMPT_RT"
 178 #else
 179 #define S_PREEMPT ""
 180 #endif
 181
 182 #define S_SMP " SMP"
 183
 184 static int __die(const char *str, long err, struct pt_regs *regs)
 185 {
 186         static int die_counter;
 187         int ret;
 188
 189         pr_emerg("Internal error: %s: %016lx [#%d]" S_PREEMPT S_SMP "\n",
 190                  str, err, ++die_counter);
 191
 192         /* trap and error numbers are mostly meaningless on ARM */
 193         ret = notify_die(DIE_OOPS, str, regs, err, 0, SIGSEGV);
 194         if (ret == NOTIFY_STOP)
 195                 return ret;
 196
 197         print_modules();
 198         show_regs(regs);
 199
 200         dump_kernel_instr(KERN_EMERG, regs);
 201
 202         return ret;
 203 }
 204
 205 static DEFINE_RAW_SPINLOCK(die_lock);
 206
 207 /*
 208  * This function is protected against re-entrancy.
 209  */
 210 void die(const char *str, struct pt_regs *regs, long err)
 211 {
 212         int ret;
 213         unsigned long flags;
 214
 215         raw_spin_lock_irqsave(&die_lock, flags);
 216
 217         oops_enter();
 218
 219         console_verbose();
 220         bust_spinlocks(1);
 221         ret = __die(str, err, regs);
 222
 223         if (regs && kexec_should_crash(current))
 224                 crash_kexec(regs);
 225
 226         bust_spinlocks(0);
 227         add_taint(TAINT_DIE, LOCKDEP_NOW_UNRELIABLE);
 228         oops_exit();
 229
 230         if (in_interrupt())
 231                 panic("%s: Fatal exception in interrupt", str);
 232         if (panic_on_oops)
 233                 panic("%s: Fatal exception", str);
 234
 235         raw_spin_unlock_irqrestore(&die_lock, flags);
 236
 237         if (ret != NOTIFY_STOP)
 238                 make_task_dead(SIGSEGV);
 239 }
 240
 241 static void arm64_show_signal(int signo, const char *str)
 242 {
 243         static DEFINE_RATELIMIT_STATE(rs, DEFAULT_RATELIMIT_INTERVAL,
 244                                       DEFAULT_RATELIMIT_BURST);
 245         struct task_struct *tsk = current;
 246         unsigned long esr = tsk->thread.fault_code;
 247         struct pt_regs *regs = task_pt_regs(tsk);
 248
 249         /* Leave if the signal won't be shown */
 250         if (!show_unhandled_signals ||
 251             !unhandled_signal(tsk, signo) ||
 252             !__ratelimit(&rs))
 253                 return;
 254
 255         pr_info("%s[%d]: unhandled exception: ", tsk->comm, task_pid_nr(tsk));
 256         if (esr)
 257                 pr_cont("%s, ESR 0x%016lx, ", esr_get_class_string(esr), esr);
 258
 259         pr_cont("%s", str);
 260         print_vma_addr(KERN_CONT " in ", regs->pc);
 261         pr_cont("\n");
 262         __show_regs(regs);
 263 }
 264
 265 void arm64_force_sig_fault(int signo, int code, unsigned long far,
 266                            const char *str)
 267 {
 268         arm64_show_signal(signo, str);
 269         if (signo == SIGKILL)
 270                 force_sig(SIGKILL);
 271         else
 272                 force_sig_fault(signo, code, (void __user *)far);
 273 }
 274
 275 void arm64_force_sig_mceerr(int code, unsigned long far, short lsb,
 276                             const char *str)
 277 {
 278         arm64_show_signal(SIGBUS, str);
 279         force_sig_mceerr(code, (void __user *)far, lsb);
 280 }
 281
 282 void arm64_force_sig_ptrace_errno_trap(int errno, unsigned long far,
 283                                        const char *str)
 284 {
 285         arm64_show_signal(SIGTRAP, str);
 286         force_sig_ptrace_errno_trap(errno, (void __user *)far);
 287 }
 288
 289 void arm64_notify_die(const char *str, struct pt_regs *regs,
 290                       int signo, int sicode, unsigned long far,
 291                       unsigned long err)
 292 {
 293         if (user_mode(regs)) {
 294                 WARN_ON(regs != current_pt_regs());
 295                 current->thread.fault_address = 0;
 296                 current->thread.fault_code = err;
 297
 298                 arm64_force_sig_fault(signo, sicode, far, str);
 299         } else {
 300                 die(str, regs, err);
 301         }
 302 }
 303
 304 #ifdef CONFIG_COMPAT
 305 #define PSTATE_IT_1_0_SHIFT     25
 306 #define PSTATE_IT_1_0_MASK      (0x3 << PSTATE_IT_1_0_SHIFT)
 307 #define PSTATE_IT_7_2_SHIFT     10
 308 #define PSTATE_IT_7_2_MASK      (0x3f << PSTATE_IT_7_2_SHIFT)
 309
 310 static u32 compat_get_it_state(struct pt_regs *regs)
 311 {
 312         u32 it, pstate = regs->pstate;
 313
 314         it  = (pstate & PSTATE_IT_1_0_MASK) >> PSTATE_IT_1_0_SHIFT;
 315         it |= ((pstate & PSTATE_IT_7_2_MASK) >> PSTATE_IT_7_2_SHIFT) << 2;
 316
 317         return it;
 318 }
 319
 320 static void compat_set_it_state(struct pt_regs *regs, u32 it)
 321 {
 322         u32 pstate_it;
 323
 324         pstate_it  = (it << PSTATE_IT_1_0_SHIFT) & PSTATE_IT_1_0_MASK;
 325         pstate_it |= ((it >> 2) << PSTATE_IT_7_2_SHIFT) & PSTATE_IT_7_2_MASK;
 326
 327         regs->pstate &= ~PSR_AA32_IT_MASK;
 328         regs->pstate |= pstate_it;
 329 }
 330
 331 static void advance_itstate(struct pt_regs *regs)
 332 {
 333         u32 it;
 334
 335         /* ARM mode */
 336         if (!(regs->pstate & PSR_AA32_T_BIT) ||
 337             !(regs->pstate & PSR_AA32_IT_MASK))
 338                 return;
 339
 340         it  = compat_get_it_state(regs);
 341
 342         /*
 343          * If this is the last instruction of the block, wipe the IT
 344          * state. Otherwise advance it.
 345          */
 346         if (!(it & 7))
 347                 it = 0;
 348         else
 349                 it = (it & 0xe0) | ((it << 1) & 0x1f);
 350
 351         compat_set_it_state(regs, it);
 352 }
 353 #else
 354 static void advance_itstate(struct pt_regs *regs)
 355 {
 356 }
 357 #endif
 358
 359 void arm64_skip_faulting_instruction(struct pt_regs *regs, unsigned long size)
 360 {
 361         regs->pc += size;
 362
 363         /*
 364          * If we were single stepping, we want to get the step exception after
 365          * we return from the trap.
 366          */
 367         if (user_mode(regs))
 368                 user_fastforward_single_step(current);
 369
 370         if (compat_user_mode(regs))
 371                 advance_itstate(regs);
 372         else
 373                 regs->pstate &= ~PSR_BTYPE_MASK;
 374 }
 375
 376 static LIST_HEAD(undef_hook);
 377 static DEFINE_RAW_SPINLOCK(undef_lock);
 378
 379 void register_undef_hook(struct undef_hook *hook)
 380 {
 381         unsigned long flags;
 382
 383         raw_spin_lock_irqsave(&undef_lock, flags);
 384         list_add(&hook->node, &undef_hook);
 385         raw_spin_unlock_irqrestore(&undef_lock, flags);
 386 }
 387
 388 void unregister_undef_hook(struct undef_hook *hook)
 389 {
 390         unsigned long flags;
 391
 392         raw_spin_lock_irqsave(&undef_lock, flags);
 393         list_del(&hook->node);
 394         raw_spin_unlock_irqrestore(&undef_lock, flags);
 395 }
 396
 397 static int call_undef_hook(struct pt_regs *regs)
 398 {
 399         struct undef_hook *hook;
 400         unsigned long flags;
 401         u32 instr;
 402         int (*fn)(struct pt_regs *regs, u32 instr) = NULL;
 403         unsigned long pc = instruction_pointer(regs);
 404
 405         if (!user_mode(regs)) {
 406                 __le32 instr_le;
 407                 if (get_kernel_nofault(instr_le, (__le32 *)pc))
 408                         goto exit;
 409                 instr = le32_to_cpu(instr_le);
 410         } else if (compat_thumb_mode(regs)) {
 411                 /* 16-bit Thumb instruction */
 412                 __le16 instr_le;
 413                 if (get_user(instr_le, (__le16 __user *)pc))
 414                         goto exit;
 415                 instr = le16_to_cpu(instr_le);
 416                 if (aarch32_insn_is_wide(instr)) {
 417                         u32 instr2;
 418
 419                         if (get_user(instr_le, (__le16 __user *)(pc + 2)))
 420                                 goto exit;
 421                         instr2 = le16_to_cpu(instr_le);
 422                         instr = (instr << 16) | instr2;
 423                 }
 424         } else {
 425                 /* 32-bit ARM instruction */
 426                 __le32 instr_le;
 427                 if (get_user(instr_le, (__le32 __user *)pc))
 428                         goto exit;
 429                 instr = le32_to_cpu(instr_le);
 430         }
 431
 432         raw_spin_lock_irqsave(&undef_lock, flags);
 433         list_for_each_entry(hook, &undef_hook, node)
 434                 if ((instr & hook->instr_mask) == hook->instr_val &&
 435                         (regs->pstate & hook->pstate_mask) == hook->pstate_val)
 436                         fn = hook->fn;
 437
 438         raw_spin_unlock_irqrestore(&undef_lock, flags);
 439 exit:
 440         return fn ? fn(regs, instr) : 1;
 441 }
 442
 443 void force_signal_inject(int signal, int code, unsigned long address, unsigned long err)
 444 {
 445         const char *desc;
 446         struct pt_regs *regs = current_pt_regs();
 447
 448         if (WARN_ON(!user_mode(regs)))
 449                 return;
 450
 451         switch (signal) {
 452         case SIGILL:
 453                 desc = "undefined instruction";
 454                 break;
 455         case SIGSEGV:
 456                 desc = "illegal memory access";
 457                 break;
 458         default:
 459                 desc = "unknown or unrecoverable error";
 460                 break;
 461         }
 462
 463         /* Force signals we don't understand to SIGKILL */
 464         if (WARN_ON(signal != SIGKILL &&
 465                     siginfo_layout(signal, code) != SIL_FAULT)) {
 466                 signal = SIGKILL;
 467         }
 468
 469         arm64_notify_die(desc, regs, signal, code, address, err);
 470 }
 471
 472 /*
 473  * Set up process info to signal segmentation fault - called on access error.
 474  */
 475 void arm64_notify_segfault(unsigned long addr)
 476 {
 477         int code;
 478
 479         mmap_read_lock(current->mm);
 480         if (find_vma(current->mm, untagged_addr(addr)) == NULL)
 481                 code = SEGV_MAPERR;
 482         else
 483                 code = SEGV_ACCERR;
 484         mmap_read_unlock(current->mm);
 485
 486         force_signal_inject(SIGSEGV, code, addr, 0);
 487 }
 488
 489 void do_undefinstr(struct pt_regs *regs, unsigned long esr)
 490 {
 491         /* check for AArch32 breakpoint instructions */
 492         if (!aarch32_break_handler(regs))
 493                 return;
 494
 495         if (call_undef_hook(regs) == 0)
 496                 return;
 497
 498         if (!user_mode(regs))
 499                 die("Oops - Undefined instruction", regs, esr);
 500
 501         force_signal_inject(SIGILL, ILL_ILLOPC, regs->pc, 0);
 502 }
 503 NOKPROBE_SYMBOL(do_undefinstr);
 504
 505 void do_el0_bti(struct pt_regs *regs)
 506 {
 507         force_signal_inject(SIGILL, ILL_ILLOPC, regs->pc, 0);
 508 }
 509
 510 void do_el1_bti(struct pt_regs *regs, unsigned long esr)
 511 {
 512         die("Oops - BTI", regs, esr);
 513 }
 514 NOKPROBE_SYMBOL(do_el1_bti);
 515
 516 void do_el0_fpac(struct pt_regs *regs, unsigned long esr)
 517 {
 518         force_signal_inject(SIGILL, ILL_ILLOPN, regs->pc, esr);
 519 }
 520
 521 void do_el1_fpac(struct pt_regs *regs, unsigned long esr)
 522 {
 523         /*
 524          * Unexpected FPAC exception in the kernel: kill the task before it
 525          * does any more harm.
 526          */
 527         die("Oops - FPAC", regs, esr);
 528 }
 529 NOKPROBE_SYMBOL(do_el1_fpac)
 530
 531 #define __user_cache_maint(insn, address, res)                  \
 532         if (address >= TASK_SIZE_MAX) {                         \
 533                 res = -EFAULT;                                  \
 534         } else {                                                \
 535                 uaccess_ttbr0_enable();                         \
 536                 asm volatile (                                  \
 537                         "1:     " insn ", %1\n"                 \
 538                         "       mov     %w0, #0\n"              \
 539                         "2:\n"                                  \
 540                         _ASM_EXTABLE_UACCESS_ERR(1b, 2b, %w0)   \
 541                         : "=r" (res)                            \
 542                         : "r" (address));                       \
 543                 uaccess_ttbr0_disable();                        \
 544         }
 545
 546 static void user_cache_maint_handler(unsigned long esr, struct pt_regs *regs)
 547 {
 548         unsigned long tagged_address, address;
 549         int rt = ESR_ELx_SYS64_ISS_RT(esr);
 550         int crm = (esr & ESR_ELx_SYS64_ISS_CRM_MASK) >> ESR_ELx_SYS64_ISS_CRM_SHIFT;
 551         int ret = 0;
 552
 553         tagged_address = pt_regs_read_reg(regs, rt);
 554         address = untagged_addr(tagged_address);
 555
 556         switch (crm) {
 557         case ESR_ELx_SYS64_ISS_CRM_DC_CVAU:     /* DC CVAU, gets promoted */
 558                 __user_cache_maint("dc civac", address, ret);
 559                 break;
 560         case ESR_ELx_SYS64_ISS_CRM_DC_CVAC:     /* DC CVAC, gets promoted */
 561                 __user_cache_maint("dc civac", address, ret);
 562                 break;
 563         case ESR_ELx_SYS64_ISS_CRM_DC_CVADP:    /* DC CVADP */
 564                 __user_cache_maint("sys 3, c7, c13, 1", address, ret);
 565                 break;
 566         case ESR_ELx_SYS64_ISS_CRM_DC_CVAP:     /* DC CVAP */
 567                 __user_cache_maint("sys 3, c7, c12, 1", address, ret);
 568                 break;
 569         case ESR_ELx_SYS64_ISS_CRM_DC_CIVAC:    /* DC CIVAC */
 570                 __user_cache_maint("dc civac", address, ret);
 571                 break;
 572         case ESR_ELx_SYS64_ISS_CRM_IC_IVAU:     /* IC IVAU */
 573                 __user_cache_maint("ic ivau", address, ret);
 574                 break;
 575         default:
 576                 force_signal_inject(SIGILL, ILL_ILLOPC, regs->pc, 0);
 577                 return;
 578         }
 579
 580         if (ret)
 581                 arm64_notify_segfault(tagged_address);
 582         else
 583                 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE);
 584 }
 585
 586 static void ctr_read_handler(unsigned long esr, struct pt_regs *regs)
 587 {
 588         int rt = ESR_ELx_SYS64_ISS_RT(esr);
 589         unsigned long val = arm64_ftr_reg_user_value(&arm64_ftr_reg_ctrel0);
 590
 591         if (cpus_have_const_cap(ARM64_WORKAROUND_1542419)) {
 592                 /* Hide DIC so that we can trap the unnecessary maintenance...*/
 593                 val &= ~BIT(CTR_EL0_DIC_SHIFT);
 594
 595                 /* ... and fake IminLine to reduce the number of traps. */
 596                 val &= ~CTR_EL0_IminLine_MASK;
 597                 val |= (PAGE_SHIFT - 2) & CTR_EL0_IminLine_MASK;
 598         }
 599
 600         pt_regs_write_reg(regs, rt, val);
 601
 602         arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE);
 603 }
 604
 605 static void cntvct_read_handler(unsigned long esr, struct pt_regs *regs)
 606 {
 607         int rt = ESR_ELx_SYS64_ISS_RT(esr);
 608
 609         pt_regs_write_reg(regs, rt, arch_timer_read_counter());
 610         arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE);
 611 }
 612
 613 static void cntfrq_read_handler(unsigned long esr, struct pt_regs *regs)
 614 {
 615         int rt = ESR_ELx_SYS64_ISS_RT(esr);
 616
 617         pt_regs_write_reg(regs, rt, arch_timer_get_rate());
 618         arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE);
 619 }
 620
 621 static void mrs_handler(unsigned long esr, struct pt_regs *regs)
 622 {
 623         u32 sysreg, rt;
 624
 625         rt = ESR_ELx_SYS64_ISS_RT(esr);
 626         sysreg = esr_sys64_to_sysreg(esr);
 627
 628         if (do_emulate_mrs(regs, sysreg, rt) != 0)
 629                 force_signal_inject(SIGILL, ILL_ILLOPC, regs->pc, 0);
 630 }
 631
 632 static void wfi_handler(unsigned long esr, struct pt_regs *regs)
 633 {
 634         arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE);
 635 }
 636
 637 struct sys64_hook {
 638         unsigned long esr_mask;
 639         unsigned long esr_val;
 640         void (*handler)(unsigned long esr, struct pt_regs *regs);
 641 };
 642
 643 static const struct sys64_hook sys64_hooks[] = {
 644         {
 645                 .esr_mask = ESR_ELx_SYS64_ISS_EL0_CACHE_OP_MASK,
 646                 .esr_val = ESR_ELx_SYS64_ISS_EL0_CACHE_OP_VAL,
 647                 .handler = user_cache_maint_handler,
 648         },
 649         {
 650                 /* Trap read access to CTR_EL0 */
 651                 .esr_mask = ESR_ELx_SYS64_ISS_SYS_OP_MASK,
 652                 .esr_val = ESR_ELx_SYS64_ISS_SYS_CTR_READ,
 653                 .handler = ctr_read_handler,
 654         },
 655         {
 656                 /* Trap read access to CNTVCT_EL0 */
 657                 .esr_mask = ESR_ELx_SYS64_ISS_SYS_OP_MASK,
 658                 .esr_val = ESR_ELx_SYS64_ISS_SYS_CNTVCT,
 659                 .handler = cntvct_read_handler,
 660         },
 661         {
 662                 /* Trap read access to CNTVCTSS_EL0 */
 663                 .esr_mask = ESR_ELx_SYS64_ISS_SYS_OP_MASK,
 664                 .esr_val = ESR_ELx_SYS64_ISS_SYS_CNTVCTSS,
 665                 .handler = cntvct_read_handler,
 666         },
 667         {
 668                 /* Trap read access to CNTFRQ_EL0 */
 669                 .esr_mask = ESR_ELx_SYS64_ISS_SYS_OP_MASK,
 670                 .esr_val = ESR_ELx_SYS64_ISS_SYS_CNTFRQ,
 671                 .handler = cntfrq_read_handler,
 672         },
 673         {
 674                 /* Trap read access to CPUID registers */
 675                 .esr_mask = ESR_ELx_SYS64_ISS_SYS_MRS_OP_MASK,
 676                 .esr_val = ESR_ELx_SYS64_ISS_SYS_MRS_OP_VAL,
 677                 .handler = mrs_handler,
 678         },
 679         {
 680                 /* Trap WFI instructions executed in userspace */
 681                 .esr_mask = ESR_ELx_WFx_MASK,
 682                 .esr_val = ESR_ELx_WFx_WFI_VAL,
 683                 .handler = wfi_handler,
 684         },
 685         {},
 686 };
 687
 688 #ifdef CONFIG_COMPAT
 689 static bool cp15_cond_valid(unsigned long esr, struct pt_regs *regs)
 690 {
 691         int cond;
 692
 693         /* Only a T32 instruction can trap without CV being set */
 694         if (!(esr & ESR_ELx_CV)) {
 695                 u32 it;
 696
 697                 it = compat_get_it_state(regs);
 698                 if (!it)
 699                         return true;
 700
 701                 cond = it >> 4;
 702         } else {
 703                 cond = (esr & ESR_ELx_COND_MASK) >> ESR_ELx_COND_SHIFT;
 704         }
 705
 706         return aarch32_opcode_cond_checks[cond](regs->pstate);
 707 }
 708
 709 static void compat_cntfrq_read_handler(unsigned long esr, struct pt_regs *regs)
 710 {
 711         int reg = (esr & ESR_ELx_CP15_32_ISS_RT_MASK) >> ESR_ELx_CP15_32_ISS_RT_SHIFT;
 712
 713         pt_regs_write_reg(regs, reg, arch_timer_get_rate());
 714         arm64_skip_faulting_instruction(regs, 4);
 715 }
 716
 717 static const struct sys64_hook cp15_32_hooks[] = {
 718         {
 719                 .esr_mask = ESR_ELx_CP15_32_ISS_SYS_MASK,
 720                 .esr_val = ESR_ELx_CP15_32_ISS_SYS_CNTFRQ,
 721                 .handler = compat_cntfrq_read_handler,
 722         },
 723         {},
 724 };
 725
 726 static void compat_cntvct_read_handler(unsigned long esr, struct pt_regs *regs)
 727 {
 728         int rt = (esr & ESR_ELx_CP15_64_ISS_RT_MASK) >> ESR_ELx_CP15_64_ISS_RT_SHIFT;
 729         int rt2 = (esr & ESR_ELx_CP15_64_ISS_RT2_MASK) >> ESR_ELx_CP15_64_ISS_RT2_SHIFT;
 730         u64 val = arch_timer_read_counter();
 731
 732         pt_regs_write_reg(regs, rt, lower_32_bits(val));
 733         pt_regs_write_reg(regs, rt2, upper_32_bits(val));
 734         arm64_skip_faulting_instruction(regs, 4);
 735 }
 736
 737 static const struct sys64_hook cp15_64_hooks[] = {
 738         {
 739                 .esr_mask = ESR_ELx_CP15_64_ISS_SYS_MASK,
 740                 .esr_val = ESR_ELx_CP15_64_ISS_SYS_CNTVCT,
 741                 .handler = compat_cntvct_read_handler,
 742         },
 743         {
 744                 .esr_mask = ESR_ELx_CP15_64_ISS_SYS_MASK,
 745                 .esr_val = ESR_ELx_CP15_64_ISS_SYS_CNTVCTSS,
 746                 .handler = compat_cntvct_read_handler,
 747         },
 748         {},
 749 };
 750
 751 void do_cp15instr(unsigned long esr, struct pt_regs *regs)
 752 {
 753         const struct sys64_hook *hook, *hook_base;
 754
 755         if (!cp15_cond_valid(esr, regs)) {
 756                 /*
 757                  * There is no T16 variant of a CP access, so we
 758                  * always advance PC by 4 bytes.
 759                  */
 760                 arm64_skip_faulting_instruction(regs, 4);
 761                 return;
 762         }
 763
 764         switch (ESR_ELx_EC(esr)) {
 765         case ESR_ELx_EC_CP15_32:
 766                 hook_base = cp15_32_hooks;
 767                 break;
 768         case ESR_ELx_EC_CP15_64:
 769                 hook_base = cp15_64_hooks;
 770                 break;
 771         default:
 772                 do_undefinstr(regs, esr);
 773                 return;
 774         }
 775
 776         for (hook = hook_base; hook->handler; hook++)
 777                 if ((hook->esr_mask & esr) == hook->esr_val) {
 778                         hook->handler(esr, regs);
 779                         return;
 780                 }
 781
 782         /*
 783          * New cp15 instructions may previously have been undefined at
 784          * EL0. Fall back to our usual undefined instruction handler
 785          * so that we handle these consistently.
 786          */
 787         do_undefinstr(regs, esr);
 788 }
 789 NOKPROBE_SYMBOL(do_cp15instr);
 790 #endif
 791
 792 void do_sysinstr(unsigned long esr, struct pt_regs *regs)
 793 {
 794         const struct sys64_hook *hook;
 795
 796         for (hook = sys64_hooks; hook->handler; hook++)
 797                 if ((hook->esr_mask & esr) == hook->esr_val) {
 798                         hook->handler(esr, regs);
 799                         return;
 800                 }
 801
 802         /*
 803          * New SYS instructions may previously have been undefined at EL0. Fall
 804          * back to our usual undefined instruction handler so that we handle
 805          * these consistently.
 806          */
 807         do_undefinstr(regs, esr);
 808 }
 809 NOKPROBE_SYMBOL(do_sysinstr);
 810
 811 static const char *esr_class_str[] = {
 812         [0 ... ESR_ELx_EC_MAX]          = "UNRECOGNIZED EC",
 813         [ESR_ELx_EC_UNKNOWN]            = "Unknown/Uncategorized",
 814         [ESR_ELx_EC_WFx]                = "WFI/WFE",
 815         [ESR_ELx_EC_CP15_32]            = "CP15 MCR/MRC",
 816         [ESR_ELx_EC_CP15_64]            = "CP15 MCRR/MRRC",
 817         [ESR_ELx_EC_CP14_MR]            = "CP14 MCR/MRC",
 818         [ESR_ELx_EC_CP14_LS]            = "CP14 LDC/STC",
 819         [ESR_ELx_EC_FP_ASIMD]           = "ASIMD",
 820         [ESR_ELx_EC_CP10_ID]            = "CP10 MRC/VMRS",
 821         [ESR_ELx_EC_PAC]                = "PAC",
 822         [ESR_ELx_EC_CP14_64]            = "CP14 MCRR/MRRC",
 823         [ESR_ELx_EC_BTI]                = "BTI",
 824         [ESR_ELx_EC_ILL]                = "PSTATE.IL",
 825         [ESR_ELx_EC_SVC32]              = "SVC (AArch32)",
 826         [ESR_ELx_EC_HVC32]              = "HVC (AArch32)",
 827         [ESR_ELx_EC_SMC32]              = "SMC (AArch32)",
 828         [ESR_ELx_EC_SVC64]              = "SVC (AArch64)",
 829         [ESR_ELx_EC_HVC64]              = "HVC (AArch64)",
 830         [ESR_ELx_EC_SMC64]              = "SMC (AArch64)",
 831         [ESR_ELx_EC_SYS64]              = "MSR/MRS (AArch64)",
 832         [ESR_ELx_EC_SVE]                = "SVE",
 833         [ESR_ELx_EC_ERET]               = "ERET/ERETAA/ERETAB",
 834         [ESR_ELx_EC_FPAC]               = "FPAC",
 835         [ESR_ELx_EC_SME]                = "SME",
 836         [ESR_ELx_EC_IMP_DEF]            = "EL3 IMP DEF",
 837         [ESR_ELx_EC_IABT_LOW]           = "IABT (lower EL)",
 838         [ESR_ELx_EC_IABT_CUR]           = "IABT (current EL)",
 839         [ESR_ELx_EC_PC_ALIGN]           = "PC Alignment",
 840         [ESR_ELx_EC_DABT_LOW]           = "DABT (lower EL)",
 841         [ESR_ELx_EC_DABT_CUR]           = "DABT (current EL)",
 842         [ESR_ELx_EC_SP_ALIGN]           = "SP Alignment",
 843         [ESR_ELx_EC_FP_EXC32]           = "FP (AArch32)",
 844         [ESR_ELx_EC_FP_EXC64]           = "FP (AArch64)",
 845         [ESR_ELx_EC_SERROR]             = "SError",
 846         [ESR_ELx_EC_BREAKPT_LOW]        = "Breakpoint (lower EL)",
 847         [ESR_ELx_EC_BREAKPT_CUR]        = "Breakpoint (current EL)",
 848         [ESR_ELx_EC_SOFTSTP_LOW]        = "Software Step (lower EL)",
 849         [ESR_ELx_EC_SOFTSTP_CUR]        = "Software Step (current EL)",
 850         [ESR_ELx_EC_WATCHPT_LOW]        = "Watchpoint (lower EL)",
 851         [ESR_ELx_EC_WATCHPT_CUR]        = "Watchpoint (current EL)",
 852         [ESR_ELx_EC_BKPT32]             = "BKPT (AArch32)",
 853         [ESR_ELx_EC_VECTOR32]           = "Vector catch (AArch32)",
 854         [ESR_ELx_EC_BRK64]              = "BRK (AArch64)",
 855 };
 856
 857 const char *esr_get_class_string(unsigned long esr)
 858 {
 859         return esr_class_str[ESR_ELx_EC(esr)];
 860 }
 861
 862 /*
 863  * bad_el0_sync handles unexpected, but potentially recoverable synchronous
 864  * exceptions taken from EL0.
 865  */
 866 void bad_el0_sync(struct pt_regs *regs, int reason, unsigned long esr)
 867 {
 868         unsigned long pc = instruction_pointer(regs);
 869
 870         current->thread.fault_address = 0;
 871         current->thread.fault_code = esr;
 872
 873         arm64_force_sig_fault(SIGILL, ILL_ILLOPC, pc,
 874                               "Bad EL0 synchronous exception");
 875 }
 876
 877 #ifdef CONFIG_VMAP_STACK
 878
 879 DEFINE_PER_CPU(unsigned long [OVERFLOW_STACK_SIZE/sizeof(long)], overflow_stack)
 880         __aligned(16);
 881
 882 void panic_bad_stack(struct pt_regs *regs, unsigned long esr, unsigned long far)
 883 {
 884         unsigned long tsk_stk = (unsigned long)current->stack;
 885         unsigned long irq_stk = (unsigned long)this_cpu_read(irq_stack_ptr);
 886         unsigned long ovf_stk = (unsigned long)this_cpu_ptr(overflow_stack);
 887
 888         console_verbose();
 889         pr_emerg("Insufficient stack space to handle exception!");
 890
 891         pr_emerg("ESR: 0x%016lx -- %s\n", esr, esr_get_class_string(esr));
 892         pr_emerg("FAR: 0x%016lx\n", far);
 893
 894         pr_emerg("Task stack:     [0x%016lx..0x%016lx]\n",
 895                  tsk_stk, tsk_stk + THREAD_SIZE);
 896         pr_emerg("IRQ stack:      [0x%016lx..0x%016lx]\n",
 897                  irq_stk, irq_stk + IRQ_STACK_SIZE);
 898         pr_emerg("Overflow stack: [0x%016lx..0x%016lx]\n",
 899                  ovf_stk, ovf_stk + OVERFLOW_STACK_SIZE);
 900
 901         __show_regs(regs);
 902
 903         /*
 904          * We use nmi_panic to limit the potential for recusive overflows, and
 905          * to get a better stack trace.
 906          */
 907         nmi_panic(NULL, "kernel stack overflow");
 908         cpu_park_loop();
 909 }
 910 #endif
 911
 912 void __noreturn arm64_serror_panic(struct pt_regs *regs, unsigned long esr)
 913 {
 914         console_verbose();
 915
 916         pr_crit("SError Interrupt on CPU%d, code 0x%016lx -- %s\n",
 917                 smp_processor_id(), esr, esr_get_class_string(esr));
 918         if (regs)
 919                 __show_regs(regs);
 920
 921         nmi_panic(regs, "Asynchronous SError Interrupt");
 922
 923         cpu_park_loop();
 924         unreachable();
 925 }
 926
 927 bool arm64_is_fatal_ras_serror(struct pt_regs *regs, unsigned long esr)
 928 {
 929         unsigned long aet = arm64_ras_serror_get_severity(esr);
 930
 931         switch (aet) {
 932         case ESR_ELx_AET_CE:    /* corrected error */
 933         case ESR_ELx_AET_UEO:   /* restartable, not yet consumed */
 934                 /*
 935                  * The CPU can make progress. We may take UEO again as
 936                  * a more severe error.
 937                  */
 938                 return false;
 939
 940         case ESR_ELx_AET_UEU:   /* Uncorrected Unrecoverable */
 941         case ESR_ELx_AET_UER:   /* Uncorrected Recoverable */
 942                 /*
 943                  * The CPU can't make progress. The exception may have
 944                  * been imprecise.
 945                  *
 946                  * Neoverse-N1 #1349291 means a non-KVM SError reported as
 947                  * Unrecoverable should be treated as Uncontainable. We
 948                  * call arm64_serror_panic() in both cases.
 949                  */
 950                 return true;
 951
 952         case ESR_ELx_AET_UC:    /* Uncontainable or Uncategorized error */
 953         default:
 954                 /* Error has been silently propagated */
 955                 arm64_serror_panic(regs, esr);
 956         }
 957 }
 958
 959 void do_serror(struct pt_regs *regs, unsigned long esr)
 960 {
 961         /* non-RAS errors are not containable */
 962         if (!arm64_is_ras_serror(esr) || arm64_is_fatal_ras_serror(regs, esr))
 963                 arm64_serror_panic(regs, esr);
 964 }
 965
 966 /* GENERIC_BUG traps */
 967
 968 int is_valid_bugaddr(unsigned long addr)
 969 {
 970         /*
 971          * bug_handler() only called for BRK #BUG_BRK_IMM.
 972          * So the answer is trivial -- any spurious instances with no
 973          * bug table entry will be rejected by report_bug() and passed
 974          * back to the debug-monitors code and handled as a fatal
 975          * unexpected debug exception.
 976          */
 977         return 1;
 978 }
 979
 980 static int bug_handler(struct pt_regs *regs, unsigned long esr)
 981 {
 982         switch (report_bug(regs->pc, regs)) {
 983         case BUG_TRAP_TYPE_BUG:
 984                 die("Oops - BUG", regs, esr);
 985                 break;
 986
 987         case BUG_TRAP_TYPE_WARN:
 988                 break;
 989
 990         default:
 991                 /* unknown/unrecognised bug trap type */
 992                 return DBG_HOOK_ERROR;
 993         }
 994
 995         /* If thread survives, skip over the BUG instruction and continue: */
 996         arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE);
 997         return DBG_HOOK_HANDLED;
 998 }
 999
1000 static struct break_hook bug_break_hook = {
1001         .fn = bug_handler,
1002         .imm = BUG_BRK_IMM,
1003 };
1004
1005 #ifdef CONFIG_CFI_CLANG
1006 static int cfi_handler(struct pt_regs *regs, unsigned long esr)
1007 {
1008         unsigned long target;
1009         u32 type;
1010
1011         target = pt_regs_read_reg(regs, FIELD_GET(CFI_BRK_IMM_TARGET, esr));
1012         type = (u32)pt_regs_read_reg(regs, FIELD_GET(CFI_BRK_IMM_TYPE, esr));
1013
1014         switch (report_cfi_failure(regs, regs->pc, &target, type)) {
1015         case BUG_TRAP_TYPE_BUG:
1016                 die("Oops - CFI", regs, 0);
1017                 break;
1018
1019         case BUG_TRAP_TYPE_WARN:
1020                 break;
1021
1022         default:
1023                 return DBG_HOOK_ERROR;
1024         }
1025
1026         arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE);
1027         return DBG_HOOK_HANDLED;
1028 }
1029
1030 static struct break_hook cfi_break_hook = {
1031         .fn = cfi_handler,
1032         .imm = CFI_BRK_IMM_BASE,
1033         .mask = CFI_BRK_IMM_MASK,
1034 };
1035 #endif /* CONFIG_CFI_CLANG */
1036
1037 static int reserved_fault_handler(struct pt_regs *regs, unsigned long esr)
1038 {
1039         pr_err("%s generated an invalid instruction at %pS!\n",
1040                 "Kernel text patching",
1041                 (void *)instruction_pointer(regs));
1042
1043         /* We cannot handle this */
1044         return DBG_HOOK_ERROR;
1045 }
1046
1047 static struct break_hook fault_break_hook = {
1048         .fn = reserved_fault_handler,
1049         .imm = FAULT_BRK_IMM,
1050 };
1051
1052 #ifdef CONFIG_KASAN_SW_TAGS
1053
1054 #define KASAN_ESR_RECOVER       0x20
1055 #define KASAN_ESR_WRITE 0x10
1056 #define KASAN_ESR_SIZE_MASK     0x0f
1057 #define KASAN_ESR_SIZE(esr)     (1 << ((esr) & KASAN_ESR_SIZE_MASK))
1058
1059 static int kasan_handler(struct pt_regs *regs, unsigned long esr)
1060 {
1061         bool recover = esr & KASAN_ESR_RECOVER;
1062         bool write = esr & KASAN_ESR_WRITE;
1063         size_t size = KASAN_ESR_SIZE(esr);
1064         u64 addr = regs->regs[0];
1065         u64 pc = regs->pc;
1066
1067         kasan_report(addr, size, write, pc);
1068
1069         /*
1070          * The instrumentation allows to control whether we can proceed after
1071          * a crash was detected. This is done by passing the -recover flag to
1072          * the compiler. Disabling recovery allows to generate more compact
1073          * code.
1074          *
1075          * Unfortunately disabling recovery doesn't work for the kernel right
1076          * now. KASAN reporting is disabled in some contexts (for example when
1077          * the allocator accesses slab object metadata; this is controlled by
1078          * current->kasan_depth). All these accesses are detected by the tool,
1079          * even though the reports for them are not printed.
1080          *
1081          * This is something that might be fixed at some point in the future.
1082          */
1083         if (!recover)
1084                 die("Oops - KASAN", regs, esr);
1085
1086         /* If thread survives, skip over the brk instruction and continue: */
1087         arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE);
1088         return DBG_HOOK_HANDLED;
1089 }
1090
1091 static struct break_hook kasan_break_hook = {
1092         .fn     = kasan_handler,
1093         .imm    = KASAN_BRK_IMM,
1094         .mask   = KASAN_BRK_MASK,
1095 };
1096 #endif
1097
1098
1099 #define esr_comment(esr) ((esr) & ESR_ELx_BRK64_ISS_COMMENT_MASK)
1100
1101 /*
1102  * Initial handler for AArch64 BRK exceptions
1103  * This handler only used until debug_traps_init().
1104  */
1105 int __init early_brk64(unsigned long addr, unsigned long esr,
1106                 struct pt_regs *regs)
1107 {
1108 #ifdef CONFIG_CFI_CLANG
1109         if ((esr_comment(esr) & ~CFI_BRK_IMM_MASK) == CFI_BRK_IMM_BASE)
1110                 return cfi_handler(regs, esr) != DBG_HOOK_HANDLED;
1111 #endif
1112 #ifdef CONFIG_KASAN_SW_TAGS
1113         if ((esr_comment(esr) & ~KASAN_BRK_MASK) == KASAN_BRK_IMM)
1114                 return kasan_handler(regs, esr) != DBG_HOOK_HANDLED;
1115 #endif
1116         return bug_handler(regs, esr) != DBG_HOOK_HANDLED;
1117 }
1118
1119 void __init trap_init(void)
1120 {
1121         register_kernel_break_hook(&bug_break_hook);
1122 #ifdef CONFIG_CFI_CLANG
1123         register_kernel_break_hook(&cfi_break_hook);
1124 #endif
1125         register_kernel_break_hook(&fault_break_hook);
1126 #ifdef CONFIG_KASAN_SW_TAGS
1127         register_kernel_break_hook(&kasan_break_hook);
1128 #endif
1129         debug_traps_init();
1130 }