arch/arm64/kernel/traps.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Based on arch/arm/kernel/traps.c
   4  *
   5  * Copyright (C) 1995-2009 Russell King
   6  * Copyright (C) 2012 ARM Ltd.
   7  */
   8
   9 #include <linux/bug.h>
  10 #include <linux/context_tracking.h>
  11 #include <linux/signal.h>
  12 #include <linux/personality.h>
  13 #include <linux/kallsyms.h>
  14 #include <linux/kprobes.h>
  15 #include <linux/spinlock.h>
  16 #include <linux/uaccess.h>
  17 #include <linux/hardirq.h>
  18 #include <linux/kdebug.h>
  19 #include <linux/module.h>
  20 #include <linux/kexec.h>
  21 #include <linux/delay.h>
  22 #include <linux/init.h>
  23 #include <linux/sched/signal.h>
  24 #include <linux/sched/debug.h>
  25 #include <linux/sched/task_stack.h>
  26 #include <linux/sizes.h>
  27 #include <linux/syscalls.h>
  28 #include <linux/mm_types.h>
  29 #include <linux/kasan.h>
  30
  31 #include <asm/atomic.h>
  32 #include <asm/bug.h>
  33 #include <asm/cpufeature.h>
  34 #include <asm/daifflags.h>
  35 #include <asm/debug-monitors.h>
  36 #include <asm/esr.h>
  37 #include <asm/exception.h>
  38 #include <asm/extable.h>
  39 #include <asm/insn.h>
  40 #include <asm/kprobes.h>
  41 #include <asm/traps.h>
  42 #include <asm/smp.h>
  43 #include <asm/stack_pointer.h>
  44 #include <asm/stacktrace.h>
  45 #include <asm/exception.h>
  46 #include <asm/system_misc.h>
  47 #include <asm/sysreg.h>
  48
  49 static const char *handler[]= {
  50         "Synchronous Abort",
  51         "IRQ",
  52         "FIQ",
  53         "Error"
  54 };
  55
  56 int show_unhandled_signals = 0;
  57
  58 static void dump_kernel_instr(const char *lvl, struct pt_regs *regs)
  59 {
  60         unsigned long addr = instruction_pointer(regs);
  61         char str[sizeof("00000000 ") * 5 + 2 + 1], *p = str;
  62         int i;
  63
  64         if (user_mode(regs))
  65                 return;
  66
  67         for (i = -4; i < 1; i++) {
  68                 unsigned int val, bad;
  69
  70                 bad = aarch64_insn_read(&((u32 *)addr)[i], &val);
  71
  72                 if (!bad)
  73                         p += sprintf(p, i == 0 ? "(%08x) " : "%08x ", val);
  74                 else {
  75                         p += sprintf(p, "bad PC value");
  76                         break;
  77                 }
  78         }
  79
  80         printk("%sCode: %s\n", lvl, str);
  81 }
  82
  83 #ifdef CONFIG_PREEMPT
  84 #define S_PREEMPT " PREEMPT"
  85 #elif defined(CONFIG_PREEMPT_RT)
  86 #define S_PREEMPT " PREEMPT_RT"
  87 #else
  88 #define S_PREEMPT ""
  89 #endif
  90
  91 #define S_SMP " SMP"
  92
  93 static int __die(const char *str, long err, struct pt_regs *regs)
  94 {
  95         static int die_counter;
  96         int ret;
  97
  98         pr_emerg("Internal error: %s: %016lx [#%d]" S_PREEMPT S_SMP "\n",
  99                  str, err, ++die_counter);
 100
 101         /* trap and error numbers are mostly meaningless on ARM */
 102         ret = notify_die(DIE_OOPS, str, regs, err, 0, SIGSEGV);
 103         if (ret == NOTIFY_STOP)
 104                 return ret;
 105
 106         print_modules();
 107         show_regs(regs);
 108
 109         dump_kernel_instr(KERN_EMERG, regs);
 110
 111         return ret;
 112 }
 113
 114 static DEFINE_RAW_SPINLOCK(die_lock);
 115
 116 /*
 117  * This function is protected against re-entrancy.
 118  */
 119 void die(const char *str, struct pt_regs *regs, long err)
 120 {
 121         int ret;
 122         unsigned long flags;
 123
 124         raw_spin_lock_irqsave(&die_lock, flags);
 125
 126         oops_enter();
 127
 128         console_verbose();
 129         bust_spinlocks(1);
 130         ret = __die(str, err, regs);
 131
 132         if (regs && kexec_should_crash(current))
 133                 crash_kexec(regs);
 134
 135         bust_spinlocks(0);
 136         add_taint(TAINT_DIE, LOCKDEP_NOW_UNRELIABLE);
 137         oops_exit();
 138
 139         if (in_interrupt())
 140                 panic("%s: Fatal exception in interrupt", str);
 141         if (panic_on_oops)
 142                 panic("%s: Fatal exception", str);
 143
 144         raw_spin_unlock_irqrestore(&die_lock, flags);
 145
 146         if (ret != NOTIFY_STOP)
 147                 make_task_dead(SIGSEGV);
 148 }
 149
 150 static void arm64_show_signal(int signo, const char *str)
 151 {
 152         static DEFINE_RATELIMIT_STATE(rs, DEFAULT_RATELIMIT_INTERVAL,
 153                                       DEFAULT_RATELIMIT_BURST);
 154         struct task_struct *tsk = current;
 155         unsigned int esr = tsk->thread.fault_code;
 156         struct pt_regs *regs = task_pt_regs(tsk);
 157
 158         /* Leave if the signal won't be shown */
 159         if (!show_unhandled_signals ||
 160             !unhandled_signal(tsk, signo) ||
 161             !__ratelimit(&rs))
 162                 return;
 163
 164         pr_info("%s[%d]: unhandled exception: ", tsk->comm, task_pid_nr(tsk));
 165         if (esr)
 166                 pr_cont("%s, ESR 0x%08x, ", esr_get_class_string(esr), esr);
 167
 168         pr_cont("%s", str);
 169         print_vma_addr(KERN_CONT " in ", regs->pc);
 170         pr_cont("\n");
 171         __show_regs(regs);
 172 }
 173
 174 void arm64_force_sig_fault(int signo, int code, void __user *addr,
 175                            const char *str)
 176 {
 177         arm64_show_signal(signo, str);
 178         if (signo == SIGKILL)
 179                 force_sig(SIGKILL);
 180         else
 181                 force_sig_fault(signo, code, addr);
 182 }
 183
 184 void arm64_force_sig_mceerr(int code, void __user *addr, short lsb,
 185                             const char *str)
 186 {
 187         arm64_show_signal(SIGBUS, str);
 188         force_sig_mceerr(code, addr, lsb);
 189 }
 190
 191 void arm64_force_sig_ptrace_errno_trap(int errno, void __user *addr,
 192                                        const char *str)
 193 {
 194         arm64_show_signal(SIGTRAP, str);
 195         force_sig_ptrace_errno_trap(errno, addr);
 196 }
 197
 198 void arm64_notify_die(const char *str, struct pt_regs *regs,
 199                       int signo, int sicode, void __user *addr,
 200                       int err)
 201 {
 202         if (user_mode(regs)) {
 203                 WARN_ON(regs != current_pt_regs());
 204                 current->thread.fault_address = 0;
 205                 current->thread.fault_code = err;
 206
 207                 arm64_force_sig_fault(signo, sicode, addr, str);
 208         } else {
 209                 die(str, regs, err);
 210         }
 211 }
 212
 213 #ifdef CONFIG_COMPAT
 214 #define PSTATE_IT_1_0_SHIFT     25
 215 #define PSTATE_IT_1_0_MASK      (0x3 << PSTATE_IT_1_0_SHIFT)
 216 #define PSTATE_IT_7_2_SHIFT     10
 217 #define PSTATE_IT_7_2_MASK      (0x3f << PSTATE_IT_7_2_SHIFT)
 218
 219 static u32 compat_get_it_state(struct pt_regs *regs)
 220 {
 221         u32 it, pstate = regs->pstate;
 222
 223         it  = (pstate & PSTATE_IT_1_0_MASK) >> PSTATE_IT_1_0_SHIFT;
 224         it |= ((pstate & PSTATE_IT_7_2_MASK) >> PSTATE_IT_7_2_SHIFT) << 2;
 225
 226         return it;
 227 }
 228
 229 static void compat_set_it_state(struct pt_regs *regs, u32 it)
 230 {
 231         u32 pstate_it;
 232
 233         pstate_it  = (it << PSTATE_IT_1_0_SHIFT) & PSTATE_IT_1_0_MASK;
 234         pstate_it |= ((it >> 2) << PSTATE_IT_7_2_SHIFT) & PSTATE_IT_7_2_MASK;
 235
 236         regs->pstate &= ~PSR_AA32_IT_MASK;
 237         regs->pstate |= pstate_it;
 238 }
 239
 240 static void advance_itstate(struct pt_regs *regs)
 241 {
 242         u32 it;
 243
 244         /* ARM mode */
 245         if (!(regs->pstate & PSR_AA32_T_BIT) ||
 246             !(regs->pstate & PSR_AA32_IT_MASK))
 247                 return;
 248
 249         it  = compat_get_it_state(regs);
 250
 251         /*
 252          * If this is the last instruction of the block, wipe the IT
 253          * state. Otherwise advance it.
 254          */
 255         if (!(it & 7))
 256                 it = 0;
 257         else
 258                 it = (it & 0xe0) | ((it << 1) & 0x1f);
 259
 260         compat_set_it_state(regs, it);
 261 }
 262 #else
 263 static void advance_itstate(struct pt_regs *regs)
 264 {
 265 }
 266 #endif
 267
 268 void arm64_skip_faulting_instruction(struct pt_regs *regs, unsigned long size)
 269 {
 270         regs->pc += size;
 271
 272         /*
 273          * If we were single stepping, we want to get the step exception after
 274          * we return from the trap.
 275          */
 276         if (user_mode(regs))
 277                 user_fastforward_single_step(current);
 278
 279         if (compat_user_mode(regs))
 280                 advance_itstate(regs);
 281         else
 282                 regs->pstate &= ~PSR_BTYPE_MASK;
 283 }
 284
 285 static int user_insn_read(struct pt_regs *regs, u32 *insnp)
 286 {
 287         u32 instr;
 288         void __user *pc = (void __user *)instruction_pointer(regs);
 289
 290         if (compat_thumb_mode(regs)) {
 291                 /* 16-bit Thumb instruction */
 292                 __le16 instr_le;
 293                 if (get_user(instr_le, (__le16 __user *)pc))
 294                         return -EFAULT;
 295                 instr = le16_to_cpu(instr_le);
 296                 if (aarch32_insn_is_wide(instr)) {
 297                         u32 instr2;
 298
 299                         if (get_user(instr_le, (__le16 __user *)(pc + 2)))
 300                                 return -EFAULT;
 301                         instr2 = le16_to_cpu(instr_le);
 302                         instr = (instr << 16) | instr2;
 303                 }
 304         } else {
 305                 /* 32-bit ARM instruction */
 306                 __le32 instr_le;
 307                 if (get_user(instr_le, (__le32 __user *)pc))
 308                         return -EFAULT;
 309                 instr = le32_to_cpu(instr_le);
 310         }
 311
 312         *insnp = instr;
 313         return 0;
 314 }
 315
 316 void force_signal_inject(int signal, int code, unsigned long address, unsigned int err)
 317 {
 318         const char *desc;
 319         struct pt_regs *regs = current_pt_regs();
 320
 321         if (WARN_ON(!user_mode(regs)))
 322                 return;
 323
 324         switch (signal) {
 325         case SIGILL:
 326                 desc = "undefined instruction";
 327                 break;
 328         case SIGSEGV:
 329                 desc = "illegal memory access";
 330                 break;
 331         default:
 332                 desc = "unknown or unrecoverable error";
 333                 break;
 334         }
 335
 336         /* Force signals we don't understand to SIGKILL */
 337         if (WARN_ON(signal != SIGKILL &&
 338                     siginfo_layout(signal, code) != SIL_FAULT)) {
 339                 signal = SIGKILL;
 340         }
 341
 342         arm64_notify_die(desc, regs, signal, code, (void __user *)address, err);
 343 }
 344
 345 /*
 346  * Set up process info to signal segmentation fault - called on access error.
 347  */
 348 void arm64_notify_segfault(unsigned long addr)
 349 {
 350         int code;
 351
 352         mmap_read_lock(current->mm);
 353         if (find_vma(current->mm, addr) == NULL)
 354                 code = SEGV_MAPERR;
 355         else
 356                 code = SEGV_ACCERR;
 357         mmap_read_unlock(current->mm);
 358
 359         force_signal_inject(SIGSEGV, code, addr, 0);
 360 }
 361
 362 void do_el0_undef(struct pt_regs *regs, unsigned long esr)
 363 {
 364         u32 insn;
 365
 366         /* check for AArch32 breakpoint instructions */
 367         if (!aarch32_break_handler(regs))
 368                 return;
 369
 370         if (user_insn_read(regs, &insn))
 371                 goto out_err;
 372
 373         if (try_emulate_mrs(regs, insn))
 374                 return;
 375
 376         if (try_emulate_armv8_deprecated(regs, insn))
 377                 return;
 378
 379 out_err:
 380         force_signal_inject(SIGILL, ILL_ILLOPC, regs->pc, 0);
 381 }
 382
 383 void do_el1_undef(struct pt_regs *regs, unsigned long esr)
 384 {
 385         u32 insn;
 386
 387         if (aarch64_insn_read((void *)regs->pc, &insn))
 388                 goto out_err;
 389
 390         if (try_emulate_el1_ssbs(regs, insn))
 391                 return;
 392
 393 out_err:
 394         die("Oops - Undefined instruction", regs, esr);
 395 }
 396
 397 void do_el0_bti(struct pt_regs *regs)
 398 {
 399         force_signal_inject(SIGILL, ILL_ILLOPC, regs->pc, 0);
 400 }
 401
 402 void do_el1_bti(struct pt_regs *regs, unsigned long esr)
 403 {
 404         die("Oops - BTI", regs, esr);
 405 }
 406
 407 void do_el0_fpac(struct pt_regs *regs, unsigned long esr)
 408 {
 409         force_signal_inject(SIGILL, ILL_ILLOPN, regs->pc, esr);
 410 }
 411
 412 void do_el1_fpac(struct pt_regs *regs, unsigned long esr)
 413 {
 414         /*
 415          * Unexpected FPAC exception in the kernel: kill the task before it
 416          * does any more harm.
 417          */
 418         die("Oops - FPAC", regs, esr);
 419 }
 420
 421 #define __user_cache_maint(insn, address, res)                  \
 422         if (address >= user_addr_max()) {                       \
 423                 res = -EFAULT;                                  \
 424         } else {                                                \
 425                 uaccess_ttbr0_enable();                         \
 426                 asm volatile (                                  \
 427                         "1:     " insn ", %1\n"                 \
 428                         "       mov     %w0, #0\n"              \
 429                         "2:\n"                                  \
 430                         "       .pushsection .fixup,\"ax\"\n"   \
 431                         "       .align  2\n"                    \
 432                         "3:     mov     %w0, %w2\n"             \
 433                         "       b       2b\n"                   \
 434                         "       .popsection\n"                  \
 435                         _ASM_EXTABLE(1b, 3b)                    \
 436                         : "=r" (res)                            \
 437                         : "r" (address), "i" (-EFAULT));        \
 438                 uaccess_ttbr0_disable();                        \
 439         }
 440
 441 static void user_cache_maint_handler(unsigned int esr, struct pt_regs *regs)
 442 {
 443         unsigned long address;
 444         int rt = ESR_ELx_SYS64_ISS_RT(esr);
 445         int crm = (esr & ESR_ELx_SYS64_ISS_CRM_MASK) >> ESR_ELx_SYS64_ISS_CRM_SHIFT;
 446         int ret = 0;
 447
 448         address = untagged_addr(pt_regs_read_reg(regs, rt));
 449
 450         switch (crm) {
 451         case ESR_ELx_SYS64_ISS_CRM_DC_CVAU:     /* DC CVAU, gets promoted */
 452                 __user_cache_maint("dc civac", address, ret);
 453                 break;
 454         case ESR_ELx_SYS64_ISS_CRM_DC_CVAC:     /* DC CVAC, gets promoted */
 455                 __user_cache_maint("dc civac", address, ret);
 456                 break;
 457         case ESR_ELx_SYS64_ISS_CRM_DC_CVADP:    /* DC CVADP */
 458                 __user_cache_maint("sys 3, c7, c13, 1", address, ret);
 459                 break;
 460         case ESR_ELx_SYS64_ISS_CRM_DC_CVAP:     /* DC CVAP */
 461                 __user_cache_maint("sys 3, c7, c12, 1", address, ret);
 462                 break;
 463         case ESR_ELx_SYS64_ISS_CRM_DC_CIVAC:    /* DC CIVAC */
 464                 __user_cache_maint("dc civac", address, ret);
 465                 break;
 466         case ESR_ELx_SYS64_ISS_CRM_IC_IVAU:     /* IC IVAU */
 467                 __user_cache_maint("ic ivau", address, ret);
 468                 break;
 469         default:
 470                 force_signal_inject(SIGILL, ILL_ILLOPC, regs->pc, 0);
 471                 return;
 472         }
 473
 474         if (ret)
 475                 arm64_notify_segfault(address);
 476         else
 477                 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE);
 478 }
 479
 480 static void ctr_read_handler(unsigned int esr, struct pt_regs *regs)
 481 {
 482         int rt = ESR_ELx_SYS64_ISS_RT(esr);
 483         unsigned long val = arm64_ftr_reg_user_value(&arm64_ftr_reg_ctrel0);
 484
 485         if (cpus_have_const_cap(ARM64_WORKAROUND_1542419)) {
 486                 /* Hide DIC so that we can trap the unnecessary maintenance...*/
 487                 val &= ~BIT(CTR_DIC_SHIFT);
 488
 489                 /* ... and fake IminLine to reduce the number of traps. */
 490                 val &= ~CTR_IMINLINE_MASK;
 491                 val |= (PAGE_SHIFT - 2) & CTR_IMINLINE_MASK;
 492         }
 493
 494         pt_regs_write_reg(regs, rt, val);
 495
 496         arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE);
 497 }
 498
 499 static void cntvct_read_handler(unsigned int esr, struct pt_regs *regs)
 500 {
 501         int rt = ESR_ELx_SYS64_ISS_RT(esr);
 502
 503         pt_regs_write_reg(regs, rt, arch_timer_read_counter());
 504         arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE);
 505 }
 506
 507 static void cntfrq_read_handler(unsigned int esr, struct pt_regs *regs)
 508 {
 509         int rt = ESR_ELx_SYS64_ISS_RT(esr);
 510
 511         pt_regs_write_reg(regs, rt, arch_timer_get_rate());
 512         arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE);
 513 }
 514
 515 static void mrs_handler(unsigned int esr, struct pt_regs *regs)
 516 {
 517         u32 sysreg, rt;
 518
 519         rt = ESR_ELx_SYS64_ISS_RT(esr);
 520         sysreg = esr_sys64_to_sysreg(esr);
 521
 522         if (do_emulate_mrs(regs, sysreg, rt) != 0)
 523                 force_signal_inject(SIGILL, ILL_ILLOPC, regs->pc, 0);
 524 }
 525
 526 static void wfi_handler(unsigned int esr, struct pt_regs *regs)
 527 {
 528         arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE);
 529 }
 530
 531 struct sys64_hook {
 532         unsigned int esr_mask;
 533         unsigned int esr_val;
 534         void (*handler)(unsigned int esr, struct pt_regs *regs);
 535 };
 536
 537 static const struct sys64_hook sys64_hooks[] = {
 538         {
 539                 .esr_mask = ESR_ELx_SYS64_ISS_EL0_CACHE_OP_MASK,
 540                 .esr_val = ESR_ELx_SYS64_ISS_EL0_CACHE_OP_VAL,
 541                 .handler = user_cache_maint_handler,
 542         },
 543         {
 544                 /* Trap read access to CTR_EL0 */
 545                 .esr_mask = ESR_ELx_SYS64_ISS_SYS_OP_MASK,
 546                 .esr_val = ESR_ELx_SYS64_ISS_SYS_CTR_READ,
 547                 .handler = ctr_read_handler,
 548         },
 549         {
 550                 /* Trap read access to CNTVCT_EL0 */
 551                 .esr_mask = ESR_ELx_SYS64_ISS_SYS_OP_MASK,
 552                 .esr_val = ESR_ELx_SYS64_ISS_SYS_CNTVCT,
 553                 .handler = cntvct_read_handler,
 554         },
 555         {
 556                 /* Trap read access to CNTFRQ_EL0 */
 557                 .esr_mask = ESR_ELx_SYS64_ISS_SYS_OP_MASK,
 558                 .esr_val = ESR_ELx_SYS64_ISS_SYS_CNTFRQ,
 559                 .handler = cntfrq_read_handler,
 560         },
 561         {
 562                 /* Trap read access to CPUID registers */
 563                 .esr_mask = ESR_ELx_SYS64_ISS_SYS_MRS_OP_MASK,
 564                 .esr_val = ESR_ELx_SYS64_ISS_SYS_MRS_OP_VAL,
 565                 .handler = mrs_handler,
 566         },
 567         {
 568                 /* Trap WFI instructions executed in userspace */
 569                 .esr_mask = ESR_ELx_WFx_MASK,
 570                 .esr_val = ESR_ELx_WFx_WFI_VAL,
 571                 .handler = wfi_handler,
 572         },
 573         {},
 574 };
 575
 576 #ifdef CONFIG_COMPAT
 577 static bool cp15_cond_valid(unsigned int esr, struct pt_regs *regs)
 578 {
 579         int cond;
 580
 581         /* Only a T32 instruction can trap without CV being set */
 582         if (!(esr & ESR_ELx_CV)) {
 583                 u32 it;
 584
 585                 it = compat_get_it_state(regs);
 586                 if (!it)
 587                         return true;
 588
 589                 cond = it >> 4;
 590         } else {
 591                 cond = (esr & ESR_ELx_COND_MASK) >> ESR_ELx_COND_SHIFT;
 592         }
 593
 594         return aarch32_opcode_cond_checks[cond](regs->pstate);
 595 }
 596
 597 static void compat_cntfrq_read_handler(unsigned int esr, struct pt_regs *regs)
 598 {
 599         int reg = (esr & ESR_ELx_CP15_32_ISS_RT_MASK) >> ESR_ELx_CP15_32_ISS_RT_SHIFT;
 600
 601         pt_regs_write_reg(regs, reg, arch_timer_get_rate());
 602         arm64_skip_faulting_instruction(regs, 4);
 603 }
 604
 605 static const struct sys64_hook cp15_32_hooks[] = {
 606         {
 607                 .esr_mask = ESR_ELx_CP15_32_ISS_SYS_MASK,
 608                 .esr_val = ESR_ELx_CP15_32_ISS_SYS_CNTFRQ,
 609                 .handler = compat_cntfrq_read_handler,
 610         },
 611         {},
 612 };
 613
 614 static void compat_cntvct_read_handler(unsigned int esr, struct pt_regs *regs)
 615 {
 616         int rt = (esr & ESR_ELx_CP15_64_ISS_RT_MASK) >> ESR_ELx_CP15_64_ISS_RT_SHIFT;
 617         int rt2 = (esr & ESR_ELx_CP15_64_ISS_RT2_MASK) >> ESR_ELx_CP15_64_ISS_RT2_SHIFT;
 618         u64 val = arch_timer_read_counter();
 619
 620         pt_regs_write_reg(regs, rt, lower_32_bits(val));
 621         pt_regs_write_reg(regs, rt2, upper_32_bits(val));
 622         arm64_skip_faulting_instruction(regs, 4);
 623 }
 624
 625 static const struct sys64_hook cp15_64_hooks[] = {
 626         {
 627                 .esr_mask = ESR_ELx_CP15_64_ISS_SYS_MASK,
 628                 .esr_val = ESR_ELx_CP15_64_ISS_SYS_CNTVCT,
 629                 .handler = compat_cntvct_read_handler,
 630         },
 631         {},
 632 };
 633
 634 void do_el0_cp15(unsigned long esr, struct pt_regs *regs)
 635 {
 636         const struct sys64_hook *hook, *hook_base;
 637
 638         if (!cp15_cond_valid(esr, regs)) {
 639                 /*
 640                  * There is no T16 variant of a CP access, so we
 641                  * always advance PC by 4 bytes.
 642                  */
 643                 arm64_skip_faulting_instruction(regs, 4);
 644                 return;
 645         }
 646
 647         switch (ESR_ELx_EC(esr)) {
 648         case ESR_ELx_EC_CP15_32:
 649                 hook_base = cp15_32_hooks;
 650                 break;
 651         case ESR_ELx_EC_CP15_64:
 652                 hook_base = cp15_64_hooks;
 653                 break;
 654         default:
 655                 do_el0_undef(regs, esr);
 656                 return;
 657         }
 658
 659         for (hook = hook_base; hook->handler; hook++)
 660                 if ((hook->esr_mask & esr) == hook->esr_val) {
 661                         hook->handler(esr, regs);
 662                         return;
 663                 }
 664
 665         /*
 666          * New cp15 instructions may previously have been undefined at
 667          * EL0. Fall back to our usual undefined instruction handler
 668          * so that we handle these consistently.
 669          */
 670         do_el0_undef(regs, esr);
 671 }
 672 #endif
 673
 674 void do_el0_sys(unsigned long esr, struct pt_regs *regs)
 675 {
 676         const struct sys64_hook *hook;
 677
 678         for (hook = sys64_hooks; hook->handler; hook++)
 679                 if ((hook->esr_mask & esr) == hook->esr_val) {
 680                         hook->handler(esr, regs);
 681                         return;
 682                 }
 683
 684         /*
 685          * New SYS instructions may previously have been undefined at EL0. Fall
 686          * back to our usual undefined instruction handler so that we handle
 687          * these consistently.
 688          */
 689         do_el0_undef(regs, esr);
 690 }
 691
 692 static const char *esr_class_str[] = {
 693         [0 ... ESR_ELx_EC_MAX]          = "UNRECOGNIZED EC",
 694         [ESR_ELx_EC_UNKNOWN]            = "Unknown/Uncategorized",
 695         [ESR_ELx_EC_WFx]                = "WFI/WFE",
 696         [ESR_ELx_EC_CP15_32]            = "CP15 MCR/MRC",
 697         [ESR_ELx_EC_CP15_64]            = "CP15 MCRR/MRRC",
 698         [ESR_ELx_EC_CP14_MR]            = "CP14 MCR/MRC",
 699         [ESR_ELx_EC_CP14_LS]            = "CP14 LDC/STC",
 700         [ESR_ELx_EC_FP_ASIMD]           = "ASIMD",
 701         [ESR_ELx_EC_CP10_ID]            = "CP10 MRC/VMRS",
 702         [ESR_ELx_EC_PAC]                = "PAC",
 703         [ESR_ELx_EC_CP14_64]            = "CP14 MCRR/MRRC",
 704         [ESR_ELx_EC_BTI]                = "BTI",
 705         [ESR_ELx_EC_ILL]                = "PSTATE.IL",
 706         [ESR_ELx_EC_SVC32]              = "SVC (AArch32)",
 707         [ESR_ELx_EC_HVC32]              = "HVC (AArch32)",
 708         [ESR_ELx_EC_SMC32]              = "SMC (AArch32)",
 709         [ESR_ELx_EC_SVC64]              = "SVC (AArch64)",
 710         [ESR_ELx_EC_HVC64]              = "HVC (AArch64)",
 711         [ESR_ELx_EC_SMC64]              = "SMC (AArch64)",
 712         [ESR_ELx_EC_SYS64]              = "MSR/MRS (AArch64)",
 713         [ESR_ELx_EC_SVE]                = "SVE",
 714         [ESR_ELx_EC_ERET]               = "ERET/ERETAA/ERETAB",
 715         [ESR_ELx_EC_FPAC]               = "FPAC",
 716         [ESR_ELx_EC_IMP_DEF]            = "EL3 IMP DEF",
 717         [ESR_ELx_EC_IABT_LOW]           = "IABT (lower EL)",
 718         [ESR_ELx_EC_IABT_CUR]           = "IABT (current EL)",
 719         [ESR_ELx_EC_PC_ALIGN]           = "PC Alignment",
 720         [ESR_ELx_EC_DABT_LOW]           = "DABT (lower EL)",
 721         [ESR_ELx_EC_DABT_CUR]           = "DABT (current EL)",
 722         [ESR_ELx_EC_SP_ALIGN]           = "SP Alignment",
 723         [ESR_ELx_EC_FP_EXC32]           = "FP (AArch32)",
 724         [ESR_ELx_EC_FP_EXC64]           = "FP (AArch64)",
 725         [ESR_ELx_EC_SERROR]             = "SError",
 726         [ESR_ELx_EC_BREAKPT_LOW]        = "Breakpoint (lower EL)",
 727         [ESR_ELx_EC_BREAKPT_CUR]        = "Breakpoint (current EL)",
 728         [ESR_ELx_EC_SOFTSTP_LOW]        = "Software Step (lower EL)",
 729         [ESR_ELx_EC_SOFTSTP_CUR]        = "Software Step (current EL)",
 730         [ESR_ELx_EC_WATCHPT_LOW]        = "Watchpoint (lower EL)",
 731         [ESR_ELx_EC_WATCHPT_CUR]        = "Watchpoint (current EL)",
 732         [ESR_ELx_EC_BKPT32]             = "BKPT (AArch32)",
 733         [ESR_ELx_EC_VECTOR32]           = "Vector catch (AArch32)",
 734         [ESR_ELx_EC_BRK64]              = "BRK (AArch64)",
 735 };
 736
 737 const char *esr_get_class_string(u32 esr)
 738 {
 739         return esr_class_str[ESR_ELx_EC(esr)];
 740 }
 741
 742 /*
 743  * bad_mode handles the impossible case in the exception vector. This is always
 744  * fatal.
 745  */
 746 asmlinkage void notrace bad_mode(struct pt_regs *regs, int reason, unsigned int esr)
 747 {
 748         arm64_enter_nmi(regs);
 749
 750         console_verbose();
 751
 752         pr_crit("Bad mode in %s handler detected on CPU%d, code 0x%08x -- %s\n",
 753                 handler[reason], smp_processor_id(), esr,
 754                 esr_get_class_string(esr));
 755
 756         __show_regs(regs);
 757         local_daif_mask();
 758         panic("bad mode");
 759 }
 760
 761 /*
 762  * bad_el0_sync handles unexpected, but potentially recoverable synchronous
 763  * exceptions taken from EL0. Unlike bad_mode, this returns.
 764  */
 765 void bad_el0_sync(struct pt_regs *regs, int reason, unsigned int esr)
 766 {
 767         void __user *pc = (void __user *)instruction_pointer(regs);
 768
 769         current->thread.fault_address = 0;
 770         current->thread.fault_code = esr;
 771
 772         arm64_force_sig_fault(SIGILL, ILL_ILLOPC, pc,
 773                               "Bad EL0 synchronous exception");
 774 }
 775
 776 #ifdef CONFIG_VMAP_STACK
 777
 778 DEFINE_PER_CPU(unsigned long [OVERFLOW_STACK_SIZE/sizeof(long)], overflow_stack)
 779         __aligned(16);
 780
 781 asmlinkage void noinstr handle_bad_stack(struct pt_regs *regs)
 782 {
 783         unsigned long tsk_stk = (unsigned long)current->stack;
 784         unsigned long irq_stk = (unsigned long)this_cpu_read(irq_stack_ptr);
 785         unsigned long ovf_stk = (unsigned long)this_cpu_ptr(overflow_stack);
 786         unsigned int esr = read_sysreg(esr_el1);
 787         unsigned long far = read_sysreg(far_el1);
 788
 789         arm64_enter_nmi(regs);
 790
 791         console_verbose();
 792         pr_emerg("Insufficient stack space to handle exception!");
 793
 794         pr_emerg("ESR: 0x%08x -- %s\n", esr, esr_get_class_string(esr));
 795         pr_emerg("FAR: 0x%016lx\n", far);
 796
 797         pr_emerg("Task stack:     [0x%016lx..0x%016lx]\n",
 798                  tsk_stk, tsk_stk + THREAD_SIZE);
 799         pr_emerg("IRQ stack:      [0x%016lx..0x%016lx]\n",
 800                  irq_stk, irq_stk + IRQ_STACK_SIZE);
 801         pr_emerg("Overflow stack: [0x%016lx..0x%016lx]\n",
 802                  ovf_stk, ovf_stk + OVERFLOW_STACK_SIZE);
 803
 804         __show_regs(regs);
 805
 806         /*
 807          * We use nmi_panic to limit the potential for recusive overflows, and
 808          * to get a better stack trace.
 809          */
 810         nmi_panic(NULL, "kernel stack overflow");
 811         cpu_park_loop();
 812 }
 813 #endif
 814
 815 void __noreturn arm64_serror_panic(struct pt_regs *regs, u32 esr)
 816 {
 817         console_verbose();
 818
 819         pr_crit("SError Interrupt on CPU%d, code 0x%08x -- %s\n",
 820                 smp_processor_id(), esr, esr_get_class_string(esr));
 821         if (regs)
 822                 __show_regs(regs);
 823
 824         nmi_panic(regs, "Asynchronous SError Interrupt");
 825
 826         cpu_park_loop();
 827         unreachable();
 828 }
 829
 830 bool arm64_is_fatal_ras_serror(struct pt_regs *regs, unsigned int esr)
 831 {
 832         u32 aet = arm64_ras_serror_get_severity(esr);
 833
 834         switch (aet) {
 835         case ESR_ELx_AET_CE:    /* corrected error */
 836         case ESR_ELx_AET_UEO:   /* restartable, not yet consumed */
 837                 /*
 838                  * The CPU can make progress. We may take UEO again as
 839                  * a more severe error.
 840                  */
 841                 return false;
 842
 843         case ESR_ELx_AET_UEU:   /* Uncorrected Unrecoverable */
 844         case ESR_ELx_AET_UER:   /* Uncorrected Recoverable */
 845                 /*
 846                  * The CPU can't make progress. The exception may have
 847                  * been imprecise.
 848                  *
 849                  * Neoverse-N1 #1349291 means a non-KVM SError reported as
 850                  * Unrecoverable should be treated as Uncontainable. We
 851                  * call arm64_serror_panic() in both cases.
 852                  */
 853                 return true;
 854
 855         case ESR_ELx_AET_UC:    /* Uncontainable or Uncategorized error */
 856         default:
 857                 /* Error has been silently propagated */
 858                 arm64_serror_panic(regs, esr);
 859         }
 860 }
 861
 862 asmlinkage void noinstr do_serror(struct pt_regs *regs, unsigned int esr)
 863 {
 864         arm64_enter_nmi(regs);
 865
 866         /* non-RAS errors are not containable */
 867         if (!arm64_is_ras_serror(esr) || arm64_is_fatal_ras_serror(regs, esr))
 868                 arm64_serror_panic(regs, esr);
 869
 870         arm64_exit_nmi(regs);
 871 }
 872
 873 /* GENERIC_BUG traps */
 874
 875 int is_valid_bugaddr(unsigned long addr)
 876 {
 877         /*
 878          * bug_handler() only called for BRK #BUG_BRK_IMM.
 879          * So the answer is trivial -- any spurious instances with no
 880          * bug table entry will be rejected by report_bug() and passed
 881          * back to the debug-monitors code and handled as a fatal
 882          * unexpected debug exception.
 883          */
 884         return 1;
 885 }
 886
 887 static int bug_handler(struct pt_regs *regs, unsigned int esr)
 888 {
 889         switch (report_bug(regs->pc, regs)) {
 890         case BUG_TRAP_TYPE_BUG:
 891                 die("Oops - BUG", regs, esr);
 892                 break;
 893
 894         case BUG_TRAP_TYPE_WARN:
 895                 break;
 896
 897         default:
 898                 /* unknown/unrecognised bug trap type */
 899                 return DBG_HOOK_ERROR;
 900         }
 901
 902         /* If thread survives, skip over the BUG instruction and continue: */
 903         arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE);
 904         return DBG_HOOK_HANDLED;
 905 }
 906
 907 static struct break_hook bug_break_hook = {
 908         .fn = bug_handler,
 909         .imm = BUG_BRK_IMM,
 910 };
 911
 912 static int reserved_fault_handler(struct pt_regs *regs, unsigned int esr)
 913 {
 914         pr_err("%s generated an invalid instruction at %pS!\n",
 915                 in_bpf_jit(regs) ? "BPF JIT" : "Kernel text patching",
 916                 (void *)instruction_pointer(regs));
 917
 918         /* We cannot handle this */
 919         return DBG_HOOK_ERROR;
 920 }
 921
 922 static struct break_hook fault_break_hook = {
 923         .fn = reserved_fault_handler,
 924         .imm = FAULT_BRK_IMM,
 925 };
 926
 927 #ifdef CONFIG_KASAN_SW_TAGS
 928
 929 #define KASAN_ESR_RECOVER       0x20
 930 #define KASAN_ESR_WRITE 0x10
 931 #define KASAN_ESR_SIZE_MASK     0x0f
 932 #define KASAN_ESR_SIZE(esr)     (1 << ((esr) & KASAN_ESR_SIZE_MASK))
 933
 934 static int kasan_handler(struct pt_regs *regs, unsigned int esr)
 935 {
 936         bool recover = esr & KASAN_ESR_RECOVER;
 937         bool write = esr & KASAN_ESR_WRITE;
 938         size_t size = KASAN_ESR_SIZE(esr);
 939         u64 addr = regs->regs[0];
 940         u64 pc = regs->pc;
 941
 942         kasan_report(addr, size, write, pc);
 943
 944         /*
 945          * The instrumentation allows to control whether we can proceed after
 946          * a crash was detected. This is done by passing the -recover flag to
 947          * the compiler. Disabling recovery allows to generate more compact
 948          * code.
 949          *
 950          * Unfortunately disabling recovery doesn't work for the kernel right
 951          * now. KASAN reporting is disabled in some contexts (for example when
 952          * the allocator accesses slab object metadata; this is controlled by
 953          * current->kasan_depth). All these accesses are detected by the tool,
 954          * even though the reports for them are not printed.
 955          *
 956          * This is something that might be fixed at some point in the future.
 957          */
 958         if (!recover)
 959                 die("Oops - KASAN", regs, esr);
 960
 961         /* If thread survives, skip over the brk instruction and continue: */
 962         arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE);
 963         return DBG_HOOK_HANDLED;
 964 }
 965
 966 static struct break_hook kasan_break_hook = {
 967         .fn     = kasan_handler,
 968         .imm    = KASAN_BRK_IMM,
 969         .mask   = KASAN_BRK_MASK,
 970 };
 971 #endif
 972
 973 /*
 974  * Initial handler for AArch64 BRK exceptions
 975  * This handler only used until debug_traps_init().
 976  */
 977 int __init early_brk64(unsigned long addr, unsigned int esr,
 978                 struct pt_regs *regs)
 979 {
 980 #ifdef CONFIG_KASAN_SW_TAGS
 981         unsigned int comment = esr & ESR_ELx_BRK64_ISS_COMMENT_MASK;
 982
 983         if ((comment & ~KASAN_BRK_MASK) == KASAN_BRK_IMM)
 984                 return kasan_handler(regs, esr) != DBG_HOOK_HANDLED;
 985 #endif
 986         return bug_handler(regs, esr) != DBG_HOOK_HANDLED;
 987 }
 988
 989 void __init trap_init(void)
 990 {
 991         register_kernel_break_hook(&bug_break_hook);
 992         register_kernel_break_hook(&fault_break_hook);
 993 #ifdef CONFIG_KASAN_SW_TAGS
 994         register_kernel_break_hook(&kasan_break_hook);
 995 #endif
 996         debug_traps_init();
 997 }