2 * Based on arch/arm/kernel/setup.c
4 * Copyright (C) 1995-2001 Russell King
5 * Copyright (C) 2012 ARM Ltd.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program. If not, see <http://www.gnu.org/licenses/>.
20 #include <linux/acpi.h>
21 #include <linux/export.h>
22 #include <linux/kernel.h>
23 #include <linux/stddef.h>
24 #include <linux/ioport.h>
25 #include <linux/delay.h>
26 #include <linux/utsname.h>
27 #include <linux/initrd.h>
28 #include <linux/console.h>
29 #include <linux/cache.h>
30 #include <linux/bootmem.h>
31 #include <linux/screen_info.h>
32 #include <linux/init.h>
33 #include <linux/kexec.h>
34 #include <linux/root_dev.h>
35 #include <linux/cpu.h>
36 #include <linux/interrupt.h>
37 #include <linux/smp.h>
39 #include <linux/proc_fs.h>
40 #include <linux/memblock.h>
41 #include <linux/of_fdt.h>
42 #include <linux/efi.h>
43 #include <linux/psci.h>
44 #include <linux/sched/task.h>
48 #include <asm/fixmap.h>
50 #include <asm/cputype.h>
52 #include <asm/cpufeature.h>
53 #include <asm/cpu_ops.h>
54 #include <asm/kasan.h>
56 #include <asm/sections.h>
57 #include <asm/setup.h>
58 #include <asm/smp_plat.h>
59 #include <asm/cacheflush.h>
60 #include <asm/tlbflush.h>
61 #include <asm/traps.h>
62 #include <asm/memblock.h>
64 #include <asm/xen/hypervisor.h>
65 #include <asm/mmu_context.h>
67 phys_addr_t __fdt_pointer __initdata;
70 * Standard memory resources
72 static struct resource mem_res[] = {
74 .name = "Kernel code",
77 .flags = IORESOURCE_SYSTEM_RAM
80 .name = "Kernel data",
83 .flags = IORESOURCE_SYSTEM_RAM
87 #define kernel_code mem_res[0]
88 #define kernel_data mem_res[1]
91 * The recorded values of x0 .. x3 upon kernel entry.
93 u64 __cacheline_aligned boot_args[4];
95 void __init smp_setup_processor_id(void)
97 u64 mpidr = read_cpuid_mpidr() & MPIDR_HWID_BITMASK;
98 cpu_logical_map(0) = mpidr;
101 * clear __my_cpu_offset on boot CPU to avoid hang caused by
102 * using percpu variable early, for example, lockdep will
103 * access percpu variable inside lock_release
105 set_my_cpu_offset(0);
106 pr_info("Booting Linux on physical CPU 0x%lx\n", (unsigned long)mpidr);
109 bool arch_match_cpu_phys_id(int cpu, u64 phys_id)
111 return phys_id == cpu_logical_map(cpu);
114 struct mpidr_hash mpidr_hash;
116 * smp_build_mpidr_hash - Pre-compute shifts required at each affinity
117 * level in order to build a linear index from an
118 * MPIDR value. Resulting algorithm is a collision
119 * free hash carried out through shifting and ORing
121 static void __init smp_build_mpidr_hash(void)
123 u32 i, affinity, fs[4], bits[4], ls;
126 * Pre-scan the list of MPIDRS and filter out bits that do
127 * not contribute to affinity levels, ie they never toggle.
129 for_each_possible_cpu(i)
130 mask |= (cpu_logical_map(i) ^ cpu_logical_map(0));
131 pr_debug("mask of set bits %#llx\n", mask);
133 * Find and stash the last and first bit set at all affinity levels to
134 * check how many bits are required to represent them.
136 for (i = 0; i < 4; i++) {
137 affinity = MPIDR_AFFINITY_LEVEL(mask, i);
139 * Find the MSB bit and LSB bits position
140 * to determine how many bits are required
141 * to express the affinity level.
144 fs[i] = affinity ? ffs(affinity) - 1 : 0;
145 bits[i] = ls - fs[i];
148 * An index can be created from the MPIDR_EL1 by isolating the
149 * significant bits at each affinity level and by shifting
150 * them in order to compress the 32 bits values space to a
151 * compressed set of values. This is equivalent to hashing
152 * the MPIDR_EL1 through shifting and ORing. It is a collision free
153 * hash though not minimal since some levels might contain a number
154 * of CPUs that is not an exact power of 2 and their bit
155 * representation might contain holes, eg MPIDR_EL1[7:0] = {0x2, 0x80}.
157 mpidr_hash.shift_aff[0] = MPIDR_LEVEL_SHIFT(0) + fs[0];
158 mpidr_hash.shift_aff[1] = MPIDR_LEVEL_SHIFT(1) + fs[1] - bits[0];
159 mpidr_hash.shift_aff[2] = MPIDR_LEVEL_SHIFT(2) + fs[2] -
161 mpidr_hash.shift_aff[3] = MPIDR_LEVEL_SHIFT(3) +
162 fs[3] - (bits[2] + bits[1] + bits[0]);
163 mpidr_hash.mask = mask;
164 mpidr_hash.bits = bits[3] + bits[2] + bits[1] + bits[0];
165 pr_debug("MPIDR hash: aff0[%u] aff1[%u] aff2[%u] aff3[%u] mask[%#llx] bits[%u]\n",
166 mpidr_hash.shift_aff[0],
167 mpidr_hash.shift_aff[1],
168 mpidr_hash.shift_aff[2],
169 mpidr_hash.shift_aff[3],
173 * 4x is an arbitrary value used to warn on a hash table much bigger
174 * than expected on most systems.
176 if (mpidr_hash_size() > 4 * num_possible_cpus())
177 pr_warn("Large number of MPIDR hash buckets detected\n");
180 static void __init setup_machine_fdt(phys_addr_t dt_phys)
182 void *dt_virt = fixmap_remap_fdt(dt_phys);
185 if (!dt_virt || !early_init_dt_scan(dt_virt)) {
187 "Error: invalid device tree blob at physical address %pa (virtual address 0x%p)\n"
188 "The dtb must be 8-byte aligned and must not exceed 2 MB in size\n"
189 "\nPlease check your bootloader.",
196 name = of_flat_dt_get_machine_name();
200 pr_info("Machine model: %s\n", name);
201 dump_stack_set_arch_desc("%s (DT)", name);
204 static void __init request_standard_resources(void)
206 struct memblock_region *region;
207 struct resource *res;
209 kernel_code.start = __pa_symbol(_text);
210 kernel_code.end = __pa_symbol(__init_begin - 1);
211 kernel_data.start = __pa_symbol(_sdata);
212 kernel_data.end = __pa_symbol(_end - 1);
214 for_each_memblock(memory, region) {
215 res = alloc_bootmem_low(sizeof(*res));
216 if (memblock_is_nomap(region)) {
217 res->name = "reserved";
218 res->flags = IORESOURCE_MEM;
220 res->name = "System RAM";
221 res->flags = IORESOURCE_SYSTEM_RAM | IORESOURCE_BUSY;
223 res->start = __pfn_to_phys(memblock_region_memory_base_pfn(region));
224 res->end = __pfn_to_phys(memblock_region_memory_end_pfn(region)) - 1;
226 request_resource(&iomem_resource, res);
228 if (kernel_code.start >= res->start &&
229 kernel_code.end <= res->end)
230 request_resource(res, &kernel_code);
231 if (kernel_data.start >= res->start &&
232 kernel_data.end <= res->end)
233 request_resource(res, &kernel_data);
234 #ifdef CONFIG_KEXEC_CORE
235 /* Userspace will find "Crash kernel" region in /proc/iomem. */
236 if (crashk_res.end && crashk_res.start >= res->start &&
237 crashk_res.end <= res->end)
238 request_resource(res, &crashk_res);
243 u64 __cpu_logical_map[NR_CPUS] = { [0 ... NR_CPUS-1] = INVALID_HWID };
245 void __init setup_arch(char **cmdline_p)
247 pr_info("Boot CPU: AArch64 Processor [%08x]\n", read_cpuid_id());
249 sprintf(init_utsname()->machine, UTS_MACHINE);
250 init_mm.start_code = (unsigned long) _text;
251 init_mm.end_code = (unsigned long) _etext;
252 init_mm.end_data = (unsigned long) _edata;
253 init_mm.brk = (unsigned long) _end;
255 *cmdline_p = boot_command_line;
258 early_ioremap_init();
260 setup_machine_fdt(__fdt_pointer);
265 * Unmask asynchronous aborts after bringing up possible earlycon.
266 * (Report possible System Errors once we can report this occurred)
268 local_async_enable();
271 * TTBR0 is only used for the identity mapping at this stage. Make it
272 * point to zero page to avoid speculatively fetching new entries.
274 cpu_uninstall_idmap();
278 arm64_memblock_init();
282 acpi_table_upgrade();
284 /* Parse the ACPI tables for possible boot-time configuration */
285 acpi_boot_table_init();
288 unflatten_device_tree();
294 request_standard_resources();
296 early_ioremap_reset();
303 cpu_read_bootcpu_ops();
305 smp_build_mpidr_hash();
307 #ifdef CONFIG_ARM64_SW_TTBR0_PAN
309 * Make sure init_thread_info.ttbr0 always generates translation
310 * faults in case uaccess_enable() is inadvertently called by the init
313 init_task.thread_info.ttbr0 = __pa_symbol(empty_zero_page);
317 #if defined(CONFIG_VGA_CONSOLE)
318 conswitchp = &vga_con;
319 #elif defined(CONFIG_DUMMY_CONSOLE)
320 conswitchp = &dummy_con;
323 if (boot_args[1] || boot_args[2] || boot_args[3]) {
324 pr_err("WARNING: x1-x3 nonzero in violation of boot protocol:\n"
325 "\tx1: %016llx\n\tx2: %016llx\n\tx3: %016llx\n"
326 "This indicates a broken bootloader or old kernel\n",
327 boot_args[1], boot_args[2], boot_args[3]);
331 static int __init topology_init(void)
335 for_each_online_node(i)
336 register_one_node(i);
338 for_each_possible_cpu(i) {
339 struct cpu *cpu = &per_cpu(cpu_data.cpu, i);
340 cpu->hotpluggable = 1;
341 register_cpu(cpu, i);
346 subsys_initcall(topology_init);
349 * Dump out kernel offset information on panic.
351 static int dump_kernel_offset(struct notifier_block *self, unsigned long v,
354 const unsigned long offset = kaslr_offset();
356 if (IS_ENABLED(CONFIG_RANDOMIZE_BASE) && offset > 0) {
357 pr_emerg("Kernel Offset: 0x%lx from 0x%lx\n",
358 offset, KIMAGE_VADDR);
360 pr_emerg("Kernel Offset: disabled\n");
365 static struct notifier_block kernel_offset_notifier = {
366 .notifier_call = dump_kernel_offset
369 static int __init register_kernel_offset_dumper(void)
371 atomic_notifier_chain_register(&panic_notifier_list,
372 &kernel_offset_notifier);
375 __initcall(register_kernel_offset_dumper);