1 // SPDX-License-Identifier: GPL-2.0-only
3 * Based on arch/arm/kernel/ptrace.c
6 * edited by Linus Torvalds
7 * ARM modifications Copyright (C) 2000 Russell King
8 * Copyright (C) 2012 ARM Ltd.
11 #include <linux/audit.h>
12 #include <linux/compat.h>
13 #include <linux/kernel.h>
14 #include <linux/sched/signal.h>
15 #include <linux/sched/task_stack.h>
17 #include <linux/nospec.h>
18 #include <linux/smp.h>
19 #include <linux/ptrace.h>
20 #include <linux/user.h>
21 #include <linux/seccomp.h>
22 #include <linux/security.h>
23 #include <linux/init.h>
24 #include <linux/signal.h>
25 #include <linux/string.h>
26 #include <linux/uaccess.h>
27 #include <linux/perf_event.h>
28 #include <linux/hw_breakpoint.h>
29 #include <linux/regset.h>
30 #include <linux/elf.h>
32 #include <asm/compat.h>
33 #include <asm/cpufeature.h>
34 #include <asm/debug-monitors.h>
35 #include <asm/fpsimd.h>
37 #include <asm/pointer_auth.h>
38 #include <asm/stacktrace.h>
39 #include <asm/syscall.h>
40 #include <asm/traps.h>
41 #include <asm/system_misc.h>
43 #define CREATE_TRACE_POINTS
44 #include <trace/events/syscalls.h>
46 struct pt_regs_offset {
51 #define REG_OFFSET_NAME(r) {.name = #r, .offset = offsetof(struct pt_regs, r)}
52 #define REG_OFFSET_END {.name = NULL, .offset = 0}
53 #define GPR_OFFSET_NAME(r) \
54 {.name = "x" #r, .offset = offsetof(struct pt_regs, regs[r])}
56 static const struct pt_regs_offset regoffset_table[] = {
88 {.name = "lr", .offset = offsetof(struct pt_regs, regs[30])},
91 REG_OFFSET_NAME(pstate),
96 * regs_query_register_offset() - query register offset from its name
97 * @name: the name of a register
99 * regs_query_register_offset() returns the offset of a register in struct
100 * pt_regs from its name. If the name is invalid, this returns -EINVAL;
102 int regs_query_register_offset(const char *name)
104 const struct pt_regs_offset *roff;
106 for (roff = regoffset_table; roff->name != NULL; roff++)
107 if (!strcmp(roff->name, name))
113 * regs_within_kernel_stack() - check the address in the stack
114 * @regs: pt_regs which contains kernel stack pointer.
115 * @addr: address which is checked.
117 * regs_within_kernel_stack() checks @addr is within the kernel stack page(s).
118 * If @addr is within the kernel stack, it returns true. If not, returns false.
120 static bool regs_within_kernel_stack(struct pt_regs *regs, unsigned long addr)
122 return ((addr & ~(THREAD_SIZE - 1)) ==
123 (kernel_stack_pointer(regs) & ~(THREAD_SIZE - 1))) ||
124 on_irq_stack(addr, sizeof(unsigned long));
128 * regs_get_kernel_stack_nth() - get Nth entry of the stack
129 * @regs: pt_regs which contains kernel stack pointer.
130 * @n: stack entry number.
132 * regs_get_kernel_stack_nth() returns @n th entry of the kernel stack which
133 * is specified by @regs. If the @n th entry is NOT in the kernel stack,
136 unsigned long regs_get_kernel_stack_nth(struct pt_regs *regs, unsigned int n)
138 unsigned long *addr = (unsigned long *)kernel_stack_pointer(regs);
141 if (regs_within_kernel_stack(regs, (unsigned long)addr))
148 * TODO: does not yet catch signals sent when the child dies.
149 * in exit.c or in signal.c.
153 * Called by kernel/ptrace.c when detaching..
155 void ptrace_disable(struct task_struct *child)
158 * This would be better off in core code, but PTRACE_DETACH has
159 * grown its fair share of arch-specific worts and changing it
160 * is likely to cause regressions on obscure architectures.
162 user_disable_single_step(child);
165 #ifdef CONFIG_HAVE_HW_BREAKPOINT
167 * Handle hitting a HW-breakpoint.
169 static void ptrace_hbptriggered(struct perf_event *bp,
170 struct perf_sample_data *data,
171 struct pt_regs *regs)
173 struct arch_hw_breakpoint *bkpt = counter_arch_bp(bp);
174 const char *desc = "Hardware breakpoint trap (ptrace)";
177 if (is_compat_task()) {
181 for (i = 0; i < ARM_MAX_BRP; ++i) {
182 if (current->thread.debug.hbp_break[i] == bp) {
183 si_errno = (i << 1) + 1;
188 for (i = 0; i < ARM_MAX_WRP; ++i) {
189 if (current->thread.debug.hbp_watch[i] == bp) {
190 si_errno = -((i << 1) + 1);
194 arm64_force_sig_ptrace_errno_trap(si_errno, bkpt->trigger,
199 arm64_force_sig_fault(SIGTRAP, TRAP_HWBKPT, bkpt->trigger, desc);
203 * Unregister breakpoints from this task and reset the pointers in
206 void flush_ptrace_hw_breakpoint(struct task_struct *tsk)
209 struct thread_struct *t = &tsk->thread;
211 for (i = 0; i < ARM_MAX_BRP; i++) {
212 if (t->debug.hbp_break[i]) {
213 unregister_hw_breakpoint(t->debug.hbp_break[i]);
214 t->debug.hbp_break[i] = NULL;
218 for (i = 0; i < ARM_MAX_WRP; i++) {
219 if (t->debug.hbp_watch[i]) {
220 unregister_hw_breakpoint(t->debug.hbp_watch[i]);
221 t->debug.hbp_watch[i] = NULL;
226 void ptrace_hw_copy_thread(struct task_struct *tsk)
228 memset(&tsk->thread.debug, 0, sizeof(struct debug_info));
231 static struct perf_event *ptrace_hbp_get_event(unsigned int note_type,
232 struct task_struct *tsk,
235 struct perf_event *bp = ERR_PTR(-EINVAL);
238 case NT_ARM_HW_BREAK:
239 if (idx >= ARM_MAX_BRP)
241 idx = array_index_nospec(idx, ARM_MAX_BRP);
242 bp = tsk->thread.debug.hbp_break[idx];
244 case NT_ARM_HW_WATCH:
245 if (idx >= ARM_MAX_WRP)
247 idx = array_index_nospec(idx, ARM_MAX_WRP);
248 bp = tsk->thread.debug.hbp_watch[idx];
256 static int ptrace_hbp_set_event(unsigned int note_type,
257 struct task_struct *tsk,
259 struct perf_event *bp)
264 case NT_ARM_HW_BREAK:
265 if (idx >= ARM_MAX_BRP)
267 idx = array_index_nospec(idx, ARM_MAX_BRP);
268 tsk->thread.debug.hbp_break[idx] = bp;
271 case NT_ARM_HW_WATCH:
272 if (idx >= ARM_MAX_WRP)
274 idx = array_index_nospec(idx, ARM_MAX_WRP);
275 tsk->thread.debug.hbp_watch[idx] = bp;
284 static struct perf_event *ptrace_hbp_create(unsigned int note_type,
285 struct task_struct *tsk,
288 struct perf_event *bp;
289 struct perf_event_attr attr;
293 case NT_ARM_HW_BREAK:
294 type = HW_BREAKPOINT_X;
296 case NT_ARM_HW_WATCH:
297 type = HW_BREAKPOINT_RW;
300 return ERR_PTR(-EINVAL);
303 ptrace_breakpoint_init(&attr);
306 * Initialise fields to sane defaults
307 * (i.e. values that will pass validation).
310 attr.bp_len = HW_BREAKPOINT_LEN_4;
314 bp = register_user_hw_breakpoint(&attr, ptrace_hbptriggered, NULL, tsk);
318 err = ptrace_hbp_set_event(note_type, tsk, idx, bp);
325 static int ptrace_hbp_fill_attr_ctrl(unsigned int note_type,
326 struct arch_hw_breakpoint_ctrl ctrl,
327 struct perf_event_attr *attr)
329 int err, len, type, offset, disabled = !ctrl.enabled;
331 attr->disabled = disabled;
335 err = arch_bp_generic_fields(ctrl, &len, &type, &offset);
340 case NT_ARM_HW_BREAK:
341 if ((type & HW_BREAKPOINT_X) != type)
344 case NT_ARM_HW_WATCH:
345 if ((type & HW_BREAKPOINT_RW) != type)
353 attr->bp_type = type;
354 attr->bp_addr += offset;
359 static int ptrace_hbp_get_resource_info(unsigned int note_type, u32 *info)
365 case NT_ARM_HW_BREAK:
366 num = hw_breakpoint_slots(TYPE_INST);
368 case NT_ARM_HW_WATCH:
369 num = hw_breakpoint_slots(TYPE_DATA);
375 reg |= debug_monitors_arch();
383 static int ptrace_hbp_get_ctrl(unsigned int note_type,
384 struct task_struct *tsk,
388 struct perf_event *bp = ptrace_hbp_get_event(note_type, tsk, idx);
393 *ctrl = bp ? encode_ctrl_reg(counter_arch_bp(bp)->ctrl) : 0;
397 static int ptrace_hbp_get_addr(unsigned int note_type,
398 struct task_struct *tsk,
402 struct perf_event *bp = ptrace_hbp_get_event(note_type, tsk, idx);
407 *addr = bp ? counter_arch_bp(bp)->address : 0;
411 static struct perf_event *ptrace_hbp_get_initialised_bp(unsigned int note_type,
412 struct task_struct *tsk,
415 struct perf_event *bp = ptrace_hbp_get_event(note_type, tsk, idx);
418 bp = ptrace_hbp_create(note_type, tsk, idx);
423 static int ptrace_hbp_set_ctrl(unsigned int note_type,
424 struct task_struct *tsk,
429 struct perf_event *bp;
430 struct perf_event_attr attr;
431 struct arch_hw_breakpoint_ctrl ctrl;
433 bp = ptrace_hbp_get_initialised_bp(note_type, tsk, idx);
440 decode_ctrl_reg(uctrl, &ctrl);
441 err = ptrace_hbp_fill_attr_ctrl(note_type, ctrl, &attr);
445 return modify_user_hw_breakpoint(bp, &attr);
448 static int ptrace_hbp_set_addr(unsigned int note_type,
449 struct task_struct *tsk,
454 struct perf_event *bp;
455 struct perf_event_attr attr;
457 bp = ptrace_hbp_get_initialised_bp(note_type, tsk, idx);
465 err = modify_user_hw_breakpoint(bp, &attr);
469 #define PTRACE_HBP_ADDR_SZ sizeof(u64)
470 #define PTRACE_HBP_CTRL_SZ sizeof(u32)
471 #define PTRACE_HBP_PAD_SZ sizeof(u32)
473 static int hw_break_get(struct task_struct *target,
474 const struct user_regset *regset,
477 unsigned int note_type = regset->core_note_type;
483 ret = ptrace_hbp_get_resource_info(note_type, &info);
487 membuf_write(&to, &info, sizeof(info));
488 membuf_zero(&to, sizeof(u32));
489 /* (address, ctrl) registers */
491 ret = ptrace_hbp_get_addr(note_type, target, idx, &addr);
494 ret = ptrace_hbp_get_ctrl(note_type, target, idx, &ctrl);
497 membuf_store(&to, addr);
498 membuf_store(&to, ctrl);
499 membuf_zero(&to, sizeof(u32));
505 static int hw_break_set(struct task_struct *target,
506 const struct user_regset *regset,
507 unsigned int pos, unsigned int count,
508 const void *kbuf, const void __user *ubuf)
510 unsigned int note_type = regset->core_note_type;
511 int ret, idx = 0, offset, limit;
515 /* Resource info and pad */
516 offset = offsetof(struct user_hwdebug_state, dbg_regs);
517 user_regset_copyin_ignore(&pos, &count, &kbuf, &ubuf, 0, offset);
519 /* (address, ctrl) registers */
520 limit = regset->n * regset->size;
521 while (count && offset < limit) {
522 if (count < PTRACE_HBP_ADDR_SZ)
524 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &addr,
525 offset, offset + PTRACE_HBP_ADDR_SZ);
528 ret = ptrace_hbp_set_addr(note_type, target, idx, addr);
531 offset += PTRACE_HBP_ADDR_SZ;
535 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &ctrl,
536 offset, offset + PTRACE_HBP_CTRL_SZ);
539 ret = ptrace_hbp_set_ctrl(note_type, target, idx, ctrl);
542 offset += PTRACE_HBP_CTRL_SZ;
544 user_regset_copyin_ignore(&pos, &count, &kbuf, &ubuf,
545 offset, offset + PTRACE_HBP_PAD_SZ);
546 offset += PTRACE_HBP_PAD_SZ;
552 #endif /* CONFIG_HAVE_HW_BREAKPOINT */
554 static int gpr_get(struct task_struct *target,
555 const struct user_regset *regset,
558 struct user_pt_regs *uregs = &task_pt_regs(target)->user_regs;
559 return membuf_write(&to, uregs, sizeof(*uregs));
562 static int gpr_set(struct task_struct *target, const struct user_regset *regset,
563 unsigned int pos, unsigned int count,
564 const void *kbuf, const void __user *ubuf)
567 struct user_pt_regs newregs = task_pt_regs(target)->user_regs;
569 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &newregs, 0, -1);
573 if (!valid_user_regs(&newregs, target))
576 task_pt_regs(target)->user_regs = newregs;
580 static int fpr_active(struct task_struct *target, const struct user_regset *regset)
582 if (!system_supports_fpsimd())
588 * TODO: update fp accessors for lazy context switching (sync/flush hwstate)
590 static int __fpr_get(struct task_struct *target,
591 const struct user_regset *regset,
594 struct user_fpsimd_state *uregs;
596 sve_sync_to_fpsimd(target);
598 uregs = &target->thread.uw.fpsimd_state;
600 return membuf_write(&to, uregs, sizeof(*uregs));
603 static int fpr_get(struct task_struct *target, const struct user_regset *regset,
606 if (!system_supports_fpsimd())
609 if (target == current)
610 fpsimd_preserve_current_state();
612 return __fpr_get(target, regset, to);
615 static int __fpr_set(struct task_struct *target,
616 const struct user_regset *regset,
617 unsigned int pos, unsigned int count,
618 const void *kbuf, const void __user *ubuf,
619 unsigned int start_pos)
622 struct user_fpsimd_state newstate;
625 * Ensure target->thread.uw.fpsimd_state is up to date, so that a
626 * short copyin can't resurrect stale data.
628 sve_sync_to_fpsimd(target);
630 newstate = target->thread.uw.fpsimd_state;
632 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &newstate,
633 start_pos, start_pos + sizeof(newstate));
637 target->thread.uw.fpsimd_state = newstate;
642 static int fpr_set(struct task_struct *target, const struct user_regset *regset,
643 unsigned int pos, unsigned int count,
644 const void *kbuf, const void __user *ubuf)
648 if (!system_supports_fpsimd())
651 ret = __fpr_set(target, regset, pos, count, kbuf, ubuf, 0);
655 sve_sync_from_fpsimd_zeropad(target);
656 fpsimd_flush_task_state(target);
661 static int tls_get(struct task_struct *target, const struct user_regset *regset,
666 if (target == current)
667 tls_preserve_current_state();
669 ret = membuf_store(&to, target->thread.uw.tp_value);
670 if (system_supports_tpidr2())
671 ret = membuf_store(&to, target->thread.tpidr2_el0);
673 ret = membuf_zero(&to, sizeof(u64));
678 static int tls_set(struct task_struct *target, const struct user_regset *regset,
679 unsigned int pos, unsigned int count,
680 const void *kbuf, const void __user *ubuf)
683 unsigned long tls[2];
685 tls[0] = target->thread.uw.tp_value;
686 if (system_supports_tpidr2())
687 tls[1] = target->thread.tpidr2_el0;
689 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, tls, 0, count);
693 target->thread.uw.tp_value = tls[0];
694 if (system_supports_tpidr2())
695 target->thread.tpidr2_el0 = tls[1];
700 static int system_call_get(struct task_struct *target,
701 const struct user_regset *regset,
704 return membuf_store(&to, task_pt_regs(target)->syscallno);
707 static int system_call_set(struct task_struct *target,
708 const struct user_regset *regset,
709 unsigned int pos, unsigned int count,
710 const void *kbuf, const void __user *ubuf)
712 int syscallno = task_pt_regs(target)->syscallno;
715 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &syscallno, 0, -1);
719 task_pt_regs(target)->syscallno = syscallno;
723 #ifdef CONFIG_ARM64_SVE
725 static void sve_init_header_from_task(struct user_sve_header *header,
726 struct task_struct *target,
732 enum vec_type task_type;
734 memset(header, 0, sizeof(*header));
736 /* Check if the requested registers are active for the task */
737 if (thread_sm_enabled(&target->thread))
738 task_type = ARM64_VEC_SME;
740 task_type = ARM64_VEC_SVE;
741 active = (task_type == type);
745 if (test_tsk_thread_flag(target, TIF_SVE_VL_INHERIT))
746 header->flags |= SVE_PT_VL_INHERIT;
747 fpsimd_only = !test_tsk_thread_flag(target, TIF_SVE);
750 if (test_tsk_thread_flag(target, TIF_SME_VL_INHERIT))
751 header->flags |= SVE_PT_VL_INHERIT;
761 header->flags |= SVE_PT_REGS_FPSIMD;
763 header->flags |= SVE_PT_REGS_SVE;
767 header->vl = task_get_vl(target, type);
768 vq = sve_vq_from_vl(header->vl);
770 header->max_vl = vec_max_vl(type);
771 header->size = SVE_PT_SIZE(vq, header->flags);
772 header->max_size = SVE_PT_SIZE(sve_vq_from_vl(header->max_vl),
776 static unsigned int sve_size_from_header(struct user_sve_header const *header)
778 return ALIGN(header->size, SVE_VQ_BYTES);
781 static int sve_get_common(struct task_struct *target,
782 const struct user_regset *regset,
786 struct user_sve_header header;
788 unsigned long start, end;
791 sve_init_header_from_task(&header, target, type);
792 vq = sve_vq_from_vl(header.vl);
794 membuf_write(&to, &header, sizeof(header));
796 if (target == current)
797 fpsimd_preserve_current_state();
799 BUILD_BUG_ON(SVE_PT_FPSIMD_OFFSET != sizeof(header));
800 BUILD_BUG_ON(SVE_PT_SVE_OFFSET != sizeof(header));
802 switch ((header.flags & SVE_PT_REGS_MASK)) {
803 case SVE_PT_REGS_FPSIMD:
804 return __fpr_get(target, regset, to);
806 case SVE_PT_REGS_SVE:
807 start = SVE_PT_SVE_OFFSET;
808 end = SVE_PT_SVE_FFR_OFFSET(vq) + SVE_PT_SVE_FFR_SIZE(vq);
809 membuf_write(&to, target->thread.sve_state, end - start);
812 end = SVE_PT_SVE_FPSR_OFFSET(vq);
813 membuf_zero(&to, end - start);
816 * Copy fpsr, and fpcr which must follow contiguously in
817 * struct fpsimd_state:
820 end = SVE_PT_SVE_FPCR_OFFSET(vq) + SVE_PT_SVE_FPCR_SIZE;
821 membuf_write(&to, &target->thread.uw.fpsimd_state.fpsr,
825 end = sve_size_from_header(&header);
826 return membuf_zero(&to, end - start);
833 static int sve_get(struct task_struct *target,
834 const struct user_regset *regset,
837 if (!system_supports_sve())
840 return sve_get_common(target, regset, to, ARM64_VEC_SVE);
843 static int sve_set_common(struct task_struct *target,
844 const struct user_regset *regset,
845 unsigned int pos, unsigned int count,
846 const void *kbuf, const void __user *ubuf,
850 struct user_sve_header header;
852 unsigned long start, end;
855 if (count < sizeof(header))
857 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &header,
863 * Apart from SVE_PT_REGS_MASK, all SVE_PT_* flags are consumed by
864 * vec_set_vector_length(), which will also validate them for us:
866 ret = vec_set_vector_length(target, type, header.vl,
867 ((unsigned long)header.flags & ~SVE_PT_REGS_MASK) << 16);
871 /* Actual VL set may be less than the user asked for: */
872 vq = sve_vq_from_vl(task_get_vl(target, type));
874 /* Enter/exit streaming mode */
875 if (system_supports_sme()) {
876 u64 old_svcr = target->thread.svcr;
880 target->thread.svcr &= ~SVCR_SM_MASK;
883 target->thread.svcr |= SVCR_SM_MASK;
886 * Disable traps and ensure there is SME storage but
887 * preserve any currently set values in ZA/ZT.
889 sme_alloc(target, false);
890 set_tsk_thread_flag(target, TIF_SME);
899 * If we switched then invalidate any existing SVE
900 * state and ensure there's storage.
902 if (target->thread.svcr != old_svcr)
903 sve_alloc(target, true);
906 /* Registers: FPSIMD-only case */
908 BUILD_BUG_ON(SVE_PT_FPSIMD_OFFSET != sizeof(header));
909 if ((header.flags & SVE_PT_REGS_MASK) == SVE_PT_REGS_FPSIMD) {
910 ret = __fpr_set(target, regset, pos, count, kbuf, ubuf,
911 SVE_PT_FPSIMD_OFFSET);
912 clear_tsk_thread_flag(target, TIF_SVE);
913 target->thread.fp_type = FP_STATE_FPSIMD;
918 * Otherwise: no registers or full SVE case. For backwards
919 * compatibility reasons we treat empty flags as SVE registers.
923 * If setting a different VL from the requested VL and there is
924 * register data, the data layout will be wrong: don't even
925 * try to set the registers in this case.
927 if (count && vq != sve_vq_from_vl(header.vl)) {
932 sve_alloc(target, true);
933 if (!target->thread.sve_state) {
935 clear_tsk_thread_flag(target, TIF_SVE);
936 target->thread.fp_type = FP_STATE_FPSIMD;
941 * Ensure target->thread.sve_state is up to date with target's
942 * FPSIMD regs, so that a short copyin leaves trailing
943 * registers unmodified. Only enable SVE if we are
944 * configuring normal SVE, a system with streaming SVE may not
947 fpsimd_sync_to_sve(target);
948 if (type == ARM64_VEC_SVE)
949 set_tsk_thread_flag(target, TIF_SVE);
950 target->thread.fp_type = FP_STATE_SVE;
952 BUILD_BUG_ON(SVE_PT_SVE_OFFSET != sizeof(header));
953 start = SVE_PT_SVE_OFFSET;
954 end = SVE_PT_SVE_FFR_OFFSET(vq) + SVE_PT_SVE_FFR_SIZE(vq);
955 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
956 target->thread.sve_state,
962 end = SVE_PT_SVE_FPSR_OFFSET(vq);
963 user_regset_copyin_ignore(&pos, &count, &kbuf, &ubuf, start, end);
966 * Copy fpsr, and fpcr which must follow contiguously in
967 * struct fpsimd_state:
970 end = SVE_PT_SVE_FPCR_OFFSET(vq) + SVE_PT_SVE_FPCR_SIZE;
971 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
972 &target->thread.uw.fpsimd_state.fpsr,
976 fpsimd_flush_task_state(target);
980 static int sve_set(struct task_struct *target,
981 const struct user_regset *regset,
982 unsigned int pos, unsigned int count,
983 const void *kbuf, const void __user *ubuf)
985 if (!system_supports_sve())
988 return sve_set_common(target, regset, pos, count, kbuf, ubuf,
992 #endif /* CONFIG_ARM64_SVE */
994 #ifdef CONFIG_ARM64_SME
996 static int ssve_get(struct task_struct *target,
997 const struct user_regset *regset,
1000 if (!system_supports_sme())
1003 return sve_get_common(target, regset, to, ARM64_VEC_SME);
1006 static int ssve_set(struct task_struct *target,
1007 const struct user_regset *regset,
1008 unsigned int pos, unsigned int count,
1009 const void *kbuf, const void __user *ubuf)
1011 if (!system_supports_sme())
1014 return sve_set_common(target, regset, pos, count, kbuf, ubuf,
1018 static int za_get(struct task_struct *target,
1019 const struct user_regset *regset,
1022 struct user_za_header header;
1024 unsigned long start, end;
1026 if (!system_supports_sme())
1030 memset(&header, 0, sizeof(header));
1032 if (test_tsk_thread_flag(target, TIF_SME_VL_INHERIT))
1033 header.flags |= ZA_PT_VL_INHERIT;
1035 header.vl = task_get_sme_vl(target);
1036 vq = sve_vq_from_vl(header.vl);
1037 header.max_vl = sme_max_vl();
1038 header.max_size = ZA_PT_SIZE(vq);
1040 /* If ZA is not active there is only the header */
1041 if (thread_za_enabled(&target->thread))
1042 header.size = ZA_PT_SIZE(vq);
1044 header.size = ZA_PT_ZA_OFFSET;
1046 membuf_write(&to, &header, sizeof(header));
1048 BUILD_BUG_ON(ZA_PT_ZA_OFFSET != sizeof(header));
1049 end = ZA_PT_ZA_OFFSET;
1051 if (target == current)
1052 fpsimd_preserve_current_state();
1054 /* Any register data to include? */
1055 if (thread_za_enabled(&target->thread)) {
1057 end = ZA_PT_SIZE(vq);
1058 membuf_write(&to, target->thread.sme_state, end - start);
1061 /* Zero any trailing padding */
1063 end = ALIGN(header.size, SVE_VQ_BYTES);
1064 return membuf_zero(&to, end - start);
1067 static int za_set(struct task_struct *target,
1068 const struct user_regset *regset,
1069 unsigned int pos, unsigned int count,
1070 const void *kbuf, const void __user *ubuf)
1073 struct user_za_header header;
1075 unsigned long start, end;
1077 if (!system_supports_sme())
1081 if (count < sizeof(header))
1083 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &header,
1089 * All current ZA_PT_* flags are consumed by
1090 * vec_set_vector_length(), which will also validate them for
1093 ret = vec_set_vector_length(target, ARM64_VEC_SME, header.vl,
1094 ((unsigned long)header.flags) << 16);
1098 /* Actual VL set may be less than the user asked for: */
1099 vq = sve_vq_from_vl(task_get_sme_vl(target));
1101 /* Ensure there is some SVE storage for streaming mode */
1102 if (!target->thread.sve_state) {
1103 sve_alloc(target, false);
1104 if (!target->thread.sve_state) {
1110 /* Allocate/reinit ZA storage */
1111 sme_alloc(target, true);
1112 if (!target->thread.sme_state) {
1117 /* If there is no data then disable ZA */
1119 target->thread.svcr &= ~SVCR_ZA_MASK;
1124 * If setting a different VL from the requested VL and there is
1125 * register data, the data layout will be wrong: don't even
1126 * try to set the registers in this case.
1128 if (vq != sve_vq_from_vl(header.vl)) {
1133 BUILD_BUG_ON(ZA_PT_ZA_OFFSET != sizeof(header));
1134 start = ZA_PT_ZA_OFFSET;
1135 end = ZA_PT_SIZE(vq);
1136 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
1137 target->thread.sme_state,
1142 /* Mark ZA as active and let userspace use it */
1143 set_tsk_thread_flag(target, TIF_SME);
1144 target->thread.svcr |= SVCR_ZA_MASK;
1147 fpsimd_flush_task_state(target);
1151 static int zt_get(struct task_struct *target,
1152 const struct user_regset *regset,
1155 if (!system_supports_sme2())
1159 * If PSTATE.ZA is not set then ZT will be zeroed when it is
1160 * enabled so report the current register value as zero.
1162 if (thread_za_enabled(&target->thread))
1163 membuf_write(&to, thread_zt_state(&target->thread),
1166 membuf_zero(&to, ZT_SIG_REG_BYTES);
1171 static int zt_set(struct task_struct *target,
1172 const struct user_regset *regset,
1173 unsigned int pos, unsigned int count,
1174 const void *kbuf, const void __user *ubuf)
1178 if (!system_supports_sme2())
1181 /* Ensure SVE storage in case this is first use of SME */
1182 sve_alloc(target, false);
1183 if (!target->thread.sve_state)
1186 if (!thread_za_enabled(&target->thread)) {
1187 sme_alloc(target, true);
1188 if (!target->thread.sme_state)
1192 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
1193 thread_zt_state(&target->thread),
1194 0, ZT_SIG_REG_BYTES);
1196 target->thread.svcr |= SVCR_ZA_MASK;
1197 set_tsk_thread_flag(target, TIF_SME);
1200 fpsimd_flush_task_state(target);
1205 #endif /* CONFIG_ARM64_SME */
1207 #ifdef CONFIG_ARM64_PTR_AUTH
1208 static int pac_mask_get(struct task_struct *target,
1209 const struct user_regset *regset,
1213 * The PAC bits can differ across data and instruction pointers
1214 * depending on TCR_EL1.TBID*, which we may make use of in future, so
1215 * we expose separate masks.
1217 unsigned long mask = ptrauth_user_pac_mask();
1218 struct user_pac_mask uregs = {
1223 if (!system_supports_address_auth())
1226 return membuf_write(&to, &uregs, sizeof(uregs));
1229 static int pac_enabled_keys_get(struct task_struct *target,
1230 const struct user_regset *regset,
1233 long enabled_keys = ptrauth_get_enabled_keys(target);
1235 if (IS_ERR_VALUE(enabled_keys))
1236 return enabled_keys;
1238 return membuf_write(&to, &enabled_keys, sizeof(enabled_keys));
1241 static int pac_enabled_keys_set(struct task_struct *target,
1242 const struct user_regset *regset,
1243 unsigned int pos, unsigned int count,
1244 const void *kbuf, const void __user *ubuf)
1247 long enabled_keys = ptrauth_get_enabled_keys(target);
1249 if (IS_ERR_VALUE(enabled_keys))
1250 return enabled_keys;
1252 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &enabled_keys, 0,
1257 return ptrauth_set_enabled_keys(target, PR_PAC_ENABLED_KEYS_MASK,
1261 #ifdef CONFIG_CHECKPOINT_RESTORE
1262 static __uint128_t pac_key_to_user(const struct ptrauth_key *key)
1264 return (__uint128_t)key->hi << 64 | key->lo;
1267 static struct ptrauth_key pac_key_from_user(__uint128_t ukey)
1269 struct ptrauth_key key = {
1270 .lo = (unsigned long)ukey,
1271 .hi = (unsigned long)(ukey >> 64),
1277 static void pac_address_keys_to_user(struct user_pac_address_keys *ukeys,
1278 const struct ptrauth_keys_user *keys)
1280 ukeys->apiakey = pac_key_to_user(&keys->apia);
1281 ukeys->apibkey = pac_key_to_user(&keys->apib);
1282 ukeys->apdakey = pac_key_to_user(&keys->apda);
1283 ukeys->apdbkey = pac_key_to_user(&keys->apdb);
1286 static void pac_address_keys_from_user(struct ptrauth_keys_user *keys,
1287 const struct user_pac_address_keys *ukeys)
1289 keys->apia = pac_key_from_user(ukeys->apiakey);
1290 keys->apib = pac_key_from_user(ukeys->apibkey);
1291 keys->apda = pac_key_from_user(ukeys->apdakey);
1292 keys->apdb = pac_key_from_user(ukeys->apdbkey);
1295 static int pac_address_keys_get(struct task_struct *target,
1296 const struct user_regset *regset,
1299 struct ptrauth_keys_user *keys = &target->thread.keys_user;
1300 struct user_pac_address_keys user_keys;
1302 if (!system_supports_address_auth())
1305 pac_address_keys_to_user(&user_keys, keys);
1307 return membuf_write(&to, &user_keys, sizeof(user_keys));
1310 static int pac_address_keys_set(struct task_struct *target,
1311 const struct user_regset *regset,
1312 unsigned int pos, unsigned int count,
1313 const void *kbuf, const void __user *ubuf)
1315 struct ptrauth_keys_user *keys = &target->thread.keys_user;
1316 struct user_pac_address_keys user_keys;
1319 if (!system_supports_address_auth())
1322 pac_address_keys_to_user(&user_keys, keys);
1323 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
1327 pac_address_keys_from_user(keys, &user_keys);
1332 static void pac_generic_keys_to_user(struct user_pac_generic_keys *ukeys,
1333 const struct ptrauth_keys_user *keys)
1335 ukeys->apgakey = pac_key_to_user(&keys->apga);
1338 static void pac_generic_keys_from_user(struct ptrauth_keys_user *keys,
1339 const struct user_pac_generic_keys *ukeys)
1341 keys->apga = pac_key_from_user(ukeys->apgakey);
1344 static int pac_generic_keys_get(struct task_struct *target,
1345 const struct user_regset *regset,
1348 struct ptrauth_keys_user *keys = &target->thread.keys_user;
1349 struct user_pac_generic_keys user_keys;
1351 if (!system_supports_generic_auth())
1354 pac_generic_keys_to_user(&user_keys, keys);
1356 return membuf_write(&to, &user_keys, sizeof(user_keys));
1359 static int pac_generic_keys_set(struct task_struct *target,
1360 const struct user_regset *regset,
1361 unsigned int pos, unsigned int count,
1362 const void *kbuf, const void __user *ubuf)
1364 struct ptrauth_keys_user *keys = &target->thread.keys_user;
1365 struct user_pac_generic_keys user_keys;
1368 if (!system_supports_generic_auth())
1371 pac_generic_keys_to_user(&user_keys, keys);
1372 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
1376 pac_generic_keys_from_user(keys, &user_keys);
1380 #endif /* CONFIG_CHECKPOINT_RESTORE */
1381 #endif /* CONFIG_ARM64_PTR_AUTH */
1383 #ifdef CONFIG_ARM64_TAGGED_ADDR_ABI
1384 static int tagged_addr_ctrl_get(struct task_struct *target,
1385 const struct user_regset *regset,
1388 long ctrl = get_tagged_addr_ctrl(target);
1390 if (IS_ERR_VALUE(ctrl))
1393 return membuf_write(&to, &ctrl, sizeof(ctrl));
1396 static int tagged_addr_ctrl_set(struct task_struct *target, const struct
1397 user_regset *regset, unsigned int pos,
1398 unsigned int count, const void *kbuf, const
1404 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &ctrl, 0, -1);
1408 return set_tagged_addr_ctrl(target, ctrl);
1412 enum aarch64_regset {
1416 #ifdef CONFIG_HAVE_HW_BREAKPOINT
1421 #ifdef CONFIG_ARM64_SVE
1424 #ifdef CONFIG_ARM64_SME
1429 #ifdef CONFIG_ARM64_PTR_AUTH
1431 REGSET_PAC_ENABLED_KEYS,
1432 #ifdef CONFIG_CHECKPOINT_RESTORE
1437 #ifdef CONFIG_ARM64_TAGGED_ADDR_ABI
1438 REGSET_TAGGED_ADDR_CTRL,
1442 static const struct user_regset aarch64_regsets[] = {
1444 .core_note_type = NT_PRSTATUS,
1445 .n = sizeof(struct user_pt_regs) / sizeof(u64),
1446 .size = sizeof(u64),
1447 .align = sizeof(u64),
1448 .regset_get = gpr_get,
1452 .core_note_type = NT_PRFPREG,
1453 .n = sizeof(struct user_fpsimd_state) / sizeof(u32),
1455 * We pretend we have 32-bit registers because the fpsr and
1456 * fpcr are 32-bits wide.
1458 .size = sizeof(u32),
1459 .align = sizeof(u32),
1460 .active = fpr_active,
1461 .regset_get = fpr_get,
1465 .core_note_type = NT_ARM_TLS,
1467 .size = sizeof(void *),
1468 .align = sizeof(void *),
1469 .regset_get = tls_get,
1472 #ifdef CONFIG_HAVE_HW_BREAKPOINT
1473 [REGSET_HW_BREAK] = {
1474 .core_note_type = NT_ARM_HW_BREAK,
1475 .n = sizeof(struct user_hwdebug_state) / sizeof(u32),
1476 .size = sizeof(u32),
1477 .align = sizeof(u32),
1478 .regset_get = hw_break_get,
1479 .set = hw_break_set,
1481 [REGSET_HW_WATCH] = {
1482 .core_note_type = NT_ARM_HW_WATCH,
1483 .n = sizeof(struct user_hwdebug_state) / sizeof(u32),
1484 .size = sizeof(u32),
1485 .align = sizeof(u32),
1486 .regset_get = hw_break_get,
1487 .set = hw_break_set,
1490 [REGSET_SYSTEM_CALL] = {
1491 .core_note_type = NT_ARM_SYSTEM_CALL,
1493 .size = sizeof(int),
1494 .align = sizeof(int),
1495 .regset_get = system_call_get,
1496 .set = system_call_set,
1498 #ifdef CONFIG_ARM64_SVE
1499 [REGSET_SVE] = { /* Scalable Vector Extension */
1500 .core_note_type = NT_ARM_SVE,
1501 .n = DIV_ROUND_UP(SVE_PT_SIZE(SVE_VQ_MAX, SVE_PT_REGS_SVE),
1503 .size = SVE_VQ_BYTES,
1504 .align = SVE_VQ_BYTES,
1505 .regset_get = sve_get,
1509 #ifdef CONFIG_ARM64_SME
1510 [REGSET_SSVE] = { /* Streaming mode SVE */
1511 .core_note_type = NT_ARM_SSVE,
1512 .n = DIV_ROUND_UP(SVE_PT_SIZE(SME_VQ_MAX, SVE_PT_REGS_SVE),
1514 .size = SVE_VQ_BYTES,
1515 .align = SVE_VQ_BYTES,
1516 .regset_get = ssve_get,
1519 [REGSET_ZA] = { /* SME ZA */
1520 .core_note_type = NT_ARM_ZA,
1522 * ZA is a single register but it's variably sized and
1523 * the ptrace core requires that the size of any data
1524 * be an exact multiple of the configured register
1525 * size so report as though we had SVE_VQ_BYTES
1526 * registers. These values aren't exposed to
1529 .n = DIV_ROUND_UP(ZA_PT_SIZE(SME_VQ_MAX), SVE_VQ_BYTES),
1530 .size = SVE_VQ_BYTES,
1531 .align = SVE_VQ_BYTES,
1532 .regset_get = za_get,
1535 [REGSET_ZT] = { /* SME ZT */
1536 .core_note_type = NT_ARM_ZT,
1538 .size = ZT_SIG_REG_BYTES,
1539 .align = sizeof(u64),
1540 .regset_get = zt_get,
1544 #ifdef CONFIG_ARM64_PTR_AUTH
1545 [REGSET_PAC_MASK] = {
1546 .core_note_type = NT_ARM_PAC_MASK,
1547 .n = sizeof(struct user_pac_mask) / sizeof(u64),
1548 .size = sizeof(u64),
1549 .align = sizeof(u64),
1550 .regset_get = pac_mask_get,
1551 /* this cannot be set dynamically */
1553 [REGSET_PAC_ENABLED_KEYS] = {
1554 .core_note_type = NT_ARM_PAC_ENABLED_KEYS,
1556 .size = sizeof(long),
1557 .align = sizeof(long),
1558 .regset_get = pac_enabled_keys_get,
1559 .set = pac_enabled_keys_set,
1561 #ifdef CONFIG_CHECKPOINT_RESTORE
1562 [REGSET_PACA_KEYS] = {
1563 .core_note_type = NT_ARM_PACA_KEYS,
1564 .n = sizeof(struct user_pac_address_keys) / sizeof(__uint128_t),
1565 .size = sizeof(__uint128_t),
1566 .align = sizeof(__uint128_t),
1567 .regset_get = pac_address_keys_get,
1568 .set = pac_address_keys_set,
1570 [REGSET_PACG_KEYS] = {
1571 .core_note_type = NT_ARM_PACG_KEYS,
1572 .n = sizeof(struct user_pac_generic_keys) / sizeof(__uint128_t),
1573 .size = sizeof(__uint128_t),
1574 .align = sizeof(__uint128_t),
1575 .regset_get = pac_generic_keys_get,
1576 .set = pac_generic_keys_set,
1580 #ifdef CONFIG_ARM64_TAGGED_ADDR_ABI
1581 [REGSET_TAGGED_ADDR_CTRL] = {
1582 .core_note_type = NT_ARM_TAGGED_ADDR_CTRL,
1584 .size = sizeof(long),
1585 .align = sizeof(long),
1586 .regset_get = tagged_addr_ctrl_get,
1587 .set = tagged_addr_ctrl_set,
1592 static const struct user_regset_view user_aarch64_view = {
1593 .name = "aarch64", .e_machine = EM_AARCH64,
1594 .regsets = aarch64_regsets, .n = ARRAY_SIZE(aarch64_regsets)
1597 #ifdef CONFIG_COMPAT
1598 enum compat_regset {
1603 static inline compat_ulong_t compat_get_user_reg(struct task_struct *task, int idx)
1605 struct pt_regs *regs = task_pt_regs(task);
1611 return pstate_to_compat_psr(regs->pstate);
1613 return regs->orig_x0;
1615 return regs->regs[idx];
1619 static int compat_gpr_get(struct task_struct *target,
1620 const struct user_regset *regset,
1626 membuf_store(&to, compat_get_user_reg(target, i++));
1630 static int compat_gpr_set(struct task_struct *target,
1631 const struct user_regset *regset,
1632 unsigned int pos, unsigned int count,
1633 const void *kbuf, const void __user *ubuf)
1635 struct pt_regs newregs;
1637 unsigned int i, start, num_regs;
1639 /* Calculate the number of AArch32 registers contained in count */
1640 num_regs = count / regset->size;
1642 /* Convert pos into an register number */
1643 start = pos / regset->size;
1645 if (start + num_regs > regset->n)
1648 newregs = *task_pt_regs(target);
1650 for (i = 0; i < num_regs; ++i) {
1651 unsigned int idx = start + i;
1655 memcpy(®, kbuf, sizeof(reg));
1656 kbuf += sizeof(reg);
1658 ret = copy_from_user(®, ubuf, sizeof(reg));
1664 ubuf += sizeof(reg);
1672 reg = compat_psr_to_pstate(reg);
1673 newregs.pstate = reg;
1676 newregs.orig_x0 = reg;
1679 newregs.regs[idx] = reg;
1684 if (valid_user_regs(&newregs.user_regs, target))
1685 *task_pt_regs(target) = newregs;
1692 static int compat_vfp_get(struct task_struct *target,
1693 const struct user_regset *regset,
1696 struct user_fpsimd_state *uregs;
1697 compat_ulong_t fpscr;
1699 if (!system_supports_fpsimd())
1702 uregs = &target->thread.uw.fpsimd_state;
1704 if (target == current)
1705 fpsimd_preserve_current_state();
1708 * The VFP registers are packed into the fpsimd_state, so they all sit
1709 * nicely together for us. We just need to create the fpscr separately.
1711 membuf_write(&to, uregs, VFP_STATE_SIZE - sizeof(compat_ulong_t));
1712 fpscr = (uregs->fpsr & VFP_FPSCR_STAT_MASK) |
1713 (uregs->fpcr & VFP_FPSCR_CTRL_MASK);
1714 return membuf_store(&to, fpscr);
1717 static int compat_vfp_set(struct task_struct *target,
1718 const struct user_regset *regset,
1719 unsigned int pos, unsigned int count,
1720 const void *kbuf, const void __user *ubuf)
1722 struct user_fpsimd_state *uregs;
1723 compat_ulong_t fpscr;
1724 int ret, vregs_end_pos;
1726 if (!system_supports_fpsimd())
1729 uregs = &target->thread.uw.fpsimd_state;
1731 vregs_end_pos = VFP_STATE_SIZE - sizeof(compat_ulong_t);
1732 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, uregs, 0,
1735 if (count && !ret) {
1736 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &fpscr,
1737 vregs_end_pos, VFP_STATE_SIZE);
1739 uregs->fpsr = fpscr & VFP_FPSCR_STAT_MASK;
1740 uregs->fpcr = fpscr & VFP_FPSCR_CTRL_MASK;
1744 fpsimd_flush_task_state(target);
1748 static int compat_tls_get(struct task_struct *target,
1749 const struct user_regset *regset,
1752 return membuf_store(&to, (compat_ulong_t)target->thread.uw.tp_value);
1755 static int compat_tls_set(struct task_struct *target,
1756 const struct user_regset *regset, unsigned int pos,
1757 unsigned int count, const void *kbuf,
1758 const void __user *ubuf)
1761 compat_ulong_t tls = target->thread.uw.tp_value;
1763 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &tls, 0, -1);
1767 target->thread.uw.tp_value = tls;
1771 static const struct user_regset aarch32_regsets[] = {
1772 [REGSET_COMPAT_GPR] = {
1773 .core_note_type = NT_PRSTATUS,
1774 .n = COMPAT_ELF_NGREG,
1775 .size = sizeof(compat_elf_greg_t),
1776 .align = sizeof(compat_elf_greg_t),
1777 .regset_get = compat_gpr_get,
1778 .set = compat_gpr_set
1780 [REGSET_COMPAT_VFP] = {
1781 .core_note_type = NT_ARM_VFP,
1782 .n = VFP_STATE_SIZE / sizeof(compat_ulong_t),
1783 .size = sizeof(compat_ulong_t),
1784 .align = sizeof(compat_ulong_t),
1785 .active = fpr_active,
1786 .regset_get = compat_vfp_get,
1787 .set = compat_vfp_set
1791 static const struct user_regset_view user_aarch32_view = {
1792 .name = "aarch32", .e_machine = EM_ARM,
1793 .regsets = aarch32_regsets, .n = ARRAY_SIZE(aarch32_regsets)
1796 static const struct user_regset aarch32_ptrace_regsets[] = {
1798 .core_note_type = NT_PRSTATUS,
1799 .n = COMPAT_ELF_NGREG,
1800 .size = sizeof(compat_elf_greg_t),
1801 .align = sizeof(compat_elf_greg_t),
1802 .regset_get = compat_gpr_get,
1803 .set = compat_gpr_set
1806 .core_note_type = NT_ARM_VFP,
1807 .n = VFP_STATE_SIZE / sizeof(compat_ulong_t),
1808 .size = sizeof(compat_ulong_t),
1809 .align = sizeof(compat_ulong_t),
1810 .regset_get = compat_vfp_get,
1811 .set = compat_vfp_set
1814 .core_note_type = NT_ARM_TLS,
1816 .size = sizeof(compat_ulong_t),
1817 .align = sizeof(compat_ulong_t),
1818 .regset_get = compat_tls_get,
1819 .set = compat_tls_set,
1821 #ifdef CONFIG_HAVE_HW_BREAKPOINT
1822 [REGSET_HW_BREAK] = {
1823 .core_note_type = NT_ARM_HW_BREAK,
1824 .n = sizeof(struct user_hwdebug_state) / sizeof(u32),
1825 .size = sizeof(u32),
1826 .align = sizeof(u32),
1827 .regset_get = hw_break_get,
1828 .set = hw_break_set,
1830 [REGSET_HW_WATCH] = {
1831 .core_note_type = NT_ARM_HW_WATCH,
1832 .n = sizeof(struct user_hwdebug_state) / sizeof(u32),
1833 .size = sizeof(u32),
1834 .align = sizeof(u32),
1835 .regset_get = hw_break_get,
1836 .set = hw_break_set,
1839 [REGSET_SYSTEM_CALL] = {
1840 .core_note_type = NT_ARM_SYSTEM_CALL,
1842 .size = sizeof(int),
1843 .align = sizeof(int),
1844 .regset_get = system_call_get,
1845 .set = system_call_set,
1849 static const struct user_regset_view user_aarch32_ptrace_view = {
1850 .name = "aarch32", .e_machine = EM_ARM,
1851 .regsets = aarch32_ptrace_regsets, .n = ARRAY_SIZE(aarch32_ptrace_regsets)
1854 static int compat_ptrace_read_user(struct task_struct *tsk, compat_ulong_t off,
1855 compat_ulong_t __user *ret)
1862 if (off == COMPAT_PT_TEXT_ADDR)
1863 tmp = tsk->mm->start_code;
1864 else if (off == COMPAT_PT_DATA_ADDR)
1865 tmp = tsk->mm->start_data;
1866 else if (off == COMPAT_PT_TEXT_END_ADDR)
1867 tmp = tsk->mm->end_code;
1868 else if (off < sizeof(compat_elf_gregset_t))
1869 tmp = compat_get_user_reg(tsk, off >> 2);
1870 else if (off >= COMPAT_USER_SZ)
1875 return put_user(tmp, ret);
1878 static int compat_ptrace_write_user(struct task_struct *tsk, compat_ulong_t off,
1881 struct pt_regs newregs = *task_pt_regs(tsk);
1882 unsigned int idx = off / 4;
1884 if (off & 3 || off >= COMPAT_USER_SZ)
1887 if (off >= sizeof(compat_elf_gregset_t))
1895 newregs.pstate = compat_psr_to_pstate(val);
1898 newregs.orig_x0 = val;
1901 newregs.regs[idx] = val;
1904 if (!valid_user_regs(&newregs.user_regs, tsk))
1907 *task_pt_regs(tsk) = newregs;
1911 #ifdef CONFIG_HAVE_HW_BREAKPOINT
1914 * Convert a virtual register number into an index for a thread_info
1915 * breakpoint array. Breakpoints are identified using positive numbers
1916 * whilst watchpoints are negative. The registers are laid out as pairs
1917 * of (address, control), each pair mapping to a unique hw_breakpoint struct.
1918 * Register 0 is reserved for describing resource information.
1920 static int compat_ptrace_hbp_num_to_idx(compat_long_t num)
1922 return (abs(num) - 1) >> 1;
1925 static int compat_ptrace_hbp_get_resource_info(u32 *kdata)
1927 u8 num_brps, num_wrps, debug_arch, wp_len;
1930 num_brps = hw_breakpoint_slots(TYPE_INST);
1931 num_wrps = hw_breakpoint_slots(TYPE_DATA);
1933 debug_arch = debug_monitors_arch();
1947 static int compat_ptrace_hbp_get(unsigned int note_type,
1948 struct task_struct *tsk,
1955 int err, idx = compat_ptrace_hbp_num_to_idx(num);
1958 err = ptrace_hbp_get_addr(note_type, tsk, idx, &addr);
1961 err = ptrace_hbp_get_ctrl(note_type, tsk, idx, &ctrl);
1968 static int compat_ptrace_hbp_set(unsigned int note_type,
1969 struct task_struct *tsk,
1976 int err, idx = compat_ptrace_hbp_num_to_idx(num);
1980 err = ptrace_hbp_set_addr(note_type, tsk, idx, addr);
1983 err = ptrace_hbp_set_ctrl(note_type, tsk, idx, ctrl);
1989 static int compat_ptrace_gethbpregs(struct task_struct *tsk, compat_long_t num,
1990 compat_ulong_t __user *data)
1997 ret = compat_ptrace_hbp_get(NT_ARM_HW_WATCH, tsk, num, &kdata);
1999 } else if (num == 0) {
2000 ret = compat_ptrace_hbp_get_resource_info(&kdata);
2003 ret = compat_ptrace_hbp_get(NT_ARM_HW_BREAK, tsk, num, &kdata);
2007 ret = put_user(kdata, data);
2012 static int compat_ptrace_sethbpregs(struct task_struct *tsk, compat_long_t num,
2013 compat_ulong_t __user *data)
2021 ret = get_user(kdata, data);
2026 ret = compat_ptrace_hbp_set(NT_ARM_HW_WATCH, tsk, num, &kdata);
2028 ret = compat_ptrace_hbp_set(NT_ARM_HW_BREAK, tsk, num, &kdata);
2032 #endif /* CONFIG_HAVE_HW_BREAKPOINT */
2034 long compat_arch_ptrace(struct task_struct *child, compat_long_t request,
2035 compat_ulong_t caddr, compat_ulong_t cdata)
2037 unsigned long addr = caddr;
2038 unsigned long data = cdata;
2039 void __user *datap = compat_ptr(data);
2043 case PTRACE_PEEKUSR:
2044 ret = compat_ptrace_read_user(child, addr, datap);
2047 case PTRACE_POKEUSR:
2048 ret = compat_ptrace_write_user(child, addr, data);
2051 case COMPAT_PTRACE_GETREGS:
2052 ret = copy_regset_to_user(child,
2055 0, sizeof(compat_elf_gregset_t),
2059 case COMPAT_PTRACE_SETREGS:
2060 ret = copy_regset_from_user(child,
2063 0, sizeof(compat_elf_gregset_t),
2067 case COMPAT_PTRACE_GET_THREAD_AREA:
2068 ret = put_user((compat_ulong_t)child->thread.uw.tp_value,
2069 (compat_ulong_t __user *)datap);
2072 case COMPAT_PTRACE_SET_SYSCALL:
2073 task_pt_regs(child)->syscallno = data;
2077 case COMPAT_PTRACE_GETVFPREGS:
2078 ret = copy_regset_to_user(child,
2085 case COMPAT_PTRACE_SETVFPREGS:
2086 ret = copy_regset_from_user(child,
2093 #ifdef CONFIG_HAVE_HW_BREAKPOINT
2094 case COMPAT_PTRACE_GETHBPREGS:
2095 ret = compat_ptrace_gethbpregs(child, addr, datap);
2098 case COMPAT_PTRACE_SETHBPREGS:
2099 ret = compat_ptrace_sethbpregs(child, addr, datap);
2104 ret = compat_ptrace_request(child, request, addr,
2111 #endif /* CONFIG_COMPAT */
2113 const struct user_regset_view *task_user_regset_view(struct task_struct *task)
2115 #ifdef CONFIG_COMPAT
2117 * Core dumping of 32-bit tasks or compat ptrace requests must use the
2118 * user_aarch32_view compatible with arm32. Native ptrace requests on
2119 * 32-bit children use an extended user_aarch32_ptrace_view to allow
2120 * access to the TLS register.
2122 if (is_compat_task())
2123 return &user_aarch32_view;
2124 else if (is_compat_thread(task_thread_info(task)))
2125 return &user_aarch32_ptrace_view;
2127 return &user_aarch64_view;
2130 long arch_ptrace(struct task_struct *child, long request,
2131 unsigned long addr, unsigned long data)
2134 case PTRACE_PEEKMTETAGS:
2135 case PTRACE_POKEMTETAGS:
2136 return mte_ptrace_copy_tags(child, request, addr, data);
2139 return ptrace_request(child, request, addr, data);
2142 enum ptrace_syscall_dir {
2143 PTRACE_SYSCALL_ENTER = 0,
2144 PTRACE_SYSCALL_EXIT,
2147 static void report_syscall(struct pt_regs *regs, enum ptrace_syscall_dir dir)
2150 unsigned long saved_reg;
2153 * We have some ABI weirdness here in the way that we handle syscall
2154 * exit stops because we indicate whether or not the stop has been
2155 * signalled from syscall entry or syscall exit by clobbering a general
2156 * purpose register (ip/r12 for AArch32, x7 for AArch64) in the tracee
2157 * and restoring its old value after the stop. This means that:
2159 * - Any writes by the tracer to this register during the stop are
2160 * ignored/discarded.
2162 * - The actual value of the register is not available during the stop,
2163 * so the tracer cannot save it and restore it later.
2165 * - Syscall stops behave differently to seccomp and pseudo-step traps
2166 * (the latter do not nobble any registers).
2168 regno = (is_compat_task() ? 12 : 7);
2169 saved_reg = regs->regs[regno];
2170 regs->regs[regno] = dir;
2172 if (dir == PTRACE_SYSCALL_ENTER) {
2173 if (ptrace_report_syscall_entry(regs))
2174 forget_syscall(regs);
2175 regs->regs[regno] = saved_reg;
2176 } else if (!test_thread_flag(TIF_SINGLESTEP)) {
2177 ptrace_report_syscall_exit(regs, 0);
2178 regs->regs[regno] = saved_reg;
2180 regs->regs[regno] = saved_reg;
2183 * Signal a pseudo-step exception since we are stepping but
2184 * tracer modifications to the registers may have rewound the
2187 ptrace_report_syscall_exit(regs, 1);
2191 int syscall_trace_enter(struct pt_regs *regs)
2193 unsigned long flags = read_thread_flags();
2195 if (flags & (_TIF_SYSCALL_EMU | _TIF_SYSCALL_TRACE)) {
2196 report_syscall(regs, PTRACE_SYSCALL_ENTER);
2197 if (flags & _TIF_SYSCALL_EMU)
2201 /* Do the secure computing after ptrace; failures should be fast. */
2202 if (secure_computing() == -1)
2205 if (test_thread_flag(TIF_SYSCALL_TRACEPOINT))
2206 trace_sys_enter(regs, regs->syscallno);
2208 audit_syscall_entry(regs->syscallno, regs->orig_x0, regs->regs[1],
2209 regs->regs[2], regs->regs[3]);
2211 return regs->syscallno;
2214 void syscall_trace_exit(struct pt_regs *regs)
2216 unsigned long flags = read_thread_flags();
2218 audit_syscall_exit(regs);
2220 if (flags & _TIF_SYSCALL_TRACEPOINT)
2221 trace_sys_exit(regs, syscall_get_return_value(current, regs));
2223 if (flags & (_TIF_SYSCALL_TRACE | _TIF_SINGLESTEP))
2224 report_syscall(regs, PTRACE_SYSCALL_EXIT);
2230 * SPSR_ELx bits which are always architecturally RES0 per ARM DDI 0487D.a.
2231 * We permit userspace to set SSBS (AArch64 bit 12, AArch32 bit 23) which is
2232 * not described in ARM DDI 0487D.a.
2233 * We treat PAN and UAO as RES0 bits, as they are meaningless at EL0, and may
2234 * be allocated an EL0 meaning in future.
2235 * Userspace cannot use these until they have an architectural meaning.
2236 * Note that this follows the SPSR_ELx format, not the AArch32 PSR format.
2237 * We also reserve IL for the kernel; SS is handled dynamically.
2239 #define SPSR_EL1_AARCH64_RES0_BITS \
2240 (GENMASK_ULL(63, 32) | GENMASK_ULL(27, 26) | GENMASK_ULL(23, 22) | \
2241 GENMASK_ULL(20, 13) | GENMASK_ULL(5, 5))
2242 #define SPSR_EL1_AARCH32_RES0_BITS \
2243 (GENMASK_ULL(63, 32) | GENMASK_ULL(22, 22) | GENMASK_ULL(20, 20))
2245 static int valid_compat_regs(struct user_pt_regs *regs)
2247 regs->pstate &= ~SPSR_EL1_AARCH32_RES0_BITS;
2249 if (!system_supports_mixed_endian_el0()) {
2250 if (IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
2251 regs->pstate |= PSR_AA32_E_BIT;
2253 regs->pstate &= ~PSR_AA32_E_BIT;
2256 if (user_mode(regs) && (regs->pstate & PSR_MODE32_BIT) &&
2257 (regs->pstate & PSR_AA32_A_BIT) == 0 &&
2258 (regs->pstate & PSR_AA32_I_BIT) == 0 &&
2259 (regs->pstate & PSR_AA32_F_BIT) == 0) {
2264 * Force PSR to a valid 32-bit EL0t, preserving the same bits as
2267 regs->pstate &= PSR_AA32_N_BIT | PSR_AA32_Z_BIT |
2268 PSR_AA32_C_BIT | PSR_AA32_V_BIT |
2269 PSR_AA32_Q_BIT | PSR_AA32_IT_MASK |
2270 PSR_AA32_GE_MASK | PSR_AA32_E_BIT |
2272 regs->pstate |= PSR_MODE32_BIT;
2277 static int valid_native_regs(struct user_pt_regs *regs)
2279 regs->pstate &= ~SPSR_EL1_AARCH64_RES0_BITS;
2281 if (user_mode(regs) && !(regs->pstate & PSR_MODE32_BIT) &&
2282 (regs->pstate & PSR_D_BIT) == 0 &&
2283 (regs->pstate & PSR_A_BIT) == 0 &&
2284 (regs->pstate & PSR_I_BIT) == 0 &&
2285 (regs->pstate & PSR_F_BIT) == 0) {
2289 /* Force PSR to a valid 64-bit EL0t */
2290 regs->pstate &= PSR_N_BIT | PSR_Z_BIT | PSR_C_BIT | PSR_V_BIT;
2296 * Are the current registers suitable for user mode? (used to maintain
2297 * security in signal handlers)
2299 int valid_user_regs(struct user_pt_regs *regs, struct task_struct *task)
2301 /* https://lore.kernel.org/lkml/20191118131525.GA4180@willie-the-truck */
2302 user_regs_reset_single_step(regs, task);
2304 if (is_compat_thread(task_thread_info(task)))
2305 return valid_compat_regs(regs);
2307 return valid_native_regs(regs);