1 // SPDX-License-Identifier: GPL-2.0-only
3 * arch/arm64/kernel/probes/simulate-insn.c
5 * Copyright (C) 2013 Linaro Limited.
8 #include <linux/bitops.h>
9 #include <linux/kernel.h>
10 #include <linux/kprobes.h>
12 #include <asm/ptrace.h>
13 #include <asm/traps.h>
15 #include "simulate-insn.h"
17 #define bbl_displacement(insn) \
18 sign_extend32(((insn) & 0x3ffffff) << 2, 27)
20 #define bcond_displacement(insn) \
21 sign_extend32(((insn >> 5) & 0x7ffff) << 2, 20)
23 #define cbz_displacement(insn) \
24 sign_extend32(((insn >> 5) & 0x7ffff) << 2, 20)
26 #define tbz_displacement(insn) \
27 sign_extend32(((insn >> 5) & 0x3fff) << 2, 15)
29 #define ldr_displacement(insn) \
30 sign_extend32(((insn >> 5) & 0x7ffff) << 2, 20)
32 static inline void set_x_reg(struct pt_regs *regs, int reg, u64 val)
34 pt_regs_write_reg(regs, reg, val);
37 static inline void set_w_reg(struct pt_regs *regs, int reg, u64 val)
39 pt_regs_write_reg(regs, reg, lower_32_bits(val));
42 static inline u64 get_x_reg(struct pt_regs *regs, int reg)
44 return pt_regs_read_reg(regs, reg);
47 static inline u32 get_w_reg(struct pt_regs *regs, int reg)
49 return lower_32_bits(pt_regs_read_reg(regs, reg));
52 static bool __kprobes check_cbz(u32 opcode, struct pt_regs *regs)
54 int xn = opcode & 0x1f;
56 return (opcode & (1 << 31)) ?
57 (get_x_reg(regs, xn) == 0) : (get_w_reg(regs, xn) == 0);
60 static bool __kprobes check_cbnz(u32 opcode, struct pt_regs *regs)
62 int xn = opcode & 0x1f;
64 return (opcode & (1 << 31)) ?
65 (get_x_reg(regs, xn) != 0) : (get_w_reg(regs, xn) != 0);
68 static bool __kprobes check_tbz(u32 opcode, struct pt_regs *regs)
70 int xn = opcode & 0x1f;
71 int bit_pos = ((opcode & (1 << 31)) >> 26) | ((opcode >> 19) & 0x1f);
73 return ((get_x_reg(regs, xn) >> bit_pos) & 0x1) == 0;
76 static bool __kprobes check_tbnz(u32 opcode, struct pt_regs *regs)
78 int xn = opcode & 0x1f;
79 int bit_pos = ((opcode & (1 << 31)) >> 26) | ((opcode >> 19) & 0x1f);
81 return ((get_x_reg(regs, xn) >> bit_pos) & 0x1) != 0;
85 * instruction simulation functions
88 simulate_adr_adrp(u32 opcode, long addr, struct pt_regs *regs)
93 imm = ((opcode >> 3) & 0x1ffffc) | ((opcode >> 29) & 0x3);
94 imm = sign_extend64(imm, 20);
95 if (opcode & 0x80000000)
96 val = (imm<<12) + (addr & 0xfffffffffffff000);
100 set_x_reg(regs, xn, val);
102 instruction_pointer_set(regs, instruction_pointer(regs) + 4);
106 simulate_b_bl(u32 opcode, long addr, struct pt_regs *regs)
108 int disp = bbl_displacement(opcode);
110 /* Link register is x30 */
111 if (opcode & (1 << 31))
112 set_x_reg(regs, 30, addr + 4);
114 instruction_pointer_set(regs, addr + disp);
118 simulate_b_cond(u32 opcode, long addr, struct pt_regs *regs)
122 if (aarch32_opcode_cond_checks[opcode & 0xf](regs->pstate & 0xffffffff))
123 disp = bcond_displacement(opcode);
125 instruction_pointer_set(regs, addr + disp);
129 simulate_br_blr_ret(u32 opcode, long addr, struct pt_regs *regs)
131 int xn = (opcode >> 5) & 0x1f;
133 /* update pc first in case we're doing a "blr lr" */
134 instruction_pointer_set(regs, get_x_reg(regs, xn));
136 /* Link register is x30 */
137 if (((opcode >> 21) & 0x3) == 1)
138 set_x_reg(regs, 30, addr + 4);
142 simulate_cbz_cbnz(u32 opcode, long addr, struct pt_regs *regs)
146 if (opcode & (1 << 24)) {
147 if (check_cbnz(opcode, regs))
148 disp = cbz_displacement(opcode);
150 if (check_cbz(opcode, regs))
151 disp = cbz_displacement(opcode);
153 instruction_pointer_set(regs, addr + disp);
157 simulate_tbz_tbnz(u32 opcode, long addr, struct pt_regs *regs)
161 if (opcode & (1 << 24)) {
162 if (check_tbnz(opcode, regs))
163 disp = tbz_displacement(opcode);
165 if (check_tbz(opcode, regs))
166 disp = tbz_displacement(opcode);
168 instruction_pointer_set(regs, addr + disp);
172 simulate_ldr_literal(u32 opcode, long addr, struct pt_regs *regs)
175 int xn = opcode & 0x1f;
178 disp = ldr_displacement(opcode);
179 load_addr = (u64 *) (addr + disp);
181 if (opcode & (1 << 30)) /* x0-x30 */
182 set_x_reg(regs, xn, *load_addr);
184 set_w_reg(regs, xn, *load_addr);
186 instruction_pointer_set(regs, instruction_pointer(regs) + 4);
190 simulate_ldrsw_literal(u32 opcode, long addr, struct pt_regs *regs)
193 int xn = opcode & 0x1f;
196 disp = ldr_displacement(opcode);
197 load_addr = (s32 *) (addr + disp);
199 set_x_reg(regs, xn, *load_addr);
201 instruction_pointer_set(regs, instruction_pointer(regs) + 4);