arch/arm64/kernel/perf_event.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * ARMv8 PMUv3 Performance Events handling code.
   4  *
   5  * Copyright (C) 2012 ARM Limited
   6  * Author: Will Deacon <will.deacon@arm.com>
   7  *
   8  * This code is based heavily on the ARMv7 perf event code.
   9  */
  10
  11 #include <asm/irq_regs.h>
  12 #include <asm/perf_event.h>
  13 #include <asm/sysreg.h>
  14 #include <asm/virt.h>
  15
  16 #include <clocksource/arm_arch_timer.h>
  17
  18 #include <linux/acpi.h>
  19 #include <linux/clocksource.h>
  20 #include <linux/kvm_host.h>
  21 #include <linux/of.h>
  22 #include <linux/perf/arm_pmu.h>
  23 #include <linux/platform_device.h>
  24 #include <linux/sched_clock.h>
  25 #include <linux/smp.h>
  26
  27 /* ARMv8 Cortex-A53 specific event types. */
  28 #define ARMV8_A53_PERFCTR_PREF_LINEFILL                         0xC2
  29
  30 /* ARMv8 Cavium ThunderX specific event types. */
  31 #define ARMV8_THUNDER_PERFCTR_L1D_CACHE_MISS_ST                 0xE9
  32 #define ARMV8_THUNDER_PERFCTR_L1D_CACHE_PREF_ACCESS             0xEA
  33 #define ARMV8_THUNDER_PERFCTR_L1D_CACHE_PREF_MISS               0xEB
  34 #define ARMV8_THUNDER_PERFCTR_L1I_CACHE_PREF_ACCESS             0xEC
  35 #define ARMV8_THUNDER_PERFCTR_L1I_CACHE_PREF_MISS               0xED
  36
  37 /*
  38  * ARMv8 Architectural defined events, not all of these may
  39  * be supported on any given implementation. Unsupported events will
  40  * be disabled at run-time based on the PMCEID registers.
  41  */
  42 static const unsigned armv8_pmuv3_perf_map[PERF_COUNT_HW_MAX] = {
  43         PERF_MAP_ALL_UNSUPPORTED,
  44         [PERF_COUNT_HW_CPU_CYCLES]              = ARMV8_PMUV3_PERFCTR_CPU_CYCLES,
  45         [PERF_COUNT_HW_INSTRUCTIONS]            = ARMV8_PMUV3_PERFCTR_INST_RETIRED,
  46         [PERF_COUNT_HW_CACHE_REFERENCES]        = ARMV8_PMUV3_PERFCTR_L1D_CACHE,
  47         [PERF_COUNT_HW_CACHE_MISSES]            = ARMV8_PMUV3_PERFCTR_L1D_CACHE_REFILL,
  48         [PERF_COUNT_HW_BRANCH_INSTRUCTIONS]     = ARMV8_PMUV3_PERFCTR_PC_WRITE_RETIRED,
  49         [PERF_COUNT_HW_BRANCH_MISSES]           = ARMV8_PMUV3_PERFCTR_BR_MIS_PRED,
  50         [PERF_COUNT_HW_BUS_CYCLES]              = ARMV8_PMUV3_PERFCTR_BUS_CYCLES,
  51         [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = ARMV8_PMUV3_PERFCTR_STALL_FRONTEND,
  52         [PERF_COUNT_HW_STALLED_CYCLES_BACKEND]  = ARMV8_PMUV3_PERFCTR_STALL_BACKEND,
  53 };
  54
  55 static const unsigned armv8_pmuv3_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
  56                                                 [PERF_COUNT_HW_CACHE_OP_MAX]
  57                                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
  58         PERF_CACHE_MAP_ALL_UNSUPPORTED,
  59
  60         [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)]  = ARMV8_PMUV3_PERFCTR_L1D_CACHE,
  61         [C(L1D)][C(OP_READ)][C(RESULT_MISS)]    = ARMV8_PMUV3_PERFCTR_L1D_CACHE_REFILL,
  62
  63         [C(L1I)][C(OP_READ)][C(RESULT_ACCESS)]  = ARMV8_PMUV3_PERFCTR_L1I_CACHE,
  64         [C(L1I)][C(OP_READ)][C(RESULT_MISS)]    = ARMV8_PMUV3_PERFCTR_L1I_CACHE_REFILL,
  65
  66         [C(DTLB)][C(OP_READ)][C(RESULT_MISS)]   = ARMV8_PMUV3_PERFCTR_L1D_TLB_REFILL,
  67         [C(DTLB)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L1D_TLB,
  68
  69         [C(ITLB)][C(OP_READ)][C(RESULT_MISS)]   = ARMV8_PMUV3_PERFCTR_L1I_TLB_REFILL,
  70         [C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L1I_TLB,
  71
  72         [C(LL)][C(OP_READ)][C(RESULT_MISS)]     = ARMV8_PMUV3_PERFCTR_LL_CACHE_MISS_RD,
  73         [C(LL)][C(OP_READ)][C(RESULT_ACCESS)]   = ARMV8_PMUV3_PERFCTR_LL_CACHE_RD,
  74
  75         [C(BPU)][C(OP_READ)][C(RESULT_ACCESS)]  = ARMV8_PMUV3_PERFCTR_BR_PRED,
  76         [C(BPU)][C(OP_READ)][C(RESULT_MISS)]    = ARMV8_PMUV3_PERFCTR_BR_MIS_PRED,
  77 };
  78
  79 static const unsigned armv8_a53_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
  80                                               [PERF_COUNT_HW_CACHE_OP_MAX]
  81                                               [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
  82         PERF_CACHE_MAP_ALL_UNSUPPORTED,
  83
  84         [C(L1D)][C(OP_PREFETCH)][C(RESULT_MISS)] = ARMV8_A53_PERFCTR_PREF_LINEFILL,
  85
  86         [C(NODE)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_RD,
  87         [C(NODE)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_WR,
  88 };
  89
  90 static const unsigned armv8_a57_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
  91                                               [PERF_COUNT_HW_CACHE_OP_MAX]
  92                                               [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
  93         PERF_CACHE_MAP_ALL_UNSUPPORTED,
  94
  95         [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)]  = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_RD,
  96         [C(L1D)][C(OP_READ)][C(RESULT_MISS)]    = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_RD,
  97         [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_WR,
  98         [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)]   = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_WR,
  99
 100         [C(DTLB)][C(OP_READ)][C(RESULT_MISS)]   = ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_RD,
 101         [C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)]  = ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_WR,
 102
 103         [C(NODE)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_RD,
 104         [C(NODE)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_WR,
 105 };
 106
 107 static const unsigned armv8_a73_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
 108                                               [PERF_COUNT_HW_CACHE_OP_MAX]
 109                                               [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
 110         PERF_CACHE_MAP_ALL_UNSUPPORTED,
 111
 112         [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)]  = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_RD,
 113         [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_WR,
 114 };
 115
 116 static const unsigned armv8_thunder_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
 117                                                    [PERF_COUNT_HW_CACHE_OP_MAX]
 118                                                    [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
 119         PERF_CACHE_MAP_ALL_UNSUPPORTED,
 120
 121         [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)]  = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_RD,
 122         [C(L1D)][C(OP_READ)][C(RESULT_MISS)]    = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_RD,
 123         [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_WR,
 124         [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)]   = ARMV8_THUNDER_PERFCTR_L1D_CACHE_MISS_ST,
 125         [C(L1D)][C(OP_PREFETCH)][C(RESULT_ACCESS)] = ARMV8_THUNDER_PERFCTR_L1D_CACHE_PREF_ACCESS,
 126         [C(L1D)][C(OP_PREFETCH)][C(RESULT_MISS)] = ARMV8_THUNDER_PERFCTR_L1D_CACHE_PREF_MISS,
 127
 128         [C(L1I)][C(OP_PREFETCH)][C(RESULT_ACCESS)] = ARMV8_THUNDER_PERFCTR_L1I_CACHE_PREF_ACCESS,
 129         [C(L1I)][C(OP_PREFETCH)][C(RESULT_MISS)] = ARMV8_THUNDER_PERFCTR_L1I_CACHE_PREF_MISS,
 130
 131         [C(DTLB)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_RD,
 132         [C(DTLB)][C(OP_READ)][C(RESULT_MISS)]   = ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_RD,
 133         [C(DTLB)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_WR,
 134         [C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)]  = ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_WR,
 135 };
 136
 137 static const unsigned armv8_vulcan_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
 138                                               [PERF_COUNT_HW_CACHE_OP_MAX]
 139                                               [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
 140         PERF_CACHE_MAP_ALL_UNSUPPORTED,
 141
 142         [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)]  = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_RD,
 143         [C(L1D)][C(OP_READ)][C(RESULT_MISS)]    = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_RD,
 144         [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_WR,
 145         [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)]   = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_WR,
 146
 147         [C(DTLB)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_RD,
 148         [C(DTLB)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_WR,
 149         [C(DTLB)][C(OP_READ)][C(RESULT_MISS)]   = ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_RD,
 150         [C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)]  = ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_WR,
 151
 152         [C(NODE)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_RD,
 153         [C(NODE)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_WR,
 154 };
 155
 156 static ssize_t
 157 armv8pmu_events_sysfs_show(struct device *dev,
 158                            struct device_attribute *attr, char *page)
 159 {
 160         struct perf_pmu_events_attr *pmu_attr;
 161
 162         pmu_attr = container_of(attr, struct perf_pmu_events_attr, attr);
 163
 164         return sprintf(page, "event=0x%04llx\n", pmu_attr->id);
 165 }
 166
 167 #define ARMV8_EVENT_ATTR(name, config)                                          \
 168         (&((struct perf_pmu_events_attr) {                                      \
 169                 .attr = __ATTR(name, 0444, armv8pmu_events_sysfs_show, NULL),   \
 170                 .id = config,                                                   \
 171         }).attr.attr)
 172
 173 static struct attribute *armv8_pmuv3_event_attrs[] = {
 174         /*
 175          * Don't expose the sw_incr event in /sys. It's not usable as writes to
 176          * PMSWINC_EL0 will trap as PMUSERENR.{SW,EN}=={0,0} and event rotation
 177          * means we don't have a fixed event<->counter relationship regardless.
 178          */
 179         ARMV8_EVENT_ATTR(l1i_cache_refill, ARMV8_PMUV3_PERFCTR_L1I_CACHE_REFILL),
 180         ARMV8_EVENT_ATTR(l1i_tlb_refill, ARMV8_PMUV3_PERFCTR_L1I_TLB_REFILL),
 181         ARMV8_EVENT_ATTR(l1d_cache_refill, ARMV8_PMUV3_PERFCTR_L1D_CACHE_REFILL),
 182         ARMV8_EVENT_ATTR(l1d_cache, ARMV8_PMUV3_PERFCTR_L1D_CACHE),
 183         ARMV8_EVENT_ATTR(l1d_tlb_refill, ARMV8_PMUV3_PERFCTR_L1D_TLB_REFILL),
 184         ARMV8_EVENT_ATTR(ld_retired, ARMV8_PMUV3_PERFCTR_LD_RETIRED),
 185         ARMV8_EVENT_ATTR(st_retired, ARMV8_PMUV3_PERFCTR_ST_RETIRED),
 186         ARMV8_EVENT_ATTR(inst_retired, ARMV8_PMUV3_PERFCTR_INST_RETIRED),
 187         ARMV8_EVENT_ATTR(exc_taken, ARMV8_PMUV3_PERFCTR_EXC_TAKEN),
 188         ARMV8_EVENT_ATTR(exc_return, ARMV8_PMUV3_PERFCTR_EXC_RETURN),
 189         ARMV8_EVENT_ATTR(cid_write_retired, ARMV8_PMUV3_PERFCTR_CID_WRITE_RETIRED),
 190         ARMV8_EVENT_ATTR(pc_write_retired, ARMV8_PMUV3_PERFCTR_PC_WRITE_RETIRED),
 191         ARMV8_EVENT_ATTR(br_immed_retired, ARMV8_PMUV3_PERFCTR_BR_IMMED_RETIRED),
 192         ARMV8_EVENT_ATTR(br_return_retired, ARMV8_PMUV3_PERFCTR_BR_RETURN_RETIRED),
 193         ARMV8_EVENT_ATTR(unaligned_ldst_retired, ARMV8_PMUV3_PERFCTR_UNALIGNED_LDST_RETIRED),
 194         ARMV8_EVENT_ATTR(br_mis_pred, ARMV8_PMUV3_PERFCTR_BR_MIS_PRED),
 195         ARMV8_EVENT_ATTR(cpu_cycles, ARMV8_PMUV3_PERFCTR_CPU_CYCLES),
 196         ARMV8_EVENT_ATTR(br_pred, ARMV8_PMUV3_PERFCTR_BR_PRED),
 197         ARMV8_EVENT_ATTR(mem_access, ARMV8_PMUV3_PERFCTR_MEM_ACCESS),
 198         ARMV8_EVENT_ATTR(l1i_cache, ARMV8_PMUV3_PERFCTR_L1I_CACHE),
 199         ARMV8_EVENT_ATTR(l1d_cache_wb, ARMV8_PMUV3_PERFCTR_L1D_CACHE_WB),
 200         ARMV8_EVENT_ATTR(l2d_cache, ARMV8_PMUV3_PERFCTR_L2D_CACHE),
 201         ARMV8_EVENT_ATTR(l2d_cache_refill, ARMV8_PMUV3_PERFCTR_L2D_CACHE_REFILL),
 202         ARMV8_EVENT_ATTR(l2d_cache_wb, ARMV8_PMUV3_PERFCTR_L2D_CACHE_WB),
 203         ARMV8_EVENT_ATTR(bus_access, ARMV8_PMUV3_PERFCTR_BUS_ACCESS),
 204         ARMV8_EVENT_ATTR(memory_error, ARMV8_PMUV3_PERFCTR_MEMORY_ERROR),
 205         ARMV8_EVENT_ATTR(inst_spec, ARMV8_PMUV3_PERFCTR_INST_SPEC),
 206         ARMV8_EVENT_ATTR(ttbr_write_retired, ARMV8_PMUV3_PERFCTR_TTBR_WRITE_RETIRED),
 207         ARMV8_EVENT_ATTR(bus_cycles, ARMV8_PMUV3_PERFCTR_BUS_CYCLES),
 208         /* Don't expose the chain event in /sys, since it's useless in isolation */
 209         ARMV8_EVENT_ATTR(l1d_cache_allocate, ARMV8_PMUV3_PERFCTR_L1D_CACHE_ALLOCATE),
 210         ARMV8_EVENT_ATTR(l2d_cache_allocate, ARMV8_PMUV3_PERFCTR_L2D_CACHE_ALLOCATE),
 211         ARMV8_EVENT_ATTR(br_retired, ARMV8_PMUV3_PERFCTR_BR_RETIRED),
 212         ARMV8_EVENT_ATTR(br_mis_pred_retired, ARMV8_PMUV3_PERFCTR_BR_MIS_PRED_RETIRED),
 213         ARMV8_EVENT_ATTR(stall_frontend, ARMV8_PMUV3_PERFCTR_STALL_FRONTEND),
 214         ARMV8_EVENT_ATTR(stall_backend, ARMV8_PMUV3_PERFCTR_STALL_BACKEND),
 215         ARMV8_EVENT_ATTR(l1d_tlb, ARMV8_PMUV3_PERFCTR_L1D_TLB),
 216         ARMV8_EVENT_ATTR(l1i_tlb, ARMV8_PMUV3_PERFCTR_L1I_TLB),
 217         ARMV8_EVENT_ATTR(l2i_cache, ARMV8_PMUV3_PERFCTR_L2I_CACHE),
 218         ARMV8_EVENT_ATTR(l2i_cache_refill, ARMV8_PMUV3_PERFCTR_L2I_CACHE_REFILL),
 219         ARMV8_EVENT_ATTR(l3d_cache_allocate, ARMV8_PMUV3_PERFCTR_L3D_CACHE_ALLOCATE),
 220         ARMV8_EVENT_ATTR(l3d_cache_refill, ARMV8_PMUV3_PERFCTR_L3D_CACHE_REFILL),
 221         ARMV8_EVENT_ATTR(l3d_cache, ARMV8_PMUV3_PERFCTR_L3D_CACHE),
 222         ARMV8_EVENT_ATTR(l3d_cache_wb, ARMV8_PMUV3_PERFCTR_L3D_CACHE_WB),
 223         ARMV8_EVENT_ATTR(l2d_tlb_refill, ARMV8_PMUV3_PERFCTR_L2D_TLB_REFILL),
 224         ARMV8_EVENT_ATTR(l2i_tlb_refill, ARMV8_PMUV3_PERFCTR_L2I_TLB_REFILL),
 225         ARMV8_EVENT_ATTR(l2d_tlb, ARMV8_PMUV3_PERFCTR_L2D_TLB),
 226         ARMV8_EVENT_ATTR(l2i_tlb, ARMV8_PMUV3_PERFCTR_L2I_TLB),
 227         ARMV8_EVENT_ATTR(remote_access, ARMV8_PMUV3_PERFCTR_REMOTE_ACCESS),
 228         ARMV8_EVENT_ATTR(ll_cache, ARMV8_PMUV3_PERFCTR_LL_CACHE),
 229         ARMV8_EVENT_ATTR(ll_cache_miss, ARMV8_PMUV3_PERFCTR_LL_CACHE_MISS),
 230         ARMV8_EVENT_ATTR(dtlb_walk, ARMV8_PMUV3_PERFCTR_DTLB_WALK),
 231         ARMV8_EVENT_ATTR(itlb_walk, ARMV8_PMUV3_PERFCTR_ITLB_WALK),
 232         ARMV8_EVENT_ATTR(ll_cache_rd, ARMV8_PMUV3_PERFCTR_LL_CACHE_RD),
 233         ARMV8_EVENT_ATTR(ll_cache_miss_rd, ARMV8_PMUV3_PERFCTR_LL_CACHE_MISS_RD),
 234         ARMV8_EVENT_ATTR(remote_access_rd, ARMV8_PMUV3_PERFCTR_REMOTE_ACCESS_RD),
 235         ARMV8_EVENT_ATTR(l1d_cache_lmiss_rd, ARMV8_PMUV3_PERFCTR_L1D_CACHE_LMISS_RD),
 236         ARMV8_EVENT_ATTR(op_retired, ARMV8_PMUV3_PERFCTR_OP_RETIRED),
 237         ARMV8_EVENT_ATTR(op_spec, ARMV8_PMUV3_PERFCTR_OP_SPEC),
 238         ARMV8_EVENT_ATTR(stall, ARMV8_PMUV3_PERFCTR_STALL),
 239         ARMV8_EVENT_ATTR(stall_slot_backend, ARMV8_PMUV3_PERFCTR_STALL_SLOT_BACKEND),
 240         ARMV8_EVENT_ATTR(stall_slot_frontend, ARMV8_PMUV3_PERFCTR_STALL_SLOT_FRONTEND),
 241         ARMV8_EVENT_ATTR(stall_slot, ARMV8_PMUV3_PERFCTR_STALL_SLOT),
 242         ARMV8_EVENT_ATTR(sample_pop, ARMV8_SPE_PERFCTR_SAMPLE_POP),
 243         ARMV8_EVENT_ATTR(sample_feed, ARMV8_SPE_PERFCTR_SAMPLE_FEED),
 244         ARMV8_EVENT_ATTR(sample_filtrate, ARMV8_SPE_PERFCTR_SAMPLE_FILTRATE),
 245         ARMV8_EVENT_ATTR(sample_collision, ARMV8_SPE_PERFCTR_SAMPLE_COLLISION),
 246         ARMV8_EVENT_ATTR(cnt_cycles, ARMV8_AMU_PERFCTR_CNT_CYCLES),
 247         ARMV8_EVENT_ATTR(stall_backend_mem, ARMV8_AMU_PERFCTR_STALL_BACKEND_MEM),
 248         ARMV8_EVENT_ATTR(l1i_cache_lmiss, ARMV8_PMUV3_PERFCTR_L1I_CACHE_LMISS),
 249         ARMV8_EVENT_ATTR(l2d_cache_lmiss_rd, ARMV8_PMUV3_PERFCTR_L2D_CACHE_LMISS_RD),
 250         ARMV8_EVENT_ATTR(l2i_cache_lmiss, ARMV8_PMUV3_PERFCTR_L2I_CACHE_LMISS),
 251         ARMV8_EVENT_ATTR(l3d_cache_lmiss_rd, ARMV8_PMUV3_PERFCTR_L3D_CACHE_LMISS_RD),
 252         ARMV8_EVENT_ATTR(ldst_align_lat, ARMV8_PMUV3_PERFCTR_LDST_ALIGN_LAT),
 253         ARMV8_EVENT_ATTR(ld_align_lat, ARMV8_PMUV3_PERFCTR_LD_ALIGN_LAT),
 254         ARMV8_EVENT_ATTR(st_align_lat, ARMV8_PMUV3_PERFCTR_ST_ALIGN_LAT),
 255         ARMV8_EVENT_ATTR(mem_access_checked, ARMV8_MTE_PERFCTR_MEM_ACCESS_CHECKED),
 256         ARMV8_EVENT_ATTR(mem_access_checked_rd, ARMV8_MTE_PERFCTR_MEM_ACCESS_CHECKED_RD),
 257         ARMV8_EVENT_ATTR(mem_access_checked_wr, ARMV8_MTE_PERFCTR_MEM_ACCESS_CHECKED_WR),
 258         NULL,
 259 };
 260
 261 static umode_t
 262 armv8pmu_event_attr_is_visible(struct kobject *kobj,
 263                                struct attribute *attr, int unused)
 264 {
 265         struct device *dev = kobj_to_dev(kobj);
 266         struct pmu *pmu = dev_get_drvdata(dev);
 267         struct arm_pmu *cpu_pmu = container_of(pmu, struct arm_pmu, pmu);
 268         struct perf_pmu_events_attr *pmu_attr;
 269
 270         pmu_attr = container_of(attr, struct perf_pmu_events_attr, attr.attr);
 271
 272         if (pmu_attr->id < ARMV8_PMUV3_MAX_COMMON_EVENTS &&
 273             test_bit(pmu_attr->id, cpu_pmu->pmceid_bitmap))
 274                 return attr->mode;
 275
 276         if (pmu_attr->id >= ARMV8_PMUV3_EXT_COMMON_EVENT_BASE) {
 277                 u64 id = pmu_attr->id - ARMV8_PMUV3_EXT_COMMON_EVENT_BASE;
 278
 279                 if (id < ARMV8_PMUV3_MAX_COMMON_EVENTS &&
 280                     test_bit(id, cpu_pmu->pmceid_ext_bitmap))
 281                         return attr->mode;
 282         }
 283
 284         return 0;
 285 }
 286
 287 static struct attribute_group armv8_pmuv3_events_attr_group = {
 288         .name = "events",
 289         .attrs = armv8_pmuv3_event_attrs,
 290         .is_visible = armv8pmu_event_attr_is_visible,
 291 };
 292
 293 PMU_FORMAT_ATTR(event, "config:0-15");
 294 PMU_FORMAT_ATTR(long, "config1:0");
 295
 296 static inline bool armv8pmu_event_is_64bit(struct perf_event *event)
 297 {
 298         return event->attr.config1 & 0x1;
 299 }
 300
 301 static struct attribute *armv8_pmuv3_format_attrs[] = {
 302         &format_attr_event.attr,
 303         &format_attr_long.attr,
 304         NULL,
 305 };
 306
 307 static struct attribute_group armv8_pmuv3_format_attr_group = {
 308         .name = "format",
 309         .attrs = armv8_pmuv3_format_attrs,
 310 };
 311
 312 static ssize_t slots_show(struct device *dev, struct device_attribute *attr,
 313                           char *page)
 314 {
 315         struct pmu *pmu = dev_get_drvdata(dev);
 316         struct arm_pmu *cpu_pmu = container_of(pmu, struct arm_pmu, pmu);
 317         u32 slots = cpu_pmu->reg_pmmir & ARMV8_PMU_SLOTS_MASK;
 318
 319         return sysfs_emit(page, "0x%08x\n", slots);
 320 }
 321
 322 static DEVICE_ATTR_RO(slots);
 323
 324 static struct attribute *armv8_pmuv3_caps_attrs[] = {
 325         &dev_attr_slots.attr,
 326         NULL,
 327 };
 328
 329 static struct attribute_group armv8_pmuv3_caps_attr_group = {
 330         .name = "caps",
 331         .attrs = armv8_pmuv3_caps_attrs,
 332 };
 333
 334 /*
 335  * Perf Events' indices
 336  */
 337 #define ARMV8_IDX_CYCLE_COUNTER 0
 338 #define ARMV8_IDX_COUNTER0      1
 339
 340
 341 /*
 342  * We unconditionally enable ARMv8.5-PMU long event counter support
 343  * (64-bit events) where supported. Indicate if this arm_pmu has long
 344  * event counter support.
 345  */
 346 static bool armv8pmu_has_long_event(struct arm_pmu *cpu_pmu)
 347 {
 348         return (cpu_pmu->pmuver >= ID_AA64DFR0_PMUVER_8_5);
 349 }
 350
 351 /*
 352  * We must chain two programmable counters for 64 bit events,
 353  * except when we have allocated the 64bit cycle counter (for CPU
 354  * cycles event). This must be called only when the event has
 355  * a counter allocated.
 356  */
 357 static inline bool armv8pmu_event_is_chained(struct perf_event *event)
 358 {
 359         int idx = event->hw.idx;
 360         struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu);
 361
 362         return !WARN_ON(idx < 0) &&
 363                armv8pmu_event_is_64bit(event) &&
 364                !armv8pmu_has_long_event(cpu_pmu) &&
 365                (idx != ARMV8_IDX_CYCLE_COUNTER);
 366 }
 367
 368 /*
 369  * ARMv8 low level PMU access
 370  */
 371
 372 /*
 373  * Perf Event to low level counters mapping
 374  */
 375 #define ARMV8_IDX_TO_COUNTER(x) \
 376         (((x) - ARMV8_IDX_COUNTER0) & ARMV8_PMU_COUNTER_MASK)
 377
 378 /*
 379  * This code is really good
 380  */
 381
 382 #define PMEVN_CASE(n, case_macro) \
 383         case n: case_macro(n); break
 384
 385 #define PMEVN_SWITCH(x, case_macro)                             \
 386         do {                                                    \
 387                 switch (x) {                                    \
 388                 PMEVN_CASE(0,  case_macro);                     \
 389                 PMEVN_CASE(1,  case_macro);                     \
 390                 PMEVN_CASE(2,  case_macro);                     \
 391                 PMEVN_CASE(3,  case_macro);                     \
 392                 PMEVN_CASE(4,  case_macro);                     \
 393                 PMEVN_CASE(5,  case_macro);                     \
 394                 PMEVN_CASE(6,  case_macro);                     \
 395                 PMEVN_CASE(7,  case_macro);                     \
 396                 PMEVN_CASE(8,  case_macro);                     \
 397                 PMEVN_CASE(9,  case_macro);                     \
 398                 PMEVN_CASE(10, case_macro);                     \
 399                 PMEVN_CASE(11, case_macro);                     \
 400                 PMEVN_CASE(12, case_macro);                     \
 401                 PMEVN_CASE(13, case_macro);                     \
 402                 PMEVN_CASE(14, case_macro);                     \
 403                 PMEVN_CASE(15, case_macro);                     \
 404                 PMEVN_CASE(16, case_macro);                     \
 405                 PMEVN_CASE(17, case_macro);                     \
 406                 PMEVN_CASE(18, case_macro);                     \
 407                 PMEVN_CASE(19, case_macro);                     \
 408                 PMEVN_CASE(20, case_macro);                     \
 409                 PMEVN_CASE(21, case_macro);                     \
 410                 PMEVN_CASE(22, case_macro);                     \
 411                 PMEVN_CASE(23, case_macro);                     \
 412                 PMEVN_CASE(24, case_macro);                     \
 413                 PMEVN_CASE(25, case_macro);                     \
 414                 PMEVN_CASE(26, case_macro);                     \
 415                 PMEVN_CASE(27, case_macro);                     \
 416                 PMEVN_CASE(28, case_macro);                     \
 417                 PMEVN_CASE(29, case_macro);                     \
 418                 PMEVN_CASE(30, case_macro);                     \
 419                 default: WARN(1, "Invalid PMEV* index\n");      \
 420                 }                                               \
 421         } while (0)
 422
 423 #define RETURN_READ_PMEVCNTRN(n) \
 424         return read_sysreg(pmevcntr##n##_el0)
 425 static unsigned long read_pmevcntrn(int n)
 426 {
 427         PMEVN_SWITCH(n, RETURN_READ_PMEVCNTRN);
 428         return 0;
 429 }
 430
 431 #define WRITE_PMEVCNTRN(n) \
 432         write_sysreg(val, pmevcntr##n##_el0)
 433 static void write_pmevcntrn(int n, unsigned long val)
 434 {
 435         PMEVN_SWITCH(n, WRITE_PMEVCNTRN);
 436 }
 437
 438 #define WRITE_PMEVTYPERN(n) \
 439         write_sysreg(val, pmevtyper##n##_el0)
 440 static void write_pmevtypern(int n, unsigned long val)
 441 {
 442         PMEVN_SWITCH(n, WRITE_PMEVTYPERN);
 443 }
 444
 445 static inline u32 armv8pmu_pmcr_read(void)
 446 {
 447         return read_sysreg(pmcr_el0);
 448 }
 449
 450 static inline void armv8pmu_pmcr_write(u32 val)
 451 {
 452         val &= ARMV8_PMU_PMCR_MASK;
 453         isb();
 454         write_sysreg(val, pmcr_el0);
 455 }
 456
 457 static inline int armv8pmu_has_overflowed(u32 pmovsr)
 458 {
 459         return pmovsr & ARMV8_PMU_OVERFLOWED_MASK;
 460 }
 461
 462 static inline int armv8pmu_counter_has_overflowed(u32 pmnc, int idx)
 463 {
 464         return pmnc & BIT(ARMV8_IDX_TO_COUNTER(idx));
 465 }
 466
 467 static inline u64 armv8pmu_read_evcntr(int idx)
 468 {
 469         u32 counter = ARMV8_IDX_TO_COUNTER(idx);
 470
 471         return read_pmevcntrn(counter);
 472 }
 473
 474 static inline u64 armv8pmu_read_hw_counter(struct perf_event *event)
 475 {
 476         int idx = event->hw.idx;
 477         u64 val = 0;
 478
 479         val = armv8pmu_read_evcntr(idx);
 480         if (armv8pmu_event_is_chained(event))
 481                 val = (val << 32) | armv8pmu_read_evcntr(idx - 1);
 482         return val;
 483 }
 484
 485 /*
 486  * The cycle counter is always a 64-bit counter. When ARMV8_PMU_PMCR_LP
 487  * is set the event counters also become 64-bit counters. Unless the
 488  * user has requested a long counter (attr.config1) then we want to
 489  * interrupt upon 32-bit overflow - we achieve this by applying a bias.
 490  */
 491 static bool armv8pmu_event_needs_bias(struct perf_event *event)
 492 {
 493         struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu);
 494         struct hw_perf_event *hwc = &event->hw;
 495         int idx = hwc->idx;
 496
 497         if (armv8pmu_event_is_64bit(event))
 498                 return false;
 499
 500         if (armv8pmu_has_long_event(cpu_pmu) ||
 501             idx == ARMV8_IDX_CYCLE_COUNTER)
 502                 return true;
 503
 504         return false;
 505 }
 506
 507 static u64 armv8pmu_bias_long_counter(struct perf_event *event, u64 value)
 508 {
 509         if (armv8pmu_event_needs_bias(event))
 510                 value |= GENMASK(63, 32);
 511
 512         return value;
 513 }
 514
 515 static u64 armv8pmu_unbias_long_counter(struct perf_event *event, u64 value)
 516 {
 517         if (armv8pmu_event_needs_bias(event))
 518                 value &= ~GENMASK(63, 32);
 519
 520         return value;
 521 }
 522
 523 static u64 armv8pmu_read_counter(struct perf_event *event)
 524 {
 525         struct hw_perf_event *hwc = &event->hw;
 526         int idx = hwc->idx;
 527         u64 value = 0;
 528
 529         if (idx == ARMV8_IDX_CYCLE_COUNTER)
 530                 value = read_sysreg(pmccntr_el0);
 531         else
 532                 value = armv8pmu_read_hw_counter(event);
 533
 534         return  armv8pmu_unbias_long_counter(event, value);
 535 }
 536
 537 static inline void armv8pmu_write_evcntr(int idx, u64 value)
 538 {
 539         u32 counter = ARMV8_IDX_TO_COUNTER(idx);
 540
 541         write_pmevcntrn(counter, value);
 542 }
 543
 544 static inline void armv8pmu_write_hw_counter(struct perf_event *event,
 545                                              u64 value)
 546 {
 547         int idx = event->hw.idx;
 548
 549         if (armv8pmu_event_is_chained(event)) {
 550                 armv8pmu_write_evcntr(idx, upper_32_bits(value));
 551                 armv8pmu_write_evcntr(idx - 1, lower_32_bits(value));
 552         } else {
 553                 armv8pmu_write_evcntr(idx, value);
 554         }
 555 }
 556
 557 static void armv8pmu_write_counter(struct perf_event *event, u64 value)
 558 {
 559         struct hw_perf_event *hwc = &event->hw;
 560         int idx = hwc->idx;
 561
 562         value = armv8pmu_bias_long_counter(event, value);
 563
 564         if (idx == ARMV8_IDX_CYCLE_COUNTER)
 565                 write_sysreg(value, pmccntr_el0);
 566         else
 567                 armv8pmu_write_hw_counter(event, value);
 568 }
 569
 570 static inline void armv8pmu_write_evtype(int idx, u32 val)
 571 {
 572         u32 counter = ARMV8_IDX_TO_COUNTER(idx);
 573
 574         val &= ARMV8_PMU_EVTYPE_MASK;
 575         write_pmevtypern(counter, val);
 576 }
 577
 578 static inline void armv8pmu_write_event_type(struct perf_event *event)
 579 {
 580         struct hw_perf_event *hwc = &event->hw;
 581         int idx = hwc->idx;
 582
 583         /*
 584          * For chained events, the low counter is programmed to count
 585          * the event of interest and the high counter is programmed
 586          * with CHAIN event code with filters set to count at all ELs.
 587          */
 588         if (armv8pmu_event_is_chained(event)) {
 589                 u32 chain_evt = ARMV8_PMUV3_PERFCTR_CHAIN |
 590                                 ARMV8_PMU_INCLUDE_EL2;
 591
 592                 armv8pmu_write_evtype(idx - 1, hwc->config_base);
 593                 armv8pmu_write_evtype(idx, chain_evt);
 594         } else {
 595                 if (idx == ARMV8_IDX_CYCLE_COUNTER)
 596                         write_sysreg(hwc->config_base, pmccfiltr_el0);
 597                 else
 598                         armv8pmu_write_evtype(idx, hwc->config_base);
 599         }
 600 }
 601
 602 static u32 armv8pmu_event_cnten_mask(struct perf_event *event)
 603 {
 604         int counter = ARMV8_IDX_TO_COUNTER(event->hw.idx);
 605         u32 mask = BIT(counter);
 606
 607         if (armv8pmu_event_is_chained(event))
 608                 mask |= BIT(counter - 1);
 609         return mask;
 610 }
 611
 612 static inline void armv8pmu_enable_counter(u32 mask)
 613 {
 614         /*
 615          * Make sure event configuration register writes are visible before we
 616          * enable the counter.
 617          * */
 618         isb();
 619         write_sysreg(mask, pmcntenset_el0);
 620 }
 621
 622 static inline void armv8pmu_enable_event_counter(struct perf_event *event)
 623 {
 624         struct perf_event_attr *attr = &event->attr;
 625         u32 mask = armv8pmu_event_cnten_mask(event);
 626
 627         kvm_set_pmu_events(mask, attr);
 628
 629         /* We rely on the hypervisor switch code to enable guest counters */
 630         if (!kvm_pmu_counter_deferred(attr))
 631                 armv8pmu_enable_counter(mask);
 632 }
 633
 634 static inline void armv8pmu_disable_counter(u32 mask)
 635 {
 636         write_sysreg(mask, pmcntenclr_el0);
 637         /*
 638          * Make sure the effects of disabling the counter are visible before we
 639          * start configuring the event.
 640          */
 641         isb();
 642 }
 643
 644 static inline void armv8pmu_disable_event_counter(struct perf_event *event)
 645 {
 646         struct perf_event_attr *attr = &event->attr;
 647         u32 mask = armv8pmu_event_cnten_mask(event);
 648
 649         kvm_clr_pmu_events(mask);
 650
 651         /* We rely on the hypervisor switch code to disable guest counters */
 652         if (!kvm_pmu_counter_deferred(attr))
 653                 armv8pmu_disable_counter(mask);
 654 }
 655
 656 static inline void armv8pmu_enable_intens(u32 mask)
 657 {
 658         write_sysreg(mask, pmintenset_el1);
 659 }
 660
 661 static inline void armv8pmu_enable_event_irq(struct perf_event *event)
 662 {
 663         u32 counter = ARMV8_IDX_TO_COUNTER(event->hw.idx);
 664         armv8pmu_enable_intens(BIT(counter));
 665 }
 666
 667 static inline void armv8pmu_disable_intens(u32 mask)
 668 {
 669         write_sysreg(mask, pmintenclr_el1);
 670         isb();
 671         /* Clear the overflow flag in case an interrupt is pending. */
 672         write_sysreg(mask, pmovsclr_el0);
 673         isb();
 674 }
 675
 676 static inline void armv8pmu_disable_event_irq(struct perf_event *event)
 677 {
 678         u32 counter = ARMV8_IDX_TO_COUNTER(event->hw.idx);
 679         armv8pmu_disable_intens(BIT(counter));
 680 }
 681
 682 static inline u32 armv8pmu_getreset_flags(void)
 683 {
 684         u32 value;
 685
 686         /* Read */
 687         value = read_sysreg(pmovsclr_el0);
 688
 689         /* Write to clear flags */
 690         value &= ARMV8_PMU_OVSR_MASK;
 691         write_sysreg(value, pmovsclr_el0);
 692
 693         return value;
 694 }
 695
 696 static void armv8pmu_enable_event(struct perf_event *event)
 697 {
 698         /*
 699          * Enable counter and interrupt, and set the counter to count
 700          * the event that we're interested in.
 701          */
 702
 703         /*
 704          * Disable counter
 705          */
 706         armv8pmu_disable_event_counter(event);
 707
 708         /*
 709          * Set event.
 710          */
 711         armv8pmu_write_event_type(event);
 712
 713         /*
 714          * Enable interrupt for this counter
 715          */
 716         armv8pmu_enable_event_irq(event);
 717
 718         /*
 719          * Enable counter
 720          */
 721         armv8pmu_enable_event_counter(event);
 722 }
 723
 724 static void armv8pmu_disable_event(struct perf_event *event)
 725 {
 726         /*
 727          * Disable counter
 728          */
 729         armv8pmu_disable_event_counter(event);
 730
 731         /*
 732          * Disable interrupt for this counter
 733          */
 734         armv8pmu_disable_event_irq(event);
 735 }
 736
 737 static void armv8pmu_start(struct arm_pmu *cpu_pmu)
 738 {
 739         /* Enable all counters */
 740         armv8pmu_pmcr_write(armv8pmu_pmcr_read() | ARMV8_PMU_PMCR_E);
 741 }
 742
 743 static void armv8pmu_stop(struct arm_pmu *cpu_pmu)
 744 {
 745         /* Disable all counters */
 746         armv8pmu_pmcr_write(armv8pmu_pmcr_read() & ~ARMV8_PMU_PMCR_E);
 747 }
 748
 749 static irqreturn_t armv8pmu_handle_irq(struct arm_pmu *cpu_pmu)
 750 {
 751         u32 pmovsr;
 752         struct perf_sample_data data;
 753         struct pmu_hw_events *cpuc = this_cpu_ptr(cpu_pmu->hw_events);
 754         struct pt_regs *regs;
 755         int idx;
 756
 757         /*
 758          * Get and reset the IRQ flags
 759          */
 760         pmovsr = armv8pmu_getreset_flags();
 761
 762         /*
 763          * Did an overflow occur?
 764          */
 765         if (!armv8pmu_has_overflowed(pmovsr))
 766                 return IRQ_NONE;
 767
 768         /*
 769          * Handle the counter(s) overflow(s)
 770          */
 771         regs = get_irq_regs();
 772
 773         /*
 774          * Stop the PMU while processing the counter overflows
 775          * to prevent skews in group events.
 776          */
 777         armv8pmu_stop(cpu_pmu);
 778         for (idx = 0; idx < cpu_pmu->num_events; ++idx) {
 779                 struct perf_event *event = cpuc->events[idx];
 780                 struct hw_perf_event *hwc;
 781
 782                 /* Ignore if we don't have an event. */
 783                 if (!event)
 784                         continue;
 785
 786                 /*
 787                  * We have a single interrupt for all counters. Check that
 788                  * each counter has overflowed before we process it.
 789                  */
 790                 if (!armv8pmu_counter_has_overflowed(pmovsr, idx))
 791                         continue;
 792
 793                 hwc = &event->hw;
 794                 armpmu_event_update(event);
 795                 perf_sample_data_init(&data, 0, hwc->last_period);
 796                 if (!armpmu_event_set_period(event))
 797                         continue;
 798
 799                 /*
 800                  * Perf event overflow will queue the processing of the event as
 801                  * an irq_work which will be taken care of in the handling of
 802                  * IPI_IRQ_WORK.
 803                  */
 804                 if (perf_event_overflow(event, &data, regs))
 805                         cpu_pmu->disable(event);
 806         }
 807         armv8pmu_start(cpu_pmu);
 808
 809         return IRQ_HANDLED;
 810 }
 811
 812 static int armv8pmu_get_single_idx(struct pmu_hw_events *cpuc,
 813                                     struct arm_pmu *cpu_pmu)
 814 {
 815         int idx;
 816
 817         for (idx = ARMV8_IDX_COUNTER0; idx < cpu_pmu->num_events; idx ++) {
 818                 if (!test_and_set_bit(idx, cpuc->used_mask))
 819                         return idx;
 820         }
 821         return -EAGAIN;
 822 }
 823
 824 static int armv8pmu_get_chain_idx(struct pmu_hw_events *cpuc,
 825                                    struct arm_pmu *cpu_pmu)
 826 {
 827         int idx;
 828
 829         /*
 830          * Chaining requires two consecutive event counters, where
 831          * the lower idx must be even.
 832          */
 833         for (idx = ARMV8_IDX_COUNTER0 + 1; idx < cpu_pmu->num_events; idx += 2) {
 834                 if (!test_and_set_bit(idx, cpuc->used_mask)) {
 835                         /* Check if the preceding even counter is available */
 836                         if (!test_and_set_bit(idx - 1, cpuc->used_mask))
 837                                 return idx;
 838                         /* Release the Odd counter */
 839                         clear_bit(idx, cpuc->used_mask);
 840                 }
 841         }
 842         return -EAGAIN;
 843 }
 844
 845 static int armv8pmu_get_event_idx(struct pmu_hw_events *cpuc,
 846                                   struct perf_event *event)
 847 {
 848         struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu);
 849         struct hw_perf_event *hwc = &event->hw;
 850         unsigned long evtype = hwc->config_base & ARMV8_PMU_EVTYPE_EVENT;
 851
 852         /* Always prefer to place a cycle counter into the cycle counter. */
 853         if (evtype == ARMV8_PMUV3_PERFCTR_CPU_CYCLES) {
 854                 if (!test_and_set_bit(ARMV8_IDX_CYCLE_COUNTER, cpuc->used_mask))
 855                         return ARMV8_IDX_CYCLE_COUNTER;
 856         }
 857
 858         /*
 859          * Otherwise use events counters
 860          */
 861         if (armv8pmu_event_is_64bit(event) &&
 862             !armv8pmu_has_long_event(cpu_pmu))
 863                 return  armv8pmu_get_chain_idx(cpuc, cpu_pmu);
 864         else
 865                 return armv8pmu_get_single_idx(cpuc, cpu_pmu);
 866 }
 867
 868 static void armv8pmu_clear_event_idx(struct pmu_hw_events *cpuc,
 869                                      struct perf_event *event)
 870 {
 871         int idx = event->hw.idx;
 872
 873         clear_bit(idx, cpuc->used_mask);
 874         if (armv8pmu_event_is_chained(event))
 875                 clear_bit(idx - 1, cpuc->used_mask);
 876 }
 877
 878 /*
 879  * Add an event filter to a given event.
 880  */
 881 static int armv8pmu_set_event_filter(struct hw_perf_event *event,
 882                                      struct perf_event_attr *attr)
 883 {
 884         unsigned long config_base = 0;
 885
 886         if (attr->exclude_idle)
 887                 return -EPERM;
 888
 889         /*
 890          * If we're running in hyp mode, then we *are* the hypervisor.
 891          * Therefore we ignore exclude_hv in this configuration, since
 892          * there's no hypervisor to sample anyway. This is consistent
 893          * with other architectures (x86 and Power).
 894          */
 895         if (is_kernel_in_hyp_mode()) {
 896                 if (!attr->exclude_kernel && !attr->exclude_host)
 897                         config_base |= ARMV8_PMU_INCLUDE_EL2;
 898                 if (attr->exclude_guest)
 899                         config_base |= ARMV8_PMU_EXCLUDE_EL1;
 900                 if (attr->exclude_host)
 901                         config_base |= ARMV8_PMU_EXCLUDE_EL0;
 902         } else {
 903                 if (!attr->exclude_hv && !attr->exclude_host)
 904                         config_base |= ARMV8_PMU_INCLUDE_EL2;
 905         }
 906
 907         /*
 908          * Filter out !VHE kernels and guest kernels
 909          */
 910         if (attr->exclude_kernel)
 911                 config_base |= ARMV8_PMU_EXCLUDE_EL1;
 912
 913         if (attr->exclude_user)
 914                 config_base |= ARMV8_PMU_EXCLUDE_EL0;
 915
 916         /*
 917          * Install the filter into config_base as this is used to
 918          * construct the event type.
 919          */
 920         event->config_base = config_base;
 921
 922         return 0;
 923 }
 924
 925 static int armv8pmu_filter_match(struct perf_event *event)
 926 {
 927         unsigned long evtype = event->hw.config_base & ARMV8_PMU_EVTYPE_EVENT;
 928         return evtype != ARMV8_PMUV3_PERFCTR_CHAIN;
 929 }
 930
 931 static void armv8pmu_reset(void *info)
 932 {
 933         struct arm_pmu *cpu_pmu = (struct arm_pmu *)info;
 934         u32 pmcr;
 935
 936         /* The counter and interrupt enable registers are unknown at reset. */
 937         armv8pmu_disable_counter(U32_MAX);
 938         armv8pmu_disable_intens(U32_MAX);
 939
 940         /* Clear the counters we flip at guest entry/exit */
 941         kvm_clr_pmu_events(U32_MAX);
 942
 943         /*
 944          * Initialize & Reset PMNC. Request overflow interrupt for
 945          * 64 bit cycle counter but cheat in armv8pmu_write_counter().
 946          */
 947         pmcr = ARMV8_PMU_PMCR_P | ARMV8_PMU_PMCR_C | ARMV8_PMU_PMCR_LC;
 948
 949         /* Enable long event counter support where available */
 950         if (armv8pmu_has_long_event(cpu_pmu))
 951                 pmcr |= ARMV8_PMU_PMCR_LP;
 952
 953         armv8pmu_pmcr_write(pmcr);
 954 }
 955
 956 static int __armv8_pmuv3_map_event(struct perf_event *event,
 957                                    const unsigned (*extra_event_map)
 958                                                   [PERF_COUNT_HW_MAX],
 959                                    const unsigned (*extra_cache_map)
 960                                                   [PERF_COUNT_HW_CACHE_MAX]
 961                                                   [PERF_COUNT_HW_CACHE_OP_MAX]
 962                                                   [PERF_COUNT_HW_CACHE_RESULT_MAX])
 963 {
 964         int hw_event_id;
 965         struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
 966
 967         hw_event_id = armpmu_map_event(event, &armv8_pmuv3_perf_map,
 968                                        &armv8_pmuv3_perf_cache_map,
 969                                        ARMV8_PMU_EVTYPE_EVENT);
 970
 971         if (armv8pmu_event_is_64bit(event))
 972                 event->hw.flags |= ARMPMU_EVT_64BIT;
 973
 974         /* Only expose micro/arch events supported by this PMU */
 975         if ((hw_event_id > 0) && (hw_event_id < ARMV8_PMUV3_MAX_COMMON_EVENTS)
 976             && test_bit(hw_event_id, armpmu->pmceid_bitmap)) {
 977                 return hw_event_id;
 978         }
 979
 980         return armpmu_map_event(event, extra_event_map, extra_cache_map,
 981                                 ARMV8_PMU_EVTYPE_EVENT);
 982 }
 983
 984 static int armv8_pmuv3_map_event(struct perf_event *event)
 985 {
 986         return __armv8_pmuv3_map_event(event, NULL, NULL);
 987 }
 988
 989 static int armv8_a53_map_event(struct perf_event *event)
 990 {
 991         return __armv8_pmuv3_map_event(event, NULL, &armv8_a53_perf_cache_map);
 992 }
 993
 994 static int armv8_a57_map_event(struct perf_event *event)
 995 {
 996         return __armv8_pmuv3_map_event(event, NULL, &armv8_a57_perf_cache_map);
 997 }
 998
 999 static int armv8_a73_map_event(struct perf_event *event)
1000 {
1001         return __armv8_pmuv3_map_event(event, NULL, &armv8_a73_perf_cache_map);
1002 }
1003
1004 static int armv8_thunder_map_event(struct perf_event *event)
1005 {
1006         return __armv8_pmuv3_map_event(event, NULL,
1007                                        &armv8_thunder_perf_cache_map);
1008 }
1009
1010 static int armv8_vulcan_map_event(struct perf_event *event)
1011 {
1012         return __armv8_pmuv3_map_event(event, NULL,
1013                                        &armv8_vulcan_perf_cache_map);
1014 }
1015
1016 struct armv8pmu_probe_info {
1017         struct arm_pmu *pmu;
1018         bool present;
1019 };
1020
1021 static void __armv8pmu_probe_pmu(void *info)
1022 {
1023         struct armv8pmu_probe_info *probe = info;
1024         struct arm_pmu *cpu_pmu = probe->pmu;
1025         u64 dfr0;
1026         u64 pmceid_raw[2];
1027         u32 pmceid[2];
1028         int pmuver;
1029
1030         dfr0 = read_sysreg(id_aa64dfr0_el1);
1031         pmuver = cpuid_feature_extract_unsigned_field(dfr0,
1032                         ID_AA64DFR0_PMUVER_SHIFT);
1033         if (pmuver == 0xf || pmuver == 0)
1034                 return;
1035
1036         cpu_pmu->pmuver = pmuver;
1037         probe->present = true;
1038
1039         /* Read the nb of CNTx counters supported from PMNC */
1040         cpu_pmu->num_events = (armv8pmu_pmcr_read() >> ARMV8_PMU_PMCR_N_SHIFT)
1041                 & ARMV8_PMU_PMCR_N_MASK;
1042
1043         /* Add the CPU cycles counter */
1044         cpu_pmu->num_events += 1;
1045
1046         pmceid[0] = pmceid_raw[0] = read_sysreg(pmceid0_el0);
1047         pmceid[1] = pmceid_raw[1] = read_sysreg(pmceid1_el0);
1048
1049         bitmap_from_arr32(cpu_pmu->pmceid_bitmap,
1050                              pmceid, ARMV8_PMUV3_MAX_COMMON_EVENTS);
1051
1052         pmceid[0] = pmceid_raw[0] >> 32;
1053         pmceid[1] = pmceid_raw[1] >> 32;
1054
1055         bitmap_from_arr32(cpu_pmu->pmceid_ext_bitmap,
1056                              pmceid, ARMV8_PMUV3_MAX_COMMON_EVENTS);
1057
1058         /* store PMMIR_EL1 register for sysfs */
1059         if (pmuver >= ID_AA64DFR0_PMUVER_8_4 && (pmceid_raw[1] & BIT(31)))
1060                 cpu_pmu->reg_pmmir = read_cpuid(PMMIR_EL1);
1061         else
1062                 cpu_pmu->reg_pmmir = 0;
1063 }
1064
1065 static int armv8pmu_probe_pmu(struct arm_pmu *cpu_pmu)
1066 {
1067         struct armv8pmu_probe_info probe = {
1068                 .pmu = cpu_pmu,
1069                 .present = false,
1070         };
1071         int ret;
1072
1073         ret = smp_call_function_any(&cpu_pmu->supported_cpus,
1074                                     __armv8pmu_probe_pmu,
1075                                     &probe, 1);
1076         if (ret)
1077                 return ret;
1078
1079         return probe.present ? 0 : -ENODEV;
1080 }
1081
1082 static int armv8_pmu_init(struct arm_pmu *cpu_pmu, char *name,
1083                           int (*map_event)(struct perf_event *event),
1084                           const struct attribute_group *events,
1085                           const struct attribute_group *format,
1086                           const struct attribute_group *caps)
1087 {
1088         int ret = armv8pmu_probe_pmu(cpu_pmu);
1089         if (ret)
1090                 return ret;
1091
1092         cpu_pmu->handle_irq             = armv8pmu_handle_irq;
1093         cpu_pmu->enable                 = armv8pmu_enable_event;
1094         cpu_pmu->disable                = armv8pmu_disable_event;
1095         cpu_pmu->read_counter           = armv8pmu_read_counter;
1096         cpu_pmu->write_counter          = armv8pmu_write_counter;
1097         cpu_pmu->get_event_idx          = armv8pmu_get_event_idx;
1098         cpu_pmu->clear_event_idx        = armv8pmu_clear_event_idx;
1099         cpu_pmu->start                  = armv8pmu_start;
1100         cpu_pmu->stop                   = armv8pmu_stop;
1101         cpu_pmu->reset                  = armv8pmu_reset;
1102         cpu_pmu->set_event_filter       = armv8pmu_set_event_filter;
1103         cpu_pmu->filter_match           = armv8pmu_filter_match;
1104
1105         cpu_pmu->name                   = name;
1106         cpu_pmu->map_event              = map_event;
1107         cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] = events ?
1108                         events : &armv8_pmuv3_events_attr_group;
1109         cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_FORMATS] = format ?
1110                         format : &armv8_pmuv3_format_attr_group;
1111         cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_CAPS] = caps ?
1112                         caps : &armv8_pmuv3_caps_attr_group;
1113
1114         return 0;
1115 }
1116
1117 static int armv8_pmu_init_nogroups(struct arm_pmu *cpu_pmu, char *name,
1118                                    int (*map_event)(struct perf_event *event))
1119 {
1120         return armv8_pmu_init(cpu_pmu, name, map_event, NULL, NULL, NULL);
1121 }
1122
1123 static int armv8_pmuv3_init(struct arm_pmu *cpu_pmu)
1124 {
1125         return armv8_pmu_init_nogroups(cpu_pmu, "armv8_pmuv3",
1126                                        armv8_pmuv3_map_event);
1127 }
1128
1129 static int armv8_a34_pmu_init(struct arm_pmu *cpu_pmu)
1130 {
1131         return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_a34",
1132                                        armv8_pmuv3_map_event);
1133 }
1134
1135 static int armv8_a35_pmu_init(struct arm_pmu *cpu_pmu)
1136 {
1137         return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_a35",
1138                                        armv8_a53_map_event);
1139 }
1140
1141 static int armv8_a53_pmu_init(struct arm_pmu *cpu_pmu)
1142 {
1143         return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_a53",
1144                                        armv8_a53_map_event);
1145 }
1146
1147 static int armv8_a55_pmu_init(struct arm_pmu *cpu_pmu)
1148 {
1149         return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_a55",
1150                                        armv8_pmuv3_map_event);
1151 }
1152
1153 static int armv8_a57_pmu_init(struct arm_pmu *cpu_pmu)
1154 {
1155         return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_a57",
1156                                        armv8_a57_map_event);
1157 }
1158
1159 static int armv8_a65_pmu_init(struct arm_pmu *cpu_pmu)
1160 {
1161         return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_a65",
1162                                        armv8_pmuv3_map_event);
1163 }
1164
1165 static int armv8_a72_pmu_init(struct arm_pmu *cpu_pmu)
1166 {
1167         return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_a72",
1168                                        armv8_a57_map_event);
1169 }
1170
1171 static int armv8_a73_pmu_init(struct arm_pmu *cpu_pmu)
1172 {
1173         return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_a73",
1174                                        armv8_a73_map_event);
1175 }
1176
1177 static int armv8_a75_pmu_init(struct arm_pmu *cpu_pmu)
1178 {
1179         return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_a75",
1180                                        armv8_pmuv3_map_event);
1181 }
1182
1183 static int armv8_a76_pmu_init(struct arm_pmu *cpu_pmu)
1184 {
1185         return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_a76",
1186                                        armv8_pmuv3_map_event);
1187 }
1188
1189 static int armv8_a77_pmu_init(struct arm_pmu *cpu_pmu)
1190 {
1191         return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_a77",
1192                                        armv8_pmuv3_map_event);
1193 }
1194
1195 static int armv8_e1_pmu_init(struct arm_pmu *cpu_pmu)
1196 {
1197         return armv8_pmu_init_nogroups(cpu_pmu, "armv8_neoverse_e1",
1198                                        armv8_pmuv3_map_event);
1199 }
1200
1201 static int armv8_n1_pmu_init(struct arm_pmu *cpu_pmu)
1202 {
1203         return armv8_pmu_init_nogroups(cpu_pmu, "armv8_neoverse_n1",
1204                                        armv8_pmuv3_map_event);
1205 }
1206
1207 static int armv8_thunder_pmu_init(struct arm_pmu *cpu_pmu)
1208 {
1209         return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cavium_thunder",
1210                                        armv8_thunder_map_event);
1211 }
1212
1213 static int armv8_vulcan_pmu_init(struct arm_pmu *cpu_pmu)
1214 {
1215         return armv8_pmu_init_nogroups(cpu_pmu, "armv8_brcm_vulcan",
1216                                        armv8_vulcan_map_event);
1217 }
1218
1219 static const struct of_device_id armv8_pmu_of_device_ids[] = {
1220         {.compatible = "arm,armv8-pmuv3",       .data = armv8_pmuv3_init},
1221         {.compatible = "arm,cortex-a34-pmu",    .data = armv8_a34_pmu_init},
1222         {.compatible = "arm,cortex-a35-pmu",    .data = armv8_a35_pmu_init},
1223         {.compatible = "arm,cortex-a53-pmu",    .data = armv8_a53_pmu_init},
1224         {.compatible = "arm,cortex-a55-pmu",    .data = armv8_a55_pmu_init},
1225         {.compatible = "arm,cortex-a57-pmu",    .data = armv8_a57_pmu_init},
1226         {.compatible = "arm,cortex-a65-pmu",    .data = armv8_a65_pmu_init},
1227         {.compatible = "arm,cortex-a72-pmu",    .data = armv8_a72_pmu_init},
1228         {.compatible = "arm,cortex-a73-pmu",    .data = armv8_a73_pmu_init},
1229         {.compatible = "arm,cortex-a75-pmu",    .data = armv8_a75_pmu_init},
1230         {.compatible = "arm,cortex-a76-pmu",    .data = armv8_a76_pmu_init},
1231         {.compatible = "arm,cortex-a77-pmu",    .data = armv8_a77_pmu_init},
1232         {.compatible = "arm,neoverse-e1-pmu",   .data = armv8_e1_pmu_init},
1233         {.compatible = "arm,neoverse-n1-pmu",   .data = armv8_n1_pmu_init},
1234         {.compatible = "cavium,thunder-pmu",    .data = armv8_thunder_pmu_init},
1235         {.compatible = "brcm,vulcan-pmu",       .data = armv8_vulcan_pmu_init},
1236         {},
1237 };
1238
1239 static int armv8_pmu_device_probe(struct platform_device *pdev)
1240 {
1241         return arm_pmu_device_probe(pdev, armv8_pmu_of_device_ids, NULL);
1242 }
1243
1244 static struct platform_driver armv8_pmu_driver = {
1245         .driver         = {
1246                 .name   = ARMV8_PMU_PDEV_NAME,
1247                 .of_match_table = armv8_pmu_of_device_ids,
1248                 .suppress_bind_attrs = true,
1249         },
1250         .probe          = armv8_pmu_device_probe,
1251 };
1252
1253 static int __init armv8_pmu_driver_init(void)
1254 {
1255         if (acpi_disabled)
1256                 return platform_driver_register(&armv8_pmu_driver);
1257         else
1258                 return arm_pmu_acpi_probe(armv8_pmuv3_init);
1259 }
1260 device_initcall(armv8_pmu_driver_init)
1261
1262 void arch_perf_update_userpage(struct perf_event *event,
1263                                struct perf_event_mmap_page *userpg, u64 now)
1264 {
1265         struct clock_read_data *rd;
1266         unsigned int seq;
1267         u64 ns;
1268
1269         userpg->cap_user_time = 0;
1270         userpg->cap_user_time_zero = 0;
1271         userpg->cap_user_time_short = 0;
1272
1273         do {
1274                 rd = sched_clock_read_begin(&seq);
1275
1276                 if (rd->read_sched_clock != arch_timer_read_counter)
1277                         return;
1278
1279                 userpg->time_mult = rd->mult;
1280                 userpg->time_shift = rd->shift;
1281                 userpg->time_zero = rd->epoch_ns;
1282                 userpg->time_cycles = rd->epoch_cyc;
1283                 userpg->time_mask = rd->sched_clock_mask;
1284
1285                 /*
1286                  * Subtract the cycle base, such that software that
1287                  * doesn't know about cap_user_time_short still 'works'
1288                  * assuming no wraps.
1289                  */
1290                 ns = mul_u64_u32_shr(rd->epoch_cyc, rd->mult, rd->shift);
1291                 userpg->time_zero -= ns;
1292
1293         } while (sched_clock_read_retry(seq));
1294
1295         userpg->time_offset = userpg->time_zero - now;
1296
1297         /*
1298          * time_shift is not expected to be greater than 31 due to
1299          * the original published conversion algorithm shifting a
1300          * 32-bit value (now specifies a 64-bit value) - refer
1301          * perf_event_mmap_page documentation in perf_event.h.
1302          */
1303         if (userpg->time_shift == 32) {
1304                 userpg->time_shift = 31;
1305                 userpg->time_mult >>= 1;
1306         }
1307
1308         /*
1309          * Internal timekeeping for enabled/running/stopped times
1310          * is always computed with the sched_clock.
1311          */
1312         userpg->cap_user_time = 1;
1313         userpg->cap_user_time_zero = 1;
1314         userpg->cap_user_time_short = 1;
1315 }