1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2014-2017 Linaro Ltd. <ard.biesheuvel@linaro.org>
7 #include <linux/ftrace.h>
8 #include <linux/kernel.h>
9 #include <linux/module.h>
10 #include <linux/moduleloader.h>
11 #include <linux/sort.h>
13 static struct plt_entry __get_adrp_add_pair(u64 dst, u64 pc,
14 enum aarch64_insn_register reg)
18 adrp = aarch64_insn_gen_adr(pc, dst, reg, AARCH64_INSN_ADR_TYPE_ADRP);
19 add = aarch64_insn_gen_add_sub_imm(reg, reg, dst % SZ_4K,
20 AARCH64_INSN_VARIANT_64BIT,
21 AARCH64_INSN_ADSB_ADD);
23 return (struct plt_entry){ cpu_to_le32(adrp), cpu_to_le32(add) };
26 struct plt_entry get_plt_entry(u64 dst, void *pc)
32 br = aarch64_insn_gen_branch_reg(AARCH64_INSN_REG_16,
33 AARCH64_INSN_BRANCH_NOLINK);
35 plt = __get_adrp_add_pair(dst, (u64)pc, AARCH64_INSN_REG_16);
36 plt.br = cpu_to_le32(br);
41 bool plt_entries_equal(const struct plt_entry *a, const struct plt_entry *b)
46 * Check whether both entries refer to the same target:
47 * do the cheapest checks first.
48 * If the 'add' or 'br' opcodes are different, then the target
51 if (a->add != b->add || a->br != b->br)
54 p = ALIGN_DOWN((u64)a, SZ_4K);
55 q = ALIGN_DOWN((u64)b, SZ_4K);
58 * If the 'adrp' opcodes are the same then we just need to check
59 * that they refer to the same 4k region.
61 if (a->adrp == b->adrp && p == q)
64 return (p + aarch64_insn_adrp_get_offset(le32_to_cpu(a->adrp))) ==
65 (q + aarch64_insn_adrp_get_offset(le32_to_cpu(b->adrp)));
68 static bool in_init(const struct module *mod, void *loc)
70 return (u64)loc - (u64)mod->init_layout.base < mod->init_layout.size;
73 u64 module_emit_plt_entry(struct module *mod, Elf64_Shdr *sechdrs,
74 void *loc, const Elf64_Rela *rela,
77 struct mod_plt_sec *pltsec = !in_init(mod, loc) ? &mod->arch.core :
79 struct plt_entry *plt = (struct plt_entry *)sechdrs[pltsec->plt_shndx].sh_addr;
80 int i = pltsec->plt_num_entries;
82 u64 val = sym->st_value + rela->r_addend;
84 if (is_forbidden_offset_for_adrp(&plt[i].adrp))
87 plt[i] = get_plt_entry(val, &plt[i]);
90 * Check if the entry we just created is a duplicate. Given that the
91 * relocations are sorted, this will be the last entry we allocated.
94 if (j >= 0 && plt_entries_equal(plt + i, plt + j))
97 pltsec->plt_num_entries += i - j;
98 if (WARN_ON(pltsec->plt_num_entries > pltsec->plt_max_entries))
104 #ifdef CONFIG_ARM64_ERRATUM_843419
105 u64 module_emit_veneer_for_adrp(struct module *mod, Elf64_Shdr *sechdrs,
108 struct mod_plt_sec *pltsec = !in_init(mod, loc) ? &mod->arch.core :
110 struct plt_entry *plt = (struct plt_entry *)sechdrs[pltsec->plt_shndx].sh_addr;
111 int i = pltsec->plt_num_entries++;
115 if (WARN_ON(pltsec->plt_num_entries > pltsec->plt_max_entries))
118 if (is_forbidden_offset_for_adrp(&plt[i].adrp))
119 i = pltsec->plt_num_entries++;
121 /* get the destination register of the ADRP instruction */
122 rd = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RD,
123 le32_to_cpup((__le32 *)loc));
125 br = aarch64_insn_gen_branch_imm((u64)&plt[i].br, (u64)loc + 4,
126 AARCH64_INSN_BRANCH_NOLINK);
128 plt[i] = __get_adrp_add_pair(val, (u64)&plt[i], rd);
129 plt[i].br = cpu_to_le32(br);
135 #define cmp_3way(a, b) ((a) < (b) ? -1 : (a) > (b))
137 static int cmp_rela(const void *a, const void *b)
139 const Elf64_Rela *x = a, *y = b;
142 /* sort by type, symbol index and addend */
143 i = cmp_3way(ELF64_R_TYPE(x->r_info), ELF64_R_TYPE(y->r_info));
145 i = cmp_3way(ELF64_R_SYM(x->r_info), ELF64_R_SYM(y->r_info));
147 i = cmp_3way(x->r_addend, y->r_addend);
151 static bool duplicate_rel(const Elf64_Rela *rela, int num)
154 * Entries are sorted by type, symbol index and addend. That means
155 * that, if a duplicate entry exists, it must be in the preceding
158 return num > 0 && cmp_rela(rela + num, rela + num - 1) == 0;
161 static unsigned int count_plts(Elf64_Sym *syms, Elf64_Rela *rela, int num,
162 Elf64_Word dstidx, Elf_Shdr *dstsec)
164 unsigned int ret = 0;
168 for (i = 0; i < num; i++) {
171 switch (ELF64_R_TYPE(rela[i].r_info)) {
172 case R_AARCH64_JUMP26:
173 case R_AARCH64_CALL26:
174 if (!IS_ENABLED(CONFIG_RANDOMIZE_BASE))
178 * We only have to consider branch targets that resolve
179 * to symbols that are defined in a different section.
180 * This is not simply a heuristic, it is a fundamental
181 * limitation, since there is no guaranteed way to emit
182 * PLT entries sufficiently close to the branch if the
183 * section size exceeds the range of a branch
184 * instruction. So ignore relocations against defined
185 * symbols if they live in the same section as the
188 s = syms + ELF64_R_SYM(rela[i].r_info);
189 if (s->st_shndx == dstidx)
193 * Jump relocations with non-zero addends against
194 * undefined symbols are supported by the ELF spec, but
195 * do not occur in practice (e.g., 'jump n bytes past
196 * the entry point of undefined function symbol f').
197 * So we need to support them, but there is no need to
198 * take them into consideration when trying to optimize
199 * this code. So let's only check for duplicates when
200 * the addend is zero: this allows us to record the PLT
201 * entry address in the symbol table itself, rather than
202 * having to search the list for duplicates each time we
205 if (rela[i].r_addend != 0 || !duplicate_rel(rela, i))
208 case R_AARCH64_ADR_PREL_PG_HI21_NC:
209 case R_AARCH64_ADR_PREL_PG_HI21:
210 if (!IS_ENABLED(CONFIG_ARM64_ERRATUM_843419) ||
211 !cpus_have_const_cap(ARM64_WORKAROUND_843419))
215 * Determine the minimal safe alignment for this ADRP
216 * instruction: the section alignment at which it is
217 * guaranteed not to appear at a vulnerable offset.
219 * This comes down to finding the least significant zero
220 * bit in bits [11:3] of the section offset, and
221 * increasing the section's alignment so that the
222 * resulting address of this instruction is guaranteed
223 * to equal the offset in that particular bit (as well
224 * as all less signficant bits). This ensures that the
225 * address modulo 4 KB != 0xfff8 or 0xfffc (which would
226 * have all ones in bits [11:3])
228 min_align = 2ULL << ffz(rela[i].r_offset | 0x7);
231 * Allocate veneer space for each ADRP that may appear
232 * at a vulnerable offset nonetheless. At relocation
233 * time, some of these will remain unused since some
234 * ADRP instructions can be patched to ADR instructions
237 if (min_align > SZ_4K)
240 dstsec->sh_addralign = max(dstsec->sh_addralign,
246 if (IS_ENABLED(CONFIG_ARM64_ERRATUM_843419) &&
247 cpus_have_const_cap(ARM64_WORKAROUND_843419))
249 * Add some slack so we can skip PLT slots that may trigger
250 * the erratum due to the placement of the ADRP instruction.
252 ret += DIV_ROUND_UP(ret, (SZ_4K / sizeof(struct plt_entry)));
257 static bool branch_rela_needs_plt(Elf64_Sym *syms, Elf64_Rela *rela,
261 Elf64_Sym *s = syms + ELF64_R_SYM(rela->r_info);
263 if (s->st_shndx == dstidx)
266 return ELF64_R_TYPE(rela->r_info) == R_AARCH64_JUMP26 ||
267 ELF64_R_TYPE(rela->r_info) == R_AARCH64_CALL26;
270 /* Group branch PLT relas at the front end of the array. */
271 static int partition_branch_plt_relas(Elf64_Sym *syms, Elf64_Rela *rela,
272 int numrels, Elf64_Word dstidx)
274 int i = 0, j = numrels - 1;
276 if (!IS_ENABLED(CONFIG_RANDOMIZE_BASE))
280 if (branch_rela_needs_plt(syms, &rela[i], dstidx))
282 else if (branch_rela_needs_plt(syms, &rela[j], dstidx))
283 swap(rela[i], rela[j]);
291 int module_frob_arch_sections(Elf_Ehdr *ehdr, Elf_Shdr *sechdrs,
292 char *secstrings, struct module *mod)
294 unsigned long core_plts = 0;
295 unsigned long init_plts = 0;
296 Elf64_Sym *syms = NULL;
297 Elf_Shdr *pltsec, *tramp = NULL;
301 * Find the empty .plt section so we can expand it to store the PLT
302 * entries. Record the symtab address as well.
304 for (i = 0; i < ehdr->e_shnum; i++) {
305 if (!strcmp(secstrings + sechdrs[i].sh_name, ".plt"))
306 mod->arch.core.plt_shndx = i;
307 else if (!strcmp(secstrings + sechdrs[i].sh_name, ".init.plt"))
308 mod->arch.init.plt_shndx = i;
309 else if (!strcmp(secstrings + sechdrs[i].sh_name,
310 ".text.ftrace_trampoline"))
312 else if (sechdrs[i].sh_type == SHT_SYMTAB)
313 syms = (Elf64_Sym *)sechdrs[i].sh_addr;
316 if (!mod->arch.core.plt_shndx || !mod->arch.init.plt_shndx) {
317 pr_err("%s: module PLT section(s) missing\n", mod->name);
321 pr_err("%s: module symtab section missing\n", mod->name);
325 for (i = 0; i < ehdr->e_shnum; i++) {
326 Elf64_Rela *rels = (void *)ehdr + sechdrs[i].sh_offset;
327 int nents, numrels = sechdrs[i].sh_size / sizeof(Elf64_Rela);
328 Elf64_Shdr *dstsec = sechdrs + sechdrs[i].sh_info;
330 if (sechdrs[i].sh_type != SHT_RELA)
333 /* ignore relocations that operate on non-exec sections */
334 if (!(dstsec->sh_flags & SHF_EXECINSTR))
338 * sort branch relocations requiring a PLT by type, symbol index
341 nents = partition_branch_plt_relas(syms, rels, numrels,
344 sort(rels, nents, sizeof(Elf64_Rela), cmp_rela, NULL);
346 if (!module_init_layout_section(secstrings + dstsec->sh_name))
347 core_plts += count_plts(syms, rels, numrels,
348 sechdrs[i].sh_info, dstsec);
350 init_plts += count_plts(syms, rels, numrels,
351 sechdrs[i].sh_info, dstsec);
354 pltsec = sechdrs + mod->arch.core.plt_shndx;
355 pltsec->sh_type = SHT_NOBITS;
356 pltsec->sh_flags = SHF_EXECINSTR | SHF_ALLOC;
357 pltsec->sh_addralign = L1_CACHE_BYTES;
358 pltsec->sh_size = (core_plts + 1) * sizeof(struct plt_entry);
359 mod->arch.core.plt_num_entries = 0;
360 mod->arch.core.plt_max_entries = core_plts;
362 pltsec = sechdrs + mod->arch.init.plt_shndx;
363 pltsec->sh_type = SHT_NOBITS;
364 pltsec->sh_flags = SHF_EXECINSTR | SHF_ALLOC;
365 pltsec->sh_addralign = L1_CACHE_BYTES;
366 pltsec->sh_size = (init_plts + 1) * sizeof(struct plt_entry);
367 mod->arch.init.plt_num_entries = 0;
368 mod->arch.init.plt_max_entries = init_plts;
371 tramp->sh_type = SHT_NOBITS;
372 tramp->sh_flags = SHF_EXECINSTR | SHF_ALLOC;
373 tramp->sh_addralign = __alignof__(struct plt_entry);
374 tramp->sh_size = NR_FTRACE_PLTS * sizeof(struct plt_entry);