arch/arm64/kernel/hw_breakpoint.c

   1 /*
   2  * HW_breakpoint: a unified kernel/user-space hardware breakpoint facility,
   3  * using the CPU's debug registers.
   4  *
   5  * Copyright (C) 2012 ARM Limited
   6  * Author: Will Deacon <will.deacon@arm.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  19  */
  20
  21 #define pr_fmt(fmt) "hw-breakpoint: " fmt
  22
  23 #include <linux/compat.h>
  24 #include <linux/cpu_pm.h>
  25 #include <linux/errno.h>
  26 #include <linux/hw_breakpoint.h>
  27 #include <linux/kprobes.h>
  28 #include <linux/perf_event.h>
  29 #include <linux/ptrace.h>
  30 #include <linux/smp.h>
  31
  32 #include <asm/compat.h>
  33 #include <asm/current.h>
  34 #include <asm/debug-monitors.h>
  35 #include <asm/hw_breakpoint.h>
  36 #include <asm/traps.h>
  37 #include <asm/cputype.h>
  38 #include <asm/system_misc.h>
  39 #include <asm/uaccess.h>
  40
  41 /* Breakpoint currently in use for each BRP. */
  42 static DEFINE_PER_CPU(struct perf_event *, bp_on_reg[ARM_MAX_BRP]);
  43
  44 /* Watchpoint currently in use for each WRP. */
  45 static DEFINE_PER_CPU(struct perf_event *, wp_on_reg[ARM_MAX_WRP]);
  46
  47 /* Currently stepping a per-CPU kernel breakpoint. */
  48 static DEFINE_PER_CPU(int, stepping_kernel_bp);
  49
  50 /* Number of BRP/WRP registers on this CPU. */
  51 static int core_num_brps;
  52 static int core_num_wrps;
  53
  54 int hw_breakpoint_slots(int type)
  55 {
  56         /*
  57          * We can be called early, so don't rely on
  58          * our static variables being initialised.
  59          */
  60         switch (type) {
  61         case TYPE_INST:
  62                 return get_num_brps();
  63         case TYPE_DATA:
  64                 return get_num_wrps();
  65         default:
  66                 pr_warning("unknown slot type: %d\n", type);
  67                 return 0;
  68         }
  69 }
  70
  71 #define READ_WB_REG_CASE(OFF, N, REG, VAL)      \
  72         case (OFF + N):                         \
  73                 AARCH64_DBG_READ(N, REG, VAL);  \
  74                 break
  75
  76 #define WRITE_WB_REG_CASE(OFF, N, REG, VAL)     \
  77         case (OFF + N):                         \
  78                 AARCH64_DBG_WRITE(N, REG, VAL); \
  79                 break
  80
  81 #define GEN_READ_WB_REG_CASES(OFF, REG, VAL)    \
  82         READ_WB_REG_CASE(OFF,  0, REG, VAL);    \
  83         READ_WB_REG_CASE(OFF,  1, REG, VAL);    \
  84         READ_WB_REG_CASE(OFF,  2, REG, VAL);    \
  85         READ_WB_REG_CASE(OFF,  3, REG, VAL);    \
  86         READ_WB_REG_CASE(OFF,  4, REG, VAL);    \
  87         READ_WB_REG_CASE(OFF,  5, REG, VAL);    \
  88         READ_WB_REG_CASE(OFF,  6, REG, VAL);    \
  89         READ_WB_REG_CASE(OFF,  7, REG, VAL);    \
  90         READ_WB_REG_CASE(OFF,  8, REG, VAL);    \
  91         READ_WB_REG_CASE(OFF,  9, REG, VAL);    \
  92         READ_WB_REG_CASE(OFF, 10, REG, VAL);    \
  93         READ_WB_REG_CASE(OFF, 11, REG, VAL);    \
  94         READ_WB_REG_CASE(OFF, 12, REG, VAL);    \
  95         READ_WB_REG_CASE(OFF, 13, REG, VAL);    \
  96         READ_WB_REG_CASE(OFF, 14, REG, VAL);    \
  97         READ_WB_REG_CASE(OFF, 15, REG, VAL)
  98
  99 #define GEN_WRITE_WB_REG_CASES(OFF, REG, VAL)   \
 100         WRITE_WB_REG_CASE(OFF,  0, REG, VAL);   \
 101         WRITE_WB_REG_CASE(OFF,  1, REG, VAL);   \
 102         WRITE_WB_REG_CASE(OFF,  2, REG, VAL);   \
 103         WRITE_WB_REG_CASE(OFF,  3, REG, VAL);   \
 104         WRITE_WB_REG_CASE(OFF,  4, REG, VAL);   \
 105         WRITE_WB_REG_CASE(OFF,  5, REG, VAL);   \
 106         WRITE_WB_REG_CASE(OFF,  6, REG, VAL);   \
 107         WRITE_WB_REG_CASE(OFF,  7, REG, VAL);   \
 108         WRITE_WB_REG_CASE(OFF,  8, REG, VAL);   \
 109         WRITE_WB_REG_CASE(OFF,  9, REG, VAL);   \
 110         WRITE_WB_REG_CASE(OFF, 10, REG, VAL);   \
 111         WRITE_WB_REG_CASE(OFF, 11, REG, VAL);   \
 112         WRITE_WB_REG_CASE(OFF, 12, REG, VAL);   \
 113         WRITE_WB_REG_CASE(OFF, 13, REG, VAL);   \
 114         WRITE_WB_REG_CASE(OFF, 14, REG, VAL);   \
 115         WRITE_WB_REG_CASE(OFF, 15, REG, VAL)
 116
 117 static u64 read_wb_reg(int reg, int n)
 118 {
 119         u64 val = 0;
 120
 121         switch (reg + n) {
 122         GEN_READ_WB_REG_CASES(AARCH64_DBG_REG_BVR, AARCH64_DBG_REG_NAME_BVR, val);
 123         GEN_READ_WB_REG_CASES(AARCH64_DBG_REG_BCR, AARCH64_DBG_REG_NAME_BCR, val);
 124         GEN_READ_WB_REG_CASES(AARCH64_DBG_REG_WVR, AARCH64_DBG_REG_NAME_WVR, val);
 125         GEN_READ_WB_REG_CASES(AARCH64_DBG_REG_WCR, AARCH64_DBG_REG_NAME_WCR, val);
 126         default:
 127                 pr_warning("attempt to read from unknown breakpoint register %d\n", n);
 128         }
 129
 130         return val;
 131 }
 132 NOKPROBE_SYMBOL(read_wb_reg);
 133
 134 static void write_wb_reg(int reg, int n, u64 val)
 135 {
 136         switch (reg + n) {
 137         GEN_WRITE_WB_REG_CASES(AARCH64_DBG_REG_BVR, AARCH64_DBG_REG_NAME_BVR, val);
 138         GEN_WRITE_WB_REG_CASES(AARCH64_DBG_REG_BCR, AARCH64_DBG_REG_NAME_BCR, val);
 139         GEN_WRITE_WB_REG_CASES(AARCH64_DBG_REG_WVR, AARCH64_DBG_REG_NAME_WVR, val);
 140         GEN_WRITE_WB_REG_CASES(AARCH64_DBG_REG_WCR, AARCH64_DBG_REG_NAME_WCR, val);
 141         default:
 142                 pr_warning("attempt to write to unknown breakpoint register %d\n", n);
 143         }
 144         isb();
 145 }
 146 NOKPROBE_SYMBOL(write_wb_reg);
 147
 148 /*
 149  * Convert a breakpoint privilege level to the corresponding exception
 150  * level.
 151  */
 152 static enum dbg_active_el debug_exception_level(int privilege)
 153 {
 154         switch (privilege) {
 155         case AARCH64_BREAKPOINT_EL0:
 156                 return DBG_ACTIVE_EL0;
 157         case AARCH64_BREAKPOINT_EL1:
 158                 return DBG_ACTIVE_EL1;
 159         default:
 160                 pr_warning("invalid breakpoint privilege level %d\n", privilege);
 161                 return -EINVAL;
 162         }
 163 }
 164 NOKPROBE_SYMBOL(debug_exception_level);
 165
 166 enum hw_breakpoint_ops {
 167         HW_BREAKPOINT_INSTALL,
 168         HW_BREAKPOINT_UNINSTALL,
 169         HW_BREAKPOINT_RESTORE
 170 };
 171
 172 static int is_compat_bp(struct perf_event *bp)
 173 {
 174         struct task_struct *tsk = bp->hw.target;
 175
 176         /*
 177          * tsk can be NULL for per-cpu (non-ptrace) breakpoints.
 178          * In this case, use the native interface, since we don't have
 179          * the notion of a "compat CPU" and could end up relying on
 180          * deprecated behaviour if we use unaligned watchpoints in
 181          * AArch64 state.
 182          */
 183         return tsk && is_compat_thread(task_thread_info(tsk));
 184 }
 185
 186 /**
 187  * hw_breakpoint_slot_setup - Find and setup a perf slot according to
 188  *                            operations
 189  *
 190  * @slots: pointer to array of slots
 191  * @max_slots: max number of slots
 192  * @bp: perf_event to setup
 193  * @ops: operation to be carried out on the slot
 194  *
 195  * Return:
 196  *      slot index on success
 197  *      -ENOSPC if no slot is available/matches
 198  *      -EINVAL on wrong operations parameter
 199  */
 200 static int hw_breakpoint_slot_setup(struct perf_event **slots, int max_slots,
 201                                     struct perf_event *bp,
 202                                     enum hw_breakpoint_ops ops)
 203 {
 204         int i;
 205         struct perf_event **slot;
 206
 207         for (i = 0; i < max_slots; ++i) {
 208                 slot = &slots[i];
 209                 switch (ops) {
 210                 case HW_BREAKPOINT_INSTALL:
 211                         if (!*slot) {
 212                                 *slot = bp;
 213                                 return i;
 214                         }
 215                         break;
 216                 case HW_BREAKPOINT_UNINSTALL:
 217                         if (*slot == bp) {
 218                                 *slot = NULL;
 219                                 return i;
 220                         }
 221                         break;
 222                 case HW_BREAKPOINT_RESTORE:
 223                         if (*slot == bp)
 224                                 return i;
 225                         break;
 226                 default:
 227                         pr_warn_once("Unhandled hw breakpoint ops %d\n", ops);
 228                         return -EINVAL;
 229                 }
 230         }
 231         return -ENOSPC;
 232 }
 233
 234 static int hw_breakpoint_control(struct perf_event *bp,
 235                                  enum hw_breakpoint_ops ops)
 236 {
 237         struct arch_hw_breakpoint *info = counter_arch_bp(bp);
 238         struct perf_event **slots;
 239         struct debug_info *debug_info = &current->thread.debug;
 240         int i, max_slots, ctrl_reg, val_reg, reg_enable;
 241         enum dbg_active_el dbg_el = debug_exception_level(info->ctrl.privilege);
 242         u32 ctrl;
 243
 244         if (info->ctrl.type == ARM_BREAKPOINT_EXECUTE) {
 245                 /* Breakpoint */
 246                 ctrl_reg = AARCH64_DBG_REG_BCR;
 247                 val_reg = AARCH64_DBG_REG_BVR;
 248                 slots = this_cpu_ptr(bp_on_reg);
 249                 max_slots = core_num_brps;
 250                 reg_enable = !debug_info->bps_disabled;
 251         } else {
 252                 /* Watchpoint */
 253                 ctrl_reg = AARCH64_DBG_REG_WCR;
 254                 val_reg = AARCH64_DBG_REG_WVR;
 255                 slots = this_cpu_ptr(wp_on_reg);
 256                 max_slots = core_num_wrps;
 257                 reg_enable = !debug_info->wps_disabled;
 258         }
 259
 260         i = hw_breakpoint_slot_setup(slots, max_slots, bp, ops);
 261
 262         if (WARN_ONCE(i < 0, "Can't find any breakpoint slot"))
 263                 return i;
 264
 265         switch (ops) {
 266         case HW_BREAKPOINT_INSTALL:
 267                 /*
 268                  * Ensure debug monitors are enabled at the correct exception
 269                  * level.
 270                  */
 271                 enable_debug_monitors(dbg_el);
 272                 /* Fall through */
 273         case HW_BREAKPOINT_RESTORE:
 274                 /* Setup the address register. */
 275                 write_wb_reg(val_reg, i, info->address);
 276
 277                 /* Setup the control register. */
 278                 ctrl = encode_ctrl_reg(info->ctrl);
 279                 write_wb_reg(ctrl_reg, i,
 280                              reg_enable ? ctrl | 0x1 : ctrl & ~0x1);
 281                 break;
 282         case HW_BREAKPOINT_UNINSTALL:
 283                 /* Reset the control register. */
 284                 write_wb_reg(ctrl_reg, i, 0);
 285
 286                 /*
 287                  * Release the debug monitors for the correct exception
 288                  * level.
 289                  */
 290                 disable_debug_monitors(dbg_el);
 291                 break;
 292         }
 293
 294         return 0;
 295 }
 296
 297 /*
 298  * Install a perf counter breakpoint.
 299  */
 300 int arch_install_hw_breakpoint(struct perf_event *bp)
 301 {
 302         return hw_breakpoint_control(bp, HW_BREAKPOINT_INSTALL);
 303 }
 304
 305 void arch_uninstall_hw_breakpoint(struct perf_event *bp)
 306 {
 307         hw_breakpoint_control(bp, HW_BREAKPOINT_UNINSTALL);
 308 }
 309
 310 static int get_hbp_len(u8 hbp_len)
 311 {
 312         unsigned int len_in_bytes = 0;
 313
 314         switch (hbp_len) {
 315         case ARM_BREAKPOINT_LEN_1:
 316                 len_in_bytes = 1;
 317                 break;
 318         case ARM_BREAKPOINT_LEN_2:
 319                 len_in_bytes = 2;
 320                 break;
 321         case ARM_BREAKPOINT_LEN_4:
 322                 len_in_bytes = 4;
 323                 break;
 324         case ARM_BREAKPOINT_LEN_8:
 325                 len_in_bytes = 8;
 326                 break;
 327         }
 328
 329         return len_in_bytes;
 330 }
 331
 332 /*
 333  * Check whether bp virtual address is in kernel space.
 334  */
 335 int arch_check_bp_in_kernelspace(struct perf_event *bp)
 336 {
 337         unsigned int len;
 338         unsigned long va;
 339         struct arch_hw_breakpoint *info = counter_arch_bp(bp);
 340
 341         va = info->address;
 342         len = get_hbp_len(info->ctrl.len);
 343
 344         return (va >= TASK_SIZE) && ((va + len - 1) >= TASK_SIZE);
 345 }
 346
 347 /*
 348  * Extract generic type and length encodings from an arch_hw_breakpoint_ctrl.
 349  * Hopefully this will disappear when ptrace can bypass the conversion
 350  * to generic breakpoint descriptions.
 351  */
 352 int arch_bp_generic_fields(struct arch_hw_breakpoint_ctrl ctrl,
 353                            int *gen_len, int *gen_type)
 354 {
 355         /* Type */
 356         switch (ctrl.type) {
 357         case ARM_BREAKPOINT_EXECUTE:
 358                 *gen_type = HW_BREAKPOINT_X;
 359                 break;
 360         case ARM_BREAKPOINT_LOAD:
 361                 *gen_type = HW_BREAKPOINT_R;
 362                 break;
 363         case ARM_BREAKPOINT_STORE:
 364                 *gen_type = HW_BREAKPOINT_W;
 365                 break;
 366         case ARM_BREAKPOINT_LOAD | ARM_BREAKPOINT_STORE:
 367                 *gen_type = HW_BREAKPOINT_RW;
 368                 break;
 369         default:
 370                 return -EINVAL;
 371         }
 372
 373         /* Len */
 374         switch (ctrl.len) {
 375         case ARM_BREAKPOINT_LEN_1:
 376                 *gen_len = HW_BREAKPOINT_LEN_1;
 377                 break;
 378         case ARM_BREAKPOINT_LEN_2:
 379                 *gen_len = HW_BREAKPOINT_LEN_2;
 380                 break;
 381         case ARM_BREAKPOINT_LEN_4:
 382                 *gen_len = HW_BREAKPOINT_LEN_4;
 383                 break;
 384         case ARM_BREAKPOINT_LEN_8:
 385                 *gen_len = HW_BREAKPOINT_LEN_8;
 386                 break;
 387         default:
 388                 return -EINVAL;
 389         }
 390
 391         return 0;
 392 }
 393
 394 /*
 395  * Construct an arch_hw_breakpoint from a perf_event.
 396  */
 397 static int arch_build_bp_info(struct perf_event *bp)
 398 {
 399         struct arch_hw_breakpoint *info = counter_arch_bp(bp);
 400
 401         /* Type */
 402         switch (bp->attr.bp_type) {
 403         case HW_BREAKPOINT_X:
 404                 info->ctrl.type = ARM_BREAKPOINT_EXECUTE;
 405                 break;
 406         case HW_BREAKPOINT_R:
 407                 info->ctrl.type = ARM_BREAKPOINT_LOAD;
 408                 break;
 409         case HW_BREAKPOINT_W:
 410                 info->ctrl.type = ARM_BREAKPOINT_STORE;
 411                 break;
 412         case HW_BREAKPOINT_RW:
 413                 info->ctrl.type = ARM_BREAKPOINT_LOAD | ARM_BREAKPOINT_STORE;
 414                 break;
 415         default:
 416                 return -EINVAL;
 417         }
 418
 419         /* Len */
 420         switch (bp->attr.bp_len) {
 421         case HW_BREAKPOINT_LEN_1:
 422                 info->ctrl.len = ARM_BREAKPOINT_LEN_1;
 423                 break;
 424         case HW_BREAKPOINT_LEN_2:
 425                 info->ctrl.len = ARM_BREAKPOINT_LEN_2;
 426                 break;
 427         case HW_BREAKPOINT_LEN_4:
 428                 info->ctrl.len = ARM_BREAKPOINT_LEN_4;
 429                 break;
 430         case HW_BREAKPOINT_LEN_8:
 431                 info->ctrl.len = ARM_BREAKPOINT_LEN_8;
 432                 break;
 433         default:
 434                 return -EINVAL;
 435         }
 436
 437         /*
 438          * On AArch64, we only permit breakpoints of length 4, whereas
 439          * AArch32 also requires breakpoints of length 2 for Thumb.
 440          * Watchpoints can be of length 1, 2, 4 or 8 bytes.
 441          */
 442         if (info->ctrl.type == ARM_BREAKPOINT_EXECUTE) {
 443                 if (is_compat_bp(bp)) {
 444                         if (info->ctrl.len != ARM_BREAKPOINT_LEN_2 &&
 445                             info->ctrl.len != ARM_BREAKPOINT_LEN_4)
 446                                 return -EINVAL;
 447                 } else if (info->ctrl.len != ARM_BREAKPOINT_LEN_4) {
 448                         /*
 449                          * FIXME: Some tools (I'm looking at you perf) assume
 450                          *        that breakpoints should be sizeof(long). This
 451                          *        is nonsense. For now, we fix up the parameter
 452                          *        but we should probably return -EINVAL instead.
 453                          */
 454                         info->ctrl.len = ARM_BREAKPOINT_LEN_4;
 455                 }
 456         }
 457
 458         /* Address */
 459         info->address = bp->attr.bp_addr;
 460
 461         /*
 462          * Privilege
 463          * Note that we disallow combined EL0/EL1 breakpoints because
 464          * that would complicate the stepping code.
 465          */
 466         if (arch_check_bp_in_kernelspace(bp))
 467                 info->ctrl.privilege = AARCH64_BREAKPOINT_EL1;
 468         else
 469                 info->ctrl.privilege = AARCH64_BREAKPOINT_EL0;
 470
 471         /* Enabled? */
 472         info->ctrl.enabled = !bp->attr.disabled;
 473
 474         return 0;
 475 }
 476
 477 /*
 478  * Validate the arch-specific HW Breakpoint register settings.
 479  */
 480 int arch_validate_hwbkpt_settings(struct perf_event *bp)
 481 {
 482         struct arch_hw_breakpoint *info = counter_arch_bp(bp);
 483         int ret;
 484         u64 alignment_mask, offset;
 485
 486         /* Build the arch_hw_breakpoint. */
 487         ret = arch_build_bp_info(bp);
 488         if (ret)
 489                 return ret;
 490
 491         /*
 492          * Check address alignment.
 493          * We don't do any clever alignment correction for watchpoints
 494          * because using 64-bit unaligned addresses is deprecated for
 495          * AArch64.
 496          *
 497          * AArch32 tasks expect some simple alignment fixups, so emulate
 498          * that here.
 499          */
 500         if (is_compat_bp(bp)) {
 501                 if (info->ctrl.len == ARM_BREAKPOINT_LEN_8)
 502                         alignment_mask = 0x7;
 503                 else
 504                         alignment_mask = 0x3;
 505                 offset = info->address & alignment_mask;
 506                 switch (offset) {
 507                 case 0:
 508                         /* Aligned */
 509                         break;
 510                 case 1:
 511                 case 2:
 512                         /* Allow halfword watchpoints and breakpoints. */
 513                         if (info->ctrl.len == ARM_BREAKPOINT_LEN_2)
 514                                 break;
 515                 case 3:
 516                         /* Allow single byte watchpoint. */
 517                         if (info->ctrl.len == ARM_BREAKPOINT_LEN_1)
 518                                 break;
 519                 default:
 520                         return -EINVAL;
 521                 }
 522
 523                 info->address &= ~alignment_mask;
 524                 info->ctrl.len <<= offset;
 525         } else {
 526                 if (info->ctrl.type == ARM_BREAKPOINT_EXECUTE)
 527                         alignment_mask = 0x3;
 528                 else
 529                         alignment_mask = 0x7;
 530                 if (info->address & alignment_mask)
 531                         return -EINVAL;
 532         }
 533
 534         /*
 535          * Disallow per-task kernel breakpoints since these would
 536          * complicate the stepping code.
 537          */
 538         if (info->ctrl.privilege == AARCH64_BREAKPOINT_EL1 && bp->hw.target)
 539                 return -EINVAL;
 540
 541         return 0;
 542 }
 543
 544 /*
 545  * Enable/disable all of the breakpoints active at the specified
 546  * exception level at the register level.
 547  * This is used when single-stepping after a breakpoint exception.
 548  */
 549 static void toggle_bp_registers(int reg, enum dbg_active_el el, int enable)
 550 {
 551         int i, max_slots, privilege;
 552         u32 ctrl;
 553         struct perf_event **slots;
 554
 555         switch (reg) {
 556         case AARCH64_DBG_REG_BCR:
 557                 slots = this_cpu_ptr(bp_on_reg);
 558                 max_slots = core_num_brps;
 559                 break;
 560         case AARCH64_DBG_REG_WCR:
 561                 slots = this_cpu_ptr(wp_on_reg);
 562                 max_slots = core_num_wrps;
 563                 break;
 564         default:
 565                 return;
 566         }
 567
 568         for (i = 0; i < max_slots; ++i) {
 569                 if (!slots[i])
 570                         continue;
 571
 572                 privilege = counter_arch_bp(slots[i])->ctrl.privilege;
 573                 if (debug_exception_level(privilege) != el)
 574                         continue;
 575
 576                 ctrl = read_wb_reg(reg, i);
 577                 if (enable)
 578                         ctrl |= 0x1;
 579                 else
 580                         ctrl &= ~0x1;
 581                 write_wb_reg(reg, i, ctrl);
 582         }
 583 }
 584 NOKPROBE_SYMBOL(toggle_bp_registers);
 585
 586 /*
 587  * Debug exception handlers.
 588  */
 589 static int breakpoint_handler(unsigned long unused, unsigned int esr,
 590                               struct pt_regs *regs)
 591 {
 592         int i, step = 0, *kernel_step;
 593         u32 ctrl_reg;
 594         u64 addr, val;
 595         struct perf_event *bp, **slots;
 596         struct debug_info *debug_info;
 597         struct arch_hw_breakpoint_ctrl ctrl;
 598
 599         slots = this_cpu_ptr(bp_on_reg);
 600         addr = instruction_pointer(regs);
 601         debug_info = &current->thread.debug;
 602
 603         for (i = 0; i < core_num_brps; ++i) {
 604                 rcu_read_lock();
 605
 606                 bp = slots[i];
 607
 608                 if (bp == NULL)
 609                         goto unlock;
 610
 611                 /* Check if the breakpoint value matches. */
 612                 val = read_wb_reg(AARCH64_DBG_REG_BVR, i);
 613                 if (val != (addr & ~0x3))
 614                         goto unlock;
 615
 616                 /* Possible match, check the byte address select to confirm. */
 617                 ctrl_reg = read_wb_reg(AARCH64_DBG_REG_BCR, i);
 618                 decode_ctrl_reg(ctrl_reg, &ctrl);
 619                 if (!((1 << (addr & 0x3)) & ctrl.len))
 620                         goto unlock;
 621
 622                 counter_arch_bp(bp)->trigger = addr;
 623                 perf_bp_event(bp, regs);
 624
 625                 /* Do we need to handle the stepping? */
 626                 if (is_default_overflow_handler(bp))
 627                         step = 1;
 628 unlock:
 629                 rcu_read_unlock();
 630         }
 631
 632         if (!step)
 633                 return 0;
 634
 635         if (user_mode(regs)) {
 636                 debug_info->bps_disabled = 1;
 637                 toggle_bp_registers(AARCH64_DBG_REG_BCR, DBG_ACTIVE_EL0, 0);
 638
 639                 /* If we're already stepping a watchpoint, just return. */
 640                 if (debug_info->wps_disabled)
 641                         return 0;
 642
 643                 if (test_thread_flag(TIF_SINGLESTEP))
 644                         debug_info->suspended_step = 1;
 645                 else
 646                         user_enable_single_step(current);
 647         } else {
 648                 toggle_bp_registers(AARCH64_DBG_REG_BCR, DBG_ACTIVE_EL1, 0);
 649                 kernel_step = this_cpu_ptr(&stepping_kernel_bp);
 650
 651                 if (*kernel_step != ARM_KERNEL_STEP_NONE)
 652                         return 0;
 653
 654                 if (kernel_active_single_step()) {
 655                         *kernel_step = ARM_KERNEL_STEP_SUSPEND;
 656                 } else {
 657                         *kernel_step = ARM_KERNEL_STEP_ACTIVE;
 658                         kernel_enable_single_step(regs);
 659                 }
 660         }
 661
 662         return 0;
 663 }
 664 NOKPROBE_SYMBOL(breakpoint_handler);
 665
 666 static int watchpoint_handler(unsigned long addr, unsigned int esr,
 667                               struct pt_regs *regs)
 668 {
 669         int i, step = 0, *kernel_step, access;
 670         u32 ctrl_reg;
 671         u64 val, alignment_mask;
 672         struct perf_event *wp, **slots;
 673         struct debug_info *debug_info;
 674         struct arch_hw_breakpoint *info;
 675         struct arch_hw_breakpoint_ctrl ctrl;
 676
 677         slots = this_cpu_ptr(wp_on_reg);
 678         debug_info = &current->thread.debug;
 679
 680         for (i = 0; i < core_num_wrps; ++i) {
 681                 rcu_read_lock();
 682
 683                 wp = slots[i];
 684
 685                 if (wp == NULL)
 686                         goto unlock;
 687
 688                 info = counter_arch_bp(wp);
 689                 /* AArch32 watchpoints are either 4 or 8 bytes aligned. */
 690                 if (is_compat_task()) {
 691                         if (info->ctrl.len == ARM_BREAKPOINT_LEN_8)
 692                                 alignment_mask = 0x7;
 693                         else
 694                                 alignment_mask = 0x3;
 695                 } else {
 696                         alignment_mask = 0x7;
 697                 }
 698
 699                 /* Check if the watchpoint value matches. */
 700                 val = read_wb_reg(AARCH64_DBG_REG_WVR, i);
 701                 if (val != (untagged_addr(addr) & ~alignment_mask))
 702                         goto unlock;
 703
 704                 /* Possible match, check the byte address select to confirm. */
 705                 ctrl_reg = read_wb_reg(AARCH64_DBG_REG_WCR, i);
 706                 decode_ctrl_reg(ctrl_reg, &ctrl);
 707                 if (!((1 << (addr & alignment_mask)) & ctrl.len))
 708                         goto unlock;
 709
 710                 /*
 711                  * Check that the access type matches.
 712                  * 0 => load, otherwise => store
 713                  */
 714                 access = (esr & AARCH64_ESR_ACCESS_MASK) ? HW_BREAKPOINT_W :
 715                          HW_BREAKPOINT_R;
 716                 if (!(access & hw_breakpoint_type(wp)))
 717                         goto unlock;
 718
 719                 info->trigger = addr;
 720                 perf_bp_event(wp, regs);
 721
 722                 /* Do we need to handle the stepping? */
 723                 if (is_default_overflow_handler(wp))
 724                         step = 1;
 725
 726 unlock:
 727                 rcu_read_unlock();
 728         }
 729
 730         if (!step)
 731                 return 0;
 732
 733         /*
 734          * We always disable EL0 watchpoints because the kernel can
 735          * cause these to fire via an unprivileged access.
 736          */
 737         toggle_bp_registers(AARCH64_DBG_REG_WCR, DBG_ACTIVE_EL0, 0);
 738
 739         if (user_mode(regs)) {
 740                 debug_info->wps_disabled = 1;
 741
 742                 /* If we're already stepping a breakpoint, just return. */
 743                 if (debug_info->bps_disabled)
 744                         return 0;
 745
 746                 if (test_thread_flag(TIF_SINGLESTEP))
 747                         debug_info->suspended_step = 1;
 748                 else
 749                         user_enable_single_step(current);
 750         } else {
 751                 toggle_bp_registers(AARCH64_DBG_REG_WCR, DBG_ACTIVE_EL1, 0);
 752                 kernel_step = this_cpu_ptr(&stepping_kernel_bp);
 753
 754                 if (*kernel_step != ARM_KERNEL_STEP_NONE)
 755                         return 0;
 756
 757                 if (kernel_active_single_step()) {
 758                         *kernel_step = ARM_KERNEL_STEP_SUSPEND;
 759                 } else {
 760                         *kernel_step = ARM_KERNEL_STEP_ACTIVE;
 761                         kernel_enable_single_step(regs);
 762                 }
 763         }
 764
 765         return 0;
 766 }
 767 NOKPROBE_SYMBOL(watchpoint_handler);
 768
 769 /*
 770  * Handle single-step exception.
 771  */
 772 int reinstall_suspended_bps(struct pt_regs *regs)
 773 {
 774         struct debug_info *debug_info = &current->thread.debug;
 775         int handled_exception = 0, *kernel_step;
 776
 777         kernel_step = this_cpu_ptr(&stepping_kernel_bp);
 778
 779         /*
 780          * Called from single-step exception handler.
 781          * Return 0 if execution can resume, 1 if a SIGTRAP should be
 782          * reported.
 783          */
 784         if (user_mode(regs)) {
 785                 if (debug_info->bps_disabled) {
 786                         debug_info->bps_disabled = 0;
 787                         toggle_bp_registers(AARCH64_DBG_REG_BCR, DBG_ACTIVE_EL0, 1);
 788                         handled_exception = 1;
 789                 }
 790
 791                 if (debug_info->wps_disabled) {
 792                         debug_info->wps_disabled = 0;
 793                         toggle_bp_registers(AARCH64_DBG_REG_WCR, DBG_ACTIVE_EL0, 1);
 794                         handled_exception = 1;
 795                 }
 796
 797                 if (handled_exception) {
 798                         if (debug_info->suspended_step) {
 799                                 debug_info->suspended_step = 0;
 800                                 /* Allow exception handling to fall-through. */
 801                                 handled_exception = 0;
 802                         } else {
 803                                 user_disable_single_step(current);
 804                         }
 805                 }
 806         } else if (*kernel_step != ARM_KERNEL_STEP_NONE) {
 807                 toggle_bp_registers(AARCH64_DBG_REG_BCR, DBG_ACTIVE_EL1, 1);
 808                 toggle_bp_registers(AARCH64_DBG_REG_WCR, DBG_ACTIVE_EL1, 1);
 809
 810                 if (!debug_info->wps_disabled)
 811                         toggle_bp_registers(AARCH64_DBG_REG_WCR, DBG_ACTIVE_EL0, 1);
 812
 813                 if (*kernel_step != ARM_KERNEL_STEP_SUSPEND) {
 814                         kernel_disable_single_step();
 815                         handled_exception = 1;
 816                 } else {
 817                         handled_exception = 0;
 818                 }
 819
 820                 *kernel_step = ARM_KERNEL_STEP_NONE;
 821         }
 822
 823         return !handled_exception;
 824 }
 825 NOKPROBE_SYMBOL(reinstall_suspended_bps);
 826
 827 /*
 828  * Context-switcher for restoring suspended breakpoints.
 829  */
 830 void hw_breakpoint_thread_switch(struct task_struct *next)
 831 {
 832         /*
 833          *           current        next
 834          * disabled: 0              0     => The usual case, NOTIFY_DONE
 835          *           0              1     => Disable the registers
 836          *           1              0     => Enable the registers
 837          *           1              1     => NOTIFY_DONE. per-task bps will
 838          *                                   get taken care of by perf.
 839          */
 840
 841         struct debug_info *current_debug_info, *next_debug_info;
 842
 843         current_debug_info = &current->thread.debug;
 844         next_debug_info = &next->thread.debug;
 845
 846         /* Update breakpoints. */
 847         if (current_debug_info->bps_disabled != next_debug_info->bps_disabled)
 848                 toggle_bp_registers(AARCH64_DBG_REG_BCR,
 849                                     DBG_ACTIVE_EL0,
 850                                     !next_debug_info->bps_disabled);
 851
 852         /* Update watchpoints. */
 853         if (current_debug_info->wps_disabled != next_debug_info->wps_disabled)
 854                 toggle_bp_registers(AARCH64_DBG_REG_WCR,
 855                                     DBG_ACTIVE_EL0,
 856                                     !next_debug_info->wps_disabled);
 857 }
 858
 859 /*
 860  * CPU initialisation.
 861  */
 862 static int hw_breakpoint_reset(unsigned int cpu)
 863 {
 864         int i;
 865         struct perf_event **slots;
 866         /*
 867          * When a CPU goes through cold-boot, it does not have any installed
 868          * slot, so it is safe to share the same function for restoring and
 869          * resetting breakpoints; when a CPU is hotplugged in, it goes
 870          * through the slots, which are all empty, hence it just resets control
 871          * and value for debug registers.
 872          * When this function is triggered on warm-boot through a CPU PM
 873          * notifier some slots might be initialized; if so they are
 874          * reprogrammed according to the debug slots content.
 875          */
 876         for (slots = this_cpu_ptr(bp_on_reg), i = 0; i < core_num_brps; ++i) {
 877                 if (slots[i]) {
 878                         hw_breakpoint_control(slots[i], HW_BREAKPOINT_RESTORE);
 879                 } else {
 880                         write_wb_reg(AARCH64_DBG_REG_BCR, i, 0UL);
 881                         write_wb_reg(AARCH64_DBG_REG_BVR, i, 0UL);
 882                 }
 883         }
 884
 885         for (slots = this_cpu_ptr(wp_on_reg), i = 0; i < core_num_wrps; ++i) {
 886                 if (slots[i]) {
 887                         hw_breakpoint_control(slots[i], HW_BREAKPOINT_RESTORE);
 888                 } else {
 889                         write_wb_reg(AARCH64_DBG_REG_WCR, i, 0UL);
 890                         write_wb_reg(AARCH64_DBG_REG_WVR, i, 0UL);
 891                 }
 892         }
 893
 894         return 0;
 895 }
 896
 897 #ifdef CONFIG_CPU_PM
 898 extern void cpu_suspend_set_dbg_restorer(int (*hw_bp_restore)(unsigned int));
 899 #else
 900 static inline void cpu_suspend_set_dbg_restorer(int (*hw_bp_restore)(unsigned int))
 901 {
 902 }
 903 #endif
 904
 905 /*
 906  * One-time initialisation.
 907  */
 908 static int __init arch_hw_breakpoint_init(void)
 909 {
 910         int ret;
 911
 912         core_num_brps = get_num_brps();
 913         core_num_wrps = get_num_wrps();
 914
 915         pr_info("found %d breakpoint and %d watchpoint registers.\n",
 916                 core_num_brps, core_num_wrps);
 917
 918         /* Register debug fault handlers. */
 919         hook_debug_fault_code(DBG_ESR_EVT_HWBP, breakpoint_handler, SIGTRAP,
 920                               TRAP_HWBKPT, "hw-breakpoint handler");
 921         hook_debug_fault_code(DBG_ESR_EVT_HWWP, watchpoint_handler, SIGTRAP,
 922                               TRAP_HWBKPT, "hw-watchpoint handler");
 923
 924         /*
 925          * Reset the breakpoint resources. We assume that a halting
 926          * debugger will leave the world in a nice state for us.
 927          */
 928         ret = cpuhp_setup_state(CPUHP_AP_PERF_ARM_HW_BREAKPOINT_STARTING,
 929                           "CPUHP_AP_PERF_ARM_HW_BREAKPOINT_STARTING",
 930                           hw_breakpoint_reset, NULL);
 931         if (ret)
 932                 pr_err("failed to register CPU hotplug notifier: %d\n", ret);
 933
 934         /* Register cpu_suspend hw breakpoint restore hook */
 935         cpu_suspend_set_dbg_restorer(hw_breakpoint_reset);
 936
 937         return ret;
 938 }
 939 arch_initcall(arch_hw_breakpoint_init);
 940
 941 void hw_breakpoint_pmu_read(struct perf_event *bp)
 942 {
 943 }
 944
 945 /*
 946  * Dummy function to register with die_notifier.
 947  */
 948 int hw_breakpoint_exceptions_notify(struct notifier_block *unused,
 949                                     unsigned long val, void *data)
 950 {
 951         return NOTIFY_DONE;
 952 }