2 * HW_breakpoint: a unified kernel/user-space hardware breakpoint facility,
3 * using the CPU's debug registers.
5 * Copyright (C) 2012 ARM Limited
6 * Author: Will Deacon <will.deacon@arm.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program. If not, see <http://www.gnu.org/licenses/>.
21 #define pr_fmt(fmt) "hw-breakpoint: " fmt
23 #include <linux/compat.h>
24 #include <linux/cpu_pm.h>
25 #include <linux/errno.h>
26 #include <linux/hw_breakpoint.h>
27 #include <linux/kprobes.h>
28 #include <linux/perf_event.h>
29 #include <linux/ptrace.h>
30 #include <linux/smp.h>
32 #include <asm/compat.h>
33 #include <asm/current.h>
34 #include <asm/debug-monitors.h>
35 #include <asm/hw_breakpoint.h>
36 #include <asm/traps.h>
37 #include <asm/cputype.h>
38 #include <asm/system_misc.h>
39 #include <asm/uaccess.h>
41 /* Breakpoint currently in use for each BRP. */
42 static DEFINE_PER_CPU(struct perf_event *, bp_on_reg[ARM_MAX_BRP]);
44 /* Watchpoint currently in use for each WRP. */
45 static DEFINE_PER_CPU(struct perf_event *, wp_on_reg[ARM_MAX_WRP]);
47 /* Currently stepping a per-CPU kernel breakpoint. */
48 static DEFINE_PER_CPU(int, stepping_kernel_bp);
50 /* Number of BRP/WRP registers on this CPU. */
51 static int core_num_brps;
52 static int core_num_wrps;
54 int hw_breakpoint_slots(int type)
57 * We can be called early, so don't rely on
58 * our static variables being initialised.
62 return get_num_brps();
64 return get_num_wrps();
66 pr_warning("unknown slot type: %d\n", type);
71 #define READ_WB_REG_CASE(OFF, N, REG, VAL) \
73 AARCH64_DBG_READ(N, REG, VAL); \
76 #define WRITE_WB_REG_CASE(OFF, N, REG, VAL) \
78 AARCH64_DBG_WRITE(N, REG, VAL); \
81 #define GEN_READ_WB_REG_CASES(OFF, REG, VAL) \
82 READ_WB_REG_CASE(OFF, 0, REG, VAL); \
83 READ_WB_REG_CASE(OFF, 1, REG, VAL); \
84 READ_WB_REG_CASE(OFF, 2, REG, VAL); \
85 READ_WB_REG_CASE(OFF, 3, REG, VAL); \
86 READ_WB_REG_CASE(OFF, 4, REG, VAL); \
87 READ_WB_REG_CASE(OFF, 5, REG, VAL); \
88 READ_WB_REG_CASE(OFF, 6, REG, VAL); \
89 READ_WB_REG_CASE(OFF, 7, REG, VAL); \
90 READ_WB_REG_CASE(OFF, 8, REG, VAL); \
91 READ_WB_REG_CASE(OFF, 9, REG, VAL); \
92 READ_WB_REG_CASE(OFF, 10, REG, VAL); \
93 READ_WB_REG_CASE(OFF, 11, REG, VAL); \
94 READ_WB_REG_CASE(OFF, 12, REG, VAL); \
95 READ_WB_REG_CASE(OFF, 13, REG, VAL); \
96 READ_WB_REG_CASE(OFF, 14, REG, VAL); \
97 READ_WB_REG_CASE(OFF, 15, REG, VAL)
99 #define GEN_WRITE_WB_REG_CASES(OFF, REG, VAL) \
100 WRITE_WB_REG_CASE(OFF, 0, REG, VAL); \
101 WRITE_WB_REG_CASE(OFF, 1, REG, VAL); \
102 WRITE_WB_REG_CASE(OFF, 2, REG, VAL); \
103 WRITE_WB_REG_CASE(OFF, 3, REG, VAL); \
104 WRITE_WB_REG_CASE(OFF, 4, REG, VAL); \
105 WRITE_WB_REG_CASE(OFF, 5, REG, VAL); \
106 WRITE_WB_REG_CASE(OFF, 6, REG, VAL); \
107 WRITE_WB_REG_CASE(OFF, 7, REG, VAL); \
108 WRITE_WB_REG_CASE(OFF, 8, REG, VAL); \
109 WRITE_WB_REG_CASE(OFF, 9, REG, VAL); \
110 WRITE_WB_REG_CASE(OFF, 10, REG, VAL); \
111 WRITE_WB_REG_CASE(OFF, 11, REG, VAL); \
112 WRITE_WB_REG_CASE(OFF, 12, REG, VAL); \
113 WRITE_WB_REG_CASE(OFF, 13, REG, VAL); \
114 WRITE_WB_REG_CASE(OFF, 14, REG, VAL); \
115 WRITE_WB_REG_CASE(OFF, 15, REG, VAL)
117 static u64 read_wb_reg(int reg, int n)
122 GEN_READ_WB_REG_CASES(AARCH64_DBG_REG_BVR, AARCH64_DBG_REG_NAME_BVR, val);
123 GEN_READ_WB_REG_CASES(AARCH64_DBG_REG_BCR, AARCH64_DBG_REG_NAME_BCR, val);
124 GEN_READ_WB_REG_CASES(AARCH64_DBG_REG_WVR, AARCH64_DBG_REG_NAME_WVR, val);
125 GEN_READ_WB_REG_CASES(AARCH64_DBG_REG_WCR, AARCH64_DBG_REG_NAME_WCR, val);
127 pr_warning("attempt to read from unknown breakpoint register %d\n", n);
132 NOKPROBE_SYMBOL(read_wb_reg);
134 static void write_wb_reg(int reg, int n, u64 val)
137 GEN_WRITE_WB_REG_CASES(AARCH64_DBG_REG_BVR, AARCH64_DBG_REG_NAME_BVR, val);
138 GEN_WRITE_WB_REG_CASES(AARCH64_DBG_REG_BCR, AARCH64_DBG_REG_NAME_BCR, val);
139 GEN_WRITE_WB_REG_CASES(AARCH64_DBG_REG_WVR, AARCH64_DBG_REG_NAME_WVR, val);
140 GEN_WRITE_WB_REG_CASES(AARCH64_DBG_REG_WCR, AARCH64_DBG_REG_NAME_WCR, val);
142 pr_warning("attempt to write to unknown breakpoint register %d\n", n);
146 NOKPROBE_SYMBOL(write_wb_reg);
149 * Convert a breakpoint privilege level to the corresponding exception
152 static enum dbg_active_el debug_exception_level(int privilege)
155 case AARCH64_BREAKPOINT_EL0:
156 return DBG_ACTIVE_EL0;
157 case AARCH64_BREAKPOINT_EL1:
158 return DBG_ACTIVE_EL1;
160 pr_warning("invalid breakpoint privilege level %d\n", privilege);
164 NOKPROBE_SYMBOL(debug_exception_level);
166 enum hw_breakpoint_ops {
167 HW_BREAKPOINT_INSTALL,
168 HW_BREAKPOINT_UNINSTALL,
169 HW_BREAKPOINT_RESTORE
172 static int is_compat_bp(struct perf_event *bp)
174 struct task_struct *tsk = bp->hw.target;
177 * tsk can be NULL for per-cpu (non-ptrace) breakpoints.
178 * In this case, use the native interface, since we don't have
179 * the notion of a "compat CPU" and could end up relying on
180 * deprecated behaviour if we use unaligned watchpoints in
183 return tsk && is_compat_thread(task_thread_info(tsk));
187 * hw_breakpoint_slot_setup - Find and setup a perf slot according to
190 * @slots: pointer to array of slots
191 * @max_slots: max number of slots
192 * @bp: perf_event to setup
193 * @ops: operation to be carried out on the slot
196 * slot index on success
197 * -ENOSPC if no slot is available/matches
198 * -EINVAL on wrong operations parameter
200 static int hw_breakpoint_slot_setup(struct perf_event **slots, int max_slots,
201 struct perf_event *bp,
202 enum hw_breakpoint_ops ops)
205 struct perf_event **slot;
207 for (i = 0; i < max_slots; ++i) {
210 case HW_BREAKPOINT_INSTALL:
216 case HW_BREAKPOINT_UNINSTALL:
222 case HW_BREAKPOINT_RESTORE:
227 pr_warn_once("Unhandled hw breakpoint ops %d\n", ops);
234 static int hw_breakpoint_control(struct perf_event *bp,
235 enum hw_breakpoint_ops ops)
237 struct arch_hw_breakpoint *info = counter_arch_bp(bp);
238 struct perf_event **slots;
239 struct debug_info *debug_info = ¤t->thread.debug;
240 int i, max_slots, ctrl_reg, val_reg, reg_enable;
241 enum dbg_active_el dbg_el = debug_exception_level(info->ctrl.privilege);
244 if (info->ctrl.type == ARM_BREAKPOINT_EXECUTE) {
246 ctrl_reg = AARCH64_DBG_REG_BCR;
247 val_reg = AARCH64_DBG_REG_BVR;
248 slots = this_cpu_ptr(bp_on_reg);
249 max_slots = core_num_brps;
250 reg_enable = !debug_info->bps_disabled;
253 ctrl_reg = AARCH64_DBG_REG_WCR;
254 val_reg = AARCH64_DBG_REG_WVR;
255 slots = this_cpu_ptr(wp_on_reg);
256 max_slots = core_num_wrps;
257 reg_enable = !debug_info->wps_disabled;
260 i = hw_breakpoint_slot_setup(slots, max_slots, bp, ops);
262 if (WARN_ONCE(i < 0, "Can't find any breakpoint slot"))
266 case HW_BREAKPOINT_INSTALL:
268 * Ensure debug monitors are enabled at the correct exception
271 enable_debug_monitors(dbg_el);
273 case HW_BREAKPOINT_RESTORE:
274 /* Setup the address register. */
275 write_wb_reg(val_reg, i, info->address);
277 /* Setup the control register. */
278 ctrl = encode_ctrl_reg(info->ctrl);
279 write_wb_reg(ctrl_reg, i,
280 reg_enable ? ctrl | 0x1 : ctrl & ~0x1);
282 case HW_BREAKPOINT_UNINSTALL:
283 /* Reset the control register. */
284 write_wb_reg(ctrl_reg, i, 0);
287 * Release the debug monitors for the correct exception
290 disable_debug_monitors(dbg_el);
298 * Install a perf counter breakpoint.
300 int arch_install_hw_breakpoint(struct perf_event *bp)
302 return hw_breakpoint_control(bp, HW_BREAKPOINT_INSTALL);
305 void arch_uninstall_hw_breakpoint(struct perf_event *bp)
307 hw_breakpoint_control(bp, HW_BREAKPOINT_UNINSTALL);
310 static int get_hbp_len(u8 hbp_len)
312 unsigned int len_in_bytes = 0;
315 case ARM_BREAKPOINT_LEN_1:
318 case ARM_BREAKPOINT_LEN_2:
321 case ARM_BREAKPOINT_LEN_4:
324 case ARM_BREAKPOINT_LEN_8:
333 * Check whether bp virtual address is in kernel space.
335 int arch_check_bp_in_kernelspace(struct perf_event *bp)
339 struct arch_hw_breakpoint *info = counter_arch_bp(bp);
342 len = get_hbp_len(info->ctrl.len);
344 return (va >= TASK_SIZE) && ((va + len - 1) >= TASK_SIZE);
348 * Extract generic type and length encodings from an arch_hw_breakpoint_ctrl.
349 * Hopefully this will disappear when ptrace can bypass the conversion
350 * to generic breakpoint descriptions.
352 int arch_bp_generic_fields(struct arch_hw_breakpoint_ctrl ctrl,
353 int *gen_len, int *gen_type)
357 case ARM_BREAKPOINT_EXECUTE:
358 *gen_type = HW_BREAKPOINT_X;
360 case ARM_BREAKPOINT_LOAD:
361 *gen_type = HW_BREAKPOINT_R;
363 case ARM_BREAKPOINT_STORE:
364 *gen_type = HW_BREAKPOINT_W;
366 case ARM_BREAKPOINT_LOAD | ARM_BREAKPOINT_STORE:
367 *gen_type = HW_BREAKPOINT_RW;
375 case ARM_BREAKPOINT_LEN_1:
376 *gen_len = HW_BREAKPOINT_LEN_1;
378 case ARM_BREAKPOINT_LEN_2:
379 *gen_len = HW_BREAKPOINT_LEN_2;
381 case ARM_BREAKPOINT_LEN_4:
382 *gen_len = HW_BREAKPOINT_LEN_4;
384 case ARM_BREAKPOINT_LEN_8:
385 *gen_len = HW_BREAKPOINT_LEN_8;
395 * Construct an arch_hw_breakpoint from a perf_event.
397 static int arch_build_bp_info(struct perf_event *bp)
399 struct arch_hw_breakpoint *info = counter_arch_bp(bp);
402 switch (bp->attr.bp_type) {
403 case HW_BREAKPOINT_X:
404 info->ctrl.type = ARM_BREAKPOINT_EXECUTE;
406 case HW_BREAKPOINT_R:
407 info->ctrl.type = ARM_BREAKPOINT_LOAD;
409 case HW_BREAKPOINT_W:
410 info->ctrl.type = ARM_BREAKPOINT_STORE;
412 case HW_BREAKPOINT_RW:
413 info->ctrl.type = ARM_BREAKPOINT_LOAD | ARM_BREAKPOINT_STORE;
420 switch (bp->attr.bp_len) {
421 case HW_BREAKPOINT_LEN_1:
422 info->ctrl.len = ARM_BREAKPOINT_LEN_1;
424 case HW_BREAKPOINT_LEN_2:
425 info->ctrl.len = ARM_BREAKPOINT_LEN_2;
427 case HW_BREAKPOINT_LEN_4:
428 info->ctrl.len = ARM_BREAKPOINT_LEN_4;
430 case HW_BREAKPOINT_LEN_8:
431 info->ctrl.len = ARM_BREAKPOINT_LEN_8;
438 * On AArch64, we only permit breakpoints of length 4, whereas
439 * AArch32 also requires breakpoints of length 2 for Thumb.
440 * Watchpoints can be of length 1, 2, 4 or 8 bytes.
442 if (info->ctrl.type == ARM_BREAKPOINT_EXECUTE) {
443 if (is_compat_bp(bp)) {
444 if (info->ctrl.len != ARM_BREAKPOINT_LEN_2 &&
445 info->ctrl.len != ARM_BREAKPOINT_LEN_4)
447 } else if (info->ctrl.len != ARM_BREAKPOINT_LEN_4) {
449 * FIXME: Some tools (I'm looking at you perf) assume
450 * that breakpoints should be sizeof(long). This
451 * is nonsense. For now, we fix up the parameter
452 * but we should probably return -EINVAL instead.
454 info->ctrl.len = ARM_BREAKPOINT_LEN_4;
459 info->address = bp->attr.bp_addr;
463 * Note that we disallow combined EL0/EL1 breakpoints because
464 * that would complicate the stepping code.
466 if (arch_check_bp_in_kernelspace(bp))
467 info->ctrl.privilege = AARCH64_BREAKPOINT_EL1;
469 info->ctrl.privilege = AARCH64_BREAKPOINT_EL0;
472 info->ctrl.enabled = !bp->attr.disabled;
478 * Validate the arch-specific HW Breakpoint register settings.
480 int arch_validate_hwbkpt_settings(struct perf_event *bp)
482 struct arch_hw_breakpoint *info = counter_arch_bp(bp);
484 u64 alignment_mask, offset;
486 /* Build the arch_hw_breakpoint. */
487 ret = arch_build_bp_info(bp);
492 * Check address alignment.
493 * We don't do any clever alignment correction for watchpoints
494 * because using 64-bit unaligned addresses is deprecated for
497 * AArch32 tasks expect some simple alignment fixups, so emulate
500 if (is_compat_bp(bp)) {
501 if (info->ctrl.len == ARM_BREAKPOINT_LEN_8)
502 alignment_mask = 0x7;
504 alignment_mask = 0x3;
505 offset = info->address & alignment_mask;
512 /* Allow halfword watchpoints and breakpoints. */
513 if (info->ctrl.len == ARM_BREAKPOINT_LEN_2)
516 /* Allow single byte watchpoint. */
517 if (info->ctrl.len == ARM_BREAKPOINT_LEN_1)
523 info->address &= ~alignment_mask;
524 info->ctrl.len <<= offset;
526 if (info->ctrl.type == ARM_BREAKPOINT_EXECUTE)
527 alignment_mask = 0x3;
529 alignment_mask = 0x7;
530 if (info->address & alignment_mask)
535 * Disallow per-task kernel breakpoints since these would
536 * complicate the stepping code.
538 if (info->ctrl.privilege == AARCH64_BREAKPOINT_EL1 && bp->hw.target)
545 * Enable/disable all of the breakpoints active at the specified
546 * exception level at the register level.
547 * This is used when single-stepping after a breakpoint exception.
549 static void toggle_bp_registers(int reg, enum dbg_active_el el, int enable)
551 int i, max_slots, privilege;
553 struct perf_event **slots;
556 case AARCH64_DBG_REG_BCR:
557 slots = this_cpu_ptr(bp_on_reg);
558 max_slots = core_num_brps;
560 case AARCH64_DBG_REG_WCR:
561 slots = this_cpu_ptr(wp_on_reg);
562 max_slots = core_num_wrps;
568 for (i = 0; i < max_slots; ++i) {
572 privilege = counter_arch_bp(slots[i])->ctrl.privilege;
573 if (debug_exception_level(privilege) != el)
576 ctrl = read_wb_reg(reg, i);
581 write_wb_reg(reg, i, ctrl);
584 NOKPROBE_SYMBOL(toggle_bp_registers);
587 * Debug exception handlers.
589 static int breakpoint_handler(unsigned long unused, unsigned int esr,
590 struct pt_regs *regs)
592 int i, step = 0, *kernel_step;
595 struct perf_event *bp, **slots;
596 struct debug_info *debug_info;
597 struct arch_hw_breakpoint_ctrl ctrl;
599 slots = this_cpu_ptr(bp_on_reg);
600 addr = instruction_pointer(regs);
601 debug_info = ¤t->thread.debug;
603 for (i = 0; i < core_num_brps; ++i) {
611 /* Check if the breakpoint value matches. */
612 val = read_wb_reg(AARCH64_DBG_REG_BVR, i);
613 if (val != (addr & ~0x3))
616 /* Possible match, check the byte address select to confirm. */
617 ctrl_reg = read_wb_reg(AARCH64_DBG_REG_BCR, i);
618 decode_ctrl_reg(ctrl_reg, &ctrl);
619 if (!((1 << (addr & 0x3)) & ctrl.len))
622 counter_arch_bp(bp)->trigger = addr;
623 perf_bp_event(bp, regs);
625 /* Do we need to handle the stepping? */
626 if (is_default_overflow_handler(bp))
635 if (user_mode(regs)) {
636 debug_info->bps_disabled = 1;
637 toggle_bp_registers(AARCH64_DBG_REG_BCR, DBG_ACTIVE_EL0, 0);
639 /* If we're already stepping a watchpoint, just return. */
640 if (debug_info->wps_disabled)
643 if (test_thread_flag(TIF_SINGLESTEP))
644 debug_info->suspended_step = 1;
646 user_enable_single_step(current);
648 toggle_bp_registers(AARCH64_DBG_REG_BCR, DBG_ACTIVE_EL1, 0);
649 kernel_step = this_cpu_ptr(&stepping_kernel_bp);
651 if (*kernel_step != ARM_KERNEL_STEP_NONE)
654 if (kernel_active_single_step()) {
655 *kernel_step = ARM_KERNEL_STEP_SUSPEND;
657 *kernel_step = ARM_KERNEL_STEP_ACTIVE;
658 kernel_enable_single_step(regs);
664 NOKPROBE_SYMBOL(breakpoint_handler);
666 static int watchpoint_handler(unsigned long addr, unsigned int esr,
667 struct pt_regs *regs)
669 int i, step = 0, *kernel_step, access;
671 u64 val, alignment_mask;
672 struct perf_event *wp, **slots;
673 struct debug_info *debug_info;
674 struct arch_hw_breakpoint *info;
675 struct arch_hw_breakpoint_ctrl ctrl;
677 slots = this_cpu_ptr(wp_on_reg);
678 debug_info = ¤t->thread.debug;
680 for (i = 0; i < core_num_wrps; ++i) {
688 info = counter_arch_bp(wp);
689 /* AArch32 watchpoints are either 4 or 8 bytes aligned. */
690 if (is_compat_task()) {
691 if (info->ctrl.len == ARM_BREAKPOINT_LEN_8)
692 alignment_mask = 0x7;
694 alignment_mask = 0x3;
696 alignment_mask = 0x7;
699 /* Check if the watchpoint value matches. */
700 val = read_wb_reg(AARCH64_DBG_REG_WVR, i);
701 if (val != (untagged_addr(addr) & ~alignment_mask))
704 /* Possible match, check the byte address select to confirm. */
705 ctrl_reg = read_wb_reg(AARCH64_DBG_REG_WCR, i);
706 decode_ctrl_reg(ctrl_reg, &ctrl);
707 if (!((1 << (addr & alignment_mask)) & ctrl.len))
711 * Check that the access type matches.
712 * 0 => load, otherwise => store
714 access = (esr & AARCH64_ESR_ACCESS_MASK) ? HW_BREAKPOINT_W :
716 if (!(access & hw_breakpoint_type(wp)))
719 info->trigger = addr;
720 perf_bp_event(wp, regs);
722 /* Do we need to handle the stepping? */
723 if (is_default_overflow_handler(wp))
734 * We always disable EL0 watchpoints because the kernel can
735 * cause these to fire via an unprivileged access.
737 toggle_bp_registers(AARCH64_DBG_REG_WCR, DBG_ACTIVE_EL0, 0);
739 if (user_mode(regs)) {
740 debug_info->wps_disabled = 1;
742 /* If we're already stepping a breakpoint, just return. */
743 if (debug_info->bps_disabled)
746 if (test_thread_flag(TIF_SINGLESTEP))
747 debug_info->suspended_step = 1;
749 user_enable_single_step(current);
751 toggle_bp_registers(AARCH64_DBG_REG_WCR, DBG_ACTIVE_EL1, 0);
752 kernel_step = this_cpu_ptr(&stepping_kernel_bp);
754 if (*kernel_step != ARM_KERNEL_STEP_NONE)
757 if (kernel_active_single_step()) {
758 *kernel_step = ARM_KERNEL_STEP_SUSPEND;
760 *kernel_step = ARM_KERNEL_STEP_ACTIVE;
761 kernel_enable_single_step(regs);
767 NOKPROBE_SYMBOL(watchpoint_handler);
770 * Handle single-step exception.
772 int reinstall_suspended_bps(struct pt_regs *regs)
774 struct debug_info *debug_info = ¤t->thread.debug;
775 int handled_exception = 0, *kernel_step;
777 kernel_step = this_cpu_ptr(&stepping_kernel_bp);
780 * Called from single-step exception handler.
781 * Return 0 if execution can resume, 1 if a SIGTRAP should be
784 if (user_mode(regs)) {
785 if (debug_info->bps_disabled) {
786 debug_info->bps_disabled = 0;
787 toggle_bp_registers(AARCH64_DBG_REG_BCR, DBG_ACTIVE_EL0, 1);
788 handled_exception = 1;
791 if (debug_info->wps_disabled) {
792 debug_info->wps_disabled = 0;
793 toggle_bp_registers(AARCH64_DBG_REG_WCR, DBG_ACTIVE_EL0, 1);
794 handled_exception = 1;
797 if (handled_exception) {
798 if (debug_info->suspended_step) {
799 debug_info->suspended_step = 0;
800 /* Allow exception handling to fall-through. */
801 handled_exception = 0;
803 user_disable_single_step(current);
806 } else if (*kernel_step != ARM_KERNEL_STEP_NONE) {
807 toggle_bp_registers(AARCH64_DBG_REG_BCR, DBG_ACTIVE_EL1, 1);
808 toggle_bp_registers(AARCH64_DBG_REG_WCR, DBG_ACTIVE_EL1, 1);
810 if (!debug_info->wps_disabled)
811 toggle_bp_registers(AARCH64_DBG_REG_WCR, DBG_ACTIVE_EL0, 1);
813 if (*kernel_step != ARM_KERNEL_STEP_SUSPEND) {
814 kernel_disable_single_step();
815 handled_exception = 1;
817 handled_exception = 0;
820 *kernel_step = ARM_KERNEL_STEP_NONE;
823 return !handled_exception;
825 NOKPROBE_SYMBOL(reinstall_suspended_bps);
828 * Context-switcher for restoring suspended breakpoints.
830 void hw_breakpoint_thread_switch(struct task_struct *next)
834 * disabled: 0 0 => The usual case, NOTIFY_DONE
835 * 0 1 => Disable the registers
836 * 1 0 => Enable the registers
837 * 1 1 => NOTIFY_DONE. per-task bps will
838 * get taken care of by perf.
841 struct debug_info *current_debug_info, *next_debug_info;
843 current_debug_info = ¤t->thread.debug;
844 next_debug_info = &next->thread.debug;
846 /* Update breakpoints. */
847 if (current_debug_info->bps_disabled != next_debug_info->bps_disabled)
848 toggle_bp_registers(AARCH64_DBG_REG_BCR,
850 !next_debug_info->bps_disabled);
852 /* Update watchpoints. */
853 if (current_debug_info->wps_disabled != next_debug_info->wps_disabled)
854 toggle_bp_registers(AARCH64_DBG_REG_WCR,
856 !next_debug_info->wps_disabled);
860 * CPU initialisation.
862 static int hw_breakpoint_reset(unsigned int cpu)
865 struct perf_event **slots;
867 * When a CPU goes through cold-boot, it does not have any installed
868 * slot, so it is safe to share the same function for restoring and
869 * resetting breakpoints; when a CPU is hotplugged in, it goes
870 * through the slots, which are all empty, hence it just resets control
871 * and value for debug registers.
872 * When this function is triggered on warm-boot through a CPU PM
873 * notifier some slots might be initialized; if so they are
874 * reprogrammed according to the debug slots content.
876 for (slots = this_cpu_ptr(bp_on_reg), i = 0; i < core_num_brps; ++i) {
878 hw_breakpoint_control(slots[i], HW_BREAKPOINT_RESTORE);
880 write_wb_reg(AARCH64_DBG_REG_BCR, i, 0UL);
881 write_wb_reg(AARCH64_DBG_REG_BVR, i, 0UL);
885 for (slots = this_cpu_ptr(wp_on_reg), i = 0; i < core_num_wrps; ++i) {
887 hw_breakpoint_control(slots[i], HW_BREAKPOINT_RESTORE);
889 write_wb_reg(AARCH64_DBG_REG_WCR, i, 0UL);
890 write_wb_reg(AARCH64_DBG_REG_WVR, i, 0UL);
898 extern void cpu_suspend_set_dbg_restorer(int (*hw_bp_restore)(unsigned int));
900 static inline void cpu_suspend_set_dbg_restorer(int (*hw_bp_restore)(unsigned int))
906 * One-time initialisation.
908 static int __init arch_hw_breakpoint_init(void)
912 core_num_brps = get_num_brps();
913 core_num_wrps = get_num_wrps();
915 pr_info("found %d breakpoint and %d watchpoint registers.\n",
916 core_num_brps, core_num_wrps);
918 /* Register debug fault handlers. */
919 hook_debug_fault_code(DBG_ESR_EVT_HWBP, breakpoint_handler, SIGTRAP,
920 TRAP_HWBKPT, "hw-breakpoint handler");
921 hook_debug_fault_code(DBG_ESR_EVT_HWWP, watchpoint_handler, SIGTRAP,
922 TRAP_HWBKPT, "hw-watchpoint handler");
925 * Reset the breakpoint resources. We assume that a halting
926 * debugger will leave the world in a nice state for us.
928 ret = cpuhp_setup_state(CPUHP_AP_PERF_ARM_HW_BREAKPOINT_STARTING,
929 "CPUHP_AP_PERF_ARM_HW_BREAKPOINT_STARTING",
930 hw_breakpoint_reset, NULL);
932 pr_err("failed to register CPU hotplug notifier: %d\n", ret);
934 /* Register cpu_suspend hw breakpoint restore hook */
935 cpu_suspend_set_dbg_restorer(hw_breakpoint_reset);
939 arch_initcall(arch_hw_breakpoint_init);
941 void hw_breakpoint_pmu_read(struct perf_event *bp)
946 * Dummy function to register with die_notifier.
948 int hw_breakpoint_exceptions_notify(struct notifier_block *unused,
949 unsigned long val, void *data)