2 * Low-level CPU initialisation
3 * Based on arch/arm/kernel/head.S
5 * Copyright (C) 1994-2002 Russell King
6 * Copyright (C) 2003-2012 ARM Ltd.
7 * Authors: Catalin Marinas <catalin.marinas@arm.com>
8 * Will Deacon <will.deacon@arm.com>
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program. If not, see <http://www.gnu.org/licenses/>.
23 #include <linux/linkage.h>
24 #include <linux/init.h>
25 #include <linux/irqchip/arm-gic-v3.h>
27 #include <asm/assembler.h>
29 #include <asm/ptrace.h>
30 #include <asm/asm-offsets.h>
31 #include <asm/cache.h>
32 #include <asm/cputype.h>
34 #include <asm/kernel-pgtable.h>
35 #include <asm/kvm_arm.h>
36 #include <asm/memory.h>
37 #include <asm/pgtable-hwdef.h>
38 #include <asm/pgtable.h>
41 #include <asm/sysreg.h>
42 #include <asm/thread_info.h>
45 #include "efi-header.S"
47 #define __PHYS_OFFSET (KERNEL_START - TEXT_OFFSET)
49 #if (TEXT_OFFSET & 0xfff) != 0
50 #error TEXT_OFFSET must be at least 4KB aligned
51 #elif (PAGE_OFFSET & 0x1fffff) != 0
52 #error PAGE_OFFSET must be at least 2MB aligned
53 #elif TEXT_OFFSET > 0x1fffff
54 #error TEXT_OFFSET must be less than 2MB
58 * Kernel startup entry point.
59 * ---------------------------
61 * The requirements are:
62 * MMU = off, D-cache = off, I-cache = on or off,
63 * x0 = physical address to the FDT blob.
65 * This code is mostly position independent so you call this at
66 * __pa(PAGE_OFFSET + TEXT_OFFSET).
68 * Note that the callee-saved registers are used for storing variables
69 * that are useful before the MMU is enabled. The allocations are described
70 * in the entry routines.
75 * DO NOT MODIFY. Image header expected by Linux boot-loaders.
79 * This add instruction has no meaningful effect except that
80 * its opcode forms the magic "MZ" signature required by UEFI.
85 b stext // branch to kernel start, magic
88 le64sym _kernel_offset_le // Image load offset from start of RAM, little-endian
89 le64sym _kernel_size_le // Effective size of kernel image, little-endian
90 le64sym _kernel_flags_le // Informative flags, little-endian
94 .ascii "ARM\x64" // Magic number
96 .long pe_header - _head // Offset to the PE header.
107 * The following callee saved general purpose registers are used on the
108 * primary lowlevel boot path:
110 * Register Scope Purpose
111 * x21 stext() .. start_kernel() FDT pointer passed at boot in x0
112 * x23 stext() .. start_kernel() physical misalignment/KASLR offset
113 * x28 __create_page_tables() callee preserved temp register
114 * x19/x20 __primary_switch() callee preserved temp registers
117 bl preserve_boot_args
118 bl el2_setup // Drop to EL1, w0=cpu_boot_mode
119 adrp x23, __PHYS_OFFSET
120 and x23, x23, MIN_KIMG_ALIGN - 1 // KASLR offset, defaults to 0
121 bl set_cpu_boot_mode_flag
122 bl __create_page_tables
124 * The following calls CPU setup code, see arch/arm64/mm/proc.S for
126 * On return, the CPU will be ready for the MMU to be turned on and
127 * the TCR will have been set.
129 bl __cpu_setup // initialise processor
134 * Preserve the arguments passed by the bootloader in x0 .. x3
137 mov x21, x0 // x21=FDT
139 adr_l x0, boot_args // record the contents of
140 stp x21, x1, [x0] // x0 .. x3 at kernel entry
141 stp x2, x3, [x0, #16]
143 dmb sy // needed before dc ivac with
146 mov x1, #0x20 // 4 x 8 bytes
147 b __inval_dcache_area // tail call
148 ENDPROC(preserve_boot_args)
151 * Macro to create a table entry to the next page.
153 * tbl: page table address
154 * virt: virtual address
155 * shift: #imm page table shift
156 * ptrs: #imm pointers per table page
159 * Corrupts: ptrs, tmp1, tmp2
160 * Returns: tbl -> next level table page address
162 .macro create_table_entry, tbl, virt, shift, ptrs, tmp1, tmp2
163 add \tmp1, \tbl, #PAGE_SIZE
164 phys_to_pte \tmp2, \tmp1
165 orr \tmp2, \tmp2, #PMD_TYPE_TABLE // address of next table and entry type
166 lsr \tmp1, \virt, #\shift
168 and \tmp1, \tmp1, \ptrs // table index
169 str \tmp2, [\tbl, \tmp1, lsl #3]
170 add \tbl, \tbl, #PAGE_SIZE // next level table page
174 * Macro to populate page table entries, these entries can be pointers to the next level
175 * or last level entries pointing to physical memory.
177 * tbl: page table address
178 * rtbl: pointer to page table or physical memory
179 * index: start index to write
180 * eindex: end index to write - [index, eindex] written to
181 * flags: flags for pagetable entry to or in
182 * inc: increment to rtbl between each entry
183 * tmp1: temporary variable
185 * Preserves: tbl, eindex, flags, inc
186 * Corrupts: index, tmp1
189 .macro populate_entries, tbl, rtbl, index, eindex, flags, inc, tmp1
190 .Lpe\@: phys_to_pte \tmp1, \rtbl
191 orr \tmp1, \tmp1, \flags // tmp1 = table entry
192 str \tmp1, [\tbl, \index, lsl #3]
193 add \rtbl, \rtbl, \inc // rtbl = pa next level
194 add \index, \index, #1
200 * Compute indices of table entries from virtual address range. If multiple entries
201 * were needed in the previous page table level then the next page table level is assumed
202 * to be composed of multiple pages. (This effectively scales the end index).
204 * vstart: virtual address of start of range
205 * vend: virtual address of end of range - we map [vstart, vend]
206 * shift: shift used to transform virtual address into index
207 * ptrs: number of entries in page table
208 * istart: index in table corresponding to vstart
209 * iend: index in table corresponding to vend
210 * count: On entry: how many extra entries were required in previous level, scales
212 * On exit: returns how many extra entries required for next page table level
214 * Preserves: vstart, vend, shift, ptrs
215 * Returns: istart, iend, count
217 .macro compute_indices, vstart, vend, shift, ptrs, istart, iend, count
218 lsr \iend, \vend, \shift
220 sub \istart, \istart, #1
221 and \iend, \iend, \istart // iend = (vend >> shift) & (ptrs - 1)
223 mul \istart, \istart, \count
224 add \iend, \iend, \istart // iend += (count - 1) * ptrs
225 // our entries span multiple tables
227 lsr \istart, \vstart, \shift
229 sub \count, \count, #1
230 and \istart, \istart, \count
232 sub \count, \iend, \istart
236 * Map memory for specified virtual address range. Each level of page table needed supports
237 * multiple entries. If a level requires n entries the next page table level is assumed to be
238 * formed from n pages.
240 * tbl: location of page table
241 * rtbl: address to be used for first level page table entry (typically tbl + PAGE_SIZE)
242 * vstart: virtual address of start of range
243 * vend: virtual address of end of range - we map [vstart, vend - 1]
244 * flags: flags to use to map last level entries
245 * phys: physical address corresponding to vstart - physical memory is contiguous
246 * pgds: the number of pgd entries
248 * Temporaries: istart, iend, tmp, count, sv - these need to be different registers
249 * Preserves: vstart, flags
250 * Corrupts: tbl, rtbl, vend, istart, iend, tmp, count, sv
252 .macro map_memory, tbl, rtbl, vstart, vend, flags, phys, pgds, istart, iend, tmp, count, sv
254 add \rtbl, \tbl, #PAGE_SIZE
257 compute_indices \vstart, \vend, #PGDIR_SHIFT, \pgds, \istart, \iend, \count
258 populate_entries \tbl, \rtbl, \istart, \iend, #PMD_TYPE_TABLE, #PAGE_SIZE, \tmp
262 #if SWAPPER_PGTABLE_LEVELS > 3
263 compute_indices \vstart, \vend, #PUD_SHIFT, #PTRS_PER_PUD, \istart, \iend, \count
264 populate_entries \tbl, \rtbl, \istart, \iend, #PMD_TYPE_TABLE, #PAGE_SIZE, \tmp
269 #if SWAPPER_PGTABLE_LEVELS > 2
270 compute_indices \vstart, \vend, #SWAPPER_TABLE_SHIFT, #PTRS_PER_PMD, \istart, \iend, \count
271 populate_entries \tbl, \rtbl, \istart, \iend, #PMD_TYPE_TABLE, #PAGE_SIZE, \tmp
275 compute_indices \vstart, \vend, #SWAPPER_BLOCK_SHIFT, #PTRS_PER_PTE, \istart, \iend, \count
276 bic \count, \phys, #SWAPPER_BLOCK_SIZE - 1
277 populate_entries \tbl, \count, \istart, \iend, \flags, #SWAPPER_BLOCK_SIZE, \tmp
281 * Setup the initial page tables. We only setup the barest amount which is
282 * required to get the kernel running. The following sections are required:
283 * - identity mapping to enable the MMU (low address, TTBR0)
284 * - first few MB of the kernel linear mapping to jump to once the MMU has
287 __create_page_tables:
291 * Invalidate the idmap and swapper page tables to avoid potential
292 * dirty cache lines being evicted.
294 adrp x0, idmap_pg_dir
295 adrp x1, swapper_pg_end
297 bl __inval_dcache_area
300 * Clear the idmap and swapper page tables.
302 adrp x0, idmap_pg_dir
303 adrp x1, swapper_pg_end
305 1: stp xzr, xzr, [x0], #16
306 stp xzr, xzr, [x0], #16
307 stp xzr, xzr, [x0], #16
308 stp xzr, xzr, [x0], #16
312 mov x7, SWAPPER_MM_MMUFLAGS
315 * Create the identity mapping.
317 adrp x0, idmap_pg_dir
318 adrp x3, __idmap_text_start // __pa(__idmap_text_start)
321 * VA_BITS may be too small to allow for an ID mapping to be created
322 * that covers system RAM if that is located sufficiently high in the
323 * physical address space. So for the ID map, use an extended virtual
324 * range in that case, and configure an additional translation level
327 * Calculate the maximum allowed value for TCR_EL1.T0SZ so that the
328 * entire ID map region can be mapped. As T0SZ == (64 - #bits used),
329 * this number conveniently equals the number of leading zeroes in
330 * the physical address of __idmap_text_end.
332 adrp x5, __idmap_text_end
334 cmp x5, TCR_T0SZ(VA_BITS) // default T0SZ small enough?
335 b.ge 1f // .. then skip VA range extension
340 dc ivac, x6 // Invalidate potentially stale cache line
343 #define EXTRA_SHIFT (PGDIR_SHIFT + PAGE_SHIFT - 3)
344 #define EXTRA_PTRS (1 << (PHYS_MASK_SHIFT - EXTRA_SHIFT))
347 * If VA_BITS < 48, we have to configure an additional table level.
348 * First, we have to verify our assumption that the current value of
349 * VA_BITS was chosen such that all translation levels are fully
350 * utilised, and that lowering T0SZ will always result in an additional
351 * translation level to be configured.
353 #if VA_BITS != EXTRA_SHIFT
354 #error "Mismatch between VA_BITS and page size/number of translation levels"
358 create_table_entry x0, x3, EXTRA_SHIFT, x4, x5, x6
361 * If VA_BITS == 48, we don't have to configure an additional
362 * translation level, but the top-level table has more entries.
364 mov x4, #1 << (PHYS_MASK_SHIFT - PGDIR_SHIFT)
365 str_l x4, idmap_ptrs_per_pgd, x5
368 ldr_l x4, idmap_ptrs_per_pgd
369 mov x5, x3 // __pa(__idmap_text_start)
370 adr_l x6, __idmap_text_end // __pa(__idmap_text_end)
372 map_memory x0, x1, x3, x6, x7, x3, x4, x10, x11, x12, x13, x14
375 * Map the kernel image (starting with PHYS_OFFSET).
377 adrp x0, swapper_pg_dir
378 mov_q x5, KIMAGE_VADDR + TEXT_OFFSET // compile time __va(_text)
379 add x5, x5, x23 // add KASLR displacement
381 adrp x6, _end // runtime __pa(_end)
382 adrp x3, _text // runtime __pa(_text)
383 sub x6, x6, x3 // _end - _text
384 add x6, x6, x5 // runtime __va(_end)
386 map_memory x0, x1, x5, x6, x7, x3, x4, x10, x11, x12, x13, x14
389 * Since the page tables have been populated with non-cacheable
390 * accesses (MMU disabled), invalidate the idmap and swapper page
391 * tables again to remove any speculatively loaded cache lines.
393 adrp x0, idmap_pg_dir
394 adrp x1, swapper_pg_end
397 bl __inval_dcache_area
400 ENDPROC(__create_page_tables)
404 * The following fragment of code is executed with the MMU enabled.
409 adrp x4, init_thread_union
410 add sp, x4, #THREAD_SIZE
412 msr sp_el0, x5 // Save thread_info
414 adr_l x8, vectors // load VBAR_EL1 with virtual
415 msr vbar_el1, x8 // vector table address
418 stp xzr, x30, [sp, #-16]!
421 str_l x21, __fdt_pointer, x5 // Save FDT pointer
423 ldr_l x4, kimage_vaddr // Save the offset between
424 sub x4, x4, x0 // the kernel virtual and
425 str_l x4, kimage_voffset, x5 // physical mappings
428 adr_l x0, __bss_start
433 dsb ishst // Make zero page visible to PTW
438 #ifdef CONFIG_RANDOMIZE_BASE
439 tst x23, ~(MIN_KIMG_ALIGN - 1) // already running randomized?
441 mov x0, x21 // pass FDT address in x0
442 bl kaslr_early_init // parse FDT for KASLR options
443 cbz x0, 0f // KASLR disabled? just proceed
444 orr x23, x23, x0 // record KASLR offset
445 ldp x29, x30, [sp], #16 // we must enable KASLR, return
446 ret // to __primary_switch()
453 ENDPROC(__primary_switched)
456 * end early head section, begin head code that is also used for
457 * hotplug and needs to have the same protections as the text region
459 .section ".idmap.text","awx"
462 .quad _text - TEXT_OFFSET
465 * If we're fortunate enough to boot at EL2, ensure that the world is
466 * sane before dropping to EL1.
468 * Returns either BOOT_CPU_MODE_EL1 or BOOT_CPU_MODE_EL2 in w0 if
469 * booted in EL1 or EL2 respectively.
472 msr SPsel, #1 // We want to use SP_EL{1,2}
474 cmp x0, #CurrentEL_EL2
476 mov_q x0, (SCTLR_EL1_RES1 | ENDIAN_SET_EL1)
478 mov w0, #BOOT_CPU_MODE_EL1 // This cpu booted in EL1
482 1: mov_q x0, (SCTLR_EL2_RES1 | ENDIAN_SET_EL2)
485 #ifdef CONFIG_ARM64_VHE
487 * Check for VHE being present. For the rest of the EL2 setup,
488 * x2 being non-zero indicates that we do have VHE, and that the
489 * kernel is intended to run at EL2.
491 mrs x2, id_aa64mmfr1_el1
497 /* Hyp configuration. */
498 mov_q x0, HCR_HOST_NVHE_FLAGS
500 mov_q x0, HCR_HOST_VHE_FLAGS
506 * Allow Non-secure EL1 and EL0 to access physical timer and counter.
507 * This is not necessary for VHE, since the host kernel runs in EL2,
508 * and EL0 accesses are configured in the later stage of boot process.
509 * Note that when HCR_EL2.E2H == 1, CNTHCTL_EL2 has the same bit layout
510 * as CNTKCTL_EL1, and CNTKCTL_EL1 accessing instructions are redefined
511 * to access CNTHCTL_EL2. This allows the kernel designed to run at EL1
512 * to transparently mess with the EL0 bits via CNTKCTL_EL1 access in
517 orr x0, x0, #3 // Enable EL1 physical timers
520 msr cntvoff_el2, xzr // Clear virtual offset
522 #ifdef CONFIG_ARM_GIC_V3
523 /* GICv3 system register access */
524 mrs x0, id_aa64pfr0_el1
528 mrs_s x0, SYS_ICC_SRE_EL2
529 orr x0, x0, #ICC_SRE_EL2_SRE // Set ICC_SRE_EL2.SRE==1
530 orr x0, x0, #ICC_SRE_EL2_ENABLE // Set ICC_SRE_EL2.Enable==1
531 msr_s SYS_ICC_SRE_EL2, x0
532 isb // Make sure SRE is now set
533 mrs_s x0, SYS_ICC_SRE_EL2 // Read SRE back,
534 tbz x0, #0, 3f // and check that it sticks
535 msr_s SYS_ICH_HCR_EL2, xzr // Reset ICC_HCR_EL2 to defaults
540 /* Populate ID registers. */
547 msr hstr_el2, xzr // Disable CP15 traps to EL2
551 mrs x1, id_aa64dfr0_el1 // Check ID_AA64DFR0_EL1 PMUVer
554 b.lt 4f // Skip if no PMU present
555 mrs x0, pmcr_el0 // Disable debug access traps
556 ubfx x0, x0, #11, #5 // to EL2 and allow access to
558 csel x3, xzr, x0, lt // all PMU counters from EL1
560 /* Statistical profiling */
561 ubfx x0, x1, #32, #4 // Check ID_AA64DFR0_EL1 PMSVer
562 cbz x0, 7f // Skip if SPE not present
564 mrs_s x4, SYS_PMBIDR_EL1 // If SPE available at EL2,
565 and x4, x4, #(1 << SYS_PMBIDR_EL1_P_SHIFT)
566 cbnz x4, 5f // then permit sampling of physical
567 mov x4, #(1 << SYS_PMSCR_EL2_PCT_SHIFT | \
568 1 << SYS_PMSCR_EL2_PA_SHIFT)
569 msr_s SYS_PMSCR_EL2, x4 // addresses and physical counter
571 mov x1, #(MDCR_EL2_E2PB_MASK << MDCR_EL2_E2PB_SHIFT)
572 orr x3, x3, x1 // If we don't have VHE, then
573 b 7f // use EL1&0 translation.
574 6: // For VHE, use EL2 translation
575 orr x3, x3, #MDCR_EL2_TPMS // and disable access from EL1
577 msr mdcr_el2, x3 // Configure debug traps
580 mrs x1, id_aa64mmfr1_el1
581 ubfx x0, x1, #ID_AA64MMFR1_LOR_SHIFT, 4
583 msr_s SYS_LORC_EL1, xzr
586 /* Stage-2 translation */
589 cbz x2, install_el2_stub
591 mov w0, #BOOT_CPU_MODE_EL2 // This CPU booted in EL2
597 * When VHE is not in use, early init of EL2 and EL1 needs to be
599 * When VHE _is_ in use, EL1 will not be used in the host and
600 * requires no configuration, and all non-hyp-specific EL2 setup
601 * will be done via the _EL1 system register aliases in __cpu_setup.
603 mov_q x0, (SCTLR_EL1_RES1 | ENDIAN_SET_EL1)
606 /* Coprocessor traps. */
608 msr cptr_el2, x0 // Disable copro. traps to EL2
610 /* SVE register access */
611 mrs x1, id_aa64pfr0_el1
612 ubfx x1, x1, #ID_AA64PFR0_SVE_SHIFT, #4
615 bic x0, x0, #CPTR_EL2_TZ // Also disable SVE traps
616 msr cptr_el2, x0 // Disable copro. traps to EL2
618 mov x1, #ZCR_ELx_LEN_MASK // SVE: Enable full vector
619 msr_s SYS_ZCR_EL2, x1 // length for EL1.
621 /* Hypervisor stub */
622 7: adr_l x0, __hyp_stub_vectors
626 mov x0, #(PSR_F_BIT | PSR_I_BIT | PSR_A_BIT | PSR_D_BIT |\
630 mov w0, #BOOT_CPU_MODE_EL2 // This CPU booted in EL2
635 * Sets the __boot_cpu_mode flag depending on the CPU boot mode passed
636 * in w0. See arch/arm64/include/asm/virt.h for more info.
638 set_cpu_boot_mode_flag:
639 adr_l x1, __boot_cpu_mode
640 cmp w0, #BOOT_CPU_MODE_EL2
643 1: str w0, [x1] // This CPU has booted in EL1
645 dc ivac, x1 // Invalidate potentially stale cache line
647 ENDPROC(set_cpu_boot_mode_flag)
650 * These values are written with the MMU off, but read with the MMU on.
651 * Writers will invalidate the corresponding address, discarding up to a
652 * 'Cache Writeback Granule' (CWG) worth of data. The linker script ensures
653 * sufficient alignment that the CWG doesn't overlap another section.
655 .pushsection ".mmuoff.data.write", "aw"
657 * We need to find out the CPU boot mode long after boot, so we need to
658 * store it in a writable variable.
660 * This is not in .bss, because we set it sufficiently early that the boot-time
661 * zeroing of .bss would clobber it.
663 ENTRY(__boot_cpu_mode)
664 .long BOOT_CPU_MODE_EL2
665 .long BOOT_CPU_MODE_EL1
667 * The booting CPU updates the failed status @__early_cpu_boot_status,
668 * with MMU turned off.
670 ENTRY(__early_cpu_boot_status)
676 * This provides a "holding pen" for platforms to hold all secondary
677 * cores are held until we're ready for them to initialise.
679 ENTRY(secondary_holding_pen)
680 bl el2_setup // Drop to EL1, w0=cpu_boot_mode
681 bl set_cpu_boot_mode_flag
683 mov_q x1, MPIDR_HWID_BITMASK
685 adr_l x3, secondary_holding_pen_release
688 b.eq secondary_startup
691 ENDPROC(secondary_holding_pen)
694 * Secondary entry point that jumps straight into the kernel. Only to
695 * be used where CPUs are brought online dynamically by the kernel.
697 ENTRY(secondary_entry)
698 bl el2_setup // Drop to EL1
699 bl set_cpu_boot_mode_flag
701 ENDPROC(secondary_entry)
705 * Common entry point for secondary CPUs.
707 bl __cpu_secondary_check52bitva
708 bl __cpu_setup // initialise processor
710 ldr x8, =__secondary_switched
712 ENDPROC(secondary_startup)
714 __secondary_switched:
719 adr_l x0, secondary_data
720 ldr x1, [x0, #CPU_BOOT_STACK] // get secondary_data.stack
722 ldr x2, [x0, #CPU_BOOT_TASK]
726 b secondary_start_kernel
727 ENDPROC(__secondary_switched)
730 * The booting CPU updates the failed status @__early_cpu_boot_status,
731 * with MMU turned off.
733 * update_early_cpu_boot_status tmp, status
734 * - Corrupts tmp1, tmp2
735 * - Writes 'status' to __early_cpu_boot_status and makes sure
736 * it is committed to memory.
739 .macro update_early_cpu_boot_status status, tmp1, tmp2
741 adr_l \tmp1, __early_cpu_boot_status
744 dc ivac, \tmp1 // Invalidate potentially stale cache line
750 * x0 = SCTLR_EL1 value for turning on the MMU.
752 * Returns to the caller via x30/lr. This requires the caller to be covered
753 * by the .idmap.text section.
755 * Checks if the selected granule size is supported by the CPU.
756 * If it isn't, park the CPU
759 mrs x1, ID_AA64MMFR0_EL1
760 ubfx x2, x1, #ID_AA64MMFR0_TGRAN_SHIFT, 4
761 cmp x2, #ID_AA64MMFR0_TGRAN_SUPPORTED
762 b.ne __no_granule_support
763 update_early_cpu_boot_status 0, x1, x2
764 adrp x1, idmap_pg_dir
765 adrp x2, swapper_pg_dir
768 msr ttbr0_el1, x3 // load TTBR0
769 msr ttbr1_el1, x4 // load TTBR1
774 * Invalidate the local I-cache so that any instructions fetched
775 * speculatively from the PoC are discarded, since they may have
776 * been dynamically patched at the PoU.
782 ENDPROC(__enable_mmu)
784 ENTRY(__cpu_secondary_check52bitva)
785 #ifdef CONFIG_ARM64_52BIT_VA
786 ldr_l x0, vabits_user
790 mrs_s x0, SYS_ID_AA64MMFR2_EL1
791 and x0, x0, #(0xf << ID_AA64MMFR2_LVA_SHIFT)
794 adr_l x0, va52mismatch
798 dc ivac, x0 // Invalidate potentially stale cache line
800 update_early_cpu_boot_status CPU_STUCK_IN_KERNEL, x0, x1
807 ENDPROC(__cpu_secondary_check52bitva)
809 __no_granule_support:
810 /* Indicate that this CPU can't boot and is stuck in the kernel */
811 update_early_cpu_boot_status CPU_STUCK_IN_KERNEL, x1, x2
816 ENDPROC(__no_granule_support)
818 #ifdef CONFIG_RELOCATABLE
821 * Iterate over each entry in the relocation table, and apply the
822 * relocations in place.
824 ldr w9, =__rela_offset // offset to reloc table
825 ldr w10, =__rela_size // size of reloc table
827 mov_q x11, KIMAGE_VADDR // default virtual offset
828 add x11, x11, x23 // actual virtual offset
829 add x9, x9, x11 // __va(.rela)
830 add x10, x9, x10 // __va(.rela) + sizeof(.rela)
834 ldp x11, x12, [x9], #24
836 cmp w12, #R_AARCH64_RELATIVE
838 add x13, x13, x23 // relocate
842 ENDPROC(__relocate_kernel)
846 #ifdef CONFIG_RANDOMIZE_BASE
847 mov x19, x0 // preserve new SCTLR_EL1 value
848 mrs x20, sctlr_el1 // preserve old SCTLR_EL1 value
852 #ifdef CONFIG_RELOCATABLE
854 #ifdef CONFIG_RANDOMIZE_BASE
855 ldr x8, =__primary_switched
856 adrp x0, __PHYS_OFFSET
860 * If we return here, we have a KASLR displacement in x23 which we need
861 * to take into account by discarding the current kernel mapping and
862 * creating a new one.
864 pre_disable_mmu_workaround
865 msr sctlr_el1, x20 // disable the MMU
867 bl __create_page_tables // recreate kernel mapping
869 tlbi vmalle1 // Remove any stale TLB entries
873 msr sctlr_el1, x19 // re-enable the MMU
875 ic iallu // flush instructions fetched
876 dsb nsh // via old mapping
882 ldr x8, =__primary_switched
883 adrp x0, __PHYS_OFFSET
885 ENDPROC(__primary_switch)