2 * Low-level CPU initialisation
3 * Based on arch/arm/kernel/head.S
5 * Copyright (C) 1994-2002 Russell King
6 * Copyright (C) 2003-2012 ARM Ltd.
7 * Authors: Catalin Marinas <catalin.marinas@arm.com>
8 * Will Deacon <will.deacon@arm.com>
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program. If not, see <http://www.gnu.org/licenses/>.
23 #include <linux/linkage.h>
24 #include <linux/init.h>
25 #include <linux/irqchip/arm-gic-v3.h>
27 #include <asm/assembler.h>
28 #include <asm/ptrace.h>
29 #include <asm/asm-offsets.h>
30 #include <asm/cache.h>
31 #include <asm/cputype.h>
32 #include <asm/kernel-pgtable.h>
33 #include <asm/kvm_arm.h>
34 #include <asm/memory.h>
35 #include <asm/pgtable-hwdef.h>
36 #include <asm/pgtable.h>
38 #include <asm/sysreg.h>
39 #include <asm/thread_info.h>
42 #define __PHYS_OFFSET (KERNEL_START - TEXT_OFFSET)
44 #if (TEXT_OFFSET & 0xfff) != 0
45 #error TEXT_OFFSET must be at least 4KB aligned
46 #elif (PAGE_OFFSET & 0x1fffff) != 0
47 #error PAGE_OFFSET must be at least 2MB aligned
48 #elif TEXT_OFFSET > 0x1fffff
49 #error TEXT_OFFSET must be less than 2MB
52 #define KERNEL_START _text
53 #define KERNEL_END _end
56 * Kernel startup entry point.
57 * ---------------------------
59 * The requirements are:
60 * MMU = off, D-cache = off, I-cache = on or off,
61 * x0 = physical address to the FDT blob.
63 * This code is mostly position independent so you call this at
64 * __pa(PAGE_OFFSET + TEXT_OFFSET).
66 * Note that the callee-saved registers are used for storing variables
67 * that are useful before the MMU is enabled. The allocations are described
68 * in the entry routines.
73 * DO NOT MODIFY. Image header expected by Linux boot-loaders.
78 * This add instruction has no meaningful effect except that
79 * its opcode forms the magic "MZ" signature required by UEFI.
84 b stext // branch to kernel start, magic
87 .quad _kernel_offset_le // Image load offset from start of RAM, little-endian
88 .quad _kernel_size_le // Effective size of kernel image, little-endian
89 .quad _kernel_flags_le // Informative flags, little-endian
93 .byte 0x41 // Magic number, "ARM\x64"
98 .long pe_header - efi_head // Offset to the PE header.
104 .globl __efistub_stext_offset
105 .set __efistub_stext_offset, stext - efi_head
111 .short 0xaa64 // AArch64
112 .short 2 // nr_sections
113 .long 0 // TimeDateStamp
114 .long 0 // PointerToSymbolTable
115 .long 1 // NumberOfSymbols
116 .short section_table - optional_header // SizeOfOptionalHeader
117 .short 0x206 // Characteristics.
118 // IMAGE_FILE_DEBUG_STRIPPED |
119 // IMAGE_FILE_EXECUTABLE_IMAGE |
120 // IMAGE_FILE_LINE_NUMS_STRIPPED
122 .short 0x20b // PE32+ format
123 .byte 0x02 // MajorLinkerVersion
124 .byte 0x14 // MinorLinkerVersion
125 .long _end - stext // SizeOfCode
126 .long 0 // SizeOfInitializedData
127 .long 0 // SizeOfUninitializedData
128 .long __efistub_entry - efi_head // AddressOfEntryPoint
129 .long __efistub_stext_offset // BaseOfCode
133 .long 0x1000 // SectionAlignment
134 .long PECOFF_FILE_ALIGNMENT // FileAlignment
135 .short 0 // MajorOperatingSystemVersion
136 .short 0 // MinorOperatingSystemVersion
137 .short 0 // MajorImageVersion
138 .short 0 // MinorImageVersion
139 .short 0 // MajorSubsystemVersion
140 .short 0 // MinorSubsystemVersion
141 .long 0 // Win32VersionValue
143 .long _end - efi_head // SizeOfImage
145 // Everything before the kernel image is considered part of the header
146 .long __efistub_stext_offset // SizeOfHeaders
148 .short 0xa // Subsystem (EFI application)
149 .short 0 // DllCharacteristics
150 .quad 0 // SizeOfStackReserve
151 .quad 0 // SizeOfStackCommit
152 .quad 0 // SizeOfHeapReserve
153 .quad 0 // SizeOfHeapCommit
154 .long 0 // LoaderFlags
155 .long 0x6 // NumberOfRvaAndSizes
157 .quad 0 // ExportTable
158 .quad 0 // ImportTable
159 .quad 0 // ResourceTable
160 .quad 0 // ExceptionTable
161 .quad 0 // CertificationTable
162 .quad 0 // BaseRelocationTable
168 * The EFI application loader requires a relocation section
169 * because EFI applications must be relocatable. This is a
170 * dummy section as far as we are concerned.
174 .byte 0 // end of 0 padding of section name
177 .long 0 // SizeOfRawData
178 .long 0 // PointerToRawData
179 .long 0 // PointerToRelocations
180 .long 0 // PointerToLineNumbers
181 .short 0 // NumberOfRelocations
182 .short 0 // NumberOfLineNumbers
183 .long 0x42100040 // Characteristics (section flags)
189 .byte 0 // end of 0 padding of section name
190 .long _end - stext // VirtualSize
191 .long __efistub_stext_offset // VirtualAddress
192 .long _edata - stext // SizeOfRawData
193 .long __efistub_stext_offset // PointerToRawData
195 .long 0 // PointerToRelocations (0 for executables)
196 .long 0 // PointerToLineNumbers (0 for executables)
197 .short 0 // NumberOfRelocations (0 for executables)
198 .short 0 // NumberOfLineNumbers (0 for executables)
199 .long 0xe0500020 // Characteristics (section flags)
202 * EFI will load stext onwards at the 4k section alignment
203 * described in the PE/COFF header. To ensure that instruction
204 * sequences using an adrp and a :lo12: immediate will function
205 * correctly at this alignment, we must ensure that stext is
206 * placed at a 4k boundary in the Image to begin with.
212 bl preserve_boot_args
213 bl el2_setup // Drop to EL1, w20=cpu_boot_mode
214 adrp x24, __PHYS_OFFSET
215 bl set_cpu_boot_mode_flag
216 bl __create_page_tables // x25=TTBR0, x26=TTBR1
218 * The following calls CPU setup code, see arch/arm64/mm/proc.S for
220 * On return, the CPU will be ready for the MMU to be turned on and
221 * the TCR will have been set.
223 ldr x27, =__mmap_switched // address to jump to after
224 // MMU has been enabled
225 adr_l lr, __enable_mmu // return (PIC) address
226 b __cpu_setup // initialise processor
230 * Preserve the arguments passed by the bootloader in x0 .. x3
233 mov x21, x0 // x21=FDT
235 adr_l x0, boot_args // record the contents of
236 stp x21, x1, [x0] // x0 .. x3 at kernel entry
237 stp x2, x3, [x0, #16]
239 dmb sy // needed before dc ivac with
242 add x1, x0, #0x20 // 4 x 8 bytes
243 b __inval_cache_range // tail call
244 ENDPROC(preserve_boot_args)
247 * Macro to create a table entry to the next page.
249 * tbl: page table address
250 * virt: virtual address
251 * shift: #imm page table shift
252 * ptrs: #imm pointers per table page
255 * Corrupts: tmp1, tmp2
256 * Returns: tbl -> next level table page address
258 .macro create_table_entry, tbl, virt, shift, ptrs, tmp1, tmp2
259 lsr \tmp1, \virt, #\shift
260 and \tmp1, \tmp1, #\ptrs - 1 // table index
261 add \tmp2, \tbl, #PAGE_SIZE
262 orr \tmp2, \tmp2, #PMD_TYPE_TABLE // address of next table and entry type
263 str \tmp2, [\tbl, \tmp1, lsl #3]
264 add \tbl, \tbl, #PAGE_SIZE // next level table page
268 * Macro to populate the PGD (and possibily PUD) for the corresponding
269 * block entry in the next level (tbl) for the given virtual address.
271 * Preserves: tbl, next, virt
272 * Corrupts: tmp1, tmp2
274 .macro create_pgd_entry, tbl, virt, tmp1, tmp2
275 create_table_entry \tbl, \virt, PGDIR_SHIFT, PTRS_PER_PGD, \tmp1, \tmp2
276 #if SWAPPER_PGTABLE_LEVELS > 3
277 create_table_entry \tbl, \virt, PUD_SHIFT, PTRS_PER_PUD, \tmp1, \tmp2
279 #if SWAPPER_PGTABLE_LEVELS > 2
280 create_table_entry \tbl, \virt, SWAPPER_TABLE_SHIFT, PTRS_PER_PTE, \tmp1, \tmp2
285 * Macro to populate block entries in the page table for the start..end
286 * virtual range (inclusive).
288 * Preserves: tbl, flags
289 * Corrupts: phys, start, end, pstate
291 .macro create_block_map, tbl, flags, phys, start, end
292 lsr \phys, \phys, #SWAPPER_BLOCK_SHIFT
293 lsr \start, \start, #SWAPPER_BLOCK_SHIFT
294 and \start, \start, #PTRS_PER_PTE - 1 // table index
295 orr \phys, \flags, \phys, lsl #SWAPPER_BLOCK_SHIFT // table entry
296 lsr \end, \end, #SWAPPER_BLOCK_SHIFT
297 and \end, \end, #PTRS_PER_PTE - 1 // table end index
298 9999: str \phys, [\tbl, \start, lsl #3] // store the entry
299 add \start, \start, #1 // next entry
300 add \phys, \phys, #SWAPPER_BLOCK_SIZE // next block
306 * Setup the initial page tables. We only setup the barest amount which is
307 * required to get the kernel running. The following sections are required:
308 * - identity mapping to enable the MMU (low address, TTBR0)
309 * - first few MB of the kernel linear mapping to jump to once the MMU has
312 __create_page_tables:
313 adrp x25, idmap_pg_dir
314 adrp x26, swapper_pg_dir
318 * Invalidate the idmap and swapper page tables to avoid potential
319 * dirty cache lines being evicted.
322 add x1, x26, #SWAPPER_DIR_SIZE
323 bl __inval_cache_range
326 * Clear the idmap and swapper page tables.
329 add x6, x26, #SWAPPER_DIR_SIZE
330 1: stp xzr, xzr, [x0], #16
331 stp xzr, xzr, [x0], #16
332 stp xzr, xzr, [x0], #16
333 stp xzr, xzr, [x0], #16
337 ldr x7, =SWAPPER_MM_MMUFLAGS
340 * Create the identity mapping.
342 mov x0, x25 // idmap_pg_dir
343 adrp x3, __idmap_text_start // __pa(__idmap_text_start)
345 #ifndef CONFIG_ARM64_VA_BITS_48
346 #define EXTRA_SHIFT (PGDIR_SHIFT + PAGE_SHIFT - 3)
347 #define EXTRA_PTRS (1 << (48 - EXTRA_SHIFT))
350 * If VA_BITS < 48, it may be too small to allow for an ID mapping to be
351 * created that covers system RAM if that is located sufficiently high
352 * in the physical address space. So for the ID map, use an extended
353 * virtual range in that case, by configuring an additional translation
355 * First, we have to verify our assumption that the current value of
356 * VA_BITS was chosen such that all translation levels are fully
357 * utilised, and that lowering T0SZ will always result in an additional
358 * translation level to be configured.
360 #if VA_BITS != EXTRA_SHIFT
361 #error "Mismatch between VA_BITS and page size/number of translation levels"
365 * Calculate the maximum allowed value for TCR_EL1.T0SZ so that the
366 * entire ID map region can be mapped. As T0SZ == (64 - #bits used),
367 * this number conveniently equals the number of leading zeroes in
368 * the physical address of __idmap_text_end.
370 adrp x5, __idmap_text_end
372 cmp x5, TCR_T0SZ(VA_BITS) // default T0SZ small enough?
373 b.ge 1f // .. then skip additional level
378 dc ivac, x6 // Invalidate potentially stale cache line
380 create_table_entry x0, x3, EXTRA_SHIFT, EXTRA_PTRS, x5, x6
384 create_pgd_entry x0, x3, x5, x6
385 mov x5, x3 // __pa(__idmap_text_start)
386 adr_l x6, __idmap_text_end // __pa(__idmap_text_end)
387 create_block_map x0, x7, x3, x5, x6
390 * Map the kernel image (starting with PHYS_OFFSET).
392 mov x0, x26 // swapper_pg_dir
394 create_pgd_entry x0, x5, x3, x6
395 ldr x6, =KERNEL_END // __va(KERNEL_END)
396 mov x3, x24 // phys offset
397 create_block_map x0, x7, x3, x5, x6
400 * Since the page tables have been populated with non-cacheable
401 * accesses (MMU disabled), invalidate the idmap and swapper page
402 * tables again to remove any speculatively loaded cache lines.
405 add x1, x26, #SWAPPER_DIR_SIZE
407 bl __inval_cache_range
411 ENDPROC(__create_page_tables)
415 * The following fragment of code is executed with the MMU enabled.
417 .set initial_sp, init_thread_union + THREAD_START_SP
419 adr_l x6, __bss_start
424 str xzr, [x6], #8 // Clear BSS
428 add sp, x4, :lo12:initial_sp
429 str_l x21, __fdt_pointer, x5 // Save FDT pointer
430 str_l x24, memstart_addr, x6 // Save PHYS_OFFSET
436 ENDPROC(__mmap_switched)
439 * end early head section, begin head code that is also used for
440 * hotplug and needs to have the same protections as the text region
442 .section ".text","ax"
444 * If we're fortunate enough to boot at EL2, ensure that the world is
445 * sane before dropping to EL1.
447 * Returns either BOOT_CPU_MODE_EL1 or BOOT_CPU_MODE_EL2 in x20 if
448 * booted in EL1 or EL2 respectively.
451 msr SPsel, #1 // We want to use SP_EL{1,2}
453 cmp x0, #CurrentEL_EL2
456 CPU_BE( orr x0, x0, #(1 << 25) ) // Set the EE bit for EL2
457 CPU_LE( bic x0, x0, #(1 << 25) ) // Clear the EE bit for EL2
461 CPU_BE( orr x0, x0, #(3 << 24) ) // Set the EE and E0E bits for EL1
462 CPU_LE( bic x0, x0, #(3 << 24) ) // Clear the EE and E0E bits for EL1
464 mov w20, #BOOT_CPU_MODE_EL1 // This cpu booted in EL1
468 /* Hyp configuration. */
469 2: mov_q x0, HCR_HOST_NVHE_FLAGS
472 /* Generic timers. */
474 orr x0, x0, #3 // Enable EL1 physical timers
476 msr cntvoff_el2, xzr // Clear virtual offset
478 #ifdef CONFIG_ARM_GIC_V3
479 /* GICv3 system register access */
480 mrs x0, id_aa64pfr0_el1
484 mrs_s x0, ICC_SRE_EL2
485 orr x0, x0, #ICC_SRE_EL2_SRE // Set ICC_SRE_EL2.SRE==1
486 orr x0, x0, #ICC_SRE_EL2_ENABLE // Set ICC_SRE_EL2.Enable==1
487 msr_s ICC_SRE_EL2, x0
488 isb // Make sure SRE is now set
489 mrs_s x0, ICC_SRE_EL2 // Read SRE back,
490 tbz x0, #0, 3f // and check that it sticks
491 msr_s ICH_HCR_EL2, xzr // Reset ICC_HCR_EL2 to defaults
496 /* Populate ID registers. */
503 mov x0, #0x0800 // Set/clear RES{1,0} bits
504 CPU_BE( movk x0, #0x33d0, lsl #16 ) // Set EE and E0E on BE systems
505 CPU_LE( movk x0, #0x30d0, lsl #16 ) // Clear EE and E0E on LE systems
508 /* Coprocessor traps. */
510 msr cptr_el2, x0 // Disable copro. traps to EL2
513 msr hstr_el2, xzr // Disable CP15 traps to EL2
517 mrs x0, id_aa64dfr0_el1 // Check ID_AA64DFR0_EL1 PMUVer
520 b.lt 4f // Skip if no PMU present
521 mrs x0, pmcr_el0 // Disable debug access traps
522 ubfx x0, x0, #11, #5 // to EL2 and allow access to
524 csel x0, xzr, x0, lt // all PMU counters from EL1
525 msr mdcr_el2, x0 // (if they exist)
527 /* Stage-2 translation */
530 /* Hypervisor stub */
531 adrp x0, __hyp_stub_vectors
532 add x0, x0, #:lo12:__hyp_stub_vectors
536 mov x0, #(PSR_F_BIT | PSR_I_BIT | PSR_A_BIT | PSR_D_BIT |\
540 mov w20, #BOOT_CPU_MODE_EL2 // This CPU booted in EL2
545 * Sets the __boot_cpu_mode flag depending on the CPU boot mode passed
546 * in x20. See arch/arm64/include/asm/virt.h for more info.
548 ENTRY(set_cpu_boot_mode_flag)
549 adr_l x1, __boot_cpu_mode
550 cmp w20, #BOOT_CPU_MODE_EL2
553 1: str w20, [x1] // This CPU has booted in EL1
555 dc ivac, x1 // Invalidate potentially stale cache line
557 ENDPROC(set_cpu_boot_mode_flag)
560 * We need to find out the CPU boot mode long after boot, so we need to
561 * store it in a writable variable.
563 * This is not in .bss, because we set it sufficiently early that the boot-time
564 * zeroing of .bss would clobber it.
566 .pushsection .data..cacheline_aligned
567 .align L1_CACHE_SHIFT
568 ENTRY(__boot_cpu_mode)
569 .long BOOT_CPU_MODE_EL2
570 .long BOOT_CPU_MODE_EL1
574 * This provides a "holding pen" for platforms to hold all secondary
575 * cores are held until we're ready for them to initialise.
577 ENTRY(secondary_holding_pen)
578 bl el2_setup // Drop to EL1, w20=cpu_boot_mode
579 bl set_cpu_boot_mode_flag
581 ldr x1, =MPIDR_HWID_BITMASK
583 adr_l x3, secondary_holding_pen_release
586 b.eq secondary_startup
589 ENDPROC(secondary_holding_pen)
592 * Secondary entry point that jumps straight into the kernel. Only to
593 * be used where CPUs are brought online dynamically by the kernel.
595 ENTRY(secondary_entry)
596 bl el2_setup // Drop to EL1
597 bl set_cpu_boot_mode_flag
599 ENDPROC(secondary_entry)
601 ENTRY(secondary_startup)
603 * Common entry point for secondary CPUs.
605 adrp x25, idmap_pg_dir
606 adrp x26, swapper_pg_dir
607 bl __cpu_setup // initialise processor
609 ldr x21, =secondary_data
610 ldr x27, =__secondary_switched // address to jump to after enabling the MMU
612 ENDPROC(secondary_startup)
614 ENTRY(__secondary_switched)
615 ldr x0, [x21] // get secondary_data.stack
618 b secondary_start_kernel
619 ENDPROC(__secondary_switched)
624 * x0 = SCTLR_EL1 value for turning on the MMU.
625 * x27 = *virtual* address to jump to upon completion
627 * Other registers depend on the function called upon completion.
629 * Checks if the selected granule size is supported by the CPU.
630 * If it isn't, park the CPU
632 .section ".idmap.text", "ax"
634 mrs x1, ID_AA64MMFR0_EL1
635 ubfx x2, x1, #ID_AA64MMFR0_TGRAN_SHIFT, 4
636 cmp x2, #ID_AA64MMFR0_TGRAN_SUPPORTED
637 b.ne __no_granule_support
640 msr ttbr0_el1, x25 // load TTBR0
641 msr ttbr1_el1, x26 // load TTBR1
646 * Invalidate the local I-cache so that any instructions fetched
647 * speculatively from the PoC are discarded, since they may have
648 * been dynamically patched at the PoU.
654 ENDPROC(__enable_mmu)
656 __no_granule_support:
658 b __no_granule_support
659 ENDPROC(__no_granule_support)