1 // SPDX-License-Identifier: GPL-2.0-only
3 * FP/SIMD context switching and fault handling
5 * Copyright (C) 2012 ARM Ltd.
6 * Author: Catalin Marinas <catalin.marinas@arm.com>
9 #include <linux/bitmap.h>
10 #include <linux/bitops.h>
11 #include <linux/bottom_half.h>
12 #include <linux/bug.h>
13 #include <linux/cache.h>
14 #include <linux/compat.h>
15 #include <linux/compiler.h>
16 #include <linux/cpu.h>
17 #include <linux/cpu_pm.h>
18 #include <linux/ctype.h>
19 #include <linux/kernel.h>
20 #include <linux/linkage.h>
21 #include <linux/irqflags.h>
22 #include <linux/init.h>
23 #include <linux/percpu.h>
24 #include <linux/prctl.h>
25 #include <linux/preempt.h>
26 #include <linux/ptrace.h>
27 #include <linux/sched/signal.h>
28 #include <linux/sched/task_stack.h>
29 #include <linux/signal.h>
30 #include <linux/slab.h>
31 #include <linux/stddef.h>
32 #include <linux/sysctl.h>
33 #include <linux/swab.h>
36 #include <asm/exception.h>
37 #include <asm/fpsimd.h>
38 #include <asm/cpufeature.h>
39 #include <asm/cputype.h>
41 #include <asm/processor.h>
43 #include <asm/sigcontext.h>
44 #include <asm/sysreg.h>
45 #include <asm/traps.h>
48 #define FPEXC_IOF (1 << 0)
49 #define FPEXC_DZF (1 << 1)
50 #define FPEXC_OFF (1 << 2)
51 #define FPEXC_UFF (1 << 3)
52 #define FPEXC_IXF (1 << 4)
53 #define FPEXC_IDF (1 << 7)
56 * (Note: in this discussion, statements about FPSIMD apply equally to SVE.)
58 * In order to reduce the number of times the FPSIMD state is needlessly saved
59 * and restored, we need to keep track of two things:
60 * (a) for each task, we need to remember which CPU was the last one to have
61 * the task's FPSIMD state loaded into its FPSIMD registers;
62 * (b) for each CPU, we need to remember which task's userland FPSIMD state has
63 * been loaded into its FPSIMD registers most recently, or whether it has
64 * been used to perform kernel mode NEON in the meantime.
66 * For (a), we add a fpsimd_cpu field to thread_struct, which gets updated to
67 * the id of the current CPU every time the state is loaded onto a CPU. For (b),
68 * we add the per-cpu variable 'fpsimd_last_state' (below), which contains the
69 * address of the userland FPSIMD state of the task that was loaded onto the CPU
70 * the most recently, or NULL if kernel mode NEON has been performed after that.
72 * With this in place, we no longer have to restore the next FPSIMD state right
73 * when switching between tasks. Instead, we can defer this check to userland
74 * resume, at which time we verify whether the CPU's fpsimd_last_state and the
75 * task's fpsimd_cpu are still mutually in sync. If this is the case, we
76 * can omit the FPSIMD restore.
78 * As an optimization, we use the thread_info flag TIF_FOREIGN_FPSTATE to
79 * indicate whether or not the userland FPSIMD state of the current task is
80 * present in the registers. The flag is set unless the FPSIMD registers of this
81 * CPU currently contain the most recent userland FPSIMD state of the current
82 * task. If the task is behaving as a VMM, then this is will be managed by
83 * KVM which will clear it to indicate that the vcpu FPSIMD state is currently
84 * loaded on the CPU, allowing the state to be saved if a FPSIMD-aware
85 * softirq kicks in. Upon vcpu_put(), KVM will save the vcpu FP state and
86 * flag the register state as invalid.
88 * In order to allow softirq handlers to use FPSIMD, kernel_neon_begin() may
89 * save the task's FPSIMD context back to task_struct from softirq context.
90 * To prevent this from racing with the manipulation of the task's FPSIMD state
91 * from task context and thereby corrupting the state, it is necessary to
92 * protect any manipulation of a task's fpsimd_state or TIF_FOREIGN_FPSTATE
93 * flag with {, __}get_cpu_fpsimd_context(). This will still allow softirqs to
94 * run but prevent them to use FPSIMD.
96 * For a certain task, the sequence may look something like this:
97 * - the task gets scheduled in; if both the task's fpsimd_cpu field
98 * contains the id of the current CPU, and the CPU's fpsimd_last_state per-cpu
99 * variable points to the task's fpsimd_state, the TIF_FOREIGN_FPSTATE flag is
100 * cleared, otherwise it is set;
102 * - the task returns to userland; if TIF_FOREIGN_FPSTATE is set, the task's
103 * userland FPSIMD state is copied from memory to the registers, the task's
104 * fpsimd_cpu field is set to the id of the current CPU, the current
105 * CPU's fpsimd_last_state pointer is set to this task's fpsimd_state and the
106 * TIF_FOREIGN_FPSTATE flag is cleared;
108 * - the task executes an ordinary syscall; upon return to userland, the
109 * TIF_FOREIGN_FPSTATE flag will still be cleared, so no FPSIMD state is
112 * - the task executes a syscall which executes some NEON instructions; this is
113 * preceded by a call to kernel_neon_begin(), which copies the task's FPSIMD
114 * register contents to memory, clears the fpsimd_last_state per-cpu variable
115 * and sets the TIF_FOREIGN_FPSTATE flag;
117 * - the task gets preempted after kernel_neon_end() is called; as we have not
118 * returned from the 2nd syscall yet, TIF_FOREIGN_FPSTATE is still set so
119 * whatever is in the FPSIMD registers is not saved to memory, but discarded.
121 struct fpsimd_last_state_struct {
122 struct user_fpsimd_state *st;
130 static DEFINE_PER_CPU(struct fpsimd_last_state_struct, fpsimd_last_state);
132 __ro_after_init struct vl_info vl_info[ARM64_VEC_MAX] = {
133 #ifdef CONFIG_ARM64_SVE
135 .type = ARM64_VEC_SVE,
137 .min_vl = SVE_VL_MIN,
138 .max_vl = SVE_VL_MIN,
139 .max_virtualisable_vl = SVE_VL_MIN,
142 #ifdef CONFIG_ARM64_SME
144 .type = ARM64_VEC_SME,
150 static unsigned int vec_vl_inherit_flag(enum vec_type type)
154 return TIF_SVE_VL_INHERIT;
156 return TIF_SME_VL_INHERIT;
164 int __default_vl; /* Default VL for tasks */
167 static struct vl_config vl_config[ARM64_VEC_MAX];
169 static inline int get_default_vl(enum vec_type type)
171 return READ_ONCE(vl_config[type].__default_vl);
174 #ifdef CONFIG_ARM64_SVE
176 static inline int get_sve_default_vl(void)
178 return get_default_vl(ARM64_VEC_SVE);
181 static inline void set_default_vl(enum vec_type type, int val)
183 WRITE_ONCE(vl_config[type].__default_vl, val);
186 static inline void set_sve_default_vl(int val)
188 set_default_vl(ARM64_VEC_SVE, val);
191 static void __percpu *efi_sve_state;
193 #else /* ! CONFIG_ARM64_SVE */
195 /* Dummy declaration for code that will be optimised out: */
196 extern void __percpu *efi_sve_state;
198 #endif /* ! CONFIG_ARM64_SVE */
200 #ifdef CONFIG_ARM64_SME
202 static int get_sme_default_vl(void)
204 return get_default_vl(ARM64_VEC_SME);
207 static void set_sme_default_vl(int val)
209 set_default_vl(ARM64_VEC_SME, val);
212 static void sme_free(struct task_struct *);
216 static inline void sme_free(struct task_struct *t) { }
220 DEFINE_PER_CPU(bool, fpsimd_context_busy);
221 EXPORT_PER_CPU_SYMBOL(fpsimd_context_busy);
223 static void fpsimd_bind_task_to_cpu(void);
225 static void __get_cpu_fpsimd_context(void)
227 bool busy = __this_cpu_xchg(fpsimd_context_busy, true);
233 * Claim ownership of the CPU FPSIMD context for use by the calling context.
235 * The caller may freely manipulate the FPSIMD context metadata until
236 * put_cpu_fpsimd_context() is called.
238 * The double-underscore version must only be called if you know the task
239 * can't be preempted.
241 * On RT kernels local_bh_disable() is not sufficient because it only
242 * serializes soft interrupt related sections via a local lock, but stays
243 * preemptible. Disabling preemption is the right choice here as bottom
244 * half processing is always in thread context on RT kernels so it
245 * implicitly prevents bottom half processing as well.
247 static void get_cpu_fpsimd_context(void)
249 if (!IS_ENABLED(CONFIG_PREEMPT_RT))
253 __get_cpu_fpsimd_context();
256 static void __put_cpu_fpsimd_context(void)
258 bool busy = __this_cpu_xchg(fpsimd_context_busy, false);
260 WARN_ON(!busy); /* No matching get_cpu_fpsimd_context()? */
264 * Release the CPU FPSIMD context.
266 * Must be called from a context in which get_cpu_fpsimd_context() was
267 * previously called, with no call to put_cpu_fpsimd_context() in the
270 static void put_cpu_fpsimd_context(void)
272 __put_cpu_fpsimd_context();
273 if (!IS_ENABLED(CONFIG_PREEMPT_RT))
279 static bool have_cpu_fpsimd_context(void)
281 return !preemptible() && __this_cpu_read(fpsimd_context_busy);
284 unsigned int task_get_vl(const struct task_struct *task, enum vec_type type)
286 return task->thread.vl[type];
289 void task_set_vl(struct task_struct *task, enum vec_type type,
292 task->thread.vl[type] = vl;
295 unsigned int task_get_vl_onexec(const struct task_struct *task,
298 return task->thread.vl_onexec[type];
301 void task_set_vl_onexec(struct task_struct *task, enum vec_type type,
304 task->thread.vl_onexec[type] = vl;
308 * TIF_SME controls whether a task can use SME without trapping while
309 * in userspace, when TIF_SME is set then we must have storage
310 * alocated in sve_state and za_state to store the contents of both ZA
311 * and the SVE registers for both streaming and non-streaming modes.
313 * If both SVCR.ZA and SVCR.SM are disabled then at any point we
314 * may disable TIF_SME and reenable traps.
319 * TIF_SVE controls whether a task can use SVE without trapping while
320 * in userspace, and also (together with TIF_SME) the way a task's
321 * FPSIMD/SVE state is stored in thread_struct.
323 * The kernel uses this flag to track whether a user task is actively
324 * using SVE, and therefore whether full SVE register state needs to
325 * be tracked. If not, the cheaper FPSIMD context handling code can
326 * be used instead of the more costly SVE equivalents.
328 * * TIF_SVE or SVCR.SM set:
330 * The task can execute SVE instructions while in userspace without
331 * trapping to the kernel.
333 * When stored, Z0-Z31 (incorporating Vn in bits[127:0] or the
334 * corresponding Zn), P0-P15 and FFR are encoded in
335 * task->thread.sve_state, formatted appropriately for vector
336 * length task->thread.sve_vl or, if SVCR.SM is set,
337 * task->thread.sme_vl.
339 * task->thread.sve_state must point to a valid buffer at least
340 * sve_state_size(task) bytes in size.
342 * During any syscall, the kernel may optionally clear TIF_SVE and
343 * discard the vector state except for the FPSIMD subset.
347 * An attempt by the user task to execute an SVE instruction causes
348 * do_sve_acc() to be called, which does some preparation and then
351 * When stored, FPSIMD registers V0-V31 are encoded in
352 * task->thread.uw.fpsimd_state; bits [max : 128] for each of Z0-Z31 are
353 * logically zero but not stored anywhere; P0-P15 and FFR are not
354 * stored and have unspecified values from userspace's point of
355 * view. For hygiene purposes, the kernel zeroes them on next use,
356 * but userspace is discouraged from relying on this.
358 * task->thread.sve_state does not need to be non-NULL, valid or any
359 * particular size: it must not be dereferenced.
361 * * FPSR and FPCR are always stored in task->thread.uw.fpsimd_state
362 * irrespective of whether TIF_SVE is clear or set, since these are
363 * not vector length dependent.
367 * Update current's FPSIMD/SVE registers from thread_struct.
369 * This function should be called only when the FPSIMD/SVE state in
370 * thread_struct is known to be up to date, when preparing to enter
373 static void task_fpsimd_load(void)
375 bool restore_sve_regs = false;
378 WARN_ON(!system_supports_fpsimd());
379 WARN_ON(!have_cpu_fpsimd_context());
381 /* Check if we should restore SVE first */
382 if (IS_ENABLED(CONFIG_ARM64_SVE) && test_thread_flag(TIF_SVE)) {
383 sve_set_vq(sve_vq_from_vl(task_get_sve_vl(current)) - 1);
384 restore_sve_regs = true;
388 /* Restore SME, override SVE register configuration if needed */
389 if (system_supports_sme()) {
390 unsigned long sme_vl = task_get_sme_vl(current);
392 /* Ensure VL is set up for restoring data */
393 if (test_thread_flag(TIF_SME))
394 sme_set_vq(sve_vq_from_vl(sme_vl) - 1);
396 write_sysreg_s(current->thread.svcr, SYS_SVCR);
398 if (thread_za_enabled(¤t->thread))
399 za_load_state(current->thread.za_state);
401 if (thread_sm_enabled(¤t->thread)) {
402 restore_sve_regs = true;
403 restore_ffr = system_supports_fa64();
407 if (restore_sve_regs)
408 sve_load_state(sve_pffr(¤t->thread),
409 ¤t->thread.uw.fpsimd_state.fpsr,
412 fpsimd_load_state(¤t->thread.uw.fpsimd_state);
416 * Ensure FPSIMD/SVE storage in memory for the loaded context is up to
417 * date with respect to the CPU registers. Note carefully that the
418 * current context is the context last bound to the CPU stored in
419 * last, if KVM is involved this may be the guest VM context rather
420 * than the host thread for the VM pointed to by current. This means
421 * that we must always reference the state storage via last rather
422 * than via current, other than the TIF_ flags which KVM will
423 * carefully maintain for us.
425 static void fpsimd_save(void)
427 struct fpsimd_last_state_struct const *last =
428 this_cpu_ptr(&fpsimd_last_state);
429 /* set by fpsimd_bind_task_to_cpu() or fpsimd_bind_state_to_cpu() */
430 bool save_sve_regs = false;
434 WARN_ON(!system_supports_fpsimd());
435 WARN_ON(!have_cpu_fpsimd_context());
437 if (test_thread_flag(TIF_FOREIGN_FPSTATE))
440 if (test_thread_flag(TIF_SVE)) {
441 save_sve_regs = true;
446 if (system_supports_sme()) {
447 u64 *svcr = last->svcr;
449 *svcr = read_sysreg_s(SYS_SVCR);
451 if (*svcr & SVCR_ZA_MASK)
452 za_save_state(last->za_state);
454 /* If we are in streaming mode override regular SVE. */
455 if (*svcr & SVCR_SM_MASK) {
456 save_sve_regs = true;
457 save_ffr = system_supports_fa64();
462 if (IS_ENABLED(CONFIG_ARM64_SVE) && save_sve_regs) {
463 /* Get the configured VL from RDVL, will account for SM */
464 if (WARN_ON(sve_get_vl() != vl)) {
466 * Can't save the user regs, so current would
467 * re-enter user with corrupt state.
468 * There's no way to recover, so kill it:
470 force_signal_inject(SIGKILL, SI_KERNEL, 0, 0);
474 sve_save_state((char *)last->sve_state +
476 &last->st->fpsr, save_ffr);
478 fpsimd_save_state(last->st);
483 * All vector length selection from userspace comes through here.
484 * We're on a slow path, so some sanity-checks are included.
485 * If things go wrong there's a bug somewhere, but try to fall back to a
488 static unsigned int find_supported_vector_length(enum vec_type type,
491 struct vl_info *info = &vl_info[type];
493 int max_vl = info->max_vl;
495 if (WARN_ON(!sve_vl_valid(vl)))
498 if (WARN_ON(!sve_vl_valid(max_vl)))
499 max_vl = info->min_vl;
503 if (vl < info->min_vl)
506 bit = find_next_bit(info->vq_map, SVE_VQ_MAX,
507 __vq_to_bit(sve_vq_from_vl(vl)));
508 return sve_vl_from_vq(__bit_to_vq(bit));
511 #if defined(CONFIG_ARM64_SVE) && defined(CONFIG_SYSCTL)
513 static int vec_proc_do_default_vl(struct ctl_table *table, int write,
514 void *buffer, size_t *lenp, loff_t *ppos)
516 struct vl_info *info = table->extra1;
517 enum vec_type type = info->type;
519 int vl = get_default_vl(type);
520 struct ctl_table tmp_table = {
522 .maxlen = sizeof(vl),
525 ret = proc_dointvec(&tmp_table, write, buffer, lenp, ppos);
529 /* Writing -1 has the special meaning "set to max": */
533 if (!sve_vl_valid(vl))
536 set_default_vl(type, find_supported_vector_length(type, vl));
540 static struct ctl_table sve_default_vl_table[] = {
542 .procname = "sve_default_vector_length",
544 .proc_handler = vec_proc_do_default_vl,
545 .extra1 = &vl_info[ARM64_VEC_SVE],
550 static int __init sve_sysctl_init(void)
552 if (system_supports_sve())
553 if (!register_sysctl("abi", sve_default_vl_table))
559 #else /* ! (CONFIG_ARM64_SVE && CONFIG_SYSCTL) */
560 static int __init sve_sysctl_init(void) { return 0; }
561 #endif /* ! (CONFIG_ARM64_SVE && CONFIG_SYSCTL) */
563 #if defined(CONFIG_ARM64_SME) && defined(CONFIG_SYSCTL)
564 static struct ctl_table sme_default_vl_table[] = {
566 .procname = "sme_default_vector_length",
568 .proc_handler = vec_proc_do_default_vl,
569 .extra1 = &vl_info[ARM64_VEC_SME],
574 static int __init sme_sysctl_init(void)
576 if (system_supports_sme())
577 if (!register_sysctl("abi", sme_default_vl_table))
583 #else /* ! (CONFIG_ARM64_SME && CONFIG_SYSCTL) */
584 static int __init sme_sysctl_init(void) { return 0; }
585 #endif /* ! (CONFIG_ARM64_SME && CONFIG_SYSCTL) */
587 #define ZREG(sve_state, vq, n) ((char *)(sve_state) + \
588 (SVE_SIG_ZREG_OFFSET(vq, n) - SVE_SIG_REGS_OFFSET))
590 #ifdef CONFIG_CPU_BIG_ENDIAN
591 static __uint128_t arm64_cpu_to_le128(__uint128_t x)
594 u64 b = swab64(x >> 64);
596 return ((__uint128_t)a << 64) | b;
599 static __uint128_t arm64_cpu_to_le128(__uint128_t x)
605 #define arm64_le128_to_cpu(x) arm64_cpu_to_le128(x)
607 static void __fpsimd_to_sve(void *sst, struct user_fpsimd_state const *fst,
613 for (i = 0; i < SVE_NUM_ZREGS; ++i) {
614 p = (__uint128_t *)ZREG(sst, vq, i);
615 *p = arm64_cpu_to_le128(fst->vregs[i]);
620 * Transfer the FPSIMD state in task->thread.uw.fpsimd_state to
621 * task->thread.sve_state.
623 * Task can be a non-runnable task, or current. In the latter case,
624 * the caller must have ownership of the cpu FPSIMD context before calling
626 * task->thread.sve_state must point to at least sve_state_size(task)
627 * bytes of allocated kernel memory.
628 * task->thread.uw.fpsimd_state must be up to date before calling this
631 static void fpsimd_to_sve(struct task_struct *task)
634 void *sst = task->thread.sve_state;
635 struct user_fpsimd_state const *fst = &task->thread.uw.fpsimd_state;
637 if (!system_supports_sve() && !system_supports_sme())
640 vq = sve_vq_from_vl(thread_get_cur_vl(&task->thread));
641 __fpsimd_to_sve(sst, fst, vq);
645 * Transfer the SVE state in task->thread.sve_state to
646 * task->thread.uw.fpsimd_state.
648 * Task can be a non-runnable task, or current. In the latter case,
649 * the caller must have ownership of the cpu FPSIMD context before calling
651 * task->thread.sve_state must point to at least sve_state_size(task)
652 * bytes of allocated kernel memory.
653 * task->thread.sve_state must be up to date before calling this function.
655 static void sve_to_fpsimd(struct task_struct *task)
658 void const *sst = task->thread.sve_state;
659 struct user_fpsimd_state *fst = &task->thread.uw.fpsimd_state;
661 __uint128_t const *p;
663 if (!system_supports_sve() && !system_supports_sme())
666 vl = thread_get_cur_vl(&task->thread);
667 vq = sve_vq_from_vl(vl);
668 for (i = 0; i < SVE_NUM_ZREGS; ++i) {
669 p = (__uint128_t const *)ZREG(sst, vq, i);
670 fst->vregs[i] = arm64_le128_to_cpu(*p);
674 #ifdef CONFIG_ARM64_SVE
676 * Call __sve_free() directly only if you know task can't be scheduled
679 static void __sve_free(struct task_struct *task)
681 kfree(task->thread.sve_state);
682 task->thread.sve_state = NULL;
685 static void sve_free(struct task_struct *task)
687 WARN_ON(test_tsk_thread_flag(task, TIF_SVE));
693 * Return how many bytes of memory are required to store the full SVE
694 * state for task, given task's currently configured vector length.
696 size_t sve_state_size(struct task_struct const *task)
700 if (system_supports_sve())
701 vl = task_get_sve_vl(task);
702 if (system_supports_sme())
703 vl = max(vl, task_get_sme_vl(task));
705 return SVE_SIG_REGS_SIZE(sve_vq_from_vl(vl));
709 * Ensure that task->thread.sve_state is allocated and sufficiently large.
711 * This function should be used only in preparation for replacing
712 * task->thread.sve_state with new data. The memory is always zeroed
713 * here to prevent stale data from showing through: this is done in
714 * the interest of testability and predictability: except in the
715 * do_sve_acc() case, there is no ABI requirement to hide stale data
716 * written previously be task.
718 void sve_alloc(struct task_struct *task, bool flush)
720 if (task->thread.sve_state) {
722 memset(task->thread.sve_state, 0,
723 sve_state_size(task));
727 /* This is a small allocation (maximum ~8KB) and Should Not Fail. */
728 task->thread.sve_state =
729 kzalloc(sve_state_size(task), GFP_KERNEL);
734 * Force the FPSIMD state shared with SVE to be updated in the SVE state
735 * even if the SVE state is the current active state.
737 * This should only be called by ptrace. task must be non-runnable.
738 * task->thread.sve_state must point to at least sve_state_size(task)
739 * bytes of allocated kernel memory.
741 void fpsimd_force_sync_to_sve(struct task_struct *task)
747 * Ensure that task->thread.sve_state is up to date with respect to
748 * the user task, irrespective of when SVE is in use or not.
750 * This should only be called by ptrace. task must be non-runnable.
751 * task->thread.sve_state must point to at least sve_state_size(task)
752 * bytes of allocated kernel memory.
754 void fpsimd_sync_to_sve(struct task_struct *task)
756 if (!test_tsk_thread_flag(task, TIF_SVE) &&
757 !thread_sm_enabled(&task->thread))
762 * Ensure that task->thread.uw.fpsimd_state is up to date with respect to
763 * the user task, irrespective of whether SVE is in use or not.
765 * This should only be called by ptrace. task must be non-runnable.
766 * task->thread.sve_state must point to at least sve_state_size(task)
767 * bytes of allocated kernel memory.
769 void sve_sync_to_fpsimd(struct task_struct *task)
771 if (test_tsk_thread_flag(task, TIF_SVE) ||
772 thread_sm_enabled(&task->thread))
777 * Ensure that task->thread.sve_state is up to date with respect to
778 * the task->thread.uw.fpsimd_state.
780 * This should only be called by ptrace to merge new FPSIMD register
781 * values into a task for which SVE is currently active.
782 * task must be non-runnable.
783 * task->thread.sve_state must point to at least sve_state_size(task)
784 * bytes of allocated kernel memory.
785 * task->thread.uw.fpsimd_state must already have been initialised with
786 * the new FPSIMD register values to be merged in.
788 void sve_sync_from_fpsimd_zeropad(struct task_struct *task)
791 void *sst = task->thread.sve_state;
792 struct user_fpsimd_state const *fst = &task->thread.uw.fpsimd_state;
794 if (!test_tsk_thread_flag(task, TIF_SVE) &&
795 !thread_sm_enabled(&task->thread))
798 vq = sve_vq_from_vl(thread_get_cur_vl(&task->thread));
800 memset(sst, 0, SVE_SIG_REGS_SIZE(vq));
801 __fpsimd_to_sve(sst, fst, vq);
804 int vec_set_vector_length(struct task_struct *task, enum vec_type type,
805 unsigned long vl, unsigned long flags)
807 bool free_sme = false;
809 if (flags & ~(unsigned long)(PR_SVE_VL_INHERIT |
810 PR_SVE_SET_VL_ONEXEC))
813 if (!sve_vl_valid(vl))
817 * Clamp to the maximum vector length that VL-agnostic code
818 * can work with. A flag may be assigned in the future to
819 * allow setting of larger vector lengths without confusing
822 if (vl > VL_ARCH_MAX)
825 vl = find_supported_vector_length(type, vl);
827 if (flags & (PR_SVE_VL_INHERIT |
828 PR_SVE_SET_VL_ONEXEC))
829 task_set_vl_onexec(task, type, vl);
831 /* Reset VL to system default on next exec: */
832 task_set_vl_onexec(task, type, 0);
834 /* Only actually set the VL if not deferred: */
835 if (flags & PR_SVE_SET_VL_ONEXEC)
838 if (vl == task_get_vl(task, type))
842 * To ensure the FPSIMD bits of the SVE vector registers are preserved,
843 * write any live register state back to task_struct, and convert to a
844 * regular FPSIMD thread.
846 if (task == current) {
847 get_cpu_fpsimd_context();
852 fpsimd_flush_task_state(task);
853 if (test_and_clear_tsk_thread_flag(task, TIF_SVE) ||
854 thread_sm_enabled(&task->thread))
857 if (system_supports_sme()) {
858 if (type == ARM64_VEC_SME ||
859 !(task->thread.svcr & (SVCR_SM_MASK | SVCR_ZA_MASK))) {
861 * We are changing the SME VL or weren't using
862 * SME anyway, discard the state and force a
865 task->thread.svcr &= ~(SVCR_SM_MASK |
867 clear_tsk_thread_flag(task, TIF_SME);
873 put_cpu_fpsimd_context();
875 task_set_vl(task, type, vl);
878 * Free the changed states if they are not in use, SME will be
879 * reallocated to the correct size on next use and we just
880 * allocate SVE now in case it is needed for use in streaming
883 if (system_supports_sve()) {
885 sve_alloc(task, true);
892 update_tsk_thread_flag(task, vec_vl_inherit_flag(type),
893 flags & PR_SVE_VL_INHERIT);
899 * Encode the current vector length and flags for return.
900 * This is only required for prctl(): ptrace has separate fields.
901 * SVE and SME use the same bits for _ONEXEC and _INHERIT.
903 * flags are as for vec_set_vector_length().
905 static int vec_prctl_status(enum vec_type type, unsigned long flags)
909 if (flags & PR_SVE_SET_VL_ONEXEC)
910 ret = task_get_vl_onexec(current, type);
912 ret = task_get_vl(current, type);
914 if (test_thread_flag(vec_vl_inherit_flag(type)))
915 ret |= PR_SVE_VL_INHERIT;
921 int sve_set_current_vl(unsigned long arg)
923 unsigned long vl, flags;
926 vl = arg & PR_SVE_VL_LEN_MASK;
929 if (!system_supports_sve() || is_compat_task())
932 ret = vec_set_vector_length(current, ARM64_VEC_SVE, vl, flags);
936 return vec_prctl_status(ARM64_VEC_SVE, flags);
940 int sve_get_current_vl(void)
942 if (!system_supports_sve() || is_compat_task())
945 return vec_prctl_status(ARM64_VEC_SVE, 0);
948 #ifdef CONFIG_ARM64_SME
950 int sme_set_current_vl(unsigned long arg)
952 unsigned long vl, flags;
955 vl = arg & PR_SME_VL_LEN_MASK;
958 if (!system_supports_sme() || is_compat_task())
961 ret = vec_set_vector_length(current, ARM64_VEC_SME, vl, flags);
965 return vec_prctl_status(ARM64_VEC_SME, flags);
969 int sme_get_current_vl(void)
971 if (!system_supports_sme() || is_compat_task())
974 return vec_prctl_status(ARM64_VEC_SME, 0);
976 #endif /* CONFIG_ARM64_SME */
978 static void vec_probe_vqs(struct vl_info *info,
979 DECLARE_BITMAP(map, SVE_VQ_MAX))
983 bitmap_zero(map, SVE_VQ_MAX);
985 for (vq = SVE_VQ_MAX; vq >= SVE_VQ_MIN; --vq) {
986 write_vl(info->type, vq - 1); /* self-syncing */
988 switch (info->type) {
1000 /* Minimum VL identified? */
1001 if (sve_vq_from_vl(vl) > vq)
1004 vq = sve_vq_from_vl(vl); /* skip intervening lengths */
1005 set_bit(__vq_to_bit(vq), map);
1010 * Initialise the set of known supported VQs for the boot CPU.
1011 * This is called during kernel boot, before secondary CPUs are brought up.
1013 void __init vec_init_vq_map(enum vec_type type)
1015 struct vl_info *info = &vl_info[type];
1016 vec_probe_vqs(info, info->vq_map);
1017 bitmap_copy(info->vq_partial_map, info->vq_map, SVE_VQ_MAX);
1021 * If we haven't committed to the set of supported VQs yet, filter out
1022 * those not supported by the current CPU.
1023 * This function is called during the bring-up of early secondary CPUs only.
1025 void vec_update_vq_map(enum vec_type type)
1027 struct vl_info *info = &vl_info[type];
1028 DECLARE_BITMAP(tmp_map, SVE_VQ_MAX);
1030 vec_probe_vqs(info, tmp_map);
1031 bitmap_and(info->vq_map, info->vq_map, tmp_map, SVE_VQ_MAX);
1032 bitmap_or(info->vq_partial_map, info->vq_partial_map, tmp_map,
1037 * Check whether the current CPU supports all VQs in the committed set.
1038 * This function is called during the bring-up of late secondary CPUs only.
1040 int vec_verify_vq_map(enum vec_type type)
1042 struct vl_info *info = &vl_info[type];
1043 DECLARE_BITMAP(tmp_map, SVE_VQ_MAX);
1046 vec_probe_vqs(info, tmp_map);
1048 bitmap_complement(tmp_map, tmp_map, SVE_VQ_MAX);
1049 if (bitmap_intersects(tmp_map, info->vq_map, SVE_VQ_MAX)) {
1050 pr_warn("%s: cpu%d: Required vector length(s) missing\n",
1051 info->name, smp_processor_id());
1055 if (!IS_ENABLED(CONFIG_KVM) || !is_hyp_mode_available())
1059 * For KVM, it is necessary to ensure that this CPU doesn't
1060 * support any vector length that guests may have probed as
1064 /* Recover the set of supported VQs: */
1065 bitmap_complement(tmp_map, tmp_map, SVE_VQ_MAX);
1066 /* Find VQs supported that are not globally supported: */
1067 bitmap_andnot(tmp_map, tmp_map, info->vq_map, SVE_VQ_MAX);
1069 /* Find the lowest such VQ, if any: */
1070 b = find_last_bit(tmp_map, SVE_VQ_MAX);
1071 if (b >= SVE_VQ_MAX)
1072 return 0; /* no mismatches */
1075 * Mismatches above sve_max_virtualisable_vl are fine, since
1076 * no guest is allowed to configure ZCR_EL2.LEN to exceed this:
1078 if (sve_vl_from_vq(__bit_to_vq(b)) <= info->max_virtualisable_vl) {
1079 pr_warn("%s: cpu%d: Unsupported vector length(s) present\n",
1080 info->name, smp_processor_id());
1087 static void __init sve_efi_setup(void)
1092 if (!IS_ENABLED(CONFIG_EFI))
1095 for (i = 0; i < ARRAY_SIZE(vl_info); i++)
1096 max_vl = max(vl_info[i].max_vl, max_vl);
1099 * alloc_percpu() warns and prints a backtrace if this goes wrong.
1100 * This is evidence of a crippled system and we are returning void,
1101 * so no attempt is made to handle this situation here.
1103 if (!sve_vl_valid(max_vl))
1106 efi_sve_state = __alloc_percpu(
1107 SVE_SIG_REGS_SIZE(sve_vq_from_vl(max_vl)), SVE_VQ_BYTES);
1114 panic("Cannot allocate percpu memory for EFI SVE save/restore");
1118 * Enable SVE for EL1.
1119 * Intended for use by the cpufeatures code during CPU boot.
1121 void sve_kernel_enable(const struct arm64_cpu_capabilities *__always_unused p)
1123 write_sysreg(read_sysreg(CPACR_EL1) | CPACR_EL1_ZEN_EL1EN, CPACR_EL1);
1128 * Read the pseudo-ZCR used by cpufeatures to identify the supported SVE
1131 * Use only if SVE is present.
1132 * This function clobbers the SVE vector length.
1134 u64 read_zcr_features(void)
1137 * Set the maximum possible VL, and write zeroes to all other
1138 * bits to see if they stick.
1140 sve_kernel_enable(NULL);
1141 write_sysreg_s(ZCR_ELx_LEN_MASK, SYS_ZCR_EL1);
1143 /* Return LEN value that would be written to get the maximum VL */
1144 return sve_vq_from_vl(sve_get_vl()) - 1;
1147 void __init sve_setup(void)
1149 struct vl_info *info = &vl_info[ARM64_VEC_SVE];
1151 DECLARE_BITMAP(tmp_map, SVE_VQ_MAX);
1154 if (!system_supports_sve())
1158 * The SVE architecture mandates support for 128-bit vectors,
1159 * so sve_vq_map must have at least SVE_VQ_MIN set.
1160 * If something went wrong, at least try to patch it up:
1162 if (WARN_ON(!test_bit(__vq_to_bit(SVE_VQ_MIN), info->vq_map)))
1163 set_bit(__vq_to_bit(SVE_VQ_MIN), info->vq_map);
1165 zcr = read_sanitised_ftr_reg(SYS_ZCR_EL1);
1166 info->max_vl = sve_vl_from_vq((zcr & ZCR_ELx_LEN_MASK) + 1);
1169 * Sanity-check that the max VL we determined through CPU features
1170 * corresponds properly to sve_vq_map. If not, do our best:
1172 if (WARN_ON(info->max_vl != find_supported_vector_length(ARM64_VEC_SVE,
1174 info->max_vl = find_supported_vector_length(ARM64_VEC_SVE,
1178 * For the default VL, pick the maximum supported value <= 64.
1179 * VL == 64 is guaranteed not to grow the signal frame.
1181 set_sve_default_vl(find_supported_vector_length(ARM64_VEC_SVE, 64));
1183 bitmap_andnot(tmp_map, info->vq_partial_map, info->vq_map,
1186 b = find_last_bit(tmp_map, SVE_VQ_MAX);
1187 if (b >= SVE_VQ_MAX)
1188 /* No non-virtualisable VLs found */
1189 info->max_virtualisable_vl = SVE_VQ_MAX;
1190 else if (WARN_ON(b == SVE_VQ_MAX - 1))
1191 /* No virtualisable VLs? This is architecturally forbidden. */
1192 info->max_virtualisable_vl = SVE_VQ_MIN;
1193 else /* b + 1 < SVE_VQ_MAX */
1194 info->max_virtualisable_vl = sve_vl_from_vq(__bit_to_vq(b + 1));
1196 if (info->max_virtualisable_vl > info->max_vl)
1197 info->max_virtualisable_vl = info->max_vl;
1199 pr_info("%s: maximum available vector length %u bytes per vector\n",
1200 info->name, info->max_vl);
1201 pr_info("%s: default vector length %u bytes per vector\n",
1202 info->name, get_sve_default_vl());
1204 /* KVM decides whether to support mismatched systems. Just warn here: */
1205 if (sve_max_virtualisable_vl() < sve_max_vl())
1206 pr_warn("%s: unvirtualisable vector lengths present\n",
1213 * Called from the put_task_struct() path, which cannot get here
1214 * unless dead_task is really dead and not schedulable.
1216 void fpsimd_release_task(struct task_struct *dead_task)
1218 __sve_free(dead_task);
1219 sme_free(dead_task);
1222 #endif /* CONFIG_ARM64_SVE */
1224 #ifdef CONFIG_ARM64_SME
1227 * Ensure that task->thread.za_state is allocated and sufficiently large.
1229 * This function should be used only in preparation for replacing
1230 * task->thread.za_state with new data. The memory is always zeroed
1231 * here to prevent stale data from showing through: this is done in
1232 * the interest of testability and predictability, the architecture
1233 * guarantees that when ZA is enabled it will be zeroed.
1235 void sme_alloc(struct task_struct *task, bool flush)
1237 if (task->thread.za_state && flush) {
1238 memset(task->thread.za_state, 0, za_state_size(task));
1242 /* This could potentially be up to 64K. */
1243 task->thread.za_state =
1244 kzalloc(za_state_size(task), GFP_KERNEL);
1247 static void sme_free(struct task_struct *task)
1249 kfree(task->thread.za_state);
1250 task->thread.za_state = NULL;
1253 void sme_kernel_enable(const struct arm64_cpu_capabilities *__always_unused p)
1255 /* Set priority for all PEs to architecturally defined minimum */
1256 write_sysreg_s(read_sysreg_s(SYS_SMPRI_EL1) & ~SMPRI_EL1_PRIORITY_MASK,
1259 /* Allow SME in kernel */
1260 write_sysreg(read_sysreg(CPACR_EL1) | CPACR_EL1_SMEN_EL1EN, CPACR_EL1);
1263 /* Allow EL0 to access TPIDR2 */
1264 write_sysreg(read_sysreg(SCTLR_EL1) | SCTLR_ELx_ENTP2, SCTLR_EL1);
1269 * This must be called after sme_kernel_enable(), we rely on the
1270 * feature table being sorted to ensure this.
1272 void fa64_kernel_enable(const struct arm64_cpu_capabilities *__always_unused p)
1274 /* Allow use of FA64 */
1275 write_sysreg_s(read_sysreg_s(SYS_SMCR_EL1) | SMCR_ELx_FA64_MASK,
1280 * Read the pseudo-SMCR used by cpufeatures to identify the supported
1283 * Use only if SME is present.
1284 * This function clobbers the SME vector length.
1286 u64 read_smcr_features(void)
1288 sme_kernel_enable(NULL);
1291 * Set the maximum possible VL.
1293 write_sysreg_s(read_sysreg_s(SYS_SMCR_EL1) | SMCR_ELx_LEN_MASK,
1296 /* Return LEN value that would be written to get the maximum VL */
1297 return sve_vq_from_vl(sme_get_vl()) - 1;
1300 void __init sme_setup(void)
1302 struct vl_info *info = &vl_info[ARM64_VEC_SME];
1306 if (!system_supports_sme())
1310 * SME doesn't require any particular vector length be
1311 * supported but it does require at least one. We should have
1312 * disabled the feature entirely while bringing up CPUs but
1313 * let's double check here.
1315 WARN_ON(bitmap_empty(info->vq_map, SVE_VQ_MAX));
1317 min_bit = find_last_bit(info->vq_map, SVE_VQ_MAX);
1318 info->min_vl = sve_vl_from_vq(__bit_to_vq(min_bit));
1320 smcr = read_sanitised_ftr_reg(SYS_SMCR_EL1);
1321 info->max_vl = sve_vl_from_vq((smcr & SMCR_ELx_LEN_MASK) + 1);
1324 * Sanity-check that the max VL we determined through CPU features
1325 * corresponds properly to sme_vq_map. If not, do our best:
1327 if (WARN_ON(info->max_vl != find_supported_vector_length(ARM64_VEC_SME,
1329 info->max_vl = find_supported_vector_length(ARM64_VEC_SME,
1332 WARN_ON(info->min_vl > info->max_vl);
1335 * For the default VL, pick the maximum supported value <= 32
1336 * (256 bits) if there is one since this is guaranteed not to
1337 * grow the signal frame when in streaming mode, otherwise the
1338 * minimum available VL will be used.
1340 set_sme_default_vl(find_supported_vector_length(ARM64_VEC_SME, 32));
1342 pr_info("SME: minimum available vector length %u bytes per vector\n",
1344 pr_info("SME: maximum available vector length %u bytes per vector\n",
1346 pr_info("SME: default vector length %u bytes per vector\n",
1347 get_sme_default_vl());
1350 void sme_suspend_exit(void)
1354 if (!system_supports_sme())
1357 if (system_supports_fa64())
1358 smcr |= SMCR_ELx_FA64;
1360 write_sysreg_s(smcr, SYS_SMCR_EL1);
1361 write_sysreg_s(0, SYS_SMPRI_EL1);
1364 #endif /* CONFIG_ARM64_SME */
1366 static void sve_init_regs(void)
1369 * Convert the FPSIMD state to SVE, zeroing all the state that
1370 * is not shared with FPSIMD. If (as is likely) the current
1371 * state is live in the registers then do this there and
1372 * update our metadata for the current task including
1373 * disabling the trap, otherwise update our in-memory copy.
1374 * We are guaranteed to not be in streaming mode, we can only
1375 * take a SVE trap when not in streaming mode and we can't be
1376 * in streaming mode when taking a SME trap.
1378 if (!test_thread_flag(TIF_FOREIGN_FPSTATE)) {
1379 unsigned long vq_minus_one =
1380 sve_vq_from_vl(task_get_sve_vl(current)) - 1;
1381 sve_set_vq(vq_minus_one);
1382 sve_flush_live(true, vq_minus_one);
1383 fpsimd_bind_task_to_cpu();
1385 fpsimd_to_sve(current);
1390 * Trapped SVE access
1392 * Storage is allocated for the full SVE state, the current FPSIMD
1393 * register contents are migrated across, and the access trap is
1396 * TIF_SVE should be clear on entry: otherwise, fpsimd_restore_current_state()
1397 * would have disabled the SVE access trap for userspace during
1398 * ret_to_user, making an SVE access trap impossible in that case.
1400 void do_sve_acc(unsigned long esr, struct pt_regs *regs)
1402 /* Even if we chose not to use SVE, the hardware could still trap: */
1403 if (unlikely(!system_supports_sve()) || WARN_ON(is_compat_task())) {
1404 force_signal_inject(SIGILL, ILL_ILLOPC, regs->pc, 0);
1408 sve_alloc(current, true);
1409 if (!current->thread.sve_state) {
1414 get_cpu_fpsimd_context();
1416 if (test_and_set_thread_flag(TIF_SVE))
1417 WARN_ON(1); /* SVE access shouldn't have trapped */
1420 * Even if the task can have used streaming mode we can only
1421 * generate SVE access traps in normal SVE mode and
1422 * transitioning out of streaming mode may discard any
1423 * streaming mode state. Always clear the high bits to avoid
1424 * any potential errors tracking what is properly initialised.
1428 put_cpu_fpsimd_context();
1432 * Trapped SME access
1434 * Storage is allocated for the full SVE and SME state, the current
1435 * FPSIMD register contents are migrated to SVE if SVE is not already
1436 * active, and the access trap is disabled.
1438 * TIF_SME should be clear on entry: otherwise, fpsimd_restore_current_state()
1439 * would have disabled the SME access trap for userspace during
1440 * ret_to_user, making an SVE access trap impossible in that case.
1442 void do_sme_acc(unsigned long esr, struct pt_regs *regs)
1444 /* Even if we chose not to use SME, the hardware could still trap: */
1445 if (unlikely(!system_supports_sme()) || WARN_ON(is_compat_task())) {
1446 force_signal_inject(SIGILL, ILL_ILLOPC, regs->pc, 0);
1451 * If this not a trap due to SME being disabled then something
1452 * is being used in the wrong mode, report as SIGILL.
1454 if (ESR_ELx_ISS(esr) != ESR_ELx_SME_ISS_SME_DISABLED) {
1455 force_signal_inject(SIGILL, ILL_ILLOPC, regs->pc, 0);
1459 sve_alloc(current, false);
1460 sme_alloc(current, true);
1461 if (!current->thread.sve_state || !current->thread.za_state) {
1466 get_cpu_fpsimd_context();
1468 /* With TIF_SME userspace shouldn't generate any traps */
1469 if (test_and_set_thread_flag(TIF_SME))
1472 if (!test_thread_flag(TIF_FOREIGN_FPSTATE)) {
1473 unsigned long vq_minus_one =
1474 sve_vq_from_vl(task_get_sme_vl(current)) - 1;
1475 sme_set_vq(vq_minus_one);
1477 fpsimd_bind_task_to_cpu();
1480 put_cpu_fpsimd_context();
1484 * Trapped FP/ASIMD access.
1486 void do_fpsimd_acc(unsigned long esr, struct pt_regs *regs)
1488 /* TODO: implement lazy context saving/restoring */
1493 * Raise a SIGFPE for the current process.
1495 void do_fpsimd_exc(unsigned long esr, struct pt_regs *regs)
1497 unsigned int si_code = FPE_FLTUNK;
1499 if (esr & ESR_ELx_FP_EXC_TFV) {
1500 if (esr & FPEXC_IOF)
1501 si_code = FPE_FLTINV;
1502 else if (esr & FPEXC_DZF)
1503 si_code = FPE_FLTDIV;
1504 else if (esr & FPEXC_OFF)
1505 si_code = FPE_FLTOVF;
1506 else if (esr & FPEXC_UFF)
1507 si_code = FPE_FLTUND;
1508 else if (esr & FPEXC_IXF)
1509 si_code = FPE_FLTRES;
1512 send_sig_fault(SIGFPE, si_code,
1513 (void __user *)instruction_pointer(regs),
1517 void fpsimd_thread_switch(struct task_struct *next)
1519 bool wrong_task, wrong_cpu;
1521 if (!system_supports_fpsimd())
1524 __get_cpu_fpsimd_context();
1526 /* Save unsaved fpsimd state, if any: */
1530 * Fix up TIF_FOREIGN_FPSTATE to correctly describe next's
1531 * state. For kernel threads, FPSIMD registers are never loaded
1532 * and wrong_task and wrong_cpu will always be true.
1534 wrong_task = __this_cpu_read(fpsimd_last_state.st) !=
1535 &next->thread.uw.fpsimd_state;
1536 wrong_cpu = next->thread.fpsimd_cpu != smp_processor_id();
1538 update_tsk_thread_flag(next, TIF_FOREIGN_FPSTATE,
1539 wrong_task || wrong_cpu);
1541 __put_cpu_fpsimd_context();
1544 static void fpsimd_flush_thread_vl(enum vec_type type)
1546 int vl, supported_vl;
1549 * Reset the task vector length as required. This is where we
1550 * ensure that all user tasks have a valid vector length
1551 * configured: no kernel task can become a user task without
1552 * an exec and hence a call to this function. By the time the
1553 * first call to this function is made, all early hardware
1554 * probing is complete, so __sve_default_vl should be valid.
1555 * If a bug causes this to go wrong, we make some noise and
1556 * try to fudge thread.sve_vl to a safe value here.
1558 vl = task_get_vl_onexec(current, type);
1560 vl = get_default_vl(type);
1562 if (WARN_ON(!sve_vl_valid(vl)))
1563 vl = vl_info[type].min_vl;
1565 supported_vl = find_supported_vector_length(type, vl);
1566 if (WARN_ON(supported_vl != vl))
1569 task_set_vl(current, type, vl);
1572 * If the task is not set to inherit, ensure that the vector
1573 * length will be reset by a subsequent exec:
1575 if (!test_thread_flag(vec_vl_inherit_flag(type)))
1576 task_set_vl_onexec(current, type, 0);
1579 void fpsimd_flush_thread(void)
1581 void *sve_state = NULL;
1582 void *za_state = NULL;
1584 if (!system_supports_fpsimd())
1587 get_cpu_fpsimd_context();
1589 fpsimd_flush_task_state(current);
1590 memset(¤t->thread.uw.fpsimd_state, 0,
1591 sizeof(current->thread.uw.fpsimd_state));
1593 if (system_supports_sve()) {
1594 clear_thread_flag(TIF_SVE);
1596 /* Defer kfree() while in atomic context */
1597 sve_state = current->thread.sve_state;
1598 current->thread.sve_state = NULL;
1600 fpsimd_flush_thread_vl(ARM64_VEC_SVE);
1603 if (system_supports_sme()) {
1604 clear_thread_flag(TIF_SME);
1606 /* Defer kfree() while in atomic context */
1607 za_state = current->thread.za_state;
1608 current->thread.za_state = NULL;
1610 fpsimd_flush_thread_vl(ARM64_VEC_SME);
1611 current->thread.svcr = 0;
1614 put_cpu_fpsimd_context();
1620 * Save the userland FPSIMD state of 'current' to memory, but only if the state
1621 * currently held in the registers does in fact belong to 'current'
1623 void fpsimd_preserve_current_state(void)
1625 if (!system_supports_fpsimd())
1628 get_cpu_fpsimd_context();
1630 put_cpu_fpsimd_context();
1634 * Like fpsimd_preserve_current_state(), but ensure that
1635 * current->thread.uw.fpsimd_state is updated so that it can be copied to
1638 void fpsimd_signal_preserve_current_state(void)
1640 fpsimd_preserve_current_state();
1641 if (test_thread_flag(TIF_SVE))
1642 sve_to_fpsimd(current);
1646 * Associate current's FPSIMD context with this cpu
1647 * The caller must have ownership of the cpu FPSIMD context before calling
1650 static void fpsimd_bind_task_to_cpu(void)
1652 struct fpsimd_last_state_struct *last =
1653 this_cpu_ptr(&fpsimd_last_state);
1655 WARN_ON(!system_supports_fpsimd());
1656 last->st = ¤t->thread.uw.fpsimd_state;
1657 last->sve_state = current->thread.sve_state;
1658 last->za_state = current->thread.za_state;
1659 last->sve_vl = task_get_sve_vl(current);
1660 last->sme_vl = task_get_sme_vl(current);
1661 last->svcr = ¤t->thread.svcr;
1662 current->thread.fpsimd_cpu = smp_processor_id();
1665 * Toggle SVE and SME trapping for userspace if needed, these
1666 * are serialsied by ret_to_user().
1668 if (system_supports_sme()) {
1669 if (test_thread_flag(TIF_SME))
1675 if (system_supports_sve()) {
1676 if (test_thread_flag(TIF_SVE))
1683 void fpsimd_bind_state_to_cpu(struct user_fpsimd_state *st, void *sve_state,
1684 unsigned int sve_vl, void *za_state,
1685 unsigned int sme_vl, u64 *svcr)
1687 struct fpsimd_last_state_struct *last =
1688 this_cpu_ptr(&fpsimd_last_state);
1690 WARN_ON(!system_supports_fpsimd());
1691 WARN_ON(!in_softirq() && !irqs_disabled());
1695 last->sve_state = sve_state;
1696 last->za_state = za_state;
1697 last->sve_vl = sve_vl;
1698 last->sme_vl = sme_vl;
1702 * Load the userland FPSIMD state of 'current' from memory, but only if the
1703 * FPSIMD state already held in the registers is /not/ the most recent FPSIMD
1704 * state of 'current'. This is called when we are preparing to return to
1705 * userspace to ensure that userspace sees a good register state.
1707 void fpsimd_restore_current_state(void)
1710 * For the tasks that were created before we detected the absence of
1711 * FP/SIMD, the TIF_FOREIGN_FPSTATE could be set via fpsimd_thread_switch(),
1712 * e.g, init. This could be then inherited by the children processes.
1713 * If we later detect that the system doesn't support FP/SIMD,
1714 * we must clear the flag for all the tasks to indicate that the
1715 * FPSTATE is clean (as we can't have one) to avoid looping for ever in
1716 * do_notify_resume().
1718 if (!system_supports_fpsimd()) {
1719 clear_thread_flag(TIF_FOREIGN_FPSTATE);
1723 get_cpu_fpsimd_context();
1725 if (test_and_clear_thread_flag(TIF_FOREIGN_FPSTATE)) {
1727 fpsimd_bind_task_to_cpu();
1730 put_cpu_fpsimd_context();
1734 * Load an updated userland FPSIMD state for 'current' from memory and set the
1735 * flag that indicates that the FPSIMD register contents are the most recent
1736 * FPSIMD state of 'current'. This is used by the signal code to restore the
1737 * register state when returning from a signal handler in FPSIMD only cases,
1738 * any SVE context will be discarded.
1740 void fpsimd_update_current_state(struct user_fpsimd_state const *state)
1742 if (WARN_ON(!system_supports_fpsimd()))
1745 get_cpu_fpsimd_context();
1747 current->thread.uw.fpsimd_state = *state;
1748 if (test_thread_flag(TIF_SVE))
1749 fpsimd_to_sve(current);
1752 fpsimd_bind_task_to_cpu();
1754 clear_thread_flag(TIF_FOREIGN_FPSTATE);
1756 put_cpu_fpsimd_context();
1760 * Invalidate live CPU copies of task t's FPSIMD state
1762 * This function may be called with preemption enabled. The barrier()
1763 * ensures that the assignment to fpsimd_cpu is visible to any
1764 * preemption/softirq that could race with set_tsk_thread_flag(), so
1765 * that TIF_FOREIGN_FPSTATE cannot be spuriously re-cleared.
1767 * The final barrier ensures that TIF_FOREIGN_FPSTATE is seen set by any
1770 void fpsimd_flush_task_state(struct task_struct *t)
1772 t->thread.fpsimd_cpu = NR_CPUS;
1774 * If we don't support fpsimd, bail out after we have
1775 * reset the fpsimd_cpu for this task and clear the
1778 if (!system_supports_fpsimd())
1781 set_tsk_thread_flag(t, TIF_FOREIGN_FPSTATE);
1787 * Invalidate any task's FPSIMD state that is present on this cpu.
1788 * The FPSIMD context should be acquired with get_cpu_fpsimd_context()
1789 * before calling this function.
1791 static void fpsimd_flush_cpu_state(void)
1793 WARN_ON(!system_supports_fpsimd());
1794 __this_cpu_write(fpsimd_last_state.st, NULL);
1797 * Leaving streaming mode enabled will cause issues for any kernel
1798 * NEON and leaving streaming mode or ZA enabled may increase power
1801 if (system_supports_sme())
1804 set_thread_flag(TIF_FOREIGN_FPSTATE);
1808 * Save the FPSIMD state to memory and invalidate cpu view.
1809 * This function must be called with preemption disabled.
1811 void fpsimd_save_and_flush_cpu_state(void)
1813 if (!system_supports_fpsimd())
1815 WARN_ON(preemptible());
1816 __get_cpu_fpsimd_context();
1818 fpsimd_flush_cpu_state();
1819 __put_cpu_fpsimd_context();
1822 #ifdef CONFIG_KERNEL_MODE_NEON
1825 * Kernel-side NEON support functions
1829 * kernel_neon_begin(): obtain the CPU FPSIMD registers for use by the calling
1832 * Must not be called unless may_use_simd() returns true.
1833 * Task context in the FPSIMD registers is saved back to memory as necessary.
1835 * A matching call to kernel_neon_end() must be made before returning from the
1838 * The caller may freely use the FPSIMD registers until kernel_neon_end() is
1841 void kernel_neon_begin(void)
1843 if (WARN_ON(!system_supports_fpsimd()))
1846 BUG_ON(!may_use_simd());
1848 get_cpu_fpsimd_context();
1850 /* Save unsaved fpsimd state, if any: */
1853 /* Invalidate any task state remaining in the fpsimd regs: */
1854 fpsimd_flush_cpu_state();
1856 EXPORT_SYMBOL(kernel_neon_begin);
1859 * kernel_neon_end(): give the CPU FPSIMD registers back to the current task
1861 * Must be called from a context in which kernel_neon_begin() was previously
1862 * called, with no call to kernel_neon_end() in the meantime.
1864 * The caller must not use the FPSIMD registers after this function is called,
1865 * unless kernel_neon_begin() is called again in the meantime.
1867 void kernel_neon_end(void)
1869 if (!system_supports_fpsimd())
1872 put_cpu_fpsimd_context();
1874 EXPORT_SYMBOL(kernel_neon_end);
1878 static DEFINE_PER_CPU(struct user_fpsimd_state, efi_fpsimd_state);
1879 static DEFINE_PER_CPU(bool, efi_fpsimd_state_used);
1880 static DEFINE_PER_CPU(bool, efi_sve_state_used);
1881 static DEFINE_PER_CPU(bool, efi_sm_state);
1884 * EFI runtime services support functions
1886 * The ABI for EFI runtime services allows EFI to use FPSIMD during the call.
1887 * This means that for EFI (and only for EFI), we have to assume that FPSIMD
1888 * is always used rather than being an optional accelerator.
1890 * These functions provide the necessary support for ensuring FPSIMD
1891 * save/restore in the contexts from which EFI is used.
1893 * Do not use them for any other purpose -- if tempted to do so, you are
1894 * either doing something wrong or you need to propose some refactoring.
1898 * __efi_fpsimd_begin(): prepare FPSIMD for making an EFI runtime services call
1900 void __efi_fpsimd_begin(void)
1902 if (!system_supports_fpsimd())
1905 WARN_ON(preemptible());
1907 if (may_use_simd()) {
1908 kernel_neon_begin();
1911 * If !efi_sve_state, SVE can't be in use yet and doesn't need
1914 if (system_supports_sve() && likely(efi_sve_state)) {
1915 char *sve_state = this_cpu_ptr(efi_sve_state);
1919 __this_cpu_write(efi_sve_state_used, true);
1921 if (system_supports_sme()) {
1922 svcr = read_sysreg_s(SYS_SVCR);
1924 __this_cpu_write(efi_sm_state,
1925 svcr & SVCR_SM_MASK);
1928 * Unless we have FA64 FFR does not
1929 * exist in streaming mode.
1931 if (!system_supports_fa64())
1932 ffr = !(svcr & SVCR_SM_MASK);
1935 sve_save_state(sve_state + sve_ffr_offset(sve_max_vl()),
1936 &this_cpu_ptr(&efi_fpsimd_state)->fpsr,
1939 if (system_supports_sme())
1940 sysreg_clear_set_s(SYS_SVCR,
1944 fpsimd_save_state(this_cpu_ptr(&efi_fpsimd_state));
1947 __this_cpu_write(efi_fpsimd_state_used, true);
1952 * __efi_fpsimd_end(): clean up FPSIMD after an EFI runtime services call
1954 void __efi_fpsimd_end(void)
1956 if (!system_supports_fpsimd())
1959 if (!__this_cpu_xchg(efi_fpsimd_state_used, false)) {
1962 if (system_supports_sve() &&
1963 likely(__this_cpu_read(efi_sve_state_used))) {
1964 char const *sve_state = this_cpu_ptr(efi_sve_state);
1968 * Restore streaming mode; EFI calls are
1969 * normal function calls so should not return in
1972 if (system_supports_sme()) {
1973 if (__this_cpu_read(efi_sm_state)) {
1974 sysreg_clear_set_s(SYS_SVCR,
1979 * Unless we have FA64 FFR does not
1980 * exist in streaming mode.
1982 if (!system_supports_fa64())
1987 sve_load_state(sve_state + sve_ffr_offset(sve_max_vl()),
1988 &this_cpu_ptr(&efi_fpsimd_state)->fpsr,
1991 __this_cpu_write(efi_sve_state_used, false);
1993 fpsimd_load_state(this_cpu_ptr(&efi_fpsimd_state));
1998 #endif /* CONFIG_EFI */
2000 #endif /* CONFIG_KERNEL_MODE_NEON */
2002 #ifdef CONFIG_CPU_PM
2003 static int fpsimd_cpu_pm_notifier(struct notifier_block *self,
2004 unsigned long cmd, void *v)
2008 fpsimd_save_and_flush_cpu_state();
2012 case CPU_PM_ENTER_FAILED:
2019 static struct notifier_block fpsimd_cpu_pm_notifier_block = {
2020 .notifier_call = fpsimd_cpu_pm_notifier,
2023 static void __init fpsimd_pm_init(void)
2025 cpu_pm_register_notifier(&fpsimd_cpu_pm_notifier_block);
2029 static inline void fpsimd_pm_init(void) { }
2030 #endif /* CONFIG_CPU_PM */
2032 #ifdef CONFIG_HOTPLUG_CPU
2033 static int fpsimd_cpu_dead(unsigned int cpu)
2035 per_cpu(fpsimd_last_state.st, cpu) = NULL;
2039 static inline void fpsimd_hotplug_init(void)
2041 cpuhp_setup_state_nocalls(CPUHP_ARM64_FPSIMD_DEAD, "arm64/fpsimd:dead",
2042 NULL, fpsimd_cpu_dead);
2046 static inline void fpsimd_hotplug_init(void) { }
2050 * FP/SIMD support code initialisation.
2052 static int __init fpsimd_init(void)
2054 if (cpu_have_named_feature(FP)) {
2056 fpsimd_hotplug_init();
2058 pr_notice("Floating-point is not implemented\n");
2061 if (!cpu_have_named_feature(ASIMD))
2062 pr_notice("Advanced SIMD is not implemented\n");
2065 if (cpu_have_named_feature(SME) && !cpu_have_named_feature(SVE))
2066 pr_notice("SME is implemented but not SVE\n");
2073 core_initcall(fpsimd_init);