2 * Low-level exception handling code
4 * Copyright (C) 2012 ARM Ltd.
5 * Authors: Catalin Marinas <catalin.marinas@arm.com>
6 * Will Deacon <will.deacon@arm.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program. If not, see <http://www.gnu.org/licenses/>.
21 #include <linux/arm-smccc.h>
22 #include <linux/init.h>
23 #include <linux/linkage.h>
25 #include <asm/alternative.h>
26 #include <asm/assembler.h>
27 #include <asm/asm-offsets.h>
28 #include <asm/cpufeature.h>
29 #include <asm/errno.h>
32 #include <asm/memory.h>
34 #include <asm/processor.h>
35 #include <asm/ptrace.h>
36 #include <asm/thread_info.h>
37 #include <asm/asm-uaccess.h>
38 #include <asm/unistd.h>
41 * Context tracking subsystem. Used to instrument transitions
42 * between user and kernel mode.
44 .macro ct_user_exit, syscall = 0
45 #ifdef CONFIG_CONTEXT_TRACKING
46 bl context_tracking_user_exit
49 * Save/restore needed during syscalls. Restore syscall arguments from
50 * the values already saved on stack during kernel_entry.
53 ldp x2, x3, [sp, #S_X2]
54 ldp x4, x5, [sp, #S_X4]
55 ldp x6, x7, [sp, #S_X6]
61 #ifdef CONFIG_CONTEXT_TRACKING
62 bl context_tracking_user_enter
75 .macro kernel_ventry, el, label, regsize = 64
77 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0
78 alternative_if ARM64_UNMAP_KERNEL_AT_EL0
87 alternative_else_nop_endif
90 sub sp, sp, #S_FRAME_SIZE
91 #ifdef CONFIG_VMAP_STACK
93 * Test whether the SP has overflowed, without corrupting a GPR.
94 * Task and IRQ stacks are aligned to (1 << THREAD_SHIFT).
96 add sp, sp, x0 // sp' = sp + x0
97 sub x0, sp, x0 // x0' = sp' - x0 = (sp + x0) - x0 = sp
98 tbnz x0, #THREAD_SHIFT, 0f
99 sub x0, sp, x0 // x0'' = sp' - x0' = (sp + x0) - sp = x0
100 sub sp, sp, x0 // sp'' = sp' - x0 = (sp + x0) - x0 = sp
105 * Either we've just detected an overflow, or we've taken an exception
106 * while on the overflow stack. Either way, we won't return to
107 * userspace, and can clobber EL0 registers to free up GPRs.
110 /* Stash the original SP (minus S_FRAME_SIZE) in tpidr_el0. */
113 /* Recover the original x0 value and stash it in tpidrro_el0 */
117 /* Switch to the overflow stack */
118 adr_this_cpu sp, overflow_stack + OVERFLOW_STACK_SIZE, x0
121 * Check whether we were already on the overflow stack. This may happen
122 * after panic() re-enables interrupts.
124 mrs x0, tpidr_el0 // sp of interrupted context
125 sub x0, sp, x0 // delta with top of overflow stack
126 tst x0, #~(OVERFLOW_STACK_SIZE - 1) // within range?
127 b.ne __bad_stack // no? -> bad stack pointer
129 /* We were already on the overflow stack. Restore sp/x0 and carry on. */
136 .macro tramp_alias, dst, sym
137 mov_q \dst, TRAMP_VALIAS
138 add \dst, \dst, #(\sym - .entry.tramp.text)
141 // This macro corrupts x0-x3. It is the caller's duty
142 // to save/restore them if required.
143 .macro apply_ssbd, state, targ, tmp1, tmp2
144 #ifdef CONFIG_ARM64_SSBD
145 alternative_cb arm64_enable_wa2_handling
148 ldr_this_cpu \tmp2, arm64_ssbd_callback_required, \tmp1
150 ldr \tmp2, [tsk, #TSK_TI_FLAGS]
151 tbnz \tmp2, #TIF_SSBD, \targ
152 mov w0, #ARM_SMCCC_ARCH_WORKAROUND_2
154 alternative_cb arm64_update_smccc_conduit
155 nop // Patched to SMC/HVC #0
160 .macro kernel_entry, el, regsize = 64
162 mov w0, w0 // zero upper 32 bits of x0
164 stp x0, x1, [sp, #16 * 0]
165 stp x2, x3, [sp, #16 * 1]
166 stp x4, x5, [sp, #16 * 2]
167 stp x6, x7, [sp, #16 * 3]
168 stp x8, x9, [sp, #16 * 4]
169 stp x10, x11, [sp, #16 * 5]
170 stp x12, x13, [sp, #16 * 6]
171 stp x14, x15, [sp, #16 * 7]
172 stp x16, x17, [sp, #16 * 8]
173 stp x18, x19, [sp, #16 * 9]
174 stp x20, x21, [sp, #16 * 10]
175 stp x22, x23, [sp, #16 * 11]
176 stp x24, x25, [sp, #16 * 12]
177 stp x26, x27, [sp, #16 * 13]
178 stp x28, x29, [sp, #16 * 14]
182 ldr_this_cpu tsk, __entry_task, x20 // Ensure MDSCR_EL1.SS is clear,
183 ldr x19, [tsk, #TSK_TI_FLAGS] // since we can unmask debug
184 disable_step_tsk x19, x20 // exceptions when scheduling.
186 apply_ssbd 1, 1f, x22, x23
188 #ifdef CONFIG_ARM64_SSBD
189 ldp x0, x1, [sp, #16 * 0]
190 ldp x2, x3, [sp, #16 * 1]
194 mov x29, xzr // fp pointed to user-space
196 add x21, sp, #S_FRAME_SIZE
198 /* Save the task's original addr_limit and set USER_DS */
199 ldr x20, [tsk, #TSK_TI_ADDR_LIMIT]
200 str x20, [sp, #S_ORIG_ADDR_LIMIT]
202 str x20, [tsk, #TSK_TI_ADDR_LIMIT]
203 /* No need to reset PSTATE.UAO, hardware's already set it to 0 for us */
204 .endif /* \el == 0 */
207 stp lr, x21, [sp, #S_LR]
210 * In order to be able to dump the contents of struct pt_regs at the
211 * time the exception was taken (in case we attempt to walk the call
212 * stack later), chain it together with the stack frames.
215 stp xzr, xzr, [sp, #S_STACKFRAME]
217 stp x29, x22, [sp, #S_STACKFRAME]
219 add x29, sp, #S_STACKFRAME
221 #ifdef CONFIG_ARM64_SW_TTBR0_PAN
223 * Set the TTBR0 PAN bit in SPSR. When the exception is taken from
224 * EL0, there is no need to check the state of TTBR0_EL1 since
225 * accesses are always enabled.
226 * Note that the meaning of this bit differs from the ARMv8.1 PAN
227 * feature as all TTBR0_EL1 accesses are disabled, not just those to
230 alternative_if ARM64_HAS_PAN
231 b 1f // skip TTBR0 PAN
232 alternative_else_nop_endif
236 tst x21, #TTBR_ASID_MASK // Check for the reserved ASID
237 orr x23, x23, #PSR_PAN_BIT // Set the emulated PAN in the saved SPSR
238 b.eq 1f // TTBR0 access already disabled
239 and x23, x23, #~PSR_PAN_BIT // Clear the emulated PAN in the saved SPSR
242 __uaccess_ttbr0_disable x21
246 stp x22, x23, [sp, #S_PC]
248 /* Not in a syscall by default (el0_svc overwrites for real syscall) */
251 str w21, [sp, #S_SYSCALLNO]
255 * Set sp_el0 to current thread_info.
262 * Registers that may be useful after this macro is invoked:
266 * x23 - aborted PSTATE
270 .macro kernel_exit, el
272 /* Restore the task's original addr_limit. */
273 ldr x20, [sp, #S_ORIG_ADDR_LIMIT]
274 str x20, [tsk, #TSK_TI_ADDR_LIMIT]
276 /* No need to restore UAO, it will be restored from SPSR_EL1 */
279 ldp x21, x22, [sp, #S_PC] // load ELR, SPSR
284 #ifdef CONFIG_ARM64_SW_TTBR0_PAN
286 * Restore access to TTBR0_EL1. If returning to EL0, no need for SPSR
289 alternative_if ARM64_HAS_PAN
290 b 2f // skip TTBR0 PAN
291 alternative_else_nop_endif
294 tbnz x22, #22, 1f // Skip re-enabling TTBR0 access if the PSR_PAN_BIT is set
297 __uaccess_ttbr0_enable x0, x1
301 * Enable errata workarounds only if returning to user. The only
302 * workaround currently required for TTBR0_EL1 changes are for the
303 * Cavium erratum 27456 (broadcast TLBI instructions may cause I-cache
306 bl post_ttbr_update_workaround
310 and x22, x22, #~PSR_PAN_BIT // ARMv8.0 CPUs do not understand this bit
316 ldr x23, [sp, #S_SP] // load return stack pointer
318 tst x22, #PSR_MODE32_BIT // native task?
321 #ifdef CONFIG_ARM64_ERRATUM_845719
322 alternative_if ARM64_WORKAROUND_845719
323 #ifdef CONFIG_PID_IN_CONTEXTIDR
324 mrs x29, contextidr_el1
325 msr contextidr_el1, x29
327 msr contextidr_el1, xzr
329 alternative_else_nop_endif
332 apply_ssbd 0, 5f, x0, x1
336 msr elr_el1, x21 // set up the return data
338 ldp x0, x1, [sp, #16 * 0]
339 ldp x2, x3, [sp, #16 * 1]
340 ldp x4, x5, [sp, #16 * 2]
341 ldp x6, x7, [sp, #16 * 3]
342 ldp x8, x9, [sp, #16 * 4]
343 ldp x10, x11, [sp, #16 * 5]
344 ldp x12, x13, [sp, #16 * 6]
345 ldp x14, x15, [sp, #16 * 7]
346 ldp x16, x17, [sp, #16 * 8]
347 ldp x18, x19, [sp, #16 * 9]
348 ldp x20, x21, [sp, #16 * 10]
349 ldp x22, x23, [sp, #16 * 11]
350 ldp x24, x25, [sp, #16 * 12]
351 ldp x26, x27, [sp, #16 * 13]
352 ldp x28, x29, [sp, #16 * 14]
354 add sp, sp, #S_FRAME_SIZE // restore sp
357 alternative_insn eret, nop, ARM64_UNMAP_KERNEL_AT_EL0
358 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0
361 tramp_alias x30, tramp_exit_native
364 tramp_alias x30, tramp_exit_compat
372 .macro irq_stack_entry
373 mov x19, sp // preserve the original sp
376 * Compare sp with the base of the task stack.
377 * If the top ~(THREAD_SIZE - 1) bits match, we are on a task stack,
378 * and should switch to the irq stack.
380 ldr x25, [tsk, TSK_STACK]
382 and x25, x25, #~(THREAD_SIZE - 1)
385 ldr_this_cpu x25, irq_stack_ptr, x26
386 mov x26, #IRQ_STACK_SIZE
389 /* switch to the irq stack */
395 * x19 should be preserved between irq_stack_entry and
398 .macro irq_stack_exit
403 * These are the registers used in the syscall handler, and allow us to
404 * have in theory up to 7 arguments to a function - x0 to x6.
406 * x7 is reserved for the system call number in 32-bit mode.
408 wsc_nr .req w25 // number of system calls
409 xsc_nr .req x25 // number of system calls (zero-extended)
410 wscno .req w26 // syscall number
411 xscno .req x26 // syscall number (zero-extended)
412 stbl .req x27 // syscall table pointer
413 tsk .req x28 // current thread_info
416 * Interrupt handling.
419 ldr_l x1, handle_arch_irq
431 .pushsection ".entry.text", "ax"
435 kernel_ventry 1, sync_invalid // Synchronous EL1t
436 kernel_ventry 1, irq_invalid // IRQ EL1t
437 kernel_ventry 1, fiq_invalid // FIQ EL1t
438 kernel_ventry 1, error_invalid // Error EL1t
440 kernel_ventry 1, sync // Synchronous EL1h
441 kernel_ventry 1, irq // IRQ EL1h
442 kernel_ventry 1, fiq_invalid // FIQ EL1h
443 kernel_ventry 1, error_invalid // Error EL1h
445 kernel_ventry 0, sync // Synchronous 64-bit EL0
446 kernel_ventry 0, irq // IRQ 64-bit EL0
447 kernel_ventry 0, fiq_invalid // FIQ 64-bit EL0
448 kernel_ventry 0, error_invalid // Error 64-bit EL0
451 kernel_ventry 0, sync_compat, 32 // Synchronous 32-bit EL0
452 kernel_ventry 0, irq_compat, 32 // IRQ 32-bit EL0
453 kernel_ventry 0, fiq_invalid_compat, 32 // FIQ 32-bit EL0
454 kernel_ventry 0, error_invalid_compat, 32 // Error 32-bit EL0
456 kernel_ventry 0, sync_invalid, 32 // Synchronous 32-bit EL0
457 kernel_ventry 0, irq_invalid, 32 // IRQ 32-bit EL0
458 kernel_ventry 0, fiq_invalid, 32 // FIQ 32-bit EL0
459 kernel_ventry 0, error_invalid, 32 // Error 32-bit EL0
463 #ifdef CONFIG_VMAP_STACK
465 * We detected an overflow in kernel_ventry, which switched to the
466 * overflow stack. Stash the exception regs, and head to our overflow
470 /* Restore the original x0 value */
474 * Store the original GPRs to the new stack. The orginal SP (minus
475 * S_FRAME_SIZE) was stashed in tpidr_el0 by kernel_ventry.
477 sub sp, sp, #S_FRAME_SIZE
480 add x0, x0, #S_FRAME_SIZE
483 /* Stash the regs for handle_bad_stack */
489 #endif /* CONFIG_VMAP_STACK */
492 * Invalid mode handlers
494 .macro inv_entry, el, reason, regsize = 64
495 kernel_entry \el, \regsize
504 inv_entry 0, BAD_SYNC
505 ENDPROC(el0_sync_invalid)
509 ENDPROC(el0_irq_invalid)
513 ENDPROC(el0_fiq_invalid)
516 inv_entry 0, BAD_ERROR
517 ENDPROC(el0_error_invalid)
520 el0_fiq_invalid_compat:
521 inv_entry 0, BAD_FIQ, 32
522 ENDPROC(el0_fiq_invalid_compat)
524 el0_error_invalid_compat:
525 inv_entry 0, BAD_ERROR, 32
526 ENDPROC(el0_error_invalid_compat)
530 inv_entry 1, BAD_SYNC
531 ENDPROC(el1_sync_invalid)
535 ENDPROC(el1_irq_invalid)
539 ENDPROC(el1_fiq_invalid)
542 inv_entry 1, BAD_ERROR
543 ENDPROC(el1_error_invalid)
551 mrs x1, esr_el1 // read the syndrome register
552 lsr x24, x1, #ESR_ELx_EC_SHIFT // exception class
553 cmp x24, #ESR_ELx_EC_DABT_CUR // data abort in EL1
555 cmp x24, #ESR_ELx_EC_IABT_CUR // instruction abort in EL1
557 cmp x24, #ESR_ELx_EC_SYS64 // configurable trap
559 cmp x24, #ESR_ELx_EC_SP_ALIGN // stack alignment exception
561 cmp x24, #ESR_ELx_EC_PC_ALIGN // pc alignment exception
563 cmp x24, #ESR_ELx_EC_UNKNOWN // unknown exception in EL1
565 cmp x24, #ESR_ELx_EC_BREAKPT_CUR // debug exception in EL1
571 * Fall through to the Data abort case
575 * Data abort handling
579 // re-enable interrupts if they were enabled in the aborted context
580 tbnz x23, #7, 1f // PSR_I_BIT
583 clear_address_tag x0, x3
584 mov x2, sp // struct pt_regs
587 // disable interrupts before pulling preserved data off the stack
592 * Stack or PC alignment exception handling
601 * Undefined instruction
609 * Debug exception handling
611 cmp x24, #ESR_ELx_EC_BRK64 // if BRK64
612 cinc x24, x24, eq // set bit '0'
613 tbz x24, #0, el1_inv // EL1 only
615 mov x2, sp // struct pt_regs
616 bl do_debug_exception
619 // TODO: add support for undefined instructions in kernel mode
632 #ifdef CONFIG_TRACE_IRQFLAGS
633 bl trace_hardirqs_off
638 #ifdef CONFIG_PREEMPT
639 ldr w24, [tsk, #TSK_TI_PREEMPT] // get preempt count
640 cbnz w24, 1f // preempt count != 0
641 ldr x0, [tsk, #TSK_TI_FLAGS] // get flags
642 tbz x0, #TIF_NEED_RESCHED, 1f // needs rescheduling?
646 #ifdef CONFIG_TRACE_IRQFLAGS
652 #ifdef CONFIG_PREEMPT
655 1: bl preempt_schedule_irq // irq en/disable is done inside
656 ldr x0, [tsk, #TSK_TI_FLAGS] // get new tasks TI_FLAGS
657 tbnz x0, #TIF_NEED_RESCHED, 1b // needs rescheduling?
667 mrs x25, esr_el1 // read the syndrome register
668 lsr x24, x25, #ESR_ELx_EC_SHIFT // exception class
669 cmp x24, #ESR_ELx_EC_SVC64 // SVC in 64-bit state
671 cmp x24, #ESR_ELx_EC_DABT_LOW // data abort in EL0
673 cmp x24, #ESR_ELx_EC_IABT_LOW // instruction abort in EL0
675 cmp x24, #ESR_ELx_EC_FP_ASIMD // FP/ASIMD access
677 cmp x24, #ESR_ELx_EC_FP_EXC64 // FP/ASIMD exception
679 cmp x24, #ESR_ELx_EC_SYS64 // configurable trap
681 cmp x24, #ESR_ELx_EC_SP_ALIGN // stack alignment exception
683 cmp x24, #ESR_ELx_EC_PC_ALIGN // pc alignment exception
685 cmp x24, #ESR_ELx_EC_UNKNOWN // unknown exception in EL0
687 cmp x24, #ESR_ELx_EC_BREAKPT_LOW // debug exception in EL0
695 mrs x25, esr_el1 // read the syndrome register
696 lsr x24, x25, #ESR_ELx_EC_SHIFT // exception class
697 cmp x24, #ESR_ELx_EC_SVC32 // SVC in 32-bit state
699 cmp x24, #ESR_ELx_EC_DABT_LOW // data abort in EL0
701 cmp x24, #ESR_ELx_EC_IABT_LOW // instruction abort in EL0
703 cmp x24, #ESR_ELx_EC_FP_ASIMD // FP/ASIMD access
705 cmp x24, #ESR_ELx_EC_FP_EXC32 // FP/ASIMD exception
707 cmp x24, #ESR_ELx_EC_PC_ALIGN // pc alignment exception
709 cmp x24, #ESR_ELx_EC_UNKNOWN // unknown exception in EL0
711 cmp x24, #ESR_ELx_EC_CP15_32 // CP15 MRC/MCR trap
713 cmp x24, #ESR_ELx_EC_CP15_64 // CP15 MRRC/MCRR trap
715 cmp x24, #ESR_ELx_EC_CP14_MR // CP14 MRC/MCR trap
717 cmp x24, #ESR_ELx_EC_CP14_LS // CP14 LDC/STC trap
719 cmp x24, #ESR_ELx_EC_CP14_64 // CP14 MRRC/MCRR trap
721 cmp x24, #ESR_ELx_EC_BREAKPT_LOW // debug exception in EL0
726 * AArch32 syscall handling
728 adrp stbl, compat_sys_call_table // load compat syscall table pointer
729 mov wscno, w7 // syscall number in w7 (r7)
730 mov wsc_nr, #__NR_compat_syscalls
741 * Data abort handling
744 // enable interrupts before calling the main handler
747 clear_address_tag x0, x26
754 * Instruction abort handling
758 #ifdef CONFIG_TRACE_IRQFLAGS
759 bl trace_hardirqs_off
765 bl do_el0_ia_bp_hardening
769 * Floating Point or Advanced SIMD access
779 * Floating Point or Advanced SIMD exception
789 * Stack or PC alignment exception handling
793 #ifdef CONFIG_TRACE_IRQFLAGS
794 bl trace_hardirqs_off
804 * Undefined instruction
806 // enable interrupts before calling the main handler
814 * System instructions, for trapped cache maintenance instructions
824 * Debug exception handling
826 tbnz x24, #0, el0_inv // EL0 only
830 bl do_debug_exception
849 #ifdef CONFIG_TRACE_IRQFLAGS
850 bl trace_hardirqs_off
854 #ifdef CONFIG_HARDEN_BRANCH_PREDICTOR
856 bl do_el0_irq_bp_hardening
861 #ifdef CONFIG_TRACE_IRQFLAGS
868 * This is the fast syscall return path. We do as little as possible here,
869 * and this includes saving x0 back into the kernel stack.
872 disable_irq // disable interrupts
873 str x0, [sp, #S_X0] // returned x0
874 ldr x1, [tsk, #TSK_TI_FLAGS] // re-check for syscall tracing
875 and x2, x1, #_TIF_SYSCALL_WORK
876 cbnz x2, ret_fast_syscall_trace
877 and x2, x1, #_TIF_WORK_MASK
878 cbnz x2, work_pending
879 enable_step_tsk x1, x2
881 ret_fast_syscall_trace:
882 enable_irq // enable interrupts
883 b __sys_trace_return_skipped // we already saved x0
886 * Ok, we need to do extra processing, enter the slow path.
891 #ifdef CONFIG_TRACE_IRQFLAGS
892 bl trace_hardirqs_on // enabled while in userspace
894 ldr x1, [tsk, #TSK_TI_FLAGS] // re-check for single-step
897 * "slow" syscall return path.
900 disable_irq // disable interrupts
901 ldr x1, [tsk, #TSK_TI_FLAGS]
902 and x2, x1, #_TIF_WORK_MASK
903 cbnz x2, work_pending
905 enable_step_tsk x1, x2
914 adrp stbl, sys_call_table // load syscall table pointer
915 mov wscno, w8 // syscall number in w8
916 mov wsc_nr, #__NR_syscalls
917 el0_svc_naked: // compat entry point
918 stp x0, xscno, [sp, #S_ORIG_X0] // save the original x0 and syscall number
922 ldr x16, [tsk, #TSK_TI_FLAGS] // check for syscall hooks
923 tst x16, #_TIF_SYSCALL_WORK
925 cmp wscno, wsc_nr // check upper syscall limit
927 mask_nospec64 xscno, xsc_nr, x19 // enforce bounds for syscall number
928 ldr x16, [stbl, xscno, lsl #3] // address in the syscall table
929 blr x16 // call sys_* routine
938 * This is the really slow path. We're going to be doing context
939 * switches, and waiting for our parent to respond.
942 cmp wscno, #NO_SYSCALL // user-issued syscall(-1)?
944 mov x0, #-ENOSYS // set default errno if so
947 bl syscall_trace_enter
948 cmp w0, #NO_SYSCALL // skip the syscall?
949 b.eq __sys_trace_return_skipped
950 mov wscno, w0 // syscall number (possibly new)
951 mov x1, sp // pointer to regs
952 cmp wscno, wsc_nr // check upper syscall limit
954 ldp x0, x1, [sp] // restore the syscall args
955 ldp x2, x3, [sp, #S_X2]
956 ldp x4, x5, [sp, #S_X4]
957 ldp x6, x7, [sp, #S_X6]
958 ldr x16, [stbl, xscno, lsl #3] // address in the syscall table
959 blr x16 // call sys_* routine
962 str x0, [sp, #S_X0] // save returned x0
963 __sys_trace_return_skipped:
965 bl syscall_trace_exit
973 .popsection // .entry.text
975 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0
977 * Exception vectors trampoline.
979 .pushsection ".entry.tramp.text", "ax"
981 .macro tramp_map_kernel, tmp
983 sub \tmp, \tmp, #(SWAPPER_DIR_SIZE + RESERVED_TTBR0_SIZE)
984 bic \tmp, \tmp, #USER_ASID_FLAG
986 #ifdef CONFIG_QCOM_FALKOR_ERRATUM_1003
987 alternative_if ARM64_WORKAROUND_QCOM_FALKOR_E1003
988 /* ASID already in \tmp[63:48] */
989 movk \tmp, #:abs_g2_nc:(TRAMP_VALIAS >> 12)
990 movk \tmp, #:abs_g1_nc:(TRAMP_VALIAS >> 12)
991 /* 2MB boundary containing the vectors, so we nobble the walk cache */
992 movk \tmp, #:abs_g0_nc:((TRAMP_VALIAS & ~(SZ_2M - 1)) >> 12)
996 alternative_else_nop_endif
997 #endif /* CONFIG_QCOM_FALKOR_ERRATUM_1003 */
1000 .macro tramp_unmap_kernel, tmp
1002 add \tmp, \tmp, #(SWAPPER_DIR_SIZE + RESERVED_TTBR0_SIZE)
1003 orr \tmp, \tmp, #USER_ASID_FLAG
1006 * We avoid running the post_ttbr_update_workaround here because
1007 * it's only needed by Cavium ThunderX, which requires KPTI to be
1012 .macro tramp_ventry, regsize = 64
1016 msr tpidrro_el0, x30 // Restored in kernel_ventry
1019 * Defend against branch aliasing attacks by pushing a dummy
1020 * entry onto the return stack and using a RET instruction to
1021 * enter the full-fat kernel vectors.
1026 tramp_map_kernel x30
1027 #ifdef CONFIG_RANDOMIZE_BASE
1028 adr x30, tramp_vectors + PAGE_SIZE
1029 alternative_insn isb, nop, ARM64_WORKAROUND_QCOM_FALKOR_E1003
1034 prfm plil1strm, [x30, #(1b - tramp_vectors)]
1036 add x30, x30, #(1b - tramp_vectors)
1041 .macro tramp_exit, regsize = 64
1042 adr x30, tramp_vectors
1044 tramp_unmap_kernel x30
1052 ENTRY(tramp_vectors)
1066 ENTRY(tramp_exit_native)
1068 END(tramp_exit_native)
1070 ENTRY(tramp_exit_compat)
1072 END(tramp_exit_compat)
1075 .popsection // .entry.tramp.text
1076 #ifdef CONFIG_RANDOMIZE_BASE
1077 .pushsection ".rodata", "a"
1079 .globl __entry_tramp_data_start
1080 __entry_tramp_data_start:
1082 .popsection // .rodata
1083 #endif /* CONFIG_RANDOMIZE_BASE */
1084 #endif /* CONFIG_UNMAP_KERNEL_AT_EL0 */
1087 * Special system call wrappers.
1089 ENTRY(sys_rt_sigreturn_wrapper)
1092 ENDPROC(sys_rt_sigreturn_wrapper)
1095 * Register switch for AArch64. The callee-saved registers need to be saved
1096 * and restored. On entry:
1097 * x0 = previous task_struct (must be preserved across the switch)
1098 * x1 = next task_struct
1099 * Previous and next are guaranteed not to be the same.
1102 ENTRY(cpu_switch_to)
1103 mov x10, #THREAD_CPU_CONTEXT
1106 stp x19, x20, [x8], #16 // store callee-saved registers
1107 stp x21, x22, [x8], #16
1108 stp x23, x24, [x8], #16
1109 stp x25, x26, [x8], #16
1110 stp x27, x28, [x8], #16
1111 stp x29, x9, [x8], #16
1114 ldp x19, x20, [x8], #16 // restore callee-saved registers
1115 ldp x21, x22, [x8], #16
1116 ldp x23, x24, [x8], #16
1117 ldp x25, x26, [x8], #16
1118 ldp x27, x28, [x8], #16
1119 ldp x29, x9, [x8], #16
1124 ENDPROC(cpu_switch_to)
1125 NOKPROBE(cpu_switch_to)
1128 * This is how we return from a fork.
1130 ENTRY(ret_from_fork)
1132 cbz x19, 1f // not a kernel thread
1135 1: get_thread_info tsk
1137 ENDPROC(ret_from_fork)
1138 NOKPROBE(ret_from_fork)