1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Low-level exception handling code
5 * Copyright (C) 2012 ARM Ltd.
6 * Authors: Catalin Marinas <catalin.marinas@arm.com>
7 * Will Deacon <will.deacon@arm.com>
10 #include <linux/arm-smccc.h>
11 #include <linux/init.h>
12 #include <linux/linkage.h>
14 #include <asm/alternative.h>
15 #include <asm/assembler.h>
16 #include <asm/asm-offsets.h>
17 #include <asm/asm_pointer_auth.h>
19 #include <asm/cpufeature.h>
20 #include <asm/errno.h>
23 #include <asm/memory.h>
25 #include <asm/processor.h>
26 #include <asm/ptrace.h>
28 #include <asm/thread_info.h>
29 #include <asm/asm-uaccess.h>
30 #include <asm/unistd.h>
33 .irp n,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29
38 .macro kernel_ventry, el:req, ht:req, regsize:req, label:req
43 * This must be the first instruction of the EL0 vector entries. It is
44 * skipped by the trampoline vectors, to trigger the cleanup.
46 b .Lskip_tramp_vectors_cleanup\@
53 .Lskip_tramp_vectors_cleanup\@:
56 sub sp, sp, #PT_REGS_SIZE
57 #ifdef CONFIG_VMAP_STACK
59 * Test whether the SP has overflowed, without corrupting a GPR.
60 * Task and IRQ stacks are aligned so that SP & (1 << THREAD_SHIFT)
61 * should always be zero.
63 add sp, sp, x0 // sp' = sp + x0
64 sub x0, sp, x0 // x0' = sp' - x0 = (sp + x0) - x0 = sp
65 tbnz x0, #THREAD_SHIFT, 0f
66 sub x0, sp, x0 // x0'' = sp' - x0' = (sp + x0) - sp = x0
67 sub sp, sp, x0 // sp'' = sp' - x0 = (sp + x0) - x0 = sp
68 b el\el\ht\()_\regsize\()_\label
72 * Either we've just detected an overflow, or we've taken an exception
73 * while on the overflow stack. Either way, we won't return to
74 * userspace, and can clobber EL0 registers to free up GPRs.
77 /* Stash the original SP (minus PT_REGS_SIZE) in tpidr_el0. */
80 /* Recover the original x0 value and stash it in tpidrro_el0 */
84 /* Switch to the overflow stack */
85 adr_this_cpu sp, overflow_stack + OVERFLOW_STACK_SIZE, x0
88 * Check whether we were already on the overflow stack. This may happen
89 * after panic() re-enables interrupts.
91 mrs x0, tpidr_el0 // sp of interrupted context
92 sub x0, sp, x0 // delta with top of overflow stack
93 tst x0, #~(OVERFLOW_STACK_SIZE - 1) // within range?
94 b.ne __bad_stack // no? -> bad stack pointer
96 /* We were already on the overflow stack. Restore sp/x0 and carry on. */
100 b el\el\ht\()_\regsize\()_\label
101 .org .Lventry_start\@ + 128 // Did we overflow the ventry slot?
104 .macro tramp_alias, dst, sym, tmp
105 mov_q \dst, TRAMP_VALIAS
108 adr_l \tmp, .entry.tramp.text
113 * This macro corrupts x0-x3. It is the caller's duty to save/restore
116 .macro apply_ssbd, state, tmp1, tmp2
117 alternative_cb ARM64_ALWAYS_SYSTEM, spectre_v4_patch_fw_mitigation_enable
118 b .L__asm_ssbd_skip\@ // Patched to NOP
120 ldr_this_cpu \tmp2, arm64_ssbd_callback_required, \tmp1
121 cbz \tmp2, .L__asm_ssbd_skip\@
122 ldr \tmp2, [tsk, #TSK_TI_FLAGS]
123 tbnz \tmp2, #TIF_SSBD, .L__asm_ssbd_skip\@
124 mov w0, #ARM_SMCCC_ARCH_WORKAROUND_2
126 alternative_cb ARM64_ALWAYS_SYSTEM, smccc_patch_fw_mitigation_conduit
127 nop // Patched to SMC/HVC #0
132 /* Check for MTE asynchronous tag check faults */
133 .macro check_mte_async_tcf, tmp, ti_flags, thread_sctlr
134 #ifdef CONFIG_ARM64_MTE
136 alternative_if_not ARM64_MTE
138 alternative_else_nop_endif
140 * Asynchronous tag check faults are only possible in ASYNC (2) or
141 * ASYM (3) modes. In each of these modes bit 1 of SCTLR_EL1.TCF0 is
142 * set, so skip the check if it is unset.
144 tbz \thread_sctlr, #(SCTLR_EL1_TCF0_SHIFT + 1), 1f
145 mrs_s \tmp, SYS_TFSRE0_EL1
146 tbz \tmp, #SYS_TFSR_EL1_TF0_SHIFT, 1f
147 /* Asynchronous TCF occurred for TTBR0 access, set the TI flag */
148 mov \tmp, #_TIF_MTE_ASYNC_FAULT
149 add \ti_flags, tsk, #TSK_TI_FLAGS
150 stset \tmp, [\ti_flags]
155 /* Clear the MTE asynchronous tag check faults */
156 .macro clear_mte_async_tcf thread_sctlr
157 #ifdef CONFIG_ARM64_MTE
158 alternative_if ARM64_MTE
159 /* See comment in check_mte_async_tcf above. */
160 tbz \thread_sctlr, #(SCTLR_EL1_TCF0_SHIFT + 1), 1f
162 msr_s SYS_TFSRE0_EL1, xzr
164 alternative_else_nop_endif
168 .macro mte_set_gcr, mte_ctrl, tmp
169 #ifdef CONFIG_ARM64_MTE
170 ubfx \tmp, \mte_ctrl, #MTE_CTRL_GCR_USER_EXCL_SHIFT, #16
171 orr \tmp, \tmp, #SYS_GCR_EL1_RRND
172 msr_s SYS_GCR_EL1, \tmp
176 .macro mte_set_kernel_gcr, tmp, tmp2
177 #ifdef CONFIG_KASAN_HW_TAGS
178 alternative_cb ARM64_ALWAYS_SYSTEM, kasan_hw_tags_enable
181 mov \tmp, KERNEL_GCR_EL1
182 msr_s SYS_GCR_EL1, \tmp
187 .macro mte_set_user_gcr, tsk, tmp, tmp2
188 #ifdef CONFIG_KASAN_HW_TAGS
189 alternative_cb ARM64_ALWAYS_SYSTEM, kasan_hw_tags_enable
192 ldr \tmp, [\tsk, #THREAD_MTE_CTRL]
194 mte_set_gcr \tmp, \tmp2
199 .macro kernel_entry, el, regsize = 64
201 mov w0, w0 // zero upper 32 bits of x0
203 stp x0, x1, [sp, #16 * 0]
204 stp x2, x3, [sp, #16 * 1]
205 stp x4, x5, [sp, #16 * 2]
206 stp x6, x7, [sp, #16 * 3]
207 stp x8, x9, [sp, #16 * 4]
208 stp x10, x11, [sp, #16 * 5]
209 stp x12, x13, [sp, #16 * 6]
210 stp x14, x15, [sp, #16 * 7]
211 stp x16, x17, [sp, #16 * 8]
212 stp x18, x19, [sp, #16 * 9]
213 stp x20, x21, [sp, #16 * 10]
214 stp x22, x23, [sp, #16 * 11]
215 stp x24, x25, [sp, #16 * 12]
216 stp x26, x27, [sp, #16 * 13]
217 stp x28, x29, [sp, #16 * 14]
222 ldr_this_cpu tsk, __entry_task, x20
226 * Ensure MDSCR_EL1.SS is clear, since we can unmask debug exceptions
229 ldr x19, [tsk, #TSK_TI_FLAGS]
230 disable_step_tsk x19, x20
232 /* Check for asynchronous tag check faults in user space */
233 ldr x0, [tsk, THREAD_SCTLR_USER]
234 check_mte_async_tcf x22, x23, x0
236 #ifdef CONFIG_ARM64_PTR_AUTH
237 alternative_if ARM64_HAS_ADDRESS_AUTH
239 * Enable IA for in-kernel PAC if the task had it disabled. Although
240 * this could be implemented with an unconditional MRS which would avoid
241 * a load, this was measured to be slower on Cortex-A75 and Cortex-A76.
243 * Install the kernel IA key only if IA was enabled in the task. If IA
244 * was disabled on kernel exit then we would have left the kernel IA
245 * installed so there is no need to install it again.
247 tbz x0, SCTLR_ELx_ENIA_SHIFT, 1f
248 __ptrauth_keys_install_kernel_nosync tsk, x20, x22, x23
252 orr x0, x0, SCTLR_ELx_ENIA
255 alternative_else_nop_endif
258 apply_ssbd 1, x22, x23
260 mte_set_kernel_gcr x22, x23
263 * Any non-self-synchronizing system register updates required for
264 * kernel entry should be placed before this point.
266 alternative_if ARM64_MTE
269 alternative_else_nop_endif
270 alternative_if ARM64_HAS_ADDRESS_AUTH
272 alternative_else_nop_endif
277 add x21, sp, #PT_REGS_SIZE
279 .endif /* \el == 0 */
282 stp lr, x21, [sp, #S_LR]
285 * For exceptions from EL0, create a final frame record.
286 * For exceptions from EL1, create a synthetic frame record so the
287 * interrupted code shows up in the backtrace.
290 stp xzr, xzr, [sp, #S_STACKFRAME]
292 stp x29, x22, [sp, #S_STACKFRAME]
294 add x29, sp, #S_STACKFRAME
296 #ifdef CONFIG_ARM64_SW_TTBR0_PAN
297 alternative_if_not ARM64_HAS_PAN
298 bl __swpan_entry_el\el
299 alternative_else_nop_endif
302 stp x22, x23, [sp, #S_PC]
304 /* Not in a syscall by default (el0_svc overwrites for real syscall) */
307 str w21, [sp, #S_SYSCALLNO]
310 #ifdef CONFIG_ARM64_PSEUDO_NMI
312 alternative_if ARM64_HAS_IRQ_PRIO_MASKING
313 mrs_s x20, SYS_ICC_PMR_EL1
314 str x20, [sp, #S_PMR_SAVE]
315 mov x20, #GIC_PRIO_IRQON | GIC_PRIO_PSR_I_SET
316 msr_s SYS_ICC_PMR_EL1, x20
317 alternative_else_nop_endif
321 * Registers that may be useful after this macro is invoked:
326 * x23 - aborted PSTATE
330 .macro kernel_exit, el
335 #ifdef CONFIG_ARM64_PSEUDO_NMI
337 alternative_if ARM64_HAS_IRQ_PRIO_MASKING
338 ldr x20, [sp, #S_PMR_SAVE]
339 msr_s SYS_ICC_PMR_EL1, x20
340 mrs_s x21, SYS_ICC_CTLR_EL1
341 tbz x21, #6, .L__skip_pmr_sync\@ // Check for ICC_CTLR_EL1.PMHE
342 dsb sy // Ensure priority change is seen by redistributor
344 alternative_else_nop_endif
347 ldp x21, x22, [sp, #S_PC] // load ELR, SPSR
349 #ifdef CONFIG_ARM64_SW_TTBR0_PAN
350 alternative_if_not ARM64_HAS_PAN
351 bl __swpan_exit_el\el
352 alternative_else_nop_endif
356 ldr x23, [sp, #S_SP] // load return stack pointer
358 tst x22, #PSR_MODE32_BIT // native task?
361 #ifdef CONFIG_ARM64_ERRATUM_845719
362 alternative_if ARM64_WORKAROUND_845719
363 #ifdef CONFIG_PID_IN_CONTEXTIDR
364 mrs x29, contextidr_el1
365 msr contextidr_el1, x29
367 msr contextidr_el1, xzr
369 alternative_else_nop_endif
374 /* Ignore asynchronous tag check faults in the uaccess routines */
375 ldr x0, [tsk, THREAD_SCTLR_USER]
376 clear_mte_async_tcf x0
378 #ifdef CONFIG_ARM64_PTR_AUTH
379 alternative_if ARM64_HAS_ADDRESS_AUTH
381 * IA was enabled for in-kernel PAC. Disable it now if needed, or
382 * alternatively install the user's IA. All other per-task keys and
383 * SCTLR bits were updated on task switch.
385 * No kernel C function calls after this.
387 tbz x0, SCTLR_ELx_ENIA_SHIFT, 1f
388 __ptrauth_keys_install_user tsk, x0, x1, x2
392 bic x0, x0, SCTLR_ELx_ENIA
395 alternative_else_nop_endif
398 mte_set_user_gcr tsk, x0, x1
403 msr elr_el1, x21 // set up the return data
405 ldp x0, x1, [sp, #16 * 0]
406 ldp x2, x3, [sp, #16 * 1]
407 ldp x4, x5, [sp, #16 * 2]
408 ldp x6, x7, [sp, #16 * 3]
409 ldp x8, x9, [sp, #16 * 4]
410 ldp x10, x11, [sp, #16 * 5]
411 ldp x12, x13, [sp, #16 * 6]
412 ldp x14, x15, [sp, #16 * 7]
413 ldp x16, x17, [sp, #16 * 8]
414 ldp x18, x19, [sp, #16 * 9]
415 ldp x20, x21, [sp, #16 * 10]
416 ldp x22, x23, [sp, #16 * 11]
417 ldp x24, x25, [sp, #16 * 12]
418 ldp x26, x27, [sp, #16 * 13]
419 ldp x28, x29, [sp, #16 * 14]
422 alternative_if ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD
425 alternative_else_nop_endif
426 alternative_if_not ARM64_UNMAP_KERNEL_AT_EL0
428 add sp, sp, #PT_REGS_SIZE // restore sp
430 alternative_else_nop_endif
431 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0
434 tramp_alias x30, tramp_exit_native, x29
437 tramp_alias x30, tramp_exit_compat, x29
442 add sp, sp, #PT_REGS_SIZE // restore sp
444 /* Ensure any device/NC reads complete */
445 alternative_insn nop, "dmb sy", ARM64_WORKAROUND_1508412
452 #ifdef CONFIG_ARM64_SW_TTBR0_PAN
454 * Set the TTBR0 PAN bit in SPSR. When the exception is taken from
455 * EL0, there is no need to check the state of TTBR0_EL1 since
456 * accesses are always enabled.
457 * Note that the meaning of this bit differs from the ARMv8.1 PAN
458 * feature as all TTBR0_EL1 accesses are disabled, not just those to
461 SYM_CODE_START_LOCAL(__swpan_entry_el1)
463 tst x21, #TTBR_ASID_MASK // Check for the reserved ASID
464 orr x23, x23, #PSR_PAN_BIT // Set the emulated PAN in the saved SPSR
465 b.eq 1f // TTBR0 access already disabled
466 and x23, x23, #~PSR_PAN_BIT // Clear the emulated PAN in the saved SPSR
467 SYM_INNER_LABEL(__swpan_entry_el0, SYM_L_LOCAL)
468 __uaccess_ttbr0_disable x21
470 SYM_CODE_END(__swpan_entry_el1)
473 * Restore access to TTBR0_EL1. If returning to EL0, no need for SPSR
476 SYM_CODE_START_LOCAL(__swpan_exit_el1)
477 tbnz x22, #22, 1f // Skip re-enabling TTBR0 access if the PSR_PAN_BIT is set
478 __uaccess_ttbr0_enable x0, x1
479 1: and x22, x22, #~PSR_PAN_BIT // ARMv8.0 CPUs do not understand this bit
481 SYM_CODE_END(__swpan_exit_el1)
483 SYM_CODE_START_LOCAL(__swpan_exit_el0)
484 __uaccess_ttbr0_enable x0, x1
486 * Enable errata workarounds only if returning to user. The only
487 * workaround currently required for TTBR0_EL1 changes are for the
488 * Cavium erratum 27456 (broadcast TLBI instructions may cause I-cache
491 b post_ttbr_update_workaround
492 SYM_CODE_END(__swpan_exit_el0)
495 /* GPRs used by entry code */
496 tsk .req x28 // current thread_info
503 .pushsection ".entry.text", "ax"
506 SYM_CODE_START(vectors)
507 kernel_ventry 1, t, 64, sync // Synchronous EL1t
508 kernel_ventry 1, t, 64, irq // IRQ EL1t
509 kernel_ventry 1, t, 64, fiq // FIQ EL1t
510 kernel_ventry 1, t, 64, error // Error EL1t
512 kernel_ventry 1, h, 64, sync // Synchronous EL1h
513 kernel_ventry 1, h, 64, irq // IRQ EL1h
514 kernel_ventry 1, h, 64, fiq // FIQ EL1h
515 kernel_ventry 1, h, 64, error // Error EL1h
517 kernel_ventry 0, t, 64, sync // Synchronous 64-bit EL0
518 kernel_ventry 0, t, 64, irq // IRQ 64-bit EL0
519 kernel_ventry 0, t, 64, fiq // FIQ 64-bit EL0
520 kernel_ventry 0, t, 64, error // Error 64-bit EL0
522 kernel_ventry 0, t, 32, sync // Synchronous 32-bit EL0
523 kernel_ventry 0, t, 32, irq // IRQ 32-bit EL0
524 kernel_ventry 0, t, 32, fiq // FIQ 32-bit EL0
525 kernel_ventry 0, t, 32, error // Error 32-bit EL0
526 SYM_CODE_END(vectors)
528 #ifdef CONFIG_VMAP_STACK
529 SYM_CODE_START_LOCAL(__bad_stack)
531 * We detected an overflow in kernel_ventry, which switched to the
532 * overflow stack. Stash the exception regs, and head to our overflow
536 /* Restore the original x0 value */
540 * Store the original GPRs to the new stack. The orginal SP (minus
541 * PT_REGS_SIZE) was stashed in tpidr_el0 by kernel_ventry.
543 sub sp, sp, #PT_REGS_SIZE
546 add x0, x0, #PT_REGS_SIZE
549 /* Stash the regs for handle_bad_stack */
555 SYM_CODE_END(__bad_stack)
556 #endif /* CONFIG_VMAP_STACK */
559 .macro entry_handler el:req, ht:req, regsize:req, label:req
560 SYM_CODE_START_LOCAL(el\el\ht\()_\regsize\()_\label)
561 kernel_entry \el, \regsize
563 bl el\el\ht\()_\regsize\()_\label\()_handler
569 SYM_CODE_END(el\el\ht\()_\regsize\()_\label)
573 * Early exception handlers
575 entry_handler 1, t, 64, sync
576 entry_handler 1, t, 64, irq
577 entry_handler 1, t, 64, fiq
578 entry_handler 1, t, 64, error
580 entry_handler 1, h, 64, sync
581 entry_handler 1, h, 64, irq
582 entry_handler 1, h, 64, fiq
583 entry_handler 1, h, 64, error
585 entry_handler 0, t, 64, sync
586 entry_handler 0, t, 64, irq
587 entry_handler 0, t, 64, fiq
588 entry_handler 0, t, 64, error
590 entry_handler 0, t, 32, sync
591 entry_handler 0, t, 32, irq
592 entry_handler 0, t, 32, fiq
593 entry_handler 0, t, 32, error
595 SYM_CODE_START_LOCAL(ret_to_kernel)
597 SYM_CODE_END(ret_to_kernel)
599 SYM_CODE_START_LOCAL(ret_to_user)
600 ldr x19, [tsk, #TSK_TI_FLAGS] // re-check for single-step
601 enable_step_tsk x19, x2
602 #ifdef CONFIG_GCC_PLUGIN_STACKLEAK
603 bl stackleak_erase_on_task_stack
606 SYM_CODE_END(ret_to_user)
608 .popsection // .entry.text
610 // Move from tramp_pg_dir to swapper_pg_dir
611 .macro tramp_map_kernel, tmp
613 add \tmp, \tmp, #TRAMP_SWAPPER_OFFSET
614 bic \tmp, \tmp, #USER_ASID_FLAG
616 #ifdef CONFIG_QCOM_FALKOR_ERRATUM_1003
617 alternative_if ARM64_WORKAROUND_QCOM_FALKOR_E1003
618 /* ASID already in \tmp[63:48] */
619 movk \tmp, #:abs_g2_nc:(TRAMP_VALIAS >> 12)
620 movk \tmp, #:abs_g1_nc:(TRAMP_VALIAS >> 12)
621 /* 2MB boundary containing the vectors, so we nobble the walk cache */
622 movk \tmp, #:abs_g0_nc:((TRAMP_VALIAS & ~(SZ_2M - 1)) >> 12)
626 alternative_else_nop_endif
627 #endif /* CONFIG_QCOM_FALKOR_ERRATUM_1003 */
630 // Move from swapper_pg_dir to tramp_pg_dir
631 .macro tramp_unmap_kernel, tmp
633 sub \tmp, \tmp, #TRAMP_SWAPPER_OFFSET
634 orr \tmp, \tmp, #USER_ASID_FLAG
637 * We avoid running the post_ttbr_update_workaround here because
638 * it's only needed by Cavium ThunderX, which requires KPTI to be
643 .macro tramp_data_read_var dst, var
644 #ifdef CONFIG_RELOCATABLE
645 ldr \dst, .L__tramp_data_\var
646 .ifndef .L__tramp_data_\var
647 .pushsection ".entry.tramp.rodata", "a", %progbits
655 * As !RELOCATABLE implies !RANDOMIZE_BASE the address is always a
656 * compile time constant (and hence not secret and not worth hiding).
658 * As statically allocated kernel code and data always live in the top
659 * 47 bits of the address space we can sign-extend bit 47 and avoid an
660 * instruction to load the upper 16 bits (which must be 0xFFFF).
662 movz \dst, :abs_g2_s:\var
663 movk \dst, :abs_g1_nc:\var
664 movk \dst, :abs_g0_nc:\var
668 #define BHB_MITIGATION_NONE 0
669 #define BHB_MITIGATION_LOOP 1
670 #define BHB_MITIGATION_FW 2
671 #define BHB_MITIGATION_INSN 3
673 .macro tramp_ventry, vector_start, regsize, kpti, bhb
677 msr tpidrro_el0, x30 // Restored in kernel_ventry
680 .if \bhb == BHB_MITIGATION_LOOP
682 * This sequence must appear before the first indirect branch. i.e. the
683 * ret out of tramp_ventry. It appears here because x30 is free.
685 __mitigate_spectre_bhb_loop x30
686 .endif // \bhb == BHB_MITIGATION_LOOP
688 .if \bhb == BHB_MITIGATION_INSN
691 .endif // \bhb == BHB_MITIGATION_INSN
695 * Defend against branch aliasing attacks by pushing a dummy
696 * entry onto the return stack and using a RET instruction to
697 * enter the full-fat kernel vectors.
703 alternative_insn isb, nop, ARM64_WORKAROUND_QCOM_FALKOR_E1003
704 tramp_data_read_var x30, vectors
705 alternative_if_not ARM64_WORKAROUND_CAVIUM_TX2_219_PRFM
706 prfm plil1strm, [x30, #(1b - \vector_start)]
707 alternative_else_nop_endif
715 .if \bhb == BHB_MITIGATION_FW
717 * The firmware sequence must appear before the first indirect branch.
718 * i.e. the ret out of tramp_ventry. But it also needs the stack to be
719 * mapped to save/restore the registers the SMC clobbers.
721 __mitigate_spectre_bhb_fw
722 .endif // \bhb == BHB_MITIGATION_FW
724 add x30, x30, #(1b - \vector_start + 4)
726 .org 1b + 128 // Did we overflow the ventry slot?
729 .macro tramp_exit, regsize = 64
730 tramp_data_read_var x30, this_cpu_vector
731 get_this_cpu_offset x29
736 tramp_unmap_kernel x29
740 add sp, sp, #PT_REGS_SIZE // restore sp
745 .macro generate_tramp_vector, kpti, bhb
750 tramp_ventry .Lvector_start\@, 64, \kpti, \bhb
753 tramp_ventry .Lvector_start\@, 32, \kpti, \bhb
757 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0
759 * Exception vectors trampoline.
760 * The order must match __bp_harden_el1_vectors and the
761 * arm64_bp_harden_el1_vectors enum.
763 .pushsection ".entry.tramp.text", "ax"
765 SYM_CODE_START_NOALIGN(tramp_vectors)
766 #ifdef CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY
767 generate_tramp_vector kpti=1, bhb=BHB_MITIGATION_LOOP
768 generate_tramp_vector kpti=1, bhb=BHB_MITIGATION_FW
769 generate_tramp_vector kpti=1, bhb=BHB_MITIGATION_INSN
770 #endif /* CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY */
771 generate_tramp_vector kpti=1, bhb=BHB_MITIGATION_NONE
772 SYM_CODE_END(tramp_vectors)
774 SYM_CODE_START(tramp_exit_native)
776 SYM_CODE_END(tramp_exit_native)
778 SYM_CODE_START(tramp_exit_compat)
780 SYM_CODE_END(tramp_exit_compat)
781 .popsection // .entry.tramp.text
782 #endif /* CONFIG_UNMAP_KERNEL_AT_EL0 */
785 * Exception vectors for spectre mitigations on entry from EL1 when
786 * kpti is not in use.
788 .macro generate_el1_vector, bhb
790 kernel_ventry 1, t, 64, sync // Synchronous EL1t
791 kernel_ventry 1, t, 64, irq // IRQ EL1t
792 kernel_ventry 1, t, 64, fiq // FIQ EL1h
793 kernel_ventry 1, t, 64, error // Error EL1t
795 kernel_ventry 1, h, 64, sync // Synchronous EL1h
796 kernel_ventry 1, h, 64, irq // IRQ EL1h
797 kernel_ventry 1, h, 64, fiq // FIQ EL1h
798 kernel_ventry 1, h, 64, error // Error EL1h
801 tramp_ventry .Lvector_start\@, 64, 0, \bhb
804 tramp_ventry .Lvector_start\@, 32, 0, \bhb
808 /* The order must match tramp_vecs and the arm64_bp_harden_el1_vectors enum. */
809 .pushsection ".entry.text", "ax"
811 SYM_CODE_START(__bp_harden_el1_vectors)
812 #ifdef CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY
813 generate_el1_vector bhb=BHB_MITIGATION_LOOP
814 generate_el1_vector bhb=BHB_MITIGATION_FW
815 generate_el1_vector bhb=BHB_MITIGATION_INSN
816 #endif /* CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY */
817 SYM_CODE_END(__bp_harden_el1_vectors)
822 * Register switch for AArch64. The callee-saved registers need to be saved
823 * and restored. On entry:
824 * x0 = previous task_struct (must be preserved across the switch)
825 * x1 = next task_struct
826 * Previous and next are guaranteed not to be the same.
829 SYM_FUNC_START(cpu_switch_to)
830 mov x10, #THREAD_CPU_CONTEXT
833 stp x19, x20, [x8], #16 // store callee-saved registers
834 stp x21, x22, [x8], #16
835 stp x23, x24, [x8], #16
836 stp x25, x26, [x8], #16
837 stp x27, x28, [x8], #16
838 stp x29, x9, [x8], #16
841 ldp x19, x20, [x8], #16 // restore callee-saved registers
842 ldp x21, x22, [x8], #16
843 ldp x23, x24, [x8], #16
844 ldp x25, x26, [x8], #16
845 ldp x27, x28, [x8], #16
846 ldp x29, x9, [x8], #16
850 ptrauth_keys_install_kernel x1, x8, x9, x10
854 SYM_FUNC_END(cpu_switch_to)
855 NOKPROBE(cpu_switch_to)
858 * This is how we return from a fork.
860 SYM_CODE_START(ret_from_fork)
862 cbz x19, 1f // not a kernel thread
865 1: get_current_task tsk
867 bl asm_exit_to_user_mode
869 SYM_CODE_END(ret_from_fork)
870 NOKPROBE(ret_from_fork)
873 * void call_on_irq_stack(struct pt_regs *regs,
874 * void (*func)(struct pt_regs *));
876 * Calls func(regs) using this CPU's irq stack and shadow irq stack.
878 SYM_FUNC_START(call_on_irq_stack)
879 #ifdef CONFIG_SHADOW_CALL_STACK
882 ldr_this_cpu scs_sp, irq_shadow_call_stack_ptr, x17
885 /* Create a frame record to save our LR and SP (implicit in FP) */
886 stp x29, x30, [sp, #-16]!
889 ldr_this_cpu x16, irq_stack_ptr, x17
891 /* Move to the new stack and call the function there */
892 add sp, x16, #IRQ_STACK_SIZE
896 * Restore the SP from the FP, and restore the FP and LR from the frame
900 ldp x29, x30, [sp], #16
903 SYM_FUNC_END(call_on_irq_stack)
904 NOKPROBE(call_on_irq_stack)
906 #ifdef CONFIG_ARM_SDE_INTERFACE
908 #include <asm/sdei.h>
909 #include <uapi/linux/arm_sdei.h>
911 .macro sdei_handler_exit exit_mode
912 /* On success, this call never returns... */
913 cmp \exit_mode, #SDEI_EXIT_SMC
921 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0
923 * The regular SDEI entry point may have been unmapped along with the rest of
924 * the kernel. This trampoline restores the kernel mapping to make the x1 memory
925 * argument accessible.
927 * This clobbers x4, __sdei_handler() will restore this from firmware's
930 .pushsection ".entry.tramp.text", "ax"
931 SYM_CODE_START(__sdei_asm_entry_trampoline)
933 tbz x4, #USER_ASID_BIT, 1f
935 tramp_map_kernel tmp=x4
940 * Remember whether to unmap the kernel on exit.
942 1: str x4, [x1, #(SDEI_EVENT_INTREGS + S_SDEI_TTBR1)]
943 tramp_data_read_var x4, __sdei_asm_handler
945 SYM_CODE_END(__sdei_asm_entry_trampoline)
946 NOKPROBE(__sdei_asm_entry_trampoline)
949 * Make the exit call and restore the original ttbr1_el1
951 * x0 & x1: setup for the exit API call
953 * x4: struct sdei_registered_event argument from registration time.
955 SYM_CODE_START(__sdei_asm_exit_trampoline)
956 ldr x4, [x4, #(SDEI_EVENT_INTREGS + S_SDEI_TTBR1)]
959 tramp_unmap_kernel tmp=x4
961 1: sdei_handler_exit exit_mode=x2
962 SYM_CODE_END(__sdei_asm_exit_trampoline)
963 NOKPROBE(__sdei_asm_exit_trampoline)
964 .popsection // .entry.tramp.text
965 #endif /* CONFIG_UNMAP_KERNEL_AT_EL0 */
968 * Software Delegated Exception entry point.
971 * x1: struct sdei_registered_event argument from registration time.
973 * x3: interrupted PSTATE
974 * x4: maybe clobbered by the trampoline
976 * Firmware has preserved x0->x17 for us, we must save/restore the rest to
977 * follow SMC-CC. We save (or retrieve) all the registers as the handler may
980 SYM_CODE_START(__sdei_asm_handler)
981 stp x2, x3, [x1, #SDEI_EVENT_INTREGS + S_PC]
982 stp x4, x5, [x1, #SDEI_EVENT_INTREGS + 16 * 2]
983 stp x6, x7, [x1, #SDEI_EVENT_INTREGS + 16 * 3]
984 stp x8, x9, [x1, #SDEI_EVENT_INTREGS + 16 * 4]
985 stp x10, x11, [x1, #SDEI_EVENT_INTREGS + 16 * 5]
986 stp x12, x13, [x1, #SDEI_EVENT_INTREGS + 16 * 6]
987 stp x14, x15, [x1, #SDEI_EVENT_INTREGS + 16 * 7]
988 stp x16, x17, [x1, #SDEI_EVENT_INTREGS + 16 * 8]
989 stp x18, x19, [x1, #SDEI_EVENT_INTREGS + 16 * 9]
990 stp x20, x21, [x1, #SDEI_EVENT_INTREGS + 16 * 10]
991 stp x22, x23, [x1, #SDEI_EVENT_INTREGS + 16 * 11]
992 stp x24, x25, [x1, #SDEI_EVENT_INTREGS + 16 * 12]
993 stp x26, x27, [x1, #SDEI_EVENT_INTREGS + 16 * 13]
994 stp x28, x29, [x1, #SDEI_EVENT_INTREGS + 16 * 14]
996 stp lr, x4, [x1, #SDEI_EVENT_INTREGS + S_LR]
1000 /* Store the registered-event for crash_smp_send_stop() */
1001 ldrb w4, [x19, #SDEI_EVENT_PRIORITY]
1003 adr_this_cpu dst=x5, sym=sdei_active_normal_event, tmp=x6
1005 1: adr_this_cpu dst=x5, sym=sdei_active_critical_event, tmp=x6
1008 #ifdef CONFIG_VMAP_STACK
1010 * entry.S may have been using sp as a scratch register, find whether
1011 * this is a normal or critical event and switch to the appropriate
1012 * stack for this CPU.
1015 ldr_this_cpu dst=x5, sym=sdei_stack_normal_ptr, tmp=x6
1017 1: ldr_this_cpu dst=x5, sym=sdei_stack_critical_ptr, tmp=x6
1018 2: mov x6, #SDEI_STACK_SIZE
1023 #ifdef CONFIG_SHADOW_CALL_STACK
1024 /* Use a separate shadow call stack for normal and critical events */
1026 ldr_this_cpu dst=scs_sp, sym=sdei_shadow_call_stack_normal_ptr, tmp=x6
1028 3: ldr_this_cpu dst=scs_sp, sym=sdei_shadow_call_stack_critical_ptr, tmp=x6
1033 * We may have interrupted userspace, or a guest, or exit-from or
1034 * return-to either of these. We can't trust sp_el0, restore it.
1037 ldr_this_cpu dst=x0, sym=__entry_task, tmp=x1
1040 /* If we interrupted the kernel point to the previous stack/frame. */
1044 csel x29, x29, xzr, eq // fp, or zero
1045 csel x4, x2, xzr, eq // elr, or zero
1047 stp x29, x4, [sp, #-16]!
1050 add x0, x19, #SDEI_EVENT_INTREGS
1055 /* restore regs >x17 that we clobbered */
1056 mov x4, x19 // keep x4 for __sdei_asm_exit_trampoline
1057 ldp x28, x29, [x4, #SDEI_EVENT_INTREGS + 16 * 14]
1058 ldp x18, x19, [x4, #SDEI_EVENT_INTREGS + 16 * 9]
1059 ldp lr, x1, [x4, #SDEI_EVENT_INTREGS + S_LR]
1062 mov x1, x0 // address to complete_and_resume
1063 /* x0 = (x0 <= SDEI_EV_FAILED) ?
1064 * EVENT_COMPLETE:EVENT_COMPLETE_AND_RESUME
1066 cmp x0, #SDEI_EV_FAILED
1067 mov_q x2, SDEI_1_0_FN_SDEI_EVENT_COMPLETE
1068 mov_q x3, SDEI_1_0_FN_SDEI_EVENT_COMPLETE_AND_RESUME
1071 ldr_l x2, sdei_exit_mode
1073 /* Clear the registered-event seen by crash_smp_send_stop() */
1074 ldrb w3, [x4, #SDEI_EVENT_PRIORITY]
1076 adr_this_cpu dst=x5, sym=sdei_active_normal_event, tmp=x6
1078 1: adr_this_cpu dst=x5, sym=sdei_active_critical_event, tmp=x6
1081 alternative_if_not ARM64_UNMAP_KERNEL_AT_EL0
1082 sdei_handler_exit exit_mode=x2
1083 alternative_else_nop_endif
1085 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0
1086 tramp_alias dst=x5, sym=__sdei_asm_exit_trampoline, tmp=x3
1089 SYM_CODE_END(__sdei_asm_handler)
1090 NOKPROBE(__sdei_asm_handler)
1092 SYM_CODE_START(__sdei_handler_abort)
1093 mov_q x0, SDEI_1_0_FN_SDEI_EVENT_COMPLETE_AND_RESUME
1095 ldr_l x2, sdei_exit_mode
1096 sdei_handler_exit exit_mode=x2
1097 // exit the handler and jump to the next instruction.
1098 // Exit will stomp x0-x17, PSTATE, ELR_ELx, and SPSR_ELx.
1100 SYM_CODE_END(__sdei_handler_abort)
1101 NOKPROBE(__sdei_handler_abort)
1102 #endif /* CONFIG_ARM_SDE_INTERFACE */