arch/arm64/kernel/cpuinfo.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Record and handle CPU attributes.
   4  *
   5  * Copyright (C) 2014 ARM Ltd.
   6  */
   7 #include <asm/arch_timer.h>
   8 #include <asm/cache.h>
   9 #include <asm/cpu.h>
  10 #include <asm/cputype.h>
  11 #include <asm/cpufeature.h>
  12 #include <asm/fpsimd.h>
  13
  14 #include <linux/bitops.h>
  15 #include <linux/bug.h>
  16 #include <linux/compat.h>
  17 #include <linux/elf.h>
  18 #include <linux/init.h>
  19 #include <linux/kernel.h>
  20 #include <linux/personality.h>
  21 #include <linux/preempt.h>
  22 #include <linux/printk.h>
  23 #include <linux/seq_file.h>
  24 #include <linux/sched.h>
  25 #include <linux/smp.h>
  26 #include <linux/delay.h>
  27
  28 /*
  29  * In case the boot CPU is hotpluggable, we record its initial state and
  30  * current state separately. Certain system registers may contain different
  31  * values depending on configuration at or after reset.
  32  */
  33 DEFINE_PER_CPU(struct cpuinfo_arm64, cpu_data);
  34 static struct cpuinfo_arm64 boot_cpu_data;
  35
  36 static inline const char *icache_policy_str(int l1ip)
  37 {
  38         switch (l1ip) {
  39         case CTR_EL0_L1Ip_VPIPT:
  40                 return "VPIPT";
  41         case CTR_EL0_L1Ip_VIPT:
  42                 return "VIPT";
  43         case CTR_EL0_L1Ip_PIPT:
  44                 return "PIPT";
  45         default:
  46                 return "RESERVED/UNKNOWN";
  47         }
  48 }
  49
  50 unsigned long __icache_flags;
  51
  52 static const char *const hwcap_str[] = {
  53         [KERNEL_HWCAP_FP]               = "fp",
  54         [KERNEL_HWCAP_ASIMD]            = "asimd",
  55         [KERNEL_HWCAP_EVTSTRM]          = "evtstrm",
  56         [KERNEL_HWCAP_AES]              = "aes",
  57         [KERNEL_HWCAP_PMULL]            = "pmull",
  58         [KERNEL_HWCAP_SHA1]             = "sha1",
  59         [KERNEL_HWCAP_SHA2]             = "sha2",
  60         [KERNEL_HWCAP_CRC32]            = "crc32",
  61         [KERNEL_HWCAP_ATOMICS]          = "atomics",
  62         [KERNEL_HWCAP_FPHP]             = "fphp",
  63         [KERNEL_HWCAP_ASIMDHP]          = "asimdhp",
  64         [KERNEL_HWCAP_CPUID]            = "cpuid",
  65         [KERNEL_HWCAP_ASIMDRDM]         = "asimdrdm",
  66         [KERNEL_HWCAP_JSCVT]            = "jscvt",
  67         [KERNEL_HWCAP_FCMA]             = "fcma",
  68         [KERNEL_HWCAP_LRCPC]            = "lrcpc",
  69         [KERNEL_HWCAP_DCPOP]            = "dcpop",
  70         [KERNEL_HWCAP_SHA3]             = "sha3",
  71         [KERNEL_HWCAP_SM3]              = "sm3",
  72         [KERNEL_HWCAP_SM4]              = "sm4",
  73         [KERNEL_HWCAP_ASIMDDP]          = "asimddp",
  74         [KERNEL_HWCAP_SHA512]           = "sha512",
  75         [KERNEL_HWCAP_SVE]              = "sve",
  76         [KERNEL_HWCAP_ASIMDFHM]         = "asimdfhm",
  77         [KERNEL_HWCAP_DIT]              = "dit",
  78         [KERNEL_HWCAP_USCAT]            = "uscat",
  79         [KERNEL_HWCAP_ILRCPC]           = "ilrcpc",
  80         [KERNEL_HWCAP_FLAGM]            = "flagm",
  81         [KERNEL_HWCAP_SSBS]             = "ssbs",
  82         [KERNEL_HWCAP_SB]               = "sb",
  83         [KERNEL_HWCAP_PACA]             = "paca",
  84         [KERNEL_HWCAP_PACG]             = "pacg",
  85         [KERNEL_HWCAP_DCPODP]           = "dcpodp",
  86         [KERNEL_HWCAP_SVE2]             = "sve2",
  87         [KERNEL_HWCAP_SVEAES]           = "sveaes",
  88         [KERNEL_HWCAP_SVEPMULL]         = "svepmull",
  89         [KERNEL_HWCAP_SVEBITPERM]       = "svebitperm",
  90         [KERNEL_HWCAP_SVESHA3]          = "svesha3",
  91         [KERNEL_HWCAP_SVESM4]           = "svesm4",
  92         [KERNEL_HWCAP_FLAGM2]           = "flagm2",
  93         [KERNEL_HWCAP_FRINT]            = "frint",
  94         [KERNEL_HWCAP_SVEI8MM]          = "svei8mm",
  95         [KERNEL_HWCAP_SVEF32MM]         = "svef32mm",
  96         [KERNEL_HWCAP_SVEF64MM]         = "svef64mm",
  97         [KERNEL_HWCAP_SVEBF16]          = "svebf16",
  98         [KERNEL_HWCAP_I8MM]             = "i8mm",
  99         [KERNEL_HWCAP_BF16]             = "bf16",
 100         [KERNEL_HWCAP_DGH]              = "dgh",
 101         [KERNEL_HWCAP_RNG]              = "rng",
 102         [KERNEL_HWCAP_BTI]              = "bti",
 103         [KERNEL_HWCAP_MTE]              = "mte",
 104         [KERNEL_HWCAP_ECV]              = "ecv",
 105         [KERNEL_HWCAP_AFP]              = "afp",
 106         [KERNEL_HWCAP_RPRES]            = "rpres",
 107         [KERNEL_HWCAP_MTE3]             = "mte3",
 108         [KERNEL_HWCAP_SME]              = "sme",
 109         [KERNEL_HWCAP_SME_I16I64]       = "smei16i64",
 110         [KERNEL_HWCAP_SME_F64F64]       = "smef64f64",
 111         [KERNEL_HWCAP_SME_I8I32]        = "smei8i32",
 112         [KERNEL_HWCAP_SME_F16F32]       = "smef16f32",
 113         [KERNEL_HWCAP_SME_B16F32]       = "smeb16f32",
 114         [KERNEL_HWCAP_SME_F32F32]       = "smef32f32",
 115         [KERNEL_HWCAP_SME_FA64]         = "smefa64",
 116         [KERNEL_HWCAP_WFXT]             = "wfxt",
 117         [KERNEL_HWCAP_EBF16]            = "ebf16",
 118         [KERNEL_HWCAP_SVE_EBF16]        = "sveebf16",
 119         [KERNEL_HWCAP_CSSC]             = "cssc",
 120         [KERNEL_HWCAP_RPRFM]            = "rprfm",
 121         [KERNEL_HWCAP_SVE2P1]           = "sve2p1",
 122         [KERNEL_HWCAP_SME2]             = "sme2",
 123         [KERNEL_HWCAP_SME2P1]           = "sme2p1",
 124         [KERNEL_HWCAP_SME_I16I32]       = "smei16i32",
 125         [KERNEL_HWCAP_SME_BI32I32]      = "smebi32i32",
 126         [KERNEL_HWCAP_SME_B16B16]       = "smeb16b16",
 127         [KERNEL_HWCAP_SME_F16F16]       = "smef16f16",
 128         [KERNEL_HWCAP_MOPS]             = "mops",
 129         [KERNEL_HWCAP_HBC]              = "hbc",
 130         [KERNEL_HWCAP_SVE_B16B16]       = "sveb16b16",
 131         [KERNEL_HWCAP_LRCPC3]           = "lrcpc3",
 132         [KERNEL_HWCAP_LSE128]           = "lse128",
 133 };
 134
 135 #ifdef CONFIG_COMPAT
 136 #define COMPAT_KERNEL_HWCAP(x)  const_ilog2(COMPAT_HWCAP_ ## x)
 137 static const char *const compat_hwcap_str[] = {
 138         [COMPAT_KERNEL_HWCAP(SWP)]      = "swp",
 139         [COMPAT_KERNEL_HWCAP(HALF)]     = "half",
 140         [COMPAT_KERNEL_HWCAP(THUMB)]    = "thumb",
 141         [COMPAT_KERNEL_HWCAP(26BIT)]    = NULL, /* Not possible on arm64 */
 142         [COMPAT_KERNEL_HWCAP(FAST_MULT)] = "fastmult",
 143         [COMPAT_KERNEL_HWCAP(FPA)]      = NULL, /* Not possible on arm64 */
 144         [COMPAT_KERNEL_HWCAP(VFP)]      = "vfp",
 145         [COMPAT_KERNEL_HWCAP(EDSP)]     = "edsp",
 146         [COMPAT_KERNEL_HWCAP(JAVA)]     = NULL, /* Not possible on arm64 */
 147         [COMPAT_KERNEL_HWCAP(IWMMXT)]   = NULL, /* Not possible on arm64 */
 148         [COMPAT_KERNEL_HWCAP(CRUNCH)]   = NULL, /* Not possible on arm64 */
 149         [COMPAT_KERNEL_HWCAP(THUMBEE)]  = NULL, /* Not possible on arm64 */
 150         [COMPAT_KERNEL_HWCAP(NEON)]     = "neon",
 151         [COMPAT_KERNEL_HWCAP(VFPv3)]    = "vfpv3",
 152         [COMPAT_KERNEL_HWCAP(VFPV3D16)] = NULL, /* Not possible on arm64 */
 153         [COMPAT_KERNEL_HWCAP(TLS)]      = "tls",
 154         [COMPAT_KERNEL_HWCAP(VFPv4)]    = "vfpv4",
 155         [COMPAT_KERNEL_HWCAP(IDIVA)]    = "idiva",
 156         [COMPAT_KERNEL_HWCAP(IDIVT)]    = "idivt",
 157         [COMPAT_KERNEL_HWCAP(VFPD32)]   = NULL, /* Not possible on arm64 */
 158         [COMPAT_KERNEL_HWCAP(LPAE)]     = "lpae",
 159         [COMPAT_KERNEL_HWCAP(EVTSTRM)]  = "evtstrm",
 160         [COMPAT_KERNEL_HWCAP(FPHP)]     = "fphp",
 161         [COMPAT_KERNEL_HWCAP(ASIMDHP)]  = "asimdhp",
 162         [COMPAT_KERNEL_HWCAP(ASIMDDP)]  = "asimddp",
 163         [COMPAT_KERNEL_HWCAP(ASIMDFHM)] = "asimdfhm",
 164         [COMPAT_KERNEL_HWCAP(ASIMDBF16)] = "asimdbf16",
 165         [COMPAT_KERNEL_HWCAP(I8MM)]     = "i8mm",
 166 };
 167
 168 #define COMPAT_KERNEL_HWCAP2(x) const_ilog2(COMPAT_HWCAP2_ ## x)
 169 static const char *const compat_hwcap2_str[] = {
 170         [COMPAT_KERNEL_HWCAP2(AES)]     = "aes",
 171         [COMPAT_KERNEL_HWCAP2(PMULL)]   = "pmull",
 172         [COMPAT_KERNEL_HWCAP2(SHA1)]    = "sha1",
 173         [COMPAT_KERNEL_HWCAP2(SHA2)]    = "sha2",
 174         [COMPAT_KERNEL_HWCAP2(CRC32)]   = "crc32",
 175         [COMPAT_KERNEL_HWCAP2(SB)]      = "sb",
 176         [COMPAT_KERNEL_HWCAP2(SSBS)]    = "ssbs",
 177 };
 178 #endif /* CONFIG_COMPAT */
 179
 180 static int c_show(struct seq_file *m, void *v)
 181 {
 182         int i, j;
 183         bool compat = personality(current->personality) == PER_LINUX32;
 184
 185         for_each_online_cpu(i) {
 186                 struct cpuinfo_arm64 *cpuinfo = &per_cpu(cpu_data, i);
 187                 u32 midr = cpuinfo->reg_midr;
 188
 189                 /*
 190                  * glibc reads /proc/cpuinfo to determine the number of
 191                  * online processors, looking for lines beginning with
 192                  * "processor".  Give glibc what it expects.
 193                  */
 194                 seq_printf(m, "processor\t: %d\n", i);
 195                 if (compat)
 196                         seq_printf(m, "model name\t: ARMv8 Processor rev %d (%s)\n",
 197                                    MIDR_REVISION(midr), COMPAT_ELF_PLATFORM);
 198
 199                 seq_printf(m, "BogoMIPS\t: %lu.%02lu\n",
 200                            loops_per_jiffy / (500000UL/HZ),
 201                            loops_per_jiffy / (5000UL/HZ) % 100);
 202
 203                 /*
 204                  * Dump out the common processor features in a single line.
 205                  * Userspace should read the hwcaps with getauxval(AT_HWCAP)
 206                  * rather than attempting to parse this, but there's a body of
 207                  * software which does already (at least for 32-bit).
 208                  */
 209                 seq_puts(m, "Features\t:");
 210                 if (compat) {
 211 #ifdef CONFIG_COMPAT
 212                         for (j = 0; j < ARRAY_SIZE(compat_hwcap_str); j++) {
 213                                 if (compat_elf_hwcap & (1 << j)) {
 214                                         /*
 215                                          * Warn once if any feature should not
 216                                          * have been present on arm64 platform.
 217                                          */
 218                                         if (WARN_ON_ONCE(!compat_hwcap_str[j]))
 219                                                 continue;
 220
 221                                         seq_printf(m, " %s", compat_hwcap_str[j]);
 222                                 }
 223                         }
 224
 225                         for (j = 0; j < ARRAY_SIZE(compat_hwcap2_str); j++)
 226                                 if (compat_elf_hwcap2 & (1 << j))
 227                                         seq_printf(m, " %s", compat_hwcap2_str[j]);
 228 #endif /* CONFIG_COMPAT */
 229                 } else {
 230                         for (j = 0; j < ARRAY_SIZE(hwcap_str); j++)
 231                                 if (cpu_have_feature(j))
 232                                         seq_printf(m, " %s", hwcap_str[j]);
 233                 }
 234                 seq_puts(m, "\n");
 235
 236                 seq_printf(m, "CPU implementer\t: 0x%02x\n",
 237                            MIDR_IMPLEMENTOR(midr));
 238                 seq_printf(m, "CPU architecture: 8\n");
 239                 seq_printf(m, "CPU variant\t: 0x%x\n", MIDR_VARIANT(midr));
 240                 seq_printf(m, "CPU part\t: 0x%03x\n", MIDR_PARTNUM(midr));
 241                 seq_printf(m, "CPU revision\t: %d\n\n", MIDR_REVISION(midr));
 242         }
 243
 244         return 0;
 245 }
 246
 247 static void *c_start(struct seq_file *m, loff_t *pos)
 248 {
 249         return *pos < 1 ? (void *)1 : NULL;
 250 }
 251
 252 static void *c_next(struct seq_file *m, void *v, loff_t *pos)
 253 {
 254         ++*pos;
 255         return NULL;
 256 }
 257
 258 static void c_stop(struct seq_file *m, void *v)
 259 {
 260 }
 261
 262 const struct seq_operations cpuinfo_op = {
 263         .start  = c_start,
 264         .next   = c_next,
 265         .stop   = c_stop,
 266         .show   = c_show
 267 };
 268
 269
 270 static struct kobj_type cpuregs_kobj_type = {
 271         .sysfs_ops = &kobj_sysfs_ops,
 272 };
 273
 274 /*
 275  * The ARM ARM uses the phrase "32-bit register" to describe a register
 276  * whose upper 32 bits are RES0 (per C5.1.1, ARM DDI 0487A.i), however
 277  * no statement is made as to whether the upper 32 bits will or will not
 278  * be made use of in future, and between ARM DDI 0487A.c and ARM DDI
 279  * 0487A.d CLIDR_EL1 was expanded from 32-bit to 64-bit.
 280  *
 281  * Thus, while both MIDR_EL1 and REVIDR_EL1 are described as 32-bit
 282  * registers, we expose them both as 64 bit values to cater for possible
 283  * future expansion without an ABI break.
 284  */
 285 #define kobj_to_cpuinfo(kobj)   container_of(kobj, struct cpuinfo_arm64, kobj)
 286 #define CPUREGS_ATTR_RO(_name, _field)                                          \
 287         static ssize_t _name##_show(struct kobject *kobj,                       \
 288                         struct kobj_attribute *attr, char *buf)                 \
 289         {                                                                       \
 290                 struct cpuinfo_arm64 *info = kobj_to_cpuinfo(kobj);             \
 291                                                                                 \
 292                 if (info->reg_midr)                                             \
 293                         return sprintf(buf, "0x%016llx\n", info->reg_##_field); \
 294                 else                                                            \
 295                         return 0;                                               \
 296         }                                                                       \
 297         static struct kobj_attribute cpuregs_attr_##_name = __ATTR_RO(_name)
 298
 299 CPUREGS_ATTR_RO(midr_el1, midr);
 300 CPUREGS_ATTR_RO(revidr_el1, revidr);
 301 CPUREGS_ATTR_RO(smidr_el1, smidr);
 302
 303 static struct attribute *cpuregs_id_attrs[] = {
 304         &cpuregs_attr_midr_el1.attr,
 305         &cpuregs_attr_revidr_el1.attr,
 306         NULL
 307 };
 308
 309 static const struct attribute_group cpuregs_attr_group = {
 310         .attrs = cpuregs_id_attrs,
 311         .name = "identification"
 312 };
 313
 314 static struct attribute *sme_cpuregs_id_attrs[] = {
 315         &cpuregs_attr_smidr_el1.attr,
 316         NULL
 317 };
 318
 319 static const struct attribute_group sme_cpuregs_attr_group = {
 320         .attrs = sme_cpuregs_id_attrs,
 321         .name = "identification"
 322 };
 323
 324 static int cpuid_cpu_online(unsigned int cpu)
 325 {
 326         int rc;
 327         struct device *dev;
 328         struct cpuinfo_arm64 *info = &per_cpu(cpu_data, cpu);
 329
 330         dev = get_cpu_device(cpu);
 331         if (!dev) {
 332                 rc = -ENODEV;
 333                 goto out;
 334         }
 335         rc = kobject_add(&info->kobj, &dev->kobj, "regs");
 336         if (rc)
 337                 goto out;
 338         rc = sysfs_create_group(&info->kobj, &cpuregs_attr_group);
 339         if (rc)
 340                 kobject_del(&info->kobj);
 341         if (system_supports_sme())
 342                 rc = sysfs_merge_group(&info->kobj, &sme_cpuregs_attr_group);
 343 out:
 344         return rc;
 345 }
 346
 347 static int cpuid_cpu_offline(unsigned int cpu)
 348 {
 349         struct device *dev;
 350         struct cpuinfo_arm64 *info = &per_cpu(cpu_data, cpu);
 351
 352         dev = get_cpu_device(cpu);
 353         if (!dev)
 354                 return -ENODEV;
 355         if (info->kobj.parent) {
 356                 sysfs_remove_group(&info->kobj, &cpuregs_attr_group);
 357                 kobject_del(&info->kobj);
 358         }
 359
 360         return 0;
 361 }
 362
 363 static int __init cpuinfo_regs_init(void)
 364 {
 365         int cpu, ret;
 366
 367         for_each_possible_cpu(cpu) {
 368                 struct cpuinfo_arm64 *info = &per_cpu(cpu_data, cpu);
 369
 370                 kobject_init(&info->kobj, &cpuregs_kobj_type);
 371         }
 372
 373         ret = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "arm64/cpuinfo:online",
 374                                 cpuid_cpu_online, cpuid_cpu_offline);
 375         if (ret < 0) {
 376                 pr_err("cpuinfo: failed to register hotplug callbacks.\n");
 377                 return ret;
 378         }
 379         return 0;
 380 }
 381 device_initcall(cpuinfo_regs_init);
 382
 383 static void cpuinfo_detect_icache_policy(struct cpuinfo_arm64 *info)
 384 {
 385         unsigned int cpu = smp_processor_id();
 386         u32 l1ip = CTR_L1IP(info->reg_ctr);
 387
 388         switch (l1ip) {
 389         case CTR_EL0_L1Ip_PIPT:
 390                 break;
 391         case CTR_EL0_L1Ip_VPIPT:
 392                 set_bit(ICACHEF_VPIPT, &__icache_flags);
 393                 break;
 394         case CTR_EL0_L1Ip_VIPT:
 395         default:
 396                 /* Assume aliasing */
 397                 set_bit(ICACHEF_ALIASING, &__icache_flags);
 398                 break;
 399         }
 400
 401         pr_info("Detected %s I-cache on CPU%d\n", icache_policy_str(l1ip), cpu);
 402 }
 403
 404 static void __cpuinfo_store_cpu_32bit(struct cpuinfo_32bit *info)
 405 {
 406         info->reg_id_dfr0 = read_cpuid(ID_DFR0_EL1);
 407         info->reg_id_dfr1 = read_cpuid(ID_DFR1_EL1);
 408         info->reg_id_isar0 = read_cpuid(ID_ISAR0_EL1);
 409         info->reg_id_isar1 = read_cpuid(ID_ISAR1_EL1);
 410         info->reg_id_isar2 = read_cpuid(ID_ISAR2_EL1);
 411         info->reg_id_isar3 = read_cpuid(ID_ISAR3_EL1);
 412         info->reg_id_isar4 = read_cpuid(ID_ISAR4_EL1);
 413         info->reg_id_isar5 = read_cpuid(ID_ISAR5_EL1);
 414         info->reg_id_isar6 = read_cpuid(ID_ISAR6_EL1);
 415         info->reg_id_mmfr0 = read_cpuid(ID_MMFR0_EL1);
 416         info->reg_id_mmfr1 = read_cpuid(ID_MMFR1_EL1);
 417         info->reg_id_mmfr2 = read_cpuid(ID_MMFR2_EL1);
 418         info->reg_id_mmfr3 = read_cpuid(ID_MMFR3_EL1);
 419         info->reg_id_mmfr4 = read_cpuid(ID_MMFR4_EL1);
 420         info->reg_id_mmfr5 = read_cpuid(ID_MMFR5_EL1);
 421         info->reg_id_pfr0 = read_cpuid(ID_PFR0_EL1);
 422         info->reg_id_pfr1 = read_cpuid(ID_PFR1_EL1);
 423         info->reg_id_pfr2 = read_cpuid(ID_PFR2_EL1);
 424
 425         info->reg_mvfr0 = read_cpuid(MVFR0_EL1);
 426         info->reg_mvfr1 = read_cpuid(MVFR1_EL1);
 427         info->reg_mvfr2 = read_cpuid(MVFR2_EL1);
 428 }
 429
 430 static void __cpuinfo_store_cpu(struct cpuinfo_arm64 *info)
 431 {
 432         info->reg_cntfrq = arch_timer_get_cntfrq();
 433         /*
 434          * Use the effective value of the CTR_EL0 than the raw value
 435          * exposed by the CPU. CTR_EL0.IDC field value must be interpreted
 436          * with the CLIDR_EL1 fields to avoid triggering false warnings
 437          * when there is a mismatch across the CPUs. Keep track of the
 438          * effective value of the CTR_EL0 in our internal records for
 439          * accurate sanity check and feature enablement.
 440          */
 441         info->reg_ctr = read_cpuid_effective_cachetype();
 442         info->reg_dczid = read_cpuid(DCZID_EL0);
 443         info->reg_midr = read_cpuid_id();
 444         info->reg_revidr = read_cpuid(REVIDR_EL1);
 445
 446         info->reg_id_aa64dfr0 = read_cpuid(ID_AA64DFR0_EL1);
 447         info->reg_id_aa64dfr1 = read_cpuid(ID_AA64DFR1_EL1);
 448         info->reg_id_aa64isar0 = read_cpuid(ID_AA64ISAR0_EL1);
 449         info->reg_id_aa64isar1 = read_cpuid(ID_AA64ISAR1_EL1);
 450         info->reg_id_aa64isar2 = read_cpuid(ID_AA64ISAR2_EL1);
 451         info->reg_id_aa64mmfr0 = read_cpuid(ID_AA64MMFR0_EL1);
 452         info->reg_id_aa64mmfr1 = read_cpuid(ID_AA64MMFR1_EL1);
 453         info->reg_id_aa64mmfr2 = read_cpuid(ID_AA64MMFR2_EL1);
 454         info->reg_id_aa64mmfr3 = read_cpuid(ID_AA64MMFR3_EL1);
 455         info->reg_id_aa64pfr0 = read_cpuid(ID_AA64PFR0_EL1);
 456         info->reg_id_aa64pfr1 = read_cpuid(ID_AA64PFR1_EL1);
 457         info->reg_id_aa64zfr0 = read_cpuid(ID_AA64ZFR0_EL1);
 458         info->reg_id_aa64smfr0 = read_cpuid(ID_AA64SMFR0_EL1);
 459
 460         if (id_aa64pfr1_mte(info->reg_id_aa64pfr1))
 461                 info->reg_gmid = read_cpuid(GMID_EL1);
 462
 463         if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0))
 464                 __cpuinfo_store_cpu_32bit(&info->aarch32);
 465
 466         cpuinfo_detect_icache_policy(info);
 467 }
 468
 469 void cpuinfo_store_cpu(void)
 470 {
 471         struct cpuinfo_arm64 *info = this_cpu_ptr(&cpu_data);
 472         __cpuinfo_store_cpu(info);
 473         update_cpu_features(smp_processor_id(), info, &boot_cpu_data);
 474 }
 475
 476 void __init cpuinfo_store_boot_cpu(void)
 477 {
 478         struct cpuinfo_arm64 *info = &per_cpu(cpu_data, 0);
 479         __cpuinfo_store_cpu(info);
 480
 481         boot_cpu_data = *info;
 482         init_cpu_features(&boot_cpu_data);
 483 }