1 // SPDX-License-Identifier: GPL-2.0-only
3 * Contains CPU feature definitions
5 * Copyright (C) 2015 ARM Ltd.
7 * A note for the weary kernel hacker: the code here is confusing and hard to
8 * follow! That's partly because it's solving a nasty problem, but also because
9 * there's a little bit of over-abstraction that tends to obscure what's going
10 * on behind a maze of helper functions and macros.
12 * The basic problem is that hardware folks have started gluing together CPUs
13 * with distinct architectural features; in some cases even creating SoCs where
14 * user-visible instructions are available only on a subset of the available
15 * cores. We try to address this by snapshotting the feature registers of the
16 * boot CPU and comparing these with the feature registers of each secondary
17 * CPU when bringing them up. If there is a mismatch, then we update the
18 * snapshot state to indicate the lowest-common denominator of the feature,
19 * known as the "safe" value. This snapshot state can be queried to view the
20 * "sanitised" value of a feature register.
22 * The sanitised register values are used to decide which capabilities we
23 * have in the system. These may be in the form of traditional "hwcaps"
24 * advertised to userspace or internal "cpucaps" which are used to configure
25 * things like alternative patching and static keys. While a feature mismatch
26 * may result in a TAINT_CPU_OUT_OF_SPEC kernel taint, a capability mismatch
27 * may prevent a CPU from being onlined at all.
29 * Some implementation details worth remembering:
31 * - Mismatched features are *always* sanitised to a "safe" value, which
32 * usually indicates that the feature is not supported.
34 * - A mismatched feature marked with FTR_STRICT will cause a "SANITY CHECK"
35 * warning when onlining an offending CPU and the kernel will be tainted
36 * with TAINT_CPU_OUT_OF_SPEC.
38 * - Features marked as FTR_VISIBLE have their sanitised value visible to
39 * userspace. FTR_VISIBLE features in registers that are only visible
40 * to EL0 by trapping *must* have a corresponding HWCAP so that late
41 * onlining of CPUs cannot lead to features disappearing at runtime.
43 * - A "feature" is typically a 4-bit register field. A "capability" is the
44 * high-level description derived from the sanitised field value.
46 * - Read the Arm ARM (DDI 0487F.a) section D13.1.3 ("Principles of the ID
47 * scheme for fields in ID registers") to understand when feature fields
48 * may be signed or unsigned (FTR_SIGNED and FTR_UNSIGNED accordingly).
50 * - KVM exposes its own view of the feature registers to guest operating
51 * systems regardless of FTR_VISIBLE. This is typically driven from the
52 * sanitised register values to allow virtual CPUs to be migrated between
53 * arbitrary physical CPUs, but some features not present on the host are
54 * also advertised and emulated. Look at sys_reg_descs[] for the gory
57 * - If the arm64_ftr_bits[] for a register has a missing field, then this
58 * field is treated as STRICT RES0, including for read_sanitised_ftr_reg().
59 * This is stronger than FTR_HIDDEN and can be used to hide features from
63 #define pr_fmt(fmt) "CPU features: " fmt
65 #include <linux/bsearch.h>
66 #include <linux/cpumask.h>
67 #include <linux/crash_dump.h>
68 #include <linux/sort.h>
69 #include <linux/stop_machine.h>
70 #include <linux/sysfs.h>
71 #include <linux/types.h>
72 #include <linux/minmax.h>
74 #include <linux/cpu.h>
75 #include <linux/kasan.h>
76 #include <linux/percpu.h>
79 #include <asm/cpufeature.h>
80 #include <asm/cpu_ops.h>
81 #include <asm/fpsimd.h>
82 #include <asm/hwcap.h>
84 #include <asm/kvm_host.h>
85 #include <asm/mmu_context.h>
87 #include <asm/processor.h>
89 #include <asm/sysreg.h>
90 #include <asm/traps.h>
91 #include <asm/vectors.h>
94 /* Kernel representation of AT_HWCAP and AT_HWCAP2 */
95 static unsigned long elf_hwcap __read_mostly;
98 #define COMPAT_ELF_HWCAP_DEFAULT \
99 (COMPAT_HWCAP_HALF|COMPAT_HWCAP_THUMB|\
100 COMPAT_HWCAP_FAST_MULT|COMPAT_HWCAP_EDSP|\
101 COMPAT_HWCAP_TLS|COMPAT_HWCAP_IDIV|\
103 unsigned int compat_elf_hwcap __read_mostly = COMPAT_ELF_HWCAP_DEFAULT;
104 unsigned int compat_elf_hwcap2 __read_mostly;
107 DECLARE_BITMAP(cpu_hwcaps, ARM64_NCAPS);
108 EXPORT_SYMBOL(cpu_hwcaps);
109 static struct arm64_cpu_capabilities const __ro_after_init *cpu_hwcaps_ptrs[ARM64_NCAPS];
111 /* Need also bit for ARM64_CB_PATCH */
112 DECLARE_BITMAP(boot_capabilities, ARM64_NPATCHABLE);
114 bool arm64_use_ng_mappings = false;
115 EXPORT_SYMBOL(arm64_use_ng_mappings);
117 DEFINE_PER_CPU_READ_MOSTLY(const char *, this_cpu_vector) = vectors;
120 * Permit PER_LINUX32 and execve() of 32-bit binaries even if not all CPUs
123 static bool __read_mostly allow_mismatched_32bit_el0;
126 * Static branch enabled only if allow_mismatched_32bit_el0 is set and we have
127 * seen at least one CPU capable of 32-bit EL0.
129 DEFINE_STATIC_KEY_FALSE(arm64_mismatched_32bit_el0);
132 * Mask of CPUs supporting 32-bit EL0.
133 * Only valid if arm64_mismatched_32bit_el0 is enabled.
135 static cpumask_var_t cpu_32bit_el0_mask __cpumask_var_read_mostly;
138 * Flag to indicate if we have computed the system wide
139 * capabilities based on the boot time active CPUs. This
140 * will be used to determine if a new booting CPU should
141 * go through the verification process to make sure that it
142 * supports the system capabilities, without using a hotplug
143 * notifier. This is also used to decide if we could use
144 * the fast path for checking constant CPU caps.
146 DEFINE_STATIC_KEY_FALSE(arm64_const_caps_ready);
147 EXPORT_SYMBOL(arm64_const_caps_ready);
148 static inline void finalize_system_capabilities(void)
150 static_branch_enable(&arm64_const_caps_ready);
153 void dump_cpu_features(void)
155 /* file-wide pr_fmt adds "CPU features: " prefix */
156 pr_emerg("0x%*pb\n", ARM64_NCAPS, &cpu_hwcaps);
159 DEFINE_STATIC_KEY_ARRAY_FALSE(cpu_hwcap_keys, ARM64_NCAPS);
160 EXPORT_SYMBOL(cpu_hwcap_keys);
162 #define __ARM64_FTR_BITS(SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
165 .visible = VISIBLE, \
170 .safe_val = SAFE_VAL, \
173 /* Define a feature with unsigned values */
174 #define ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
175 __ARM64_FTR_BITS(FTR_UNSIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL)
177 /* Define a feature with a signed value */
178 #define S_ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
179 __ARM64_FTR_BITS(FTR_SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL)
181 #define ARM64_FTR_END \
186 static void cpu_enable_cnp(struct arm64_cpu_capabilities const *cap);
188 static bool __system_matches_cap(unsigned int n);
191 * NOTE: Any changes to the visibility of features should be kept in
192 * sync with the documentation of the CPU feature register ABI.
194 static const struct arm64_ftr_bits ftr_id_aa64isar0[] = {
195 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_RNDR_SHIFT, 4, 0),
196 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_TLB_SHIFT, 4, 0),
197 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_TS_SHIFT, 4, 0),
198 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_FHM_SHIFT, 4, 0),
199 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_DP_SHIFT, 4, 0),
200 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SM4_SHIFT, 4, 0),
201 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SM3_SHIFT, 4, 0),
202 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA3_SHIFT, 4, 0),
203 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_RDM_SHIFT, 4, 0),
204 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_ATOMICS_SHIFT, 4, 0),
205 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_CRC32_SHIFT, 4, 0),
206 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA2_SHIFT, 4, 0),
207 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA1_SHIFT, 4, 0),
208 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_AES_SHIFT, 4, 0),
212 static const struct arm64_ftr_bits ftr_id_aa64isar1[] = {
213 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_I8MM_SHIFT, 4, 0),
214 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_DGH_SHIFT, 4, 0),
215 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_BF16_SHIFT, 4, 0),
216 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_SPECRES_SHIFT, 4, 0),
217 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_SB_SHIFT, 4, 0),
218 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_FRINTTS_SHIFT, 4, 0),
219 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
220 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_GPI_SHIFT, 4, 0),
221 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
222 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_GPA_SHIFT, 4, 0),
223 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_LRCPC_SHIFT, 4, 0),
224 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_FCMA_SHIFT, 4, 0),
225 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_JSCVT_SHIFT, 4, 0),
226 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
227 FTR_STRICT, FTR_EXACT, ID_AA64ISAR1_API_SHIFT, 4, 0),
228 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
229 FTR_STRICT, FTR_EXACT, ID_AA64ISAR1_APA_SHIFT, 4, 0),
230 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_DPB_SHIFT, 4, 0),
234 static const struct arm64_ftr_bits ftr_id_aa64isar2[] = {
235 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_AA64ISAR2_CLEARBHB_SHIFT, 4, 0),
236 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_RPRES_SHIFT, 4, 0),
240 static const struct arm64_ftr_bits ftr_id_aa64pfr0[] = {
241 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_CSV3_SHIFT, 4, 0),
242 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_CSV2_SHIFT, 4, 0),
243 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_DIT_SHIFT, 4, 0),
244 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_AMU_SHIFT, 4, 0),
245 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_MPAM_SHIFT, 4, 0),
246 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_SEL2_SHIFT, 4, 0),
247 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
248 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_SVE_SHIFT, 4, 0),
249 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_RAS_SHIFT, 4, 0),
250 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_GIC_SHIFT, 4, 0),
251 S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_ASIMD_SHIFT, 4, ID_AA64PFR0_ASIMD_NI),
252 S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_FP_SHIFT, 4, ID_AA64PFR0_FP_NI),
253 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL3_SHIFT, 4, 0),
254 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL2_SHIFT, 4, 0),
255 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_SHIFT, 4, ID_AA64PFR0_ELx_64BIT_ONLY),
256 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL0_SHIFT, 4, ID_AA64PFR0_ELx_64BIT_ONLY),
260 static const struct arm64_ftr_bits ftr_id_aa64pfr1[] = {
261 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_MPAMFRAC_SHIFT, 4, 0),
262 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_RASFRAC_SHIFT, 4, 0),
263 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_MTE),
264 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_MTE_SHIFT, 4, ID_AA64PFR1_MTE_NI),
265 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR1_SSBS_SHIFT, 4, ID_AA64PFR1_SSBS_PSTATE_NI),
266 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_BTI),
267 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_BT_SHIFT, 4, 0),
271 static const struct arm64_ftr_bits ftr_id_aa64zfr0[] = {
272 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
273 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_F64MM_SHIFT, 4, 0),
274 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
275 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_F32MM_SHIFT, 4, 0),
276 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
277 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_I8MM_SHIFT, 4, 0),
278 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
279 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_SM4_SHIFT, 4, 0),
280 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
281 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_SHA3_SHIFT, 4, 0),
282 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
283 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_BF16_SHIFT, 4, 0),
284 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
285 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_BITPERM_SHIFT, 4, 0),
286 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
287 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_AES_SHIFT, 4, 0),
288 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
289 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_SVEVER_SHIFT, 4, 0),
293 static const struct arm64_ftr_bits ftr_id_aa64mmfr0[] = {
294 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_ECV_SHIFT, 4, 0),
295 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_FGT_SHIFT, 4, 0),
296 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EXS_SHIFT, 4, 0),
298 * Page size not being supported at Stage-2 is not fatal. You
299 * just give up KVM if PAGE_SIZE isn't supported there. Go fix
300 * your favourite nesting hypervisor.
302 * There is a small corner case where the hypervisor explicitly
303 * advertises a given granule size at Stage-2 (value 2) on some
304 * vCPUs, and uses the fallback to Stage-1 (value 0) for other
305 * vCPUs. Although this is not forbidden by the architecture, it
306 * indicates that the hypervisor is being silly (or buggy).
308 * We make no effort to cope with this and pretend that if these
309 * fields are inconsistent across vCPUs, then it isn't worth
310 * trying to bring KVM up.
312 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_TGRAN4_2_SHIFT, 4, 1),
313 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_TGRAN64_2_SHIFT, 4, 1),
314 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_TGRAN16_2_SHIFT, 4, 1),
316 * We already refuse to boot CPUs that don't support our configured
317 * page size, so we can only detect mismatches for a page size other
318 * than the one we're currently using. Unfortunately, SoCs like this
319 * exist in the wild so, even though we don't like it, we'll have to go
320 * along with it and treat them as non-strict.
322 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN4_SHIFT, 4, ID_AA64MMFR0_TGRAN4_NI),
323 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN64_SHIFT, 4, ID_AA64MMFR0_TGRAN64_NI),
324 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN16_SHIFT, 4, ID_AA64MMFR0_TGRAN16_NI),
326 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_BIGENDEL0_SHIFT, 4, 0),
327 /* Linux shouldn't care about secure memory */
328 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_SNSMEM_SHIFT, 4, 0),
329 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_BIGENDEL_SHIFT, 4, 0),
330 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_ASID_SHIFT, 4, 0),
332 * Differing PARange is fine as long as all peripherals and memory are mapped
333 * within the minimum PARange of all CPUs
335 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_PARANGE_SHIFT, 4, 0),
339 static const struct arm64_ftr_bits ftr_id_aa64mmfr1[] = {
340 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_AFP_SHIFT, 4, 0),
341 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_ETS_SHIFT, 4, 0),
342 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_TWED_SHIFT, 4, 0),
343 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_XNX_SHIFT, 4, 0),
344 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_AA64MMFR1_SPECSEI_SHIFT, 4, 0),
345 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_PAN_SHIFT, 4, 0),
346 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_LOR_SHIFT, 4, 0),
347 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_HPD_SHIFT, 4, 0),
348 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_VHE_SHIFT, 4, 0),
349 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_VMIDBITS_SHIFT, 4, 0),
350 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_HADBS_SHIFT, 4, 0),
354 static const struct arm64_ftr_bits ftr_id_aa64mmfr2[] = {
355 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_E0PD_SHIFT, 4, 0),
356 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EVT_SHIFT, 4, 0),
357 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_BBM_SHIFT, 4, 0),
358 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_TTL_SHIFT, 4, 0),
359 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_FWB_SHIFT, 4, 0),
360 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_IDS_SHIFT, 4, 0),
361 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_AT_SHIFT, 4, 0),
362 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_ST_SHIFT, 4, 0),
363 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_NV_SHIFT, 4, 0),
364 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_CCIDX_SHIFT, 4, 0),
365 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_LVA_SHIFT, 4, 0),
366 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_IESB_SHIFT, 4, 0),
367 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_LSM_SHIFT, 4, 0),
368 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_UAO_SHIFT, 4, 0),
369 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_CNP_SHIFT, 4, 0),
373 static const struct arm64_ftr_bits ftr_ctr[] = {
374 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, 31, 1, 1), /* RES1 */
375 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_DIC_SHIFT, 1, 1),
376 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_IDC_SHIFT, 1, 1),
377 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, CTR_CWG_SHIFT, 4, 0),
378 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, CTR_ERG_SHIFT, 4, 0),
379 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_DMINLINE_SHIFT, 4, 1),
381 * Linux can handle differing I-cache policies. Userspace JITs will
382 * make use of *minLine.
383 * If we have differing I-cache policies, report it as the weakest - VIPT.
385 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_EXACT, CTR_L1IP_SHIFT, 2, ICACHE_POLICY_VIPT), /* L1Ip */
386 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_IMINLINE_SHIFT, 4, 0),
390 static struct arm64_ftr_override __ro_after_init no_override = { };
392 struct arm64_ftr_reg arm64_ftr_reg_ctrel0 = {
393 .name = "SYS_CTR_EL0",
395 .override = &no_override,
398 static const struct arm64_ftr_bits ftr_id_mmfr0[] = {
399 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_INNERSHR_SHIFT, 4, 0xf),
400 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_FCSE_SHIFT, 4, 0),
401 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_MMFR0_AUXREG_SHIFT, 4, 0),
402 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_TCM_SHIFT, 4, 0),
403 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_SHARELVL_SHIFT, 4, 0),
404 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_OUTERSHR_SHIFT, 4, 0xf),
405 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_PMSA_SHIFT, 4, 0),
406 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_VMSA_SHIFT, 4, 0),
410 static const struct arm64_ftr_bits ftr_id_aa64dfr0[] = {
411 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_DOUBLELOCK_SHIFT, 4, 0),
412 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64DFR0_PMSVER_SHIFT, 4, 0),
413 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_CTX_CMPS_SHIFT, 4, 0),
414 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_WRPS_SHIFT, 4, 0),
415 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_BRPS_SHIFT, 4, 0),
417 * We can instantiate multiple PMU instances with different levels
420 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64DFR0_PMUVER_SHIFT, 4, 0),
421 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64DFR0_DEBUGVER_SHIFT, 4, 0x6),
425 static const struct arm64_ftr_bits ftr_mvfr2[] = {
426 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR2_FPMISC_SHIFT, 4, 0),
427 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR2_SIMDMISC_SHIFT, 4, 0),
431 static const struct arm64_ftr_bits ftr_dczid[] = {
432 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, DCZID_DZP_SHIFT, 1, 1),
433 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, DCZID_BS_SHIFT, 4, 0),
437 static const struct arm64_ftr_bits ftr_gmid[] = {
438 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, SYS_GMID_EL1_BS_SHIFT, 4, 0),
442 static const struct arm64_ftr_bits ftr_id_isar0[] = {
443 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_DIVIDE_SHIFT, 4, 0),
444 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_DEBUG_SHIFT, 4, 0),
445 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_COPROC_SHIFT, 4, 0),
446 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_CMPBRANCH_SHIFT, 4, 0),
447 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_BITFIELD_SHIFT, 4, 0),
448 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_BITCOUNT_SHIFT, 4, 0),
449 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_SWAP_SHIFT, 4, 0),
453 static const struct arm64_ftr_bits ftr_id_isar5[] = {
454 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_RDM_SHIFT, 4, 0),
455 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_CRC32_SHIFT, 4, 0),
456 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SHA2_SHIFT, 4, 0),
457 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SHA1_SHIFT, 4, 0),
458 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_AES_SHIFT, 4, 0),
459 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SEVL_SHIFT, 4, 0),
463 static const struct arm64_ftr_bits ftr_id_mmfr4[] = {
464 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EVT_SHIFT, 4, 0),
465 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_CCIDX_SHIFT, 4, 0),
466 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_LSM_SHIFT, 4, 0),
467 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_HPDS_SHIFT, 4, 0),
468 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_CNP_SHIFT, 4, 0),
469 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_XNX_SHIFT, 4, 0),
470 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_AC2_SHIFT, 4, 0),
473 * SpecSEI = 1 indicates that the PE might generate an SError on an
474 * external abort on speculative read. It is safe to assume that an
475 * SError might be generated than it will not be. Hence it has been
476 * classified as FTR_HIGHER_SAFE.
478 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_MMFR4_SPECSEI_SHIFT, 4, 0),
482 static const struct arm64_ftr_bits ftr_id_isar4[] = {
483 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_SWP_FRAC_SHIFT, 4, 0),
484 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_PSR_M_SHIFT, 4, 0),
485 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_SYNCH_PRIM_FRAC_SHIFT, 4, 0),
486 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_BARRIER_SHIFT, 4, 0),
487 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_SMC_SHIFT, 4, 0),
488 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_WRITEBACK_SHIFT, 4, 0),
489 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_WITHSHIFTS_SHIFT, 4, 0),
490 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_UNPRIV_SHIFT, 4, 0),
494 static const struct arm64_ftr_bits ftr_id_mmfr5[] = {
495 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR5_ETS_SHIFT, 4, 0),
499 static const struct arm64_ftr_bits ftr_id_isar6[] = {
500 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_I8MM_SHIFT, 4, 0),
501 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_BF16_SHIFT, 4, 0),
502 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_SPECRES_SHIFT, 4, 0),
503 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_SB_SHIFT, 4, 0),
504 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_FHM_SHIFT, 4, 0),
505 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_DP_SHIFT, 4, 0),
506 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_JSCVT_SHIFT, 4, 0),
510 static const struct arm64_ftr_bits ftr_id_pfr0[] = {
511 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_DIT_SHIFT, 4, 0),
512 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR0_CSV2_SHIFT, 4, 0),
513 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_STATE3_SHIFT, 4, 0),
514 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_STATE2_SHIFT, 4, 0),
515 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_STATE1_SHIFT, 4, 0),
516 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_STATE0_SHIFT, 4, 0),
520 static const struct arm64_ftr_bits ftr_id_pfr1[] = {
521 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_GIC_SHIFT, 4, 0),
522 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_VIRT_FRAC_SHIFT, 4, 0),
523 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_SEC_FRAC_SHIFT, 4, 0),
524 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_GENTIMER_SHIFT, 4, 0),
525 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_VIRTUALIZATION_SHIFT, 4, 0),
526 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_MPROGMOD_SHIFT, 4, 0),
527 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_SECURITY_SHIFT, 4, 0),
528 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_PROGMOD_SHIFT, 4, 0),
532 static const struct arm64_ftr_bits ftr_id_pfr2[] = {
533 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR2_SSBS_SHIFT, 4, 0),
534 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR2_CSV3_SHIFT, 4, 0),
538 static const struct arm64_ftr_bits ftr_id_dfr0[] = {
539 /* [31:28] TraceFilt */
540 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_DFR0_PERFMON_SHIFT, 4, 0),
541 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_MPROFDBG_SHIFT, 4, 0),
542 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_MMAPTRC_SHIFT, 4, 0),
543 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_COPTRC_SHIFT, 4, 0),
544 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_MMAPDBG_SHIFT, 4, 0),
545 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_COPSDBG_SHIFT, 4, 0),
546 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_COPDBG_SHIFT, 4, 0),
550 static const struct arm64_ftr_bits ftr_id_dfr1[] = {
551 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR1_MTPMU_SHIFT, 4, 0),
555 static const struct arm64_ftr_bits ftr_zcr[] = {
556 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE,
557 ZCR_ELx_LEN_SHIFT, ZCR_ELx_LEN_SIZE, 0), /* LEN */
562 * Common ftr bits for a 32bit register with all hidden, strict
563 * attributes, with 4bit feature fields and a default safe value of
564 * 0. Covers the following 32bit registers:
565 * id_isar[1-4], id_mmfr[1-3], id_pfr1, mvfr[0-1]
567 static const struct arm64_ftr_bits ftr_generic_32bits[] = {
568 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0),
569 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0),
570 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0),
571 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0),
572 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0),
573 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0),
574 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),
575 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),
579 /* Table for a single 32bit feature value */
580 static const struct arm64_ftr_bits ftr_single32[] = {
581 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 0, 32, 0),
585 static const struct arm64_ftr_bits ftr_raz[] = {
589 #define __ARM64_FTR_REG_OVERRIDE(id_str, id, table, ovr) { \
591 .reg = &(struct arm64_ftr_reg){ \
594 .ftr_bits = &((table)[0]), \
597 #define ARM64_FTR_REG_OVERRIDE(id, table, ovr) \
598 __ARM64_FTR_REG_OVERRIDE(#id, id, table, ovr)
600 #define ARM64_FTR_REG(id, table) \
601 __ARM64_FTR_REG_OVERRIDE(#id, id, table, &no_override)
603 struct arm64_ftr_override __ro_after_init id_aa64mmfr1_override;
604 struct arm64_ftr_override __ro_after_init id_aa64pfr1_override;
605 struct arm64_ftr_override __ro_after_init id_aa64isar1_override;
607 static const struct __ftr_reg_entry {
609 struct arm64_ftr_reg *reg;
610 } arm64_ftr_regs[] = {
612 /* Op1 = 0, CRn = 0, CRm = 1 */
613 ARM64_FTR_REG(SYS_ID_PFR0_EL1, ftr_id_pfr0),
614 ARM64_FTR_REG(SYS_ID_PFR1_EL1, ftr_id_pfr1),
615 ARM64_FTR_REG(SYS_ID_DFR0_EL1, ftr_id_dfr0),
616 ARM64_FTR_REG(SYS_ID_MMFR0_EL1, ftr_id_mmfr0),
617 ARM64_FTR_REG(SYS_ID_MMFR1_EL1, ftr_generic_32bits),
618 ARM64_FTR_REG(SYS_ID_MMFR2_EL1, ftr_generic_32bits),
619 ARM64_FTR_REG(SYS_ID_MMFR3_EL1, ftr_generic_32bits),
621 /* Op1 = 0, CRn = 0, CRm = 2 */
622 ARM64_FTR_REG(SYS_ID_ISAR0_EL1, ftr_id_isar0),
623 ARM64_FTR_REG(SYS_ID_ISAR1_EL1, ftr_generic_32bits),
624 ARM64_FTR_REG(SYS_ID_ISAR2_EL1, ftr_generic_32bits),
625 ARM64_FTR_REG(SYS_ID_ISAR3_EL1, ftr_generic_32bits),
626 ARM64_FTR_REG(SYS_ID_ISAR4_EL1, ftr_id_isar4),
627 ARM64_FTR_REG(SYS_ID_ISAR5_EL1, ftr_id_isar5),
628 ARM64_FTR_REG(SYS_ID_MMFR4_EL1, ftr_id_mmfr4),
629 ARM64_FTR_REG(SYS_ID_ISAR6_EL1, ftr_id_isar6),
631 /* Op1 = 0, CRn = 0, CRm = 3 */
632 ARM64_FTR_REG(SYS_MVFR0_EL1, ftr_generic_32bits),
633 ARM64_FTR_REG(SYS_MVFR1_EL1, ftr_generic_32bits),
634 ARM64_FTR_REG(SYS_MVFR2_EL1, ftr_mvfr2),
635 ARM64_FTR_REG(SYS_ID_PFR2_EL1, ftr_id_pfr2),
636 ARM64_FTR_REG(SYS_ID_DFR1_EL1, ftr_id_dfr1),
637 ARM64_FTR_REG(SYS_ID_MMFR5_EL1, ftr_id_mmfr5),
639 /* Op1 = 0, CRn = 0, CRm = 4 */
640 ARM64_FTR_REG(SYS_ID_AA64PFR0_EL1, ftr_id_aa64pfr0),
641 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64PFR1_EL1, ftr_id_aa64pfr1,
642 &id_aa64pfr1_override),
643 ARM64_FTR_REG(SYS_ID_AA64ZFR0_EL1, ftr_id_aa64zfr0),
645 /* Op1 = 0, CRn = 0, CRm = 5 */
646 ARM64_FTR_REG(SYS_ID_AA64DFR0_EL1, ftr_id_aa64dfr0),
647 ARM64_FTR_REG(SYS_ID_AA64DFR1_EL1, ftr_raz),
649 /* Op1 = 0, CRn = 0, CRm = 6 */
650 ARM64_FTR_REG(SYS_ID_AA64ISAR0_EL1, ftr_id_aa64isar0),
651 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64ISAR1_EL1, ftr_id_aa64isar1,
652 &id_aa64isar1_override),
653 ARM64_FTR_REG(SYS_ID_AA64ISAR2_EL1, ftr_id_aa64isar2),
655 /* Op1 = 0, CRn = 0, CRm = 7 */
656 ARM64_FTR_REG(SYS_ID_AA64MMFR0_EL1, ftr_id_aa64mmfr0),
657 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64MMFR1_EL1, ftr_id_aa64mmfr1,
658 &id_aa64mmfr1_override),
659 ARM64_FTR_REG(SYS_ID_AA64MMFR2_EL1, ftr_id_aa64mmfr2),
661 /* Op1 = 0, CRn = 1, CRm = 2 */
662 ARM64_FTR_REG(SYS_ZCR_EL1, ftr_zcr),
664 /* Op1 = 1, CRn = 0, CRm = 0 */
665 ARM64_FTR_REG(SYS_GMID_EL1, ftr_gmid),
667 /* Op1 = 3, CRn = 0, CRm = 0 */
668 { SYS_CTR_EL0, &arm64_ftr_reg_ctrel0 },
669 ARM64_FTR_REG(SYS_DCZID_EL0, ftr_dczid),
671 /* Op1 = 3, CRn = 14, CRm = 0 */
672 ARM64_FTR_REG(SYS_CNTFRQ_EL0, ftr_single32),
675 static int search_cmp_ftr_reg(const void *id, const void *regp)
677 return (int)(unsigned long)id - (int)((const struct __ftr_reg_entry *)regp)->sys_id;
681 * get_arm64_ftr_reg_nowarn - Looks up a feature register entry using
682 * its sys_reg() encoding. With the array arm64_ftr_regs sorted in the
683 * ascending order of sys_id, we use binary search to find a matching
686 * returns - Upon success, matching ftr_reg entry for id.
687 * - NULL on failure. It is upto the caller to decide
688 * the impact of a failure.
690 static struct arm64_ftr_reg *get_arm64_ftr_reg_nowarn(u32 sys_id)
692 const struct __ftr_reg_entry *ret;
694 ret = bsearch((const void *)(unsigned long)sys_id,
696 ARRAY_SIZE(arm64_ftr_regs),
697 sizeof(arm64_ftr_regs[0]),
705 * get_arm64_ftr_reg - Looks up a feature register entry using
706 * its sys_reg() encoding. This calls get_arm64_ftr_reg_nowarn().
708 * returns - Upon success, matching ftr_reg entry for id.
709 * - NULL on failure but with an WARN_ON().
711 static struct arm64_ftr_reg *get_arm64_ftr_reg(u32 sys_id)
713 struct arm64_ftr_reg *reg;
715 reg = get_arm64_ftr_reg_nowarn(sys_id);
718 * Requesting a non-existent register search is an error. Warn
719 * and let the caller handle it.
725 static u64 arm64_ftr_set_value(const struct arm64_ftr_bits *ftrp, s64 reg,
728 u64 mask = arm64_ftr_mask(ftrp);
731 reg |= (ftr_val << ftrp->shift) & mask;
735 static s64 arm64_ftr_safe_value(const struct arm64_ftr_bits *ftrp, s64 new,
740 switch (ftrp->type) {
742 ret = ftrp->safe_val;
747 case FTR_HIGHER_OR_ZERO_SAFE:
751 case FTR_HIGHER_SAFE:
761 static void __init sort_ftr_regs(void)
765 for (i = 0; i < ARRAY_SIZE(arm64_ftr_regs); i++) {
766 const struct arm64_ftr_reg *ftr_reg = arm64_ftr_regs[i].reg;
767 const struct arm64_ftr_bits *ftr_bits = ftr_reg->ftr_bits;
771 * Features here must be sorted in descending order with respect
772 * to their shift values and should not overlap with each other.
774 for (; ftr_bits->width != 0; ftr_bits++, j++) {
775 unsigned int width = ftr_reg->ftr_bits[j].width;
776 unsigned int shift = ftr_reg->ftr_bits[j].shift;
777 unsigned int prev_shift;
779 WARN((shift + width) > 64,
780 "%s has invalid feature at shift %d\n",
781 ftr_reg->name, shift);
784 * Skip the first feature. There is nothing to
785 * compare against for now.
790 prev_shift = ftr_reg->ftr_bits[j - 1].shift;
791 WARN((shift + width) > prev_shift,
792 "%s has feature overlap at shift %d\n",
793 ftr_reg->name, shift);
797 * Skip the first register. There is nothing to
798 * compare against for now.
803 * Registers here must be sorted in ascending order with respect
804 * to sys_id for subsequent binary search in get_arm64_ftr_reg()
807 BUG_ON(arm64_ftr_regs[i].sys_id < arm64_ftr_regs[i - 1].sys_id);
812 * Initialise the CPU feature register from Boot CPU values.
813 * Also initiliases the strict_mask for the register.
814 * Any bits that are not covered by an arm64_ftr_bits entry are considered
815 * RES0 for the system-wide value, and must strictly match.
817 static void init_cpu_ftr_reg(u32 sys_reg, u64 new)
820 u64 strict_mask = ~0x0ULL;
824 const struct arm64_ftr_bits *ftrp;
825 struct arm64_ftr_reg *reg = get_arm64_ftr_reg(sys_reg);
830 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) {
831 u64 ftr_mask = arm64_ftr_mask(ftrp);
832 s64 ftr_new = arm64_ftr_value(ftrp, new);
833 s64 ftr_ovr = arm64_ftr_value(ftrp, reg->override->val);
835 if ((ftr_mask & reg->override->mask) == ftr_mask) {
836 s64 tmp = arm64_ftr_safe_value(ftrp, ftr_ovr, ftr_new);
839 if (ftr_ovr != tmp) {
840 /* Unsafe, remove the override */
841 reg->override->mask &= ~ftr_mask;
842 reg->override->val &= ~ftr_mask;
844 str = "ignoring override";
845 } else if (ftr_new != tmp) {
846 /* Override was valid */
849 } else if (ftr_ovr == tmp) {
850 /* Override was the safe value */
855 pr_warn("%s[%d:%d]: %s to %llx\n",
857 ftrp->shift + ftrp->width - 1,
858 ftrp->shift, str, tmp);
859 } else if ((ftr_mask & reg->override->val) == ftr_mask) {
860 reg->override->val &= ~ftr_mask;
861 pr_warn("%s[%d:%d]: impossible override, ignored\n",
863 ftrp->shift + ftrp->width - 1,
867 val = arm64_ftr_set_value(ftrp, val, ftr_new);
869 valid_mask |= ftr_mask;
871 strict_mask &= ~ftr_mask;
873 user_mask |= ftr_mask;
875 reg->user_val = arm64_ftr_set_value(ftrp,
883 reg->strict_mask = strict_mask;
884 reg->user_mask = user_mask;
887 extern const struct arm64_cpu_capabilities arm64_errata[];
888 static const struct arm64_cpu_capabilities arm64_features[];
891 init_cpu_hwcaps_indirect_list_from_array(const struct arm64_cpu_capabilities *caps)
893 for (; caps->matches; caps++) {
894 if (WARN(caps->capability >= ARM64_NCAPS,
895 "Invalid capability %d\n", caps->capability))
897 if (WARN(cpu_hwcaps_ptrs[caps->capability],
898 "Duplicate entry for capability %d\n",
901 cpu_hwcaps_ptrs[caps->capability] = caps;
905 static void __init init_cpu_hwcaps_indirect_list(void)
907 init_cpu_hwcaps_indirect_list_from_array(arm64_features);
908 init_cpu_hwcaps_indirect_list_from_array(arm64_errata);
911 static void __init setup_boot_cpu_capabilities(void);
913 static void init_32bit_cpu_features(struct cpuinfo_32bit *info)
915 init_cpu_ftr_reg(SYS_ID_DFR0_EL1, info->reg_id_dfr0);
916 init_cpu_ftr_reg(SYS_ID_DFR1_EL1, info->reg_id_dfr1);
917 init_cpu_ftr_reg(SYS_ID_ISAR0_EL1, info->reg_id_isar0);
918 init_cpu_ftr_reg(SYS_ID_ISAR1_EL1, info->reg_id_isar1);
919 init_cpu_ftr_reg(SYS_ID_ISAR2_EL1, info->reg_id_isar2);
920 init_cpu_ftr_reg(SYS_ID_ISAR3_EL1, info->reg_id_isar3);
921 init_cpu_ftr_reg(SYS_ID_ISAR4_EL1, info->reg_id_isar4);
922 init_cpu_ftr_reg(SYS_ID_ISAR5_EL1, info->reg_id_isar5);
923 init_cpu_ftr_reg(SYS_ID_ISAR6_EL1, info->reg_id_isar6);
924 init_cpu_ftr_reg(SYS_ID_MMFR0_EL1, info->reg_id_mmfr0);
925 init_cpu_ftr_reg(SYS_ID_MMFR1_EL1, info->reg_id_mmfr1);
926 init_cpu_ftr_reg(SYS_ID_MMFR2_EL1, info->reg_id_mmfr2);
927 init_cpu_ftr_reg(SYS_ID_MMFR3_EL1, info->reg_id_mmfr3);
928 init_cpu_ftr_reg(SYS_ID_MMFR4_EL1, info->reg_id_mmfr4);
929 init_cpu_ftr_reg(SYS_ID_MMFR5_EL1, info->reg_id_mmfr5);
930 init_cpu_ftr_reg(SYS_ID_PFR0_EL1, info->reg_id_pfr0);
931 init_cpu_ftr_reg(SYS_ID_PFR1_EL1, info->reg_id_pfr1);
932 init_cpu_ftr_reg(SYS_ID_PFR2_EL1, info->reg_id_pfr2);
933 init_cpu_ftr_reg(SYS_MVFR0_EL1, info->reg_mvfr0);
934 init_cpu_ftr_reg(SYS_MVFR1_EL1, info->reg_mvfr1);
935 init_cpu_ftr_reg(SYS_MVFR2_EL1, info->reg_mvfr2);
938 void __init init_cpu_features(struct cpuinfo_arm64 *info)
940 /* Before we start using the tables, make sure it is sorted */
943 init_cpu_ftr_reg(SYS_CTR_EL0, info->reg_ctr);
944 init_cpu_ftr_reg(SYS_DCZID_EL0, info->reg_dczid);
945 init_cpu_ftr_reg(SYS_CNTFRQ_EL0, info->reg_cntfrq);
946 init_cpu_ftr_reg(SYS_ID_AA64DFR0_EL1, info->reg_id_aa64dfr0);
947 init_cpu_ftr_reg(SYS_ID_AA64DFR1_EL1, info->reg_id_aa64dfr1);
948 init_cpu_ftr_reg(SYS_ID_AA64ISAR0_EL1, info->reg_id_aa64isar0);
949 init_cpu_ftr_reg(SYS_ID_AA64ISAR1_EL1, info->reg_id_aa64isar1);
950 init_cpu_ftr_reg(SYS_ID_AA64ISAR2_EL1, info->reg_id_aa64isar2);
951 init_cpu_ftr_reg(SYS_ID_AA64MMFR0_EL1, info->reg_id_aa64mmfr0);
952 init_cpu_ftr_reg(SYS_ID_AA64MMFR1_EL1, info->reg_id_aa64mmfr1);
953 init_cpu_ftr_reg(SYS_ID_AA64MMFR2_EL1, info->reg_id_aa64mmfr2);
954 init_cpu_ftr_reg(SYS_ID_AA64PFR0_EL1, info->reg_id_aa64pfr0);
955 init_cpu_ftr_reg(SYS_ID_AA64PFR1_EL1, info->reg_id_aa64pfr1);
956 init_cpu_ftr_reg(SYS_ID_AA64ZFR0_EL1, info->reg_id_aa64zfr0);
958 if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0))
959 init_32bit_cpu_features(&info->aarch32);
961 if (id_aa64pfr0_sve(info->reg_id_aa64pfr0)) {
962 init_cpu_ftr_reg(SYS_ZCR_EL1, info->reg_zcr);
966 if (id_aa64pfr1_mte(info->reg_id_aa64pfr1))
967 init_cpu_ftr_reg(SYS_GMID_EL1, info->reg_gmid);
970 * Initialize the indirect array of CPU hwcaps capabilities pointers
971 * before we handle the boot CPU below.
973 init_cpu_hwcaps_indirect_list();
976 * Detect and enable early CPU capabilities based on the boot CPU,
977 * after we have initialised the CPU feature infrastructure.
979 setup_boot_cpu_capabilities();
982 static void update_cpu_ftr_reg(struct arm64_ftr_reg *reg, u64 new)
984 const struct arm64_ftr_bits *ftrp;
986 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) {
987 s64 ftr_cur = arm64_ftr_value(ftrp, reg->sys_val);
988 s64 ftr_new = arm64_ftr_value(ftrp, new);
990 if (ftr_cur == ftr_new)
992 /* Find a safe value */
993 ftr_new = arm64_ftr_safe_value(ftrp, ftr_new, ftr_cur);
994 reg->sys_val = arm64_ftr_set_value(ftrp, reg->sys_val, ftr_new);
999 static int check_update_ftr_reg(u32 sys_id, int cpu, u64 val, u64 boot)
1001 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id);
1006 update_cpu_ftr_reg(regp, val);
1007 if ((boot & regp->strict_mask) == (val & regp->strict_mask))
1009 pr_warn("SANITY CHECK: Unexpected variation in %s. Boot CPU: %#016llx, CPU%d: %#016llx\n",
1010 regp->name, boot, cpu, val);
1014 static void relax_cpu_ftr_reg(u32 sys_id, int field)
1016 const struct arm64_ftr_bits *ftrp;
1017 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id);
1022 for (ftrp = regp->ftr_bits; ftrp->width; ftrp++) {
1023 if (ftrp->shift == field) {
1024 regp->strict_mask &= ~arm64_ftr_mask(ftrp);
1030 WARN_ON(!ftrp->width);
1033 static void lazy_init_32bit_cpu_features(struct cpuinfo_arm64 *info,
1034 struct cpuinfo_arm64 *boot)
1036 static bool boot_cpu_32bit_regs_overridden = false;
1038 if (!allow_mismatched_32bit_el0 || boot_cpu_32bit_regs_overridden)
1041 if (id_aa64pfr0_32bit_el0(boot->reg_id_aa64pfr0))
1044 boot->aarch32 = info->aarch32;
1045 init_32bit_cpu_features(&boot->aarch32);
1046 boot_cpu_32bit_regs_overridden = true;
1049 static int update_32bit_cpu_features(int cpu, struct cpuinfo_32bit *info,
1050 struct cpuinfo_32bit *boot)
1053 u64 pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1);
1056 * If we don't have AArch32 at EL1, then relax the strictness of
1057 * EL1-dependent register fields to avoid spurious sanity check fails.
1059 if (!id_aa64pfr0_32bit_el1(pfr0)) {
1060 relax_cpu_ftr_reg(SYS_ID_ISAR4_EL1, ID_ISAR4_SMC_SHIFT);
1061 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_VIRT_FRAC_SHIFT);
1062 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_SEC_FRAC_SHIFT);
1063 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_VIRTUALIZATION_SHIFT);
1064 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_SECURITY_SHIFT);
1065 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_PROGMOD_SHIFT);
1068 taint |= check_update_ftr_reg(SYS_ID_DFR0_EL1, cpu,
1069 info->reg_id_dfr0, boot->reg_id_dfr0);
1070 taint |= check_update_ftr_reg(SYS_ID_DFR1_EL1, cpu,
1071 info->reg_id_dfr1, boot->reg_id_dfr1);
1072 taint |= check_update_ftr_reg(SYS_ID_ISAR0_EL1, cpu,
1073 info->reg_id_isar0, boot->reg_id_isar0);
1074 taint |= check_update_ftr_reg(SYS_ID_ISAR1_EL1, cpu,
1075 info->reg_id_isar1, boot->reg_id_isar1);
1076 taint |= check_update_ftr_reg(SYS_ID_ISAR2_EL1, cpu,
1077 info->reg_id_isar2, boot->reg_id_isar2);
1078 taint |= check_update_ftr_reg(SYS_ID_ISAR3_EL1, cpu,
1079 info->reg_id_isar3, boot->reg_id_isar3);
1080 taint |= check_update_ftr_reg(SYS_ID_ISAR4_EL1, cpu,
1081 info->reg_id_isar4, boot->reg_id_isar4);
1082 taint |= check_update_ftr_reg(SYS_ID_ISAR5_EL1, cpu,
1083 info->reg_id_isar5, boot->reg_id_isar5);
1084 taint |= check_update_ftr_reg(SYS_ID_ISAR6_EL1, cpu,
1085 info->reg_id_isar6, boot->reg_id_isar6);
1088 * Regardless of the value of the AuxReg field, the AIFSR, ADFSR, and
1089 * ACTLR formats could differ across CPUs and therefore would have to
1090 * be trapped for virtualization anyway.
1092 taint |= check_update_ftr_reg(SYS_ID_MMFR0_EL1, cpu,
1093 info->reg_id_mmfr0, boot->reg_id_mmfr0);
1094 taint |= check_update_ftr_reg(SYS_ID_MMFR1_EL1, cpu,
1095 info->reg_id_mmfr1, boot->reg_id_mmfr1);
1096 taint |= check_update_ftr_reg(SYS_ID_MMFR2_EL1, cpu,
1097 info->reg_id_mmfr2, boot->reg_id_mmfr2);
1098 taint |= check_update_ftr_reg(SYS_ID_MMFR3_EL1, cpu,
1099 info->reg_id_mmfr3, boot->reg_id_mmfr3);
1100 taint |= check_update_ftr_reg(SYS_ID_MMFR4_EL1, cpu,
1101 info->reg_id_mmfr4, boot->reg_id_mmfr4);
1102 taint |= check_update_ftr_reg(SYS_ID_MMFR5_EL1, cpu,
1103 info->reg_id_mmfr5, boot->reg_id_mmfr5);
1104 taint |= check_update_ftr_reg(SYS_ID_PFR0_EL1, cpu,
1105 info->reg_id_pfr0, boot->reg_id_pfr0);
1106 taint |= check_update_ftr_reg(SYS_ID_PFR1_EL1, cpu,
1107 info->reg_id_pfr1, boot->reg_id_pfr1);
1108 taint |= check_update_ftr_reg(SYS_ID_PFR2_EL1, cpu,
1109 info->reg_id_pfr2, boot->reg_id_pfr2);
1110 taint |= check_update_ftr_reg(SYS_MVFR0_EL1, cpu,
1111 info->reg_mvfr0, boot->reg_mvfr0);
1112 taint |= check_update_ftr_reg(SYS_MVFR1_EL1, cpu,
1113 info->reg_mvfr1, boot->reg_mvfr1);
1114 taint |= check_update_ftr_reg(SYS_MVFR2_EL1, cpu,
1115 info->reg_mvfr2, boot->reg_mvfr2);
1121 * Update system wide CPU feature registers with the values from a
1122 * non-boot CPU. Also performs SANITY checks to make sure that there
1123 * aren't any insane variations from that of the boot CPU.
1125 void update_cpu_features(int cpu,
1126 struct cpuinfo_arm64 *info,
1127 struct cpuinfo_arm64 *boot)
1132 * The kernel can handle differing I-cache policies, but otherwise
1133 * caches should look identical. Userspace JITs will make use of
1136 taint |= check_update_ftr_reg(SYS_CTR_EL0, cpu,
1137 info->reg_ctr, boot->reg_ctr);
1140 * Userspace may perform DC ZVA instructions. Mismatched block sizes
1141 * could result in too much or too little memory being zeroed if a
1142 * process is preempted and migrated between CPUs.
1144 taint |= check_update_ftr_reg(SYS_DCZID_EL0, cpu,
1145 info->reg_dczid, boot->reg_dczid);
1147 /* If different, timekeeping will be broken (especially with KVM) */
1148 taint |= check_update_ftr_reg(SYS_CNTFRQ_EL0, cpu,
1149 info->reg_cntfrq, boot->reg_cntfrq);
1152 * The kernel uses self-hosted debug features and expects CPUs to
1153 * support identical debug features. We presently need CTX_CMPs, WRPs,
1154 * and BRPs to be identical.
1155 * ID_AA64DFR1 is currently RES0.
1157 taint |= check_update_ftr_reg(SYS_ID_AA64DFR0_EL1, cpu,
1158 info->reg_id_aa64dfr0, boot->reg_id_aa64dfr0);
1159 taint |= check_update_ftr_reg(SYS_ID_AA64DFR1_EL1, cpu,
1160 info->reg_id_aa64dfr1, boot->reg_id_aa64dfr1);
1162 * Even in big.LITTLE, processors should be identical instruction-set
1165 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR0_EL1, cpu,
1166 info->reg_id_aa64isar0, boot->reg_id_aa64isar0);
1167 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR1_EL1, cpu,
1168 info->reg_id_aa64isar1, boot->reg_id_aa64isar1);
1169 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR2_EL1, cpu,
1170 info->reg_id_aa64isar2, boot->reg_id_aa64isar2);
1173 * Differing PARange support is fine as long as all peripherals and
1174 * memory are mapped within the minimum PARange of all CPUs.
1175 * Linux should not care about secure memory.
1177 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR0_EL1, cpu,
1178 info->reg_id_aa64mmfr0, boot->reg_id_aa64mmfr0);
1179 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR1_EL1, cpu,
1180 info->reg_id_aa64mmfr1, boot->reg_id_aa64mmfr1);
1181 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR2_EL1, cpu,
1182 info->reg_id_aa64mmfr2, boot->reg_id_aa64mmfr2);
1184 taint |= check_update_ftr_reg(SYS_ID_AA64PFR0_EL1, cpu,
1185 info->reg_id_aa64pfr0, boot->reg_id_aa64pfr0);
1186 taint |= check_update_ftr_reg(SYS_ID_AA64PFR1_EL1, cpu,
1187 info->reg_id_aa64pfr1, boot->reg_id_aa64pfr1);
1189 taint |= check_update_ftr_reg(SYS_ID_AA64ZFR0_EL1, cpu,
1190 info->reg_id_aa64zfr0, boot->reg_id_aa64zfr0);
1192 if (id_aa64pfr0_sve(info->reg_id_aa64pfr0)) {
1193 taint |= check_update_ftr_reg(SYS_ZCR_EL1, cpu,
1194 info->reg_zcr, boot->reg_zcr);
1196 /* Probe vector lengths, unless we already gave up on SVE */
1197 if (id_aa64pfr0_sve(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1)) &&
1198 !system_capabilities_finalized())
1199 sve_update_vq_map();
1203 * The kernel uses the LDGM/STGM instructions and the number of tags
1204 * they read/write depends on the GMID_EL1.BS field. Check that the
1205 * value is the same on all CPUs.
1207 if (IS_ENABLED(CONFIG_ARM64_MTE) &&
1208 id_aa64pfr1_mte(info->reg_id_aa64pfr1)) {
1209 taint |= check_update_ftr_reg(SYS_GMID_EL1, cpu,
1210 info->reg_gmid, boot->reg_gmid);
1214 * If we don't have AArch32 at all then skip the checks entirely
1215 * as the register values may be UNKNOWN and we're not going to be
1216 * using them for anything.
1218 * This relies on a sanitised view of the AArch64 ID registers
1219 * (e.g. SYS_ID_AA64PFR0_EL1), so we call it last.
1221 if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) {
1222 lazy_init_32bit_cpu_features(info, boot);
1223 taint |= update_32bit_cpu_features(cpu, &info->aarch32,
1228 * Mismatched CPU features are a recipe for disaster. Don't even
1229 * pretend to support them.
1232 pr_warn_once("Unsupported CPU feature variation detected.\n");
1233 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK);
1237 u64 read_sanitised_ftr_reg(u32 id)
1239 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(id);
1243 return regp->sys_val;
1245 EXPORT_SYMBOL_GPL(read_sanitised_ftr_reg);
1247 #define read_sysreg_case(r) \
1248 case r: val = read_sysreg_s(r); break;
1251 * __read_sysreg_by_encoding() - Used by a STARTING cpu before cpuinfo is populated.
1252 * Read the system register on the current CPU
1254 u64 __read_sysreg_by_encoding(u32 sys_id)
1256 struct arm64_ftr_reg *regp;
1260 read_sysreg_case(SYS_ID_PFR0_EL1);
1261 read_sysreg_case(SYS_ID_PFR1_EL1);
1262 read_sysreg_case(SYS_ID_PFR2_EL1);
1263 read_sysreg_case(SYS_ID_DFR0_EL1);
1264 read_sysreg_case(SYS_ID_DFR1_EL1);
1265 read_sysreg_case(SYS_ID_MMFR0_EL1);
1266 read_sysreg_case(SYS_ID_MMFR1_EL1);
1267 read_sysreg_case(SYS_ID_MMFR2_EL1);
1268 read_sysreg_case(SYS_ID_MMFR3_EL1);
1269 read_sysreg_case(SYS_ID_MMFR4_EL1);
1270 read_sysreg_case(SYS_ID_MMFR5_EL1);
1271 read_sysreg_case(SYS_ID_ISAR0_EL1);
1272 read_sysreg_case(SYS_ID_ISAR1_EL1);
1273 read_sysreg_case(SYS_ID_ISAR2_EL1);
1274 read_sysreg_case(SYS_ID_ISAR3_EL1);
1275 read_sysreg_case(SYS_ID_ISAR4_EL1);
1276 read_sysreg_case(SYS_ID_ISAR5_EL1);
1277 read_sysreg_case(SYS_ID_ISAR6_EL1);
1278 read_sysreg_case(SYS_MVFR0_EL1);
1279 read_sysreg_case(SYS_MVFR1_EL1);
1280 read_sysreg_case(SYS_MVFR2_EL1);
1282 read_sysreg_case(SYS_ID_AA64PFR0_EL1);
1283 read_sysreg_case(SYS_ID_AA64PFR1_EL1);
1284 read_sysreg_case(SYS_ID_AA64ZFR0_EL1);
1285 read_sysreg_case(SYS_ID_AA64DFR0_EL1);
1286 read_sysreg_case(SYS_ID_AA64DFR1_EL1);
1287 read_sysreg_case(SYS_ID_AA64MMFR0_EL1);
1288 read_sysreg_case(SYS_ID_AA64MMFR1_EL1);
1289 read_sysreg_case(SYS_ID_AA64MMFR2_EL1);
1290 read_sysreg_case(SYS_ID_AA64ISAR0_EL1);
1291 read_sysreg_case(SYS_ID_AA64ISAR1_EL1);
1292 read_sysreg_case(SYS_ID_AA64ISAR2_EL1);
1294 read_sysreg_case(SYS_CNTFRQ_EL0);
1295 read_sysreg_case(SYS_CTR_EL0);
1296 read_sysreg_case(SYS_DCZID_EL0);
1303 regp = get_arm64_ftr_reg(sys_id);
1305 val &= ~regp->override->mask;
1306 val |= (regp->override->val & regp->override->mask);
1312 #include <linux/irqchip/arm-gic-v3.h>
1315 feature_matches(u64 reg, const struct arm64_cpu_capabilities *entry)
1317 int val = cpuid_feature_extract_field(reg, entry->field_pos, entry->sign);
1319 return val >= entry->min_field_value;
1323 has_cpuid_feature(const struct arm64_cpu_capabilities *entry, int scope)
1327 WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible());
1328 if (scope == SCOPE_SYSTEM)
1329 val = read_sanitised_ftr_reg(entry->sys_reg);
1331 val = __read_sysreg_by_encoding(entry->sys_reg);
1333 return feature_matches(val, entry);
1336 const struct cpumask *system_32bit_el0_cpumask(void)
1338 if (!system_supports_32bit_el0())
1339 return cpu_none_mask;
1341 if (static_branch_unlikely(&arm64_mismatched_32bit_el0))
1342 return cpu_32bit_el0_mask;
1344 return cpu_possible_mask;
1347 static int __init parse_32bit_el0_param(char *str)
1349 allow_mismatched_32bit_el0 = true;
1352 early_param("allow_mismatched_32bit_el0", parse_32bit_el0_param);
1354 static ssize_t aarch32_el0_show(struct device *dev,
1355 struct device_attribute *attr, char *buf)
1357 const struct cpumask *mask = system_32bit_el0_cpumask();
1359 return sysfs_emit(buf, "%*pbl\n", cpumask_pr_args(mask));
1361 static const DEVICE_ATTR_RO(aarch32_el0);
1363 static int __init aarch32_el0_sysfs_init(void)
1365 if (!allow_mismatched_32bit_el0)
1368 return device_create_file(cpu_subsys.dev_root, &dev_attr_aarch32_el0);
1370 device_initcall(aarch32_el0_sysfs_init);
1372 static bool has_32bit_el0(const struct arm64_cpu_capabilities *entry, int scope)
1374 if (!has_cpuid_feature(entry, scope))
1375 return allow_mismatched_32bit_el0;
1377 if (scope == SCOPE_SYSTEM)
1378 pr_info("detected: 32-bit EL0 Support\n");
1383 static bool has_useable_gicv3_cpuif(const struct arm64_cpu_capabilities *entry, int scope)
1387 if (!has_cpuid_feature(entry, scope))
1390 has_sre = gic_enable_sre();
1392 pr_warn_once("%s present but disabled by higher exception level\n",
1398 static bool has_no_hw_prefetch(const struct arm64_cpu_capabilities *entry, int __unused)
1400 u32 midr = read_cpuid_id();
1402 /* Cavium ThunderX pass 1.x and 2.x */
1403 return midr_is_cpu_model_range(midr, MIDR_THUNDERX,
1404 MIDR_CPU_VAR_REV(0, 0),
1405 MIDR_CPU_VAR_REV(1, MIDR_REVISION_MASK));
1408 static bool has_no_fpsimd(const struct arm64_cpu_capabilities *entry, int __unused)
1410 u64 pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1);
1412 return cpuid_feature_extract_signed_field(pfr0,
1413 ID_AA64PFR0_FP_SHIFT) < 0;
1416 static bool has_cache_idc(const struct arm64_cpu_capabilities *entry,
1421 if (scope == SCOPE_SYSTEM)
1422 ctr = arm64_ftr_reg_ctrel0.sys_val;
1424 ctr = read_cpuid_effective_cachetype();
1426 return ctr & BIT(CTR_IDC_SHIFT);
1429 static void cpu_emulate_effective_ctr(const struct arm64_cpu_capabilities *__unused)
1432 * If the CPU exposes raw CTR_EL0.IDC = 0, while effectively
1433 * CTR_EL0.IDC = 1 (from CLIDR values), we need to trap accesses
1434 * to the CTR_EL0 on this CPU and emulate it with the real/safe
1437 if (!(read_cpuid_cachetype() & BIT(CTR_IDC_SHIFT)))
1438 sysreg_clear_set(sctlr_el1, SCTLR_EL1_UCT, 0);
1441 static bool has_cache_dic(const struct arm64_cpu_capabilities *entry,
1446 if (scope == SCOPE_SYSTEM)
1447 ctr = arm64_ftr_reg_ctrel0.sys_val;
1449 ctr = read_cpuid_cachetype();
1451 return ctr & BIT(CTR_DIC_SHIFT);
1454 static bool __maybe_unused
1455 has_useable_cnp(const struct arm64_cpu_capabilities *entry, int scope)
1458 * Kdump isn't guaranteed to power-off all secondary CPUs, CNP
1459 * may share TLB entries with a CPU stuck in the crashed
1462 if (is_kdump_kernel())
1465 if (cpus_have_const_cap(ARM64_WORKAROUND_NVIDIA_CARMEL_CNP))
1468 return has_cpuid_feature(entry, scope);
1472 * This check is triggered during the early boot before the cpufeature
1473 * is initialised. Checking the status on the local CPU allows the boot
1474 * CPU to detect the need for non-global mappings and thus avoiding a
1475 * pagetable re-write after all the CPUs are booted. This check will be
1476 * anyway run on individual CPUs, allowing us to get the consistent
1477 * state once the SMP CPUs are up and thus make the switch to non-global
1478 * mappings if required.
1480 bool kaslr_requires_kpti(void)
1482 if (!IS_ENABLED(CONFIG_RANDOMIZE_BASE))
1486 * E0PD does a similar job to KPTI so can be used instead
1489 if (IS_ENABLED(CONFIG_ARM64_E0PD)) {
1490 u64 mmfr2 = read_sysreg_s(SYS_ID_AA64MMFR2_EL1);
1491 if (cpuid_feature_extract_unsigned_field(mmfr2,
1492 ID_AA64MMFR2_E0PD_SHIFT))
1497 * Systems affected by Cavium erratum 24756 are incompatible
1500 if (IS_ENABLED(CONFIG_CAVIUM_ERRATUM_27456)) {
1501 extern const struct midr_range cavium_erratum_27456_cpus[];
1503 if (is_midr_in_range_list(read_cpuid_id(),
1504 cavium_erratum_27456_cpus))
1508 return kaslr_offset() > 0;
1511 static bool __meltdown_safe = true;
1512 static int __kpti_forced; /* 0: not forced, >0: forced on, <0: forced off */
1514 static bool unmap_kernel_at_el0(const struct arm64_cpu_capabilities *entry,
1517 /* List of CPUs that are not vulnerable and don't need KPTI */
1518 static const struct midr_range kpti_safe_list[] = {
1519 MIDR_ALL_VERSIONS(MIDR_CAVIUM_THUNDERX2),
1520 MIDR_ALL_VERSIONS(MIDR_BRCM_VULCAN),
1521 MIDR_ALL_VERSIONS(MIDR_BRAHMA_B53),
1522 MIDR_ALL_VERSIONS(MIDR_CORTEX_A35),
1523 MIDR_ALL_VERSIONS(MIDR_CORTEX_A53),
1524 MIDR_ALL_VERSIONS(MIDR_CORTEX_A55),
1525 MIDR_ALL_VERSIONS(MIDR_CORTEX_A57),
1526 MIDR_ALL_VERSIONS(MIDR_CORTEX_A72),
1527 MIDR_ALL_VERSIONS(MIDR_CORTEX_A73),
1528 MIDR_ALL_VERSIONS(MIDR_HISI_TSV110),
1529 MIDR_ALL_VERSIONS(MIDR_NVIDIA_CARMEL),
1530 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_2XX_GOLD),
1531 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_2XX_SILVER),
1532 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_3XX_SILVER),
1533 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_4XX_SILVER),
1536 char const *str = "kpti command line option";
1539 meltdown_safe = is_midr_in_range_list(read_cpuid_id(), kpti_safe_list);
1541 /* Defer to CPU feature registers */
1542 if (has_cpuid_feature(entry, scope))
1543 meltdown_safe = true;
1546 __meltdown_safe = false;
1549 * For reasons that aren't entirely clear, enabling KPTI on Cavium
1550 * ThunderX leads to apparent I-cache corruption of kernel text, which
1551 * ends as well as you might imagine. Don't even try. We cannot rely
1552 * on the cpus_have_*cap() helpers here to detect the CPU erratum
1553 * because cpucap detection order may change. However, since we know
1554 * affected CPUs are always in a homogeneous configuration, it is
1555 * safe to rely on this_cpu_has_cap() here.
1557 if (this_cpu_has_cap(ARM64_WORKAROUND_CAVIUM_27456)) {
1558 str = "ARM64_WORKAROUND_CAVIUM_27456";
1562 /* Useful for KASLR robustness */
1563 if (kaslr_requires_kpti()) {
1564 if (!__kpti_forced) {
1570 if (cpu_mitigations_off() && !__kpti_forced) {
1571 str = "mitigations=off";
1575 if (!IS_ENABLED(CONFIG_UNMAP_KERNEL_AT_EL0)) {
1576 pr_info_once("kernel page table isolation disabled by kernel configuration\n");
1581 if (__kpti_forced) {
1582 pr_info_once("kernel page table isolation forced %s by %s\n",
1583 __kpti_forced > 0 ? "ON" : "OFF", str);
1584 return __kpti_forced > 0;
1587 return !meltdown_safe;
1590 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0
1592 kpti_install_ng_mappings(const struct arm64_cpu_capabilities *__unused)
1594 typedef void (kpti_remap_fn)(int, int, phys_addr_t);
1595 extern kpti_remap_fn idmap_kpti_install_ng_mappings;
1596 kpti_remap_fn *remap_fn;
1598 int cpu = smp_processor_id();
1600 if (__this_cpu_read(this_cpu_vector) == vectors) {
1601 const char *v = arm64_get_bp_hardening_vector(EL1_VECTOR_KPTI);
1603 __this_cpu_write(this_cpu_vector, v);
1607 * We don't need to rewrite the page-tables if either we've done
1608 * it already or we have KASLR enabled and therefore have not
1609 * created any global mappings at all.
1611 if (arm64_use_ng_mappings)
1614 remap_fn = (void *)__pa_symbol(function_nocfi(idmap_kpti_install_ng_mappings));
1616 cpu_install_idmap();
1617 remap_fn(cpu, num_online_cpus(), __pa_symbol(swapper_pg_dir));
1618 cpu_uninstall_idmap();
1621 arm64_use_ng_mappings = true;
1625 kpti_install_ng_mappings(const struct arm64_cpu_capabilities *__unused)
1628 #endif /* CONFIG_UNMAP_KERNEL_AT_EL0 */
1630 static int __init parse_kpti(char *str)
1633 int ret = strtobool(str, &enabled);
1638 __kpti_forced = enabled ? 1 : -1;
1641 early_param("kpti", parse_kpti);
1643 #ifdef CONFIG_ARM64_HW_AFDBM
1644 static inline void __cpu_enable_hw_dbm(void)
1646 u64 tcr = read_sysreg(tcr_el1) | TCR_HD;
1648 write_sysreg(tcr, tcr_el1);
1650 local_flush_tlb_all();
1653 static bool cpu_has_broken_dbm(void)
1655 /* List of CPUs which have broken DBM support. */
1656 static const struct midr_range cpus[] = {
1657 #ifdef CONFIG_ARM64_ERRATUM_1024718
1658 MIDR_ALL_VERSIONS(MIDR_CORTEX_A55),
1659 /* Kryo4xx Silver (rdpe => r1p0) */
1660 MIDR_REV(MIDR_QCOM_KRYO_4XX_SILVER, 0xd, 0xe),
1665 return is_midr_in_range_list(read_cpuid_id(), cpus);
1668 static bool cpu_can_use_dbm(const struct arm64_cpu_capabilities *cap)
1670 return has_cpuid_feature(cap, SCOPE_LOCAL_CPU) &&
1671 !cpu_has_broken_dbm();
1674 static void cpu_enable_hw_dbm(struct arm64_cpu_capabilities const *cap)
1676 if (cpu_can_use_dbm(cap))
1677 __cpu_enable_hw_dbm();
1680 static bool has_hw_dbm(const struct arm64_cpu_capabilities *cap,
1683 static bool detected = false;
1685 * DBM is a non-conflicting feature. i.e, the kernel can safely
1686 * run a mix of CPUs with and without the feature. So, we
1687 * unconditionally enable the capability to allow any late CPU
1688 * to use the feature. We only enable the control bits on the
1689 * CPU, if it actually supports.
1691 * We have to make sure we print the "feature" detection only
1692 * when at least one CPU actually uses it. So check if this CPU
1693 * can actually use it and print the message exactly once.
1695 * This is safe as all CPUs (including secondary CPUs - due to the
1696 * LOCAL_CPU scope - and the hotplugged CPUs - via verification)
1697 * goes through the "matches" check exactly once. Also if a CPU
1698 * matches the criteria, it is guaranteed that the CPU will turn
1699 * the DBM on, as the capability is unconditionally enabled.
1701 if (!detected && cpu_can_use_dbm(cap)) {
1703 pr_info("detected: Hardware dirty bit management\n");
1711 #ifdef CONFIG_ARM64_AMU_EXTN
1714 * The "amu_cpus" cpumask only signals that the CPU implementation for the
1715 * flagged CPUs supports the Activity Monitors Unit (AMU) but does not provide
1716 * information regarding all the events that it supports. When a CPU bit is
1717 * set in the cpumask, the user of this feature can only rely on the presence
1718 * of the 4 fixed counters for that CPU. But this does not guarantee that the
1719 * counters are enabled or access to these counters is enabled by code
1720 * executed at higher exception levels (firmware).
1722 static struct cpumask amu_cpus __read_mostly;
1724 bool cpu_has_amu_feat(int cpu)
1726 return cpumask_test_cpu(cpu, &amu_cpus);
1729 int get_cpu_with_amu_feat(void)
1731 return cpumask_any(&amu_cpus);
1734 static void cpu_amu_enable(struct arm64_cpu_capabilities const *cap)
1736 if (has_cpuid_feature(cap, SCOPE_LOCAL_CPU)) {
1737 pr_info("detected CPU%d: Activity Monitors Unit (AMU)\n",
1738 smp_processor_id());
1739 cpumask_set_cpu(smp_processor_id(), &amu_cpus);
1741 /* 0 reference values signal broken/disabled counters */
1742 if (!this_cpu_has_cap(ARM64_WORKAROUND_2457168))
1743 update_freq_counters_refs();
1747 static bool has_amu(const struct arm64_cpu_capabilities *cap,
1751 * The AMU extension is a non-conflicting feature: the kernel can
1752 * safely run a mix of CPUs with and without support for the
1753 * activity monitors extension. Therefore, unconditionally enable
1754 * the capability to allow any late CPU to use the feature.
1756 * With this feature unconditionally enabled, the cpu_enable
1757 * function will be called for all CPUs that match the criteria,
1758 * including secondary and hotplugged, marking this feature as
1759 * present on that respective CPU. The enable function will also
1760 * print a detection message.
1766 int get_cpu_with_amu_feat(void)
1772 static bool runs_at_el2(const struct arm64_cpu_capabilities *entry, int __unused)
1774 return is_kernel_in_hyp_mode();
1777 static void cpu_copy_el2regs(const struct arm64_cpu_capabilities *__unused)
1780 * Copy register values that aren't redirected by hardware.
1782 * Before code patching, we only set tpidr_el1, all CPUs need to copy
1783 * this value to tpidr_el2 before we patch the code. Once we've done
1784 * that, freshly-onlined CPUs will set tpidr_el2, so we don't need to
1787 if (!alternative_is_applied(ARM64_HAS_VIRT_HOST_EXTN))
1788 write_sysreg(read_sysreg(tpidr_el1), tpidr_el2);
1791 static void cpu_has_fwb(const struct arm64_cpu_capabilities *__unused)
1793 u64 val = read_sysreg_s(SYS_CLIDR_EL1);
1795 /* Check that CLIDR_EL1.LOU{U,IS} are both 0 */
1796 WARN_ON(CLIDR_LOUU(val) || CLIDR_LOUIS(val));
1799 #ifdef CONFIG_ARM64_PAN
1800 static void cpu_enable_pan(const struct arm64_cpu_capabilities *__unused)
1803 * We modify PSTATE. This won't work from irq context as the PSTATE
1804 * is discarded once we return from the exception.
1806 WARN_ON_ONCE(in_interrupt());
1808 sysreg_clear_set(sctlr_el1, SCTLR_EL1_SPAN, 0);
1811 #endif /* CONFIG_ARM64_PAN */
1813 #ifdef CONFIG_ARM64_RAS_EXTN
1814 static void cpu_clear_disr(const struct arm64_cpu_capabilities *__unused)
1816 /* Firmware may have left a deferred SError in this register. */
1817 write_sysreg_s(0, SYS_DISR_EL1);
1819 #endif /* CONFIG_ARM64_RAS_EXTN */
1821 #ifdef CONFIG_ARM64_PTR_AUTH
1822 static bool has_address_auth_cpucap(const struct arm64_cpu_capabilities *entry, int scope)
1824 int boot_val, sec_val;
1826 /* We don't expect to be called with SCOPE_SYSTEM */
1827 WARN_ON(scope == SCOPE_SYSTEM);
1829 * The ptr-auth feature levels are not intercompatible with lower
1830 * levels. Hence we must match ptr-auth feature level of the secondary
1831 * CPUs with that of the boot CPU. The level of boot cpu is fetched
1832 * from the sanitised register whereas direct register read is done for
1833 * the secondary CPUs.
1834 * The sanitised feature state is guaranteed to match that of the
1835 * boot CPU as a mismatched secondary CPU is parked before it gets
1836 * a chance to update the state, with the capability.
1838 boot_val = cpuid_feature_extract_field(read_sanitised_ftr_reg(entry->sys_reg),
1839 entry->field_pos, entry->sign);
1840 if (scope & SCOPE_BOOT_CPU)
1841 return boot_val >= entry->min_field_value;
1842 /* Now check for the secondary CPUs with SCOPE_LOCAL_CPU scope */
1843 sec_val = cpuid_feature_extract_field(__read_sysreg_by_encoding(entry->sys_reg),
1844 entry->field_pos, entry->sign);
1845 return sec_val == boot_val;
1848 static bool has_address_auth_metacap(const struct arm64_cpu_capabilities *entry,
1851 return has_address_auth_cpucap(cpu_hwcaps_ptrs[ARM64_HAS_ADDRESS_AUTH_ARCH], scope) ||
1852 has_address_auth_cpucap(cpu_hwcaps_ptrs[ARM64_HAS_ADDRESS_AUTH_IMP_DEF], scope);
1855 static bool has_generic_auth(const struct arm64_cpu_capabilities *entry,
1858 return __system_matches_cap(ARM64_HAS_GENERIC_AUTH_ARCH) ||
1859 __system_matches_cap(ARM64_HAS_GENERIC_AUTH_IMP_DEF);
1861 #endif /* CONFIG_ARM64_PTR_AUTH */
1863 #ifdef CONFIG_ARM64_E0PD
1864 static void cpu_enable_e0pd(struct arm64_cpu_capabilities const *cap)
1866 if (this_cpu_has_cap(ARM64_HAS_E0PD))
1867 sysreg_clear_set(tcr_el1, 0, TCR_E0PD1);
1869 #endif /* CONFIG_ARM64_E0PD */
1871 #ifdef CONFIG_ARM64_PSEUDO_NMI
1872 static bool enable_pseudo_nmi;
1874 static int __init early_enable_pseudo_nmi(char *p)
1876 return strtobool(p, &enable_pseudo_nmi);
1878 early_param("irqchip.gicv3_pseudo_nmi", early_enable_pseudo_nmi);
1880 static bool can_use_gic_priorities(const struct arm64_cpu_capabilities *entry,
1883 return enable_pseudo_nmi && has_useable_gicv3_cpuif(entry, scope);
1887 #ifdef CONFIG_ARM64_BTI
1888 static void bti_enable(const struct arm64_cpu_capabilities *__unused)
1891 * Use of X16/X17 for tail-calls and trampolines that jump to
1892 * function entry points using BR is a requirement for
1893 * marking binaries with GNU_PROPERTY_AARCH64_FEATURE_1_BTI.
1894 * So, be strict and forbid other BRs using other registers to
1895 * jump onto a PACIxSP instruction:
1897 sysreg_clear_set(sctlr_el1, 0, SCTLR_EL1_BT0 | SCTLR_EL1_BT1);
1900 #endif /* CONFIG_ARM64_BTI */
1902 #ifdef CONFIG_ARM64_MTE
1903 static void cpu_enable_mte(struct arm64_cpu_capabilities const *cap)
1905 sysreg_clear_set(sctlr_el1, 0, SCTLR_ELx_ATA | SCTLR_EL1_ATA0);
1910 * Clear the tags in the zero page. This needs to be done via the
1911 * linear map which has the Tagged attribute.
1913 if (!test_and_set_bit(PG_mte_tagged, &ZERO_PAGE(0)->flags))
1914 mte_clear_page_tags(lm_alias(empty_zero_page));
1916 kasan_init_hw_tags_cpu();
1918 #endif /* CONFIG_ARM64_MTE */
1920 static void elf_hwcap_fixup(void)
1922 #ifdef CONFIG_ARM64_ERRATUM_1742098
1923 if (cpus_have_const_cap(ARM64_WORKAROUND_1742098))
1924 compat_elf_hwcap2 &= ~COMPAT_HWCAP2_AES;
1925 #endif /* ARM64_ERRATUM_1742098 */
1929 static bool is_kvm_protected_mode(const struct arm64_cpu_capabilities *entry, int __unused)
1931 if (kvm_get_mode() != KVM_MODE_PROTECTED)
1934 if (is_kernel_in_hyp_mode()) {
1935 pr_warn("Protected KVM not available with VHE\n");
1941 #endif /* CONFIG_KVM */
1943 /* Internal helper functions to match cpu capability type */
1945 cpucap_late_cpu_optional(const struct arm64_cpu_capabilities *cap)
1947 return !!(cap->type & ARM64_CPUCAP_OPTIONAL_FOR_LATE_CPU);
1951 cpucap_late_cpu_permitted(const struct arm64_cpu_capabilities *cap)
1953 return !!(cap->type & ARM64_CPUCAP_PERMITTED_FOR_LATE_CPU);
1957 cpucap_panic_on_conflict(const struct arm64_cpu_capabilities *cap)
1959 return !!(cap->type & ARM64_CPUCAP_PANIC_ON_CONFLICT);
1962 static const struct arm64_cpu_capabilities arm64_features[] = {
1964 .desc = "GIC system register CPU interface",
1965 .capability = ARM64_HAS_SYSREG_GIC_CPUIF,
1966 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE,
1967 .matches = has_useable_gicv3_cpuif,
1968 .sys_reg = SYS_ID_AA64PFR0_EL1,
1969 .field_pos = ID_AA64PFR0_GIC_SHIFT,
1970 .sign = FTR_UNSIGNED,
1971 .min_field_value = 1,
1973 #ifdef CONFIG_ARM64_PAN
1975 .desc = "Privileged Access Never",
1976 .capability = ARM64_HAS_PAN,
1977 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1978 .matches = has_cpuid_feature,
1979 .sys_reg = SYS_ID_AA64MMFR1_EL1,
1980 .field_pos = ID_AA64MMFR1_PAN_SHIFT,
1981 .sign = FTR_UNSIGNED,
1982 .min_field_value = 1,
1983 .cpu_enable = cpu_enable_pan,
1985 #endif /* CONFIG_ARM64_PAN */
1986 #ifdef CONFIG_ARM64_EPAN
1988 .desc = "Enhanced Privileged Access Never",
1989 .capability = ARM64_HAS_EPAN,
1990 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1991 .matches = has_cpuid_feature,
1992 .sys_reg = SYS_ID_AA64MMFR1_EL1,
1993 .field_pos = ID_AA64MMFR1_PAN_SHIFT,
1994 .sign = FTR_UNSIGNED,
1995 .min_field_value = 3,
1997 #endif /* CONFIG_ARM64_EPAN */
1998 #ifdef CONFIG_ARM64_LSE_ATOMICS
2000 .desc = "LSE atomic instructions",
2001 .capability = ARM64_HAS_LSE_ATOMICS,
2002 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2003 .matches = has_cpuid_feature,
2004 .sys_reg = SYS_ID_AA64ISAR0_EL1,
2005 .field_pos = ID_AA64ISAR0_ATOMICS_SHIFT,
2006 .sign = FTR_UNSIGNED,
2007 .min_field_value = 2,
2009 #endif /* CONFIG_ARM64_LSE_ATOMICS */
2011 .desc = "Software prefetching using PRFM",
2012 .capability = ARM64_HAS_NO_HW_PREFETCH,
2013 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
2014 .matches = has_no_hw_prefetch,
2017 .desc = "Virtualization Host Extensions",
2018 .capability = ARM64_HAS_VIRT_HOST_EXTN,
2019 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE,
2020 .matches = runs_at_el2,
2021 .cpu_enable = cpu_copy_el2regs,
2024 .capability = ARM64_HAS_32BIT_EL0_DO_NOT_USE,
2025 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2026 .matches = has_32bit_el0,
2027 .sys_reg = SYS_ID_AA64PFR0_EL1,
2028 .sign = FTR_UNSIGNED,
2029 .field_pos = ID_AA64PFR0_EL0_SHIFT,
2030 .min_field_value = ID_AA64PFR0_ELx_32BIT_64BIT,
2034 .desc = "32-bit EL1 Support",
2035 .capability = ARM64_HAS_32BIT_EL1,
2036 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2037 .matches = has_cpuid_feature,
2038 .sys_reg = SYS_ID_AA64PFR0_EL1,
2039 .sign = FTR_UNSIGNED,
2040 .field_pos = ID_AA64PFR0_EL1_SHIFT,
2041 .min_field_value = ID_AA64PFR0_ELx_32BIT_64BIT,
2044 .desc = "Protected KVM",
2045 .capability = ARM64_KVM_PROTECTED_MODE,
2046 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2047 .matches = is_kvm_protected_mode,
2051 .desc = "Kernel page table isolation (KPTI)",
2052 .capability = ARM64_UNMAP_KERNEL_AT_EL0,
2053 .type = ARM64_CPUCAP_BOOT_RESTRICTED_CPU_LOCAL_FEATURE,
2055 * The ID feature fields below are used to indicate that
2056 * the CPU doesn't need KPTI. See unmap_kernel_at_el0 for
2059 .sys_reg = SYS_ID_AA64PFR0_EL1,
2060 .field_pos = ID_AA64PFR0_CSV3_SHIFT,
2061 .min_field_value = 1,
2062 .matches = unmap_kernel_at_el0,
2063 .cpu_enable = kpti_install_ng_mappings,
2066 /* FP/SIMD is not implemented */
2067 .capability = ARM64_HAS_NO_FPSIMD,
2068 .type = ARM64_CPUCAP_BOOT_RESTRICTED_CPU_LOCAL_FEATURE,
2069 .min_field_value = 0,
2070 .matches = has_no_fpsimd,
2072 #ifdef CONFIG_ARM64_PMEM
2074 .desc = "Data cache clean to Point of Persistence",
2075 .capability = ARM64_HAS_DCPOP,
2076 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2077 .matches = has_cpuid_feature,
2078 .sys_reg = SYS_ID_AA64ISAR1_EL1,
2079 .field_pos = ID_AA64ISAR1_DPB_SHIFT,
2080 .min_field_value = 1,
2083 .desc = "Data cache clean to Point of Deep Persistence",
2084 .capability = ARM64_HAS_DCPODP,
2085 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2086 .matches = has_cpuid_feature,
2087 .sys_reg = SYS_ID_AA64ISAR1_EL1,
2088 .sign = FTR_UNSIGNED,
2089 .field_pos = ID_AA64ISAR1_DPB_SHIFT,
2090 .min_field_value = 2,
2093 #ifdef CONFIG_ARM64_SVE
2095 .desc = "Scalable Vector Extension",
2096 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2097 .capability = ARM64_SVE,
2098 .sys_reg = SYS_ID_AA64PFR0_EL1,
2099 .sign = FTR_UNSIGNED,
2100 .field_pos = ID_AA64PFR0_SVE_SHIFT,
2101 .min_field_value = ID_AA64PFR0_SVE,
2102 .matches = has_cpuid_feature,
2103 .cpu_enable = sve_kernel_enable,
2105 #endif /* CONFIG_ARM64_SVE */
2106 #ifdef CONFIG_ARM64_RAS_EXTN
2108 .desc = "RAS Extension Support",
2109 .capability = ARM64_HAS_RAS_EXTN,
2110 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2111 .matches = has_cpuid_feature,
2112 .sys_reg = SYS_ID_AA64PFR0_EL1,
2113 .sign = FTR_UNSIGNED,
2114 .field_pos = ID_AA64PFR0_RAS_SHIFT,
2115 .min_field_value = ID_AA64PFR0_RAS_V1,
2116 .cpu_enable = cpu_clear_disr,
2118 #endif /* CONFIG_ARM64_RAS_EXTN */
2119 #ifdef CONFIG_ARM64_AMU_EXTN
2122 * The feature is enabled by default if CONFIG_ARM64_AMU_EXTN=y.
2123 * Therefore, don't provide .desc as we don't want the detection
2124 * message to be shown until at least one CPU is detected to
2125 * support the feature.
2127 .capability = ARM64_HAS_AMU_EXTN,
2128 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
2130 .sys_reg = SYS_ID_AA64PFR0_EL1,
2131 .sign = FTR_UNSIGNED,
2132 .field_pos = ID_AA64PFR0_AMU_SHIFT,
2133 .min_field_value = ID_AA64PFR0_AMU,
2134 .cpu_enable = cpu_amu_enable,
2136 #endif /* CONFIG_ARM64_AMU_EXTN */
2138 .desc = "Data cache clean to the PoU not required for I/D coherence",
2139 .capability = ARM64_HAS_CACHE_IDC,
2140 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2141 .matches = has_cache_idc,
2142 .cpu_enable = cpu_emulate_effective_ctr,
2145 .desc = "Instruction cache invalidation not required for I/D coherence",
2146 .capability = ARM64_HAS_CACHE_DIC,
2147 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2148 .matches = has_cache_dic,
2151 .desc = "Stage-2 Force Write-Back",
2152 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2153 .capability = ARM64_HAS_STAGE2_FWB,
2154 .sys_reg = SYS_ID_AA64MMFR2_EL1,
2155 .sign = FTR_UNSIGNED,
2156 .field_pos = ID_AA64MMFR2_FWB_SHIFT,
2157 .min_field_value = 1,
2158 .matches = has_cpuid_feature,
2159 .cpu_enable = cpu_has_fwb,
2162 .desc = "ARMv8.4 Translation Table Level",
2163 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2164 .capability = ARM64_HAS_ARMv8_4_TTL,
2165 .sys_reg = SYS_ID_AA64MMFR2_EL1,
2166 .sign = FTR_UNSIGNED,
2167 .field_pos = ID_AA64MMFR2_TTL_SHIFT,
2168 .min_field_value = 1,
2169 .matches = has_cpuid_feature,
2172 .desc = "TLB range maintenance instructions",
2173 .capability = ARM64_HAS_TLB_RANGE,
2174 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2175 .matches = has_cpuid_feature,
2176 .sys_reg = SYS_ID_AA64ISAR0_EL1,
2177 .field_pos = ID_AA64ISAR0_TLB_SHIFT,
2178 .sign = FTR_UNSIGNED,
2179 .min_field_value = ID_AA64ISAR0_TLB_RANGE,
2181 #ifdef CONFIG_ARM64_HW_AFDBM
2184 * Since we turn this on always, we don't want the user to
2185 * think that the feature is available when it may not be.
2186 * So hide the description.
2188 * .desc = "Hardware pagetable Dirty Bit Management",
2191 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
2192 .capability = ARM64_HW_DBM,
2193 .sys_reg = SYS_ID_AA64MMFR1_EL1,
2194 .sign = FTR_UNSIGNED,
2195 .field_pos = ID_AA64MMFR1_HADBS_SHIFT,
2196 .min_field_value = 2,
2197 .matches = has_hw_dbm,
2198 .cpu_enable = cpu_enable_hw_dbm,
2202 .desc = "CRC32 instructions",
2203 .capability = ARM64_HAS_CRC32,
2204 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2205 .matches = has_cpuid_feature,
2206 .sys_reg = SYS_ID_AA64ISAR0_EL1,
2207 .field_pos = ID_AA64ISAR0_CRC32_SHIFT,
2208 .min_field_value = 1,
2211 .desc = "Speculative Store Bypassing Safe (SSBS)",
2212 .capability = ARM64_SSBS,
2213 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2214 .matches = has_cpuid_feature,
2215 .sys_reg = SYS_ID_AA64PFR1_EL1,
2216 .field_pos = ID_AA64PFR1_SSBS_SHIFT,
2217 .sign = FTR_UNSIGNED,
2218 .min_field_value = ID_AA64PFR1_SSBS_PSTATE_ONLY,
2220 #ifdef CONFIG_ARM64_CNP
2222 .desc = "Common not Private translations",
2223 .capability = ARM64_HAS_CNP,
2224 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2225 .matches = has_useable_cnp,
2226 .sys_reg = SYS_ID_AA64MMFR2_EL1,
2227 .sign = FTR_UNSIGNED,
2228 .field_pos = ID_AA64MMFR2_CNP_SHIFT,
2229 .min_field_value = 1,
2230 .cpu_enable = cpu_enable_cnp,
2234 .desc = "Speculation barrier (SB)",
2235 .capability = ARM64_HAS_SB,
2236 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2237 .matches = has_cpuid_feature,
2238 .sys_reg = SYS_ID_AA64ISAR1_EL1,
2239 .field_pos = ID_AA64ISAR1_SB_SHIFT,
2240 .sign = FTR_UNSIGNED,
2241 .min_field_value = 1,
2243 #ifdef CONFIG_ARM64_PTR_AUTH
2245 .desc = "Address authentication (architected algorithm)",
2246 .capability = ARM64_HAS_ADDRESS_AUTH_ARCH,
2247 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE,
2248 .sys_reg = SYS_ID_AA64ISAR1_EL1,
2249 .sign = FTR_UNSIGNED,
2250 .field_pos = ID_AA64ISAR1_APA_SHIFT,
2251 .min_field_value = ID_AA64ISAR1_APA_ARCHITECTED,
2252 .matches = has_address_auth_cpucap,
2255 .desc = "Address authentication (IMP DEF algorithm)",
2256 .capability = ARM64_HAS_ADDRESS_AUTH_IMP_DEF,
2257 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE,
2258 .sys_reg = SYS_ID_AA64ISAR1_EL1,
2259 .sign = FTR_UNSIGNED,
2260 .field_pos = ID_AA64ISAR1_API_SHIFT,
2261 .min_field_value = ID_AA64ISAR1_API_IMP_DEF,
2262 .matches = has_address_auth_cpucap,
2265 .capability = ARM64_HAS_ADDRESS_AUTH,
2266 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE,
2267 .matches = has_address_auth_metacap,
2270 .desc = "Generic authentication (architected algorithm)",
2271 .capability = ARM64_HAS_GENERIC_AUTH_ARCH,
2272 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2273 .sys_reg = SYS_ID_AA64ISAR1_EL1,
2274 .sign = FTR_UNSIGNED,
2275 .field_pos = ID_AA64ISAR1_GPA_SHIFT,
2276 .min_field_value = ID_AA64ISAR1_GPA_ARCHITECTED,
2277 .matches = has_cpuid_feature,
2280 .desc = "Generic authentication (IMP DEF algorithm)",
2281 .capability = ARM64_HAS_GENERIC_AUTH_IMP_DEF,
2282 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2283 .sys_reg = SYS_ID_AA64ISAR1_EL1,
2284 .sign = FTR_UNSIGNED,
2285 .field_pos = ID_AA64ISAR1_GPI_SHIFT,
2286 .min_field_value = ID_AA64ISAR1_GPI_IMP_DEF,
2287 .matches = has_cpuid_feature,
2290 .capability = ARM64_HAS_GENERIC_AUTH,
2291 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2292 .matches = has_generic_auth,
2294 #endif /* CONFIG_ARM64_PTR_AUTH */
2295 #ifdef CONFIG_ARM64_PSEUDO_NMI
2298 * Depends on having GICv3
2300 .desc = "IRQ priority masking",
2301 .capability = ARM64_HAS_IRQ_PRIO_MASKING,
2302 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE,
2303 .matches = can_use_gic_priorities,
2304 .sys_reg = SYS_ID_AA64PFR0_EL1,
2305 .field_pos = ID_AA64PFR0_GIC_SHIFT,
2306 .sign = FTR_UNSIGNED,
2307 .min_field_value = 1,
2310 #ifdef CONFIG_ARM64_E0PD
2313 .capability = ARM64_HAS_E0PD,
2314 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2315 .sys_reg = SYS_ID_AA64MMFR2_EL1,
2316 .sign = FTR_UNSIGNED,
2317 .field_pos = ID_AA64MMFR2_E0PD_SHIFT,
2318 .matches = has_cpuid_feature,
2319 .min_field_value = 1,
2320 .cpu_enable = cpu_enable_e0pd,
2323 #ifdef CONFIG_ARCH_RANDOM
2325 .desc = "Random Number Generator",
2326 .capability = ARM64_HAS_RNG,
2327 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2328 .matches = has_cpuid_feature,
2329 .sys_reg = SYS_ID_AA64ISAR0_EL1,
2330 .field_pos = ID_AA64ISAR0_RNDR_SHIFT,
2331 .sign = FTR_UNSIGNED,
2332 .min_field_value = 1,
2335 #ifdef CONFIG_ARM64_BTI
2337 .desc = "Branch Target Identification",
2338 .capability = ARM64_BTI,
2339 #ifdef CONFIG_ARM64_BTI_KERNEL
2340 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE,
2342 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2344 .matches = has_cpuid_feature,
2345 .cpu_enable = bti_enable,
2346 .sys_reg = SYS_ID_AA64PFR1_EL1,
2347 .field_pos = ID_AA64PFR1_BT_SHIFT,
2348 .min_field_value = ID_AA64PFR1_BT_BTI,
2349 .sign = FTR_UNSIGNED,
2352 #ifdef CONFIG_ARM64_MTE
2354 .desc = "Memory Tagging Extension",
2355 .capability = ARM64_MTE,
2356 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE,
2357 .matches = has_cpuid_feature,
2358 .sys_reg = SYS_ID_AA64PFR1_EL1,
2359 .field_pos = ID_AA64PFR1_MTE_SHIFT,
2360 .min_field_value = ID_AA64PFR1_MTE,
2361 .sign = FTR_UNSIGNED,
2362 .cpu_enable = cpu_enable_mte,
2364 #endif /* CONFIG_ARM64_MTE */
2366 .desc = "RCpc load-acquire (LDAPR)",
2367 .capability = ARM64_HAS_LDAPR,
2368 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2369 .sys_reg = SYS_ID_AA64ISAR1_EL1,
2370 .sign = FTR_UNSIGNED,
2371 .field_pos = ID_AA64ISAR1_LRCPC_SHIFT,
2372 .matches = has_cpuid_feature,
2373 .min_field_value = 1,
2378 #define HWCAP_CPUID_MATCH(reg, field, s, min_value) \
2379 .matches = has_cpuid_feature, \
2381 .field_pos = field, \
2383 .min_field_value = min_value,
2385 #define __HWCAP_CAP(name, cap_type, cap) \
2387 .type = ARM64_CPUCAP_SYSTEM_FEATURE, \
2388 .hwcap_type = cap_type, \
2391 #define HWCAP_CAP(reg, field, s, min_value, cap_type, cap) \
2393 __HWCAP_CAP(#cap, cap_type, cap) \
2394 HWCAP_CPUID_MATCH(reg, field, s, min_value) \
2397 #define HWCAP_MULTI_CAP(list, cap_type, cap) \
2399 __HWCAP_CAP(#cap, cap_type, cap) \
2400 .matches = cpucap_multi_entry_cap_matches, \
2401 .match_list = list, \
2404 #define HWCAP_CAP_MATCH(match, cap_type, cap) \
2406 __HWCAP_CAP(#cap, cap_type, cap) \
2410 #ifdef CONFIG_ARM64_PTR_AUTH
2411 static const struct arm64_cpu_capabilities ptr_auth_hwcap_addr_matches[] = {
2413 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_APA_SHIFT,
2414 FTR_UNSIGNED, ID_AA64ISAR1_APA_ARCHITECTED)
2417 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_API_SHIFT,
2418 FTR_UNSIGNED, ID_AA64ISAR1_API_IMP_DEF)
2423 static const struct arm64_cpu_capabilities ptr_auth_hwcap_gen_matches[] = {
2425 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_GPA_SHIFT,
2426 FTR_UNSIGNED, ID_AA64ISAR1_GPA_ARCHITECTED)
2429 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_GPI_SHIFT,
2430 FTR_UNSIGNED, ID_AA64ISAR1_GPI_IMP_DEF)
2436 static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = {
2437 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_PMULL),
2438 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_AES),
2439 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA1_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SHA1),
2440 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA2_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SHA2),
2441 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA2_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_SHA512),
2442 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_CRC32_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_CRC32),
2443 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_ATOMICS_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_ATOMICS),
2444 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_RDM_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDRDM),
2445 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA3_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SHA3),
2446 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SM3_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SM3),
2447 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SM4_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SM4),
2448 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_DP_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDDP),
2449 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_FHM_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDFHM),
2450 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_TS_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FLAGM),
2451 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_TS_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_FLAGM2),
2452 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_RNDR_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_RNG),
2453 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, FTR_SIGNED, 0, CAP_HWCAP, KERNEL_HWCAP_FP),
2454 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FPHP),
2455 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, FTR_SIGNED, 0, CAP_HWCAP, KERNEL_HWCAP_ASIMD),
2456 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDHP),
2457 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_DIT_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_DIT),
2458 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_DPB_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_DCPOP),
2459 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_DPB_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_DCPODP),
2460 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_JSCVT_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_JSCVT),
2461 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_FCMA_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FCMA),
2462 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_LRCPC_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_LRCPC),
2463 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_LRCPC_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_ILRCPC),
2464 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_FRINTTS_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FRINT),
2465 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_SB_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SB),
2466 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_BF16_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_BF16),
2467 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_DGH_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_DGH),
2468 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_I8MM_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_I8MM),
2469 HWCAP_CAP(SYS_ID_AA64MMFR2_EL1, ID_AA64MMFR2_AT_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_USCAT),
2470 #ifdef CONFIG_ARM64_SVE
2471 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_SVE_SHIFT, FTR_UNSIGNED, ID_AA64PFR0_SVE, CAP_HWCAP, KERNEL_HWCAP_SVE),
2472 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_SVEVER_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_SVEVER_SVE2, CAP_HWCAP, KERNEL_HWCAP_SVE2),
2473 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_AES_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_AES, CAP_HWCAP, KERNEL_HWCAP_SVEAES),
2474 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_AES_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_AES_PMULL, CAP_HWCAP, KERNEL_HWCAP_SVEPMULL),
2475 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_BITPERM_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_BITPERM, CAP_HWCAP, KERNEL_HWCAP_SVEBITPERM),
2476 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_BF16_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_BF16, CAP_HWCAP, KERNEL_HWCAP_SVEBF16),
2477 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_SHA3_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_SHA3, CAP_HWCAP, KERNEL_HWCAP_SVESHA3),
2478 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_SM4_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_SM4, CAP_HWCAP, KERNEL_HWCAP_SVESM4),
2479 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_I8MM_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_I8MM, CAP_HWCAP, KERNEL_HWCAP_SVEI8MM),
2480 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_F32MM_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_F32MM, CAP_HWCAP, KERNEL_HWCAP_SVEF32MM),
2481 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_F64MM_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_F64MM, CAP_HWCAP, KERNEL_HWCAP_SVEF64MM),
2483 HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_SSBS_SHIFT, FTR_UNSIGNED, ID_AA64PFR1_SSBS_PSTATE_INSNS, CAP_HWCAP, KERNEL_HWCAP_SSBS),
2484 #ifdef CONFIG_ARM64_BTI
2485 HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_BT_SHIFT, FTR_UNSIGNED, ID_AA64PFR1_BT_BTI, CAP_HWCAP, KERNEL_HWCAP_BTI),
2487 #ifdef CONFIG_ARM64_PTR_AUTH
2488 HWCAP_MULTI_CAP(ptr_auth_hwcap_addr_matches, CAP_HWCAP, KERNEL_HWCAP_PACA),
2489 HWCAP_MULTI_CAP(ptr_auth_hwcap_gen_matches, CAP_HWCAP, KERNEL_HWCAP_PACG),
2491 #ifdef CONFIG_ARM64_MTE
2492 HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_MTE_SHIFT, FTR_UNSIGNED, ID_AA64PFR1_MTE, CAP_HWCAP, KERNEL_HWCAP_MTE),
2493 #endif /* CONFIG_ARM64_MTE */
2494 HWCAP_CAP(SYS_ID_AA64MMFR0_EL1, ID_AA64MMFR0_ECV_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ECV),
2495 HWCAP_CAP(SYS_ID_AA64MMFR1_EL1, ID_AA64MMFR1_AFP_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_AFP),
2496 HWCAP_CAP(SYS_ID_AA64ISAR2_EL1, ID_AA64ISAR2_RPRES_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_RPRES),
2500 #ifdef CONFIG_COMPAT
2501 static bool compat_has_neon(const struct arm64_cpu_capabilities *cap, int scope)
2504 * Check that all of MVFR1_EL1.{SIMDSP, SIMDInt, SIMDLS} are available,
2505 * in line with that of arm32 as in vfp_init(). We make sure that the
2506 * check is future proof, by making sure value is non-zero.
2510 WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible());
2511 if (scope == SCOPE_SYSTEM)
2512 mvfr1 = read_sanitised_ftr_reg(SYS_MVFR1_EL1);
2514 mvfr1 = read_sysreg_s(SYS_MVFR1_EL1);
2516 return cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_SIMDSP_SHIFT) &&
2517 cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_SIMDINT_SHIFT) &&
2518 cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_SIMDLS_SHIFT);
2522 static const struct arm64_cpu_capabilities compat_elf_hwcaps[] = {
2523 #ifdef CONFIG_COMPAT
2524 HWCAP_CAP_MATCH(compat_has_neon, CAP_COMPAT_HWCAP, COMPAT_HWCAP_NEON),
2525 HWCAP_CAP(SYS_MVFR1_EL1, MVFR1_SIMDFMAC_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFPv4),
2526 /* Arm v8 mandates MVFR0.FPDP == {0, 2}. So, piggy back on this for the presence of VFP support */
2527 HWCAP_CAP(SYS_MVFR0_EL1, MVFR0_FPDP_SHIFT, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFP),
2528 HWCAP_CAP(SYS_MVFR0_EL1, MVFR0_FPDP_SHIFT, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFPv3),
2529 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_PMULL),
2530 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_AES),
2531 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA1_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA1),
2532 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA2_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA2),
2533 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_CRC32_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_CRC32),
2538 static void cap_set_elf_hwcap(const struct arm64_cpu_capabilities *cap)
2540 switch (cap->hwcap_type) {
2542 cpu_set_feature(cap->hwcap);
2544 #ifdef CONFIG_COMPAT
2545 case CAP_COMPAT_HWCAP:
2546 compat_elf_hwcap |= (u32)cap->hwcap;
2548 case CAP_COMPAT_HWCAP2:
2549 compat_elf_hwcap2 |= (u32)cap->hwcap;
2558 /* Check if we have a particular HWCAP enabled */
2559 static bool cpus_have_elf_hwcap(const struct arm64_cpu_capabilities *cap)
2563 switch (cap->hwcap_type) {
2565 rc = cpu_have_feature(cap->hwcap);
2567 #ifdef CONFIG_COMPAT
2568 case CAP_COMPAT_HWCAP:
2569 rc = (compat_elf_hwcap & (u32)cap->hwcap) != 0;
2571 case CAP_COMPAT_HWCAP2:
2572 rc = (compat_elf_hwcap2 & (u32)cap->hwcap) != 0;
2583 static void setup_elf_hwcaps(const struct arm64_cpu_capabilities *hwcaps)
2585 /* We support emulation of accesses to CPU ID feature registers */
2586 cpu_set_named_feature(CPUID);
2587 for (; hwcaps->matches; hwcaps++)
2588 if (hwcaps->matches(hwcaps, cpucap_default_scope(hwcaps)))
2589 cap_set_elf_hwcap(hwcaps);
2592 static void update_cpu_capabilities(u16 scope_mask)
2595 const struct arm64_cpu_capabilities *caps;
2597 scope_mask &= ARM64_CPUCAP_SCOPE_MASK;
2598 for (i = 0; i < ARM64_NCAPS; i++) {
2599 caps = cpu_hwcaps_ptrs[i];
2600 if (!caps || !(caps->type & scope_mask) ||
2601 cpus_have_cap(caps->capability) ||
2602 !caps->matches(caps, cpucap_default_scope(caps)))
2606 pr_info("detected: %s\n", caps->desc);
2607 cpus_set_cap(caps->capability);
2609 if ((scope_mask & SCOPE_BOOT_CPU) && (caps->type & SCOPE_BOOT_CPU))
2610 set_bit(caps->capability, boot_capabilities);
2615 * Enable all the available capabilities on this CPU. The capabilities
2616 * with BOOT_CPU scope are handled separately and hence skipped here.
2618 static int cpu_enable_non_boot_scope_capabilities(void *__unused)
2621 u16 non_boot_scope = SCOPE_ALL & ~SCOPE_BOOT_CPU;
2623 for_each_available_cap(i) {
2624 const struct arm64_cpu_capabilities *cap = cpu_hwcaps_ptrs[i];
2629 if (!(cap->type & non_boot_scope))
2632 if (cap->cpu_enable)
2633 cap->cpu_enable(cap);
2639 * Run through the enabled capabilities and enable() it on all active
2642 static void __init enable_cpu_capabilities(u16 scope_mask)
2645 const struct arm64_cpu_capabilities *caps;
2648 scope_mask &= ARM64_CPUCAP_SCOPE_MASK;
2649 boot_scope = !!(scope_mask & SCOPE_BOOT_CPU);
2651 for (i = 0; i < ARM64_NCAPS; i++) {
2654 caps = cpu_hwcaps_ptrs[i];
2655 if (!caps || !(caps->type & scope_mask))
2657 num = caps->capability;
2658 if (!cpus_have_cap(num))
2661 /* Ensure cpus_have_const_cap(num) works */
2662 static_branch_enable(&cpu_hwcap_keys[num]);
2664 if (boot_scope && caps->cpu_enable)
2666 * Capabilities with SCOPE_BOOT_CPU scope are finalised
2667 * before any secondary CPU boots. Thus, each secondary
2668 * will enable the capability as appropriate via
2669 * check_local_cpu_capabilities(). The only exception is
2670 * the boot CPU, for which the capability must be
2671 * enabled here. This approach avoids costly
2672 * stop_machine() calls for this case.
2674 caps->cpu_enable(caps);
2678 * For all non-boot scope capabilities, use stop_machine()
2679 * as it schedules the work allowing us to modify PSTATE,
2680 * instead of on_each_cpu() which uses an IPI, giving us a
2681 * PSTATE that disappears when we return.
2684 stop_machine(cpu_enable_non_boot_scope_capabilities,
2685 NULL, cpu_online_mask);
2689 * Run through the list of capabilities to check for conflicts.
2690 * If the system has already detected a capability, take necessary
2691 * action on this CPU.
2693 static void verify_local_cpu_caps(u16 scope_mask)
2696 bool cpu_has_cap, system_has_cap;
2697 const struct arm64_cpu_capabilities *caps;
2699 scope_mask &= ARM64_CPUCAP_SCOPE_MASK;
2701 for (i = 0; i < ARM64_NCAPS; i++) {
2702 caps = cpu_hwcaps_ptrs[i];
2703 if (!caps || !(caps->type & scope_mask))
2706 cpu_has_cap = caps->matches(caps, SCOPE_LOCAL_CPU);
2707 system_has_cap = cpus_have_cap(caps->capability);
2709 if (system_has_cap) {
2711 * Check if the new CPU misses an advertised feature,
2712 * which is not safe to miss.
2714 if (!cpu_has_cap && !cpucap_late_cpu_optional(caps))
2717 * We have to issue cpu_enable() irrespective of
2718 * whether the CPU has it or not, as it is enabeld
2719 * system wide. It is upto the call back to take
2720 * appropriate action on this CPU.
2722 if (caps->cpu_enable)
2723 caps->cpu_enable(caps);
2726 * Check if the CPU has this capability if it isn't
2727 * safe to have when the system doesn't.
2729 if (cpu_has_cap && !cpucap_late_cpu_permitted(caps))
2734 if (i < ARM64_NCAPS) {
2735 pr_crit("CPU%d: Detected conflict for capability %d (%s), System: %d, CPU: %d\n",
2736 smp_processor_id(), caps->capability,
2737 caps->desc, system_has_cap, cpu_has_cap);
2739 if (cpucap_panic_on_conflict(caps))
2747 * Check for CPU features that are used in early boot
2748 * based on the Boot CPU value.
2750 static void check_early_cpu_features(void)
2752 verify_cpu_asid_bits();
2754 verify_local_cpu_caps(SCOPE_BOOT_CPU);
2758 __verify_local_elf_hwcaps(const struct arm64_cpu_capabilities *caps)
2761 for (; caps->matches; caps++)
2762 if (cpus_have_elf_hwcap(caps) && !caps->matches(caps, SCOPE_LOCAL_CPU)) {
2763 pr_crit("CPU%d: missing HWCAP: %s\n",
2764 smp_processor_id(), caps->desc);
2769 static void verify_local_elf_hwcaps(void)
2771 __verify_local_elf_hwcaps(arm64_elf_hwcaps);
2773 if (id_aa64pfr0_32bit_el0(read_cpuid(ID_AA64PFR0_EL1)))
2774 __verify_local_elf_hwcaps(compat_elf_hwcaps);
2777 static void verify_sve_features(void)
2779 u64 safe_zcr = read_sanitised_ftr_reg(SYS_ZCR_EL1);
2780 u64 zcr = read_zcr_features();
2782 unsigned int safe_len = safe_zcr & ZCR_ELx_LEN_MASK;
2783 unsigned int len = zcr & ZCR_ELx_LEN_MASK;
2785 if (len < safe_len || sve_verify_vq_map()) {
2786 pr_crit("CPU%d: SVE: vector length support mismatch\n",
2787 smp_processor_id());
2791 /* Add checks on other ZCR bits here if necessary */
2794 static void verify_hyp_capabilities(void)
2796 u64 safe_mmfr1, mmfr0, mmfr1;
2797 int parange, ipa_max;
2798 unsigned int safe_vmid_bits, vmid_bits;
2800 if (!IS_ENABLED(CONFIG_KVM))
2803 safe_mmfr1 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR1_EL1);
2804 mmfr0 = read_cpuid(ID_AA64MMFR0_EL1);
2805 mmfr1 = read_cpuid(ID_AA64MMFR1_EL1);
2807 /* Verify VMID bits */
2808 safe_vmid_bits = get_vmid_bits(safe_mmfr1);
2809 vmid_bits = get_vmid_bits(mmfr1);
2810 if (vmid_bits < safe_vmid_bits) {
2811 pr_crit("CPU%d: VMID width mismatch\n", smp_processor_id());
2815 /* Verify IPA range */
2816 parange = cpuid_feature_extract_unsigned_field(mmfr0,
2817 ID_AA64MMFR0_PARANGE_SHIFT);
2818 ipa_max = id_aa64mmfr0_parange_to_phys_shift(parange);
2819 if (ipa_max < get_kvm_ipa_limit()) {
2820 pr_crit("CPU%d: IPA range mismatch\n", smp_processor_id());
2826 * Run through the enabled system capabilities and enable() it on this CPU.
2827 * The capabilities were decided based on the available CPUs at the boot time.
2828 * Any new CPU should match the system wide status of the capability. If the
2829 * new CPU doesn't have a capability which the system now has enabled, we
2830 * cannot do anything to fix it up and could cause unexpected failures. So
2833 static void verify_local_cpu_capabilities(void)
2836 * The capabilities with SCOPE_BOOT_CPU are checked from
2837 * check_early_cpu_features(), as they need to be verified
2838 * on all secondary CPUs.
2840 verify_local_cpu_caps(SCOPE_ALL & ~SCOPE_BOOT_CPU);
2841 verify_local_elf_hwcaps();
2843 if (system_supports_sve())
2844 verify_sve_features();
2846 if (is_hyp_mode_available())
2847 verify_hyp_capabilities();
2850 void check_local_cpu_capabilities(void)
2853 * All secondary CPUs should conform to the early CPU features
2854 * in use by the kernel based on boot CPU.
2856 check_early_cpu_features();
2859 * If we haven't finalised the system capabilities, this CPU gets
2860 * a chance to update the errata work arounds and local features.
2861 * Otherwise, this CPU should verify that it has all the system
2862 * advertised capabilities.
2864 if (!system_capabilities_finalized())
2865 update_cpu_capabilities(SCOPE_LOCAL_CPU);
2867 verify_local_cpu_capabilities();
2870 static void __init setup_boot_cpu_capabilities(void)
2872 /* Detect capabilities with either SCOPE_BOOT_CPU or SCOPE_LOCAL_CPU */
2873 update_cpu_capabilities(SCOPE_BOOT_CPU | SCOPE_LOCAL_CPU);
2874 /* Enable the SCOPE_BOOT_CPU capabilities alone right away */
2875 enable_cpu_capabilities(SCOPE_BOOT_CPU);
2878 bool this_cpu_has_cap(unsigned int n)
2880 if (!WARN_ON(preemptible()) && n < ARM64_NCAPS) {
2881 const struct arm64_cpu_capabilities *cap = cpu_hwcaps_ptrs[n];
2884 return cap->matches(cap, SCOPE_LOCAL_CPU);
2891 * This helper function is used in a narrow window when,
2892 * - The system wide safe registers are set with all the SMP CPUs and,
2893 * - The SYSTEM_FEATURE cpu_hwcaps may not have been set.
2894 * In all other cases cpus_have_{const_}cap() should be used.
2896 static bool __maybe_unused __system_matches_cap(unsigned int n)
2898 if (n < ARM64_NCAPS) {
2899 const struct arm64_cpu_capabilities *cap = cpu_hwcaps_ptrs[n];
2902 return cap->matches(cap, SCOPE_SYSTEM);
2907 void cpu_set_feature(unsigned int num)
2909 WARN_ON(num >= MAX_CPU_FEATURES);
2910 elf_hwcap |= BIT(num);
2912 EXPORT_SYMBOL_GPL(cpu_set_feature);
2914 bool cpu_have_feature(unsigned int num)
2916 WARN_ON(num >= MAX_CPU_FEATURES);
2917 return elf_hwcap & BIT(num);
2919 EXPORT_SYMBOL_GPL(cpu_have_feature);
2921 unsigned long cpu_get_elf_hwcap(void)
2924 * We currently only populate the first 32 bits of AT_HWCAP. Please
2925 * note that for userspace compatibility we guarantee that bits 62
2926 * and 63 will always be returned as 0.
2928 return lower_32_bits(elf_hwcap);
2931 unsigned long cpu_get_elf_hwcap2(void)
2933 return upper_32_bits(elf_hwcap);
2936 static void __init setup_system_capabilities(void)
2939 * We have finalised the system-wide safe feature
2940 * registers, finalise the capabilities that depend
2941 * on it. Also enable all the available capabilities,
2942 * that are not enabled already.
2944 update_cpu_capabilities(SCOPE_SYSTEM);
2945 enable_cpu_capabilities(SCOPE_ALL & ~SCOPE_BOOT_CPU);
2948 void __init setup_cpu_features(void)
2952 setup_system_capabilities();
2953 setup_elf_hwcaps(arm64_elf_hwcaps);
2955 if (system_supports_32bit_el0()) {
2956 setup_elf_hwcaps(compat_elf_hwcaps);
2960 if (system_uses_ttbr0_pan())
2961 pr_info("emulated: Privileged Access Never (PAN) using TTBR0_EL1 switching\n");
2964 minsigstksz_setup();
2966 /* Advertise that we have computed the system capabilities */
2967 finalize_system_capabilities();
2970 * Check for sane CTR_EL0.CWG value.
2972 cwg = cache_type_cwg();
2974 pr_warn("No Cache Writeback Granule information, assuming %d\n",
2978 static int enable_mismatched_32bit_el0(unsigned int cpu)
2981 * The first 32-bit-capable CPU we detected and so can no longer
2982 * be offlined by userspace. -1 indicates we haven't yet onlined
2983 * a 32-bit-capable CPU.
2985 static int lucky_winner = -1;
2987 struct cpuinfo_arm64 *info = &per_cpu(cpu_data, cpu);
2988 bool cpu_32bit = id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0);
2991 cpumask_set_cpu(cpu, cpu_32bit_el0_mask);
2992 static_branch_enable_cpuslocked(&arm64_mismatched_32bit_el0);
2995 if (cpumask_test_cpu(0, cpu_32bit_el0_mask) == cpu_32bit)
2998 if (lucky_winner >= 0)
3002 * We've detected a mismatch. We need to keep one of our CPUs with
3003 * 32-bit EL0 online so that is_cpu_allowed() doesn't end up rejecting
3004 * every CPU in the system for a 32-bit task.
3006 lucky_winner = cpu_32bit ? cpu : cpumask_any_and(cpu_32bit_el0_mask,
3008 get_cpu_device(lucky_winner)->offline_disabled = true;
3009 setup_elf_hwcaps(compat_elf_hwcaps);
3011 pr_info("Asymmetric 32-bit EL0 support detected on CPU %u; CPU hot-unplug disabled on CPU %u\n",
3016 static int __init init_32bit_el0_mask(void)
3018 if (!allow_mismatched_32bit_el0)
3021 if (!zalloc_cpumask_var(&cpu_32bit_el0_mask, GFP_KERNEL))
3024 return cpuhp_setup_state(CPUHP_AP_ONLINE_DYN,
3025 "arm64/mismatched_32bit_el0:online",
3026 enable_mismatched_32bit_el0, NULL);
3028 subsys_initcall_sync(init_32bit_el0_mask);
3030 static void __maybe_unused cpu_enable_cnp(struct arm64_cpu_capabilities const *cap)
3032 cpu_replace_ttbr1(lm_alias(swapper_pg_dir));
3036 * We emulate only the following system register space.
3037 * Op0 = 0x3, CRn = 0x0, Op1 = 0x0, CRm = [0, 4 - 7]
3038 * See Table C5-6 System instruction encodings for System register accesses,
3039 * ARMv8 ARM(ARM DDI 0487A.f) for more details.
3041 static inline bool __attribute_const__ is_emulated(u32 id)
3043 return (sys_reg_Op0(id) == 0x3 &&
3044 sys_reg_CRn(id) == 0x0 &&
3045 sys_reg_Op1(id) == 0x0 &&
3046 (sys_reg_CRm(id) == 0 ||
3047 ((sys_reg_CRm(id) >= 4) && (sys_reg_CRm(id) <= 7))));
3051 * With CRm == 0, reg should be one of :
3052 * MIDR_EL1, MPIDR_EL1 or REVIDR_EL1.
3054 static inline int emulate_id_reg(u32 id, u64 *valp)
3058 *valp = read_cpuid_id();
3061 *valp = SYS_MPIDR_SAFE_VAL;
3063 case SYS_REVIDR_EL1:
3064 /* IMPLEMENTATION DEFINED values are emulated with 0 */
3074 static int emulate_sys_reg(u32 id, u64 *valp)
3076 struct arm64_ftr_reg *regp;
3078 if (!is_emulated(id))
3081 if (sys_reg_CRm(id) == 0)
3082 return emulate_id_reg(id, valp);
3084 regp = get_arm64_ftr_reg_nowarn(id);
3086 *valp = arm64_ftr_reg_user_value(regp);
3089 * The untracked registers are either IMPLEMENTATION DEFINED
3090 * (e.g, ID_AFR0_EL1) or reserved RAZ.
3096 int do_emulate_mrs(struct pt_regs *regs, u32 sys_reg, u32 rt)
3101 rc = emulate_sys_reg(sys_reg, &val);
3103 pt_regs_write_reg(regs, rt, val);
3104 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE);
3109 bool try_emulate_mrs(struct pt_regs *regs, u32 insn)
3113 if (compat_user_mode(regs) || !aarch64_insn_is_mrs(insn))
3117 * sys_reg values are defined as used in mrs/msr instruction.
3118 * shift the imm value to get the encoding.
3120 sys_reg = (u32)aarch64_insn_decode_immediate(AARCH64_INSN_IMM_16, insn) << 5;
3121 rt = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RT, insn);
3122 return do_emulate_mrs(regs, sys_reg, rt) == 0;
3125 enum mitigation_state arm64_get_meltdown_state(void)
3127 if (__meltdown_safe)
3128 return SPECTRE_UNAFFECTED;
3130 if (arm64_kernel_unmapped_at_el0())
3131 return SPECTRE_MITIGATED;
3133 return SPECTRE_VULNERABLE;
3136 ssize_t cpu_show_meltdown(struct device *dev, struct device_attribute *attr,
3139 switch (arm64_get_meltdown_state()) {
3140 case SPECTRE_UNAFFECTED:
3141 return sprintf(buf, "Not affected\n");
3143 case SPECTRE_MITIGATED:
3144 return sprintf(buf, "Mitigation: PTI\n");
3147 return sprintf(buf, "Vulnerable\n");