arch/arm64/kernel/cpufeature.c

   1 /*
   2  * Contains CPU feature definitions
   3  *
   4  * Copyright (C) 2015 ARM Ltd.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  17  */
  18
  19 #define pr_fmt(fmt) "CPU features: " fmt
  20
  21 #include <linux/bsearch.h>
  22 #include <linux/cpumask.h>
  23 #include <linux/percpu.h>
  24 #include <linux/sort.h>
  25 #include <linux/stop_machine.h>
  26 #include <linux/types.h>
  27 #include <linux/mm.h>
  28 #include <linux/cpu.h>
  29
  30 #include <asm/cpu.h>
  31 #include <asm/cpufeature.h>
  32 #include <asm/cpu_ops.h>
  33 #include <asm/hwcap.h>
  34 #include <asm/mmu_context.h>
  35 #include <asm/processor.h>
  36 #include <asm/sysreg.h>
  37 #include <asm/traps.h>
  38 #include <asm/vectors.h>
  39 #include <asm/virt.h>
  40
  41 unsigned long elf_hwcap __read_mostly;
  42 EXPORT_SYMBOL_GPL(elf_hwcap);
  43
  44 #ifdef CONFIG_COMPAT
  45 #define COMPAT_ELF_HWCAP_DEFAULT        \
  46                                 (COMPAT_HWCAP_HALF|COMPAT_HWCAP_THUMB|\
  47                                  COMPAT_HWCAP_FAST_MULT|COMPAT_HWCAP_EDSP|\
  48                                  COMPAT_HWCAP_TLS|COMPAT_HWCAP_IDIV|\
  49                                  COMPAT_HWCAP_LPAE)
  50 unsigned int compat_elf_hwcap __read_mostly = COMPAT_ELF_HWCAP_DEFAULT;
  51 unsigned int compat_elf_hwcap2 __read_mostly;
  52 #endif
  53
  54 DECLARE_BITMAP(cpu_hwcaps, ARM64_NCAPS);
  55 EXPORT_SYMBOL(cpu_hwcaps);
  56
  57 DEFINE_PER_CPU_READ_MOSTLY(const char *, this_cpu_vector) = vectors;
  58
  59 static int dump_cpu_hwcaps(struct notifier_block *self, unsigned long v, void *p)
  60 {
  61         /* file-wide pr_fmt adds "CPU features: " prefix */
  62         pr_emerg("0x%*pb\n", ARM64_NCAPS, &cpu_hwcaps);
  63         return 0;
  64 }
  65
  66 static struct notifier_block cpu_hwcaps_notifier = {
  67         .notifier_call = dump_cpu_hwcaps
  68 };
  69
  70 static int __init register_cpu_hwcaps_dumper(void)
  71 {
  72         atomic_notifier_chain_register(&panic_notifier_list,
  73                                        &cpu_hwcaps_notifier);
  74         return 0;
  75 }
  76 __initcall(register_cpu_hwcaps_dumper);
  77
  78 DEFINE_STATIC_KEY_ARRAY_FALSE(cpu_hwcap_keys, ARM64_NCAPS);
  79 EXPORT_SYMBOL(cpu_hwcap_keys);
  80
  81 #define __ARM64_FTR_BITS(SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
  82         {                                               \
  83                 .sign = SIGNED,                         \
  84                 .visible = VISIBLE,                     \
  85                 .strict = STRICT,                       \
  86                 .type = TYPE,                           \
  87                 .shift = SHIFT,                         \
  88                 .width = WIDTH,                         \
  89                 .safe_val = SAFE_VAL,                   \
  90         }
  91
  92 /* Define a feature with unsigned values */
  93 #define ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
  94         __ARM64_FTR_BITS(FTR_UNSIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL)
  95
  96 /* Define a feature with a signed value */
  97 #define S_ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
  98         __ARM64_FTR_BITS(FTR_SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL)
  99
 100 #define ARM64_FTR_END                                   \
 101         {                                               \
 102                 .width = 0,                             \
 103         }
 104
 105 /* meta feature for alternatives */
 106 static bool __maybe_unused
 107 cpufeature_pan_not_uao(const struct arm64_cpu_capabilities *entry, int __unused);
 108
 109
 110 /*
 111  * NOTE: Any changes to the visibility of features should be kept in
 112  * sync with the documentation of the CPU feature register ABI.
 113  */
 114 static const struct arm64_ftr_bits ftr_id_aa64isar0[] = {
 115         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_TS_SHIFT, 4, 0),
 116         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_FHM_SHIFT, 4, 0),
 117         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_DP_SHIFT, 4, 0),
 118         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SM4_SHIFT, 4, 0),
 119         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SM3_SHIFT, 4, 0),
 120         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA3_SHIFT, 4, 0),
 121         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_RDM_SHIFT, 4, 0),
 122         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_ATOMICS_SHIFT, 4, 0),
 123         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_CRC32_SHIFT, 4, 0),
 124         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA2_SHIFT, 4, 0),
 125         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA1_SHIFT, 4, 0),
 126         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_AES_SHIFT, 4, 0),
 127         ARM64_FTR_END,
 128 };
 129
 130 static const struct arm64_ftr_bits ftr_id_aa64isar1[] = {
 131         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_LRCPC_SHIFT, 4, 0),
 132         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_FCMA_SHIFT, 4, 0),
 133         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_JSCVT_SHIFT, 4, 0),
 134         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_DPB_SHIFT, 4, 0),
 135         ARM64_FTR_END,
 136 };
 137
 138 static const struct arm64_ftr_bits ftr_id_aa64isar2[] = {
 139         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_AA64ISAR2_CLEARBHB_SHIFT, 4, 0),
 140         ARM64_FTR_END,
 141 };
 142
 143 static const struct arm64_ftr_bits ftr_id_aa64pfr0[] = {
 144         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_CSV3_SHIFT, 4, 0),
 145         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_CSV2_SHIFT, 4, 0),
 146         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_DIT_SHIFT, 4, 0),
 147         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_GIC_SHIFT, 4, 0),
 148         S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_ASIMD_SHIFT, 4, ID_AA64PFR0_ASIMD_NI),
 149         S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_FP_SHIFT, 4, ID_AA64PFR0_FP_NI),
 150         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL3_SHIFT, 4, 0),
 151         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL2_SHIFT, 4, 0),
 152         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_SHIFT, 4, ID_AA64PFR0_EL1_64BIT_ONLY),
 153         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL0_SHIFT, 4, ID_AA64PFR0_EL0_64BIT_ONLY),
 154         ARM64_FTR_END,
 155 };
 156
 157 static const struct arm64_ftr_bits ftr_id_aa64pfr1[] = {
 158         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_SSBS_SHIFT, 4, ID_AA64PFR1_SSBS_PSTATE_NI),
 159         ARM64_FTR_END,
 160 };
 161
 162 static const struct arm64_ftr_bits ftr_id_aa64mmfr0[] = {
 163         S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN4_SHIFT, 4, ID_AA64MMFR0_TGRAN4_NI),
 164         S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN64_SHIFT, 4, ID_AA64MMFR0_TGRAN64_NI),
 165         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN16_SHIFT, 4, ID_AA64MMFR0_TGRAN16_NI),
 166         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_BIGENDEL0_SHIFT, 4, 0),
 167         /* Linux shouldn't care about secure memory */
 168         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_SNSMEM_SHIFT, 4, 0),
 169         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_BIGENDEL_SHIFT, 4, 0),
 170         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_ASID_SHIFT, 4, 0),
 171         /*
 172          * Differing PARange is fine as long as all peripherals and memory are mapped
 173          * within the minimum PARange of all CPUs
 174          */
 175         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_PARANGE_SHIFT, 4, 0),
 176         ARM64_FTR_END,
 177 };
 178
 179 static const struct arm64_ftr_bits ftr_id_aa64mmfr1[] = {
 180         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_PAN_SHIFT, 4, 0),
 181         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_LOR_SHIFT, 4, 0),
 182         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_HPD_SHIFT, 4, 0),
 183         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_VHE_SHIFT, 4, 0),
 184         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_VMIDBITS_SHIFT, 4, 0),
 185         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_HADBS_SHIFT, 4, 0),
 186         ARM64_FTR_END,
 187 };
 188
 189 static const struct arm64_ftr_bits ftr_id_aa64mmfr2[] = {
 190         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_AT_SHIFT, 4, 0),
 191         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_LVA_SHIFT, 4, 0),
 192         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_IESB_SHIFT, 4, 0),
 193         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_LSM_SHIFT, 4, 0),
 194         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_UAO_SHIFT, 4, 0),
 195         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_CNP_SHIFT, 4, 0),
 196         ARM64_FTR_END,
 197 };
 198
 199 static const struct arm64_ftr_bits ftr_ctr[] = {
 200         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, 31, 1, 1),           /* RES1 */
 201         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, 29, 1, 1),      /* DIC */
 202         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, 28, 1, 1),      /* IDC */
 203         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, 24, 4, 0),     /* CWG */
 204         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, 20, 4, 0),     /* ERG */
 205         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_DMINLINE_SHIFT, 4, 1),
 206         /*
 207          * Linux can handle differing I-cache policies. Userspace JITs will
 208          * make use of *minLine.
 209          * If we have differing I-cache policies, report it as the weakest - VIPT.
 210          */
 211         ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_EXACT, 14, 2, ICACHE_POLICY_VIPT),       /* L1Ip */
 212         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_IMINLINE_SHIFT, 4, 0),
 213         ARM64_FTR_END,
 214 };
 215
 216 struct arm64_ftr_reg arm64_ftr_reg_ctrel0 = {
 217         .name           = "SYS_CTR_EL0",
 218         .ftr_bits       = ftr_ctr
 219 };
 220
 221 static const struct arm64_ftr_bits ftr_id_mmfr0[] = {
 222         S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0xf),   /* InnerShr */
 223         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0),       /* FCSE */
 224         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, 20, 4, 0),    /* AuxReg */
 225         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0),       /* TCM */
 226         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0),       /* ShareLvl */
 227         S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0xf),    /* OuterShr */
 228         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),        /* PMSA */
 229         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),        /* VMSA */
 230         ARM64_FTR_END,
 231 };
 232
 233 static const struct arm64_ftr_bits ftr_id_aa64dfr0[] = {
 234         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 36, 28, 0),
 235         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64DFR0_PMSVER_SHIFT, 4, 0),
 236         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_CTX_CMPS_SHIFT, 4, 0),
 237         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_WRPS_SHIFT, 4, 0),
 238         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_BRPS_SHIFT, 4, 0),
 239         /*
 240          * We can instantiate multiple PMU instances with different levels
 241          * of support.
 242          */
 243         S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64DFR0_PMUVER_SHIFT, 4, 0),
 244         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64DFR0_DEBUGVER_SHIFT, 4, 0x6),
 245         ARM64_FTR_END,
 246 };
 247
 248 static const struct arm64_ftr_bits ftr_mvfr2[] = {
 249         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),                /* FPMisc */
 250         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),                /* SIMDMisc */
 251         ARM64_FTR_END,
 252 };
 253
 254 static const struct arm64_ftr_bits ftr_dczid[] = {
 255         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, 4, 1, 1),            /* DZP */
 256         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),       /* BS */
 257         ARM64_FTR_END,
 258 };
 259
 260
 261 static const struct arm64_ftr_bits ftr_id_isar5[] = {
 262         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_RDM_SHIFT, 4, 0),
 263         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_CRC32_SHIFT, 4, 0),
 264         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SHA2_SHIFT, 4, 0),
 265         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SHA1_SHIFT, 4, 0),
 266         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_AES_SHIFT, 4, 0),
 267         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SEVL_SHIFT, 4, 0),
 268         ARM64_FTR_END,
 269 };
 270
 271 static const struct arm64_ftr_bits ftr_id_mmfr4[] = {
 272         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),        /* ac2 */
 273         ARM64_FTR_END,
 274 };
 275
 276 static const struct arm64_ftr_bits ftr_id_pfr0[] = {
 277         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0),               /* State3 */
 278         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0),                /* State2 */
 279         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),                /* State1 */
 280         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),                /* State0 */
 281         ARM64_FTR_END,
 282 };
 283
 284 static const struct arm64_ftr_bits ftr_id_dfr0[] = {
 285         /* [31:28] TraceFilt */
 286         S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0xf),   /* PerfMon */
 287         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0),
 288         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0),
 289         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0),
 290         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0),
 291         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),
 292         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),
 293         ARM64_FTR_END,
 294 };
 295
 296 /*
 297  * Common ftr bits for a 32bit register with all hidden, strict
 298  * attributes, with 4bit feature fields and a default safe value of
 299  * 0. Covers the following 32bit registers:
 300  * id_isar[0-4], id_mmfr[1-3], id_pfr1, mvfr[0-1]
 301  */
 302 static const struct arm64_ftr_bits ftr_generic_32bits[] = {
 303         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0),
 304         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0),
 305         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0),
 306         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0),
 307         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0),
 308         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0),
 309         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),
 310         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),
 311         ARM64_FTR_END,
 312 };
 313
 314 /* Table for a single 32bit feature value */
 315 static const struct arm64_ftr_bits ftr_single32[] = {
 316         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 0, 32, 0),
 317         ARM64_FTR_END,
 318 };
 319
 320 static const struct arm64_ftr_bits ftr_raz[] = {
 321         ARM64_FTR_END,
 322 };
 323
 324 #define ARM64_FTR_REG(id, table) {              \
 325         .sys_id = id,                           \
 326         .reg =  &(struct arm64_ftr_reg){        \
 327                 .name = #id,                    \
 328                 .ftr_bits = &((table)[0]),      \
 329         }}
 330
 331 static const struct __ftr_reg_entry {
 332         u32                     sys_id;
 333         struct arm64_ftr_reg    *reg;
 334 } arm64_ftr_regs[] = {
 335
 336         /* Op1 = 0, CRn = 0, CRm = 1 */
 337         ARM64_FTR_REG(SYS_ID_PFR0_EL1, ftr_id_pfr0),
 338         ARM64_FTR_REG(SYS_ID_PFR1_EL1, ftr_generic_32bits),
 339         ARM64_FTR_REG(SYS_ID_DFR0_EL1, ftr_id_dfr0),
 340         ARM64_FTR_REG(SYS_ID_MMFR0_EL1, ftr_id_mmfr0),
 341         ARM64_FTR_REG(SYS_ID_MMFR1_EL1, ftr_generic_32bits),
 342         ARM64_FTR_REG(SYS_ID_MMFR2_EL1, ftr_generic_32bits),
 343         ARM64_FTR_REG(SYS_ID_MMFR3_EL1, ftr_generic_32bits),
 344
 345         /* Op1 = 0, CRn = 0, CRm = 2 */
 346         ARM64_FTR_REG(SYS_ID_ISAR0_EL1, ftr_generic_32bits),
 347         ARM64_FTR_REG(SYS_ID_ISAR1_EL1, ftr_generic_32bits),
 348         ARM64_FTR_REG(SYS_ID_ISAR2_EL1, ftr_generic_32bits),
 349         ARM64_FTR_REG(SYS_ID_ISAR3_EL1, ftr_generic_32bits),
 350         ARM64_FTR_REG(SYS_ID_ISAR4_EL1, ftr_generic_32bits),
 351         ARM64_FTR_REG(SYS_ID_ISAR5_EL1, ftr_id_isar5),
 352         ARM64_FTR_REG(SYS_ID_MMFR4_EL1, ftr_id_mmfr4),
 353
 354         /* Op1 = 0, CRn = 0, CRm = 3 */
 355         ARM64_FTR_REG(SYS_MVFR0_EL1, ftr_generic_32bits),
 356         ARM64_FTR_REG(SYS_MVFR1_EL1, ftr_generic_32bits),
 357         ARM64_FTR_REG(SYS_MVFR2_EL1, ftr_mvfr2),
 358
 359         /* Op1 = 0, CRn = 0, CRm = 4 */
 360         ARM64_FTR_REG(SYS_ID_AA64PFR0_EL1, ftr_id_aa64pfr0),
 361         ARM64_FTR_REG(SYS_ID_AA64PFR1_EL1, ftr_id_aa64pfr1),
 362
 363         /* Op1 = 0, CRn = 0, CRm = 5 */
 364         ARM64_FTR_REG(SYS_ID_AA64DFR0_EL1, ftr_id_aa64dfr0),
 365         ARM64_FTR_REG(SYS_ID_AA64DFR1_EL1, ftr_raz),
 366
 367         /* Op1 = 0, CRn = 0, CRm = 6 */
 368         ARM64_FTR_REG(SYS_ID_AA64ISAR0_EL1, ftr_id_aa64isar0),
 369         ARM64_FTR_REG(SYS_ID_AA64ISAR1_EL1, ftr_id_aa64isar1),
 370         ARM64_FTR_REG(SYS_ID_AA64ISAR2_EL1, ftr_id_aa64isar2),
 371
 372         /* Op1 = 0, CRn = 0, CRm = 7 */
 373         ARM64_FTR_REG(SYS_ID_AA64MMFR0_EL1, ftr_id_aa64mmfr0),
 374         ARM64_FTR_REG(SYS_ID_AA64MMFR1_EL1, ftr_id_aa64mmfr1),
 375         ARM64_FTR_REG(SYS_ID_AA64MMFR2_EL1, ftr_id_aa64mmfr2),
 376
 377         /* Op1 = 3, CRn = 0, CRm = 0 */
 378         { SYS_CTR_EL0, &arm64_ftr_reg_ctrel0 },
 379         ARM64_FTR_REG(SYS_DCZID_EL0, ftr_dczid),
 380
 381         /* Op1 = 3, CRn = 14, CRm = 0 */
 382         ARM64_FTR_REG(SYS_CNTFRQ_EL0, ftr_single32),
 383 };
 384
 385 static int search_cmp_ftr_reg(const void *id, const void *regp)
 386 {
 387         return (int)(unsigned long)id - (int)((const struct __ftr_reg_entry *)regp)->sys_id;
 388 }
 389
 390 /*
 391  * get_arm64_ftr_reg - Lookup a feature register entry using its
 392  * sys_reg() encoding. With the array arm64_ftr_regs sorted in the
 393  * ascending order of sys_id , we use binary search to find a matching
 394  * entry.
 395  *
 396  * returns - Upon success,  matching ftr_reg entry for id.
 397  *         - NULL on failure. It is upto the caller to decide
 398  *           the impact of a failure.
 399  */
 400 static struct arm64_ftr_reg *get_arm64_ftr_reg(u32 sys_id)
 401 {
 402         const struct __ftr_reg_entry *ret;
 403
 404         ret = bsearch((const void *)(unsigned long)sys_id,
 405                         arm64_ftr_regs,
 406                         ARRAY_SIZE(arm64_ftr_regs),
 407                         sizeof(arm64_ftr_regs[0]),
 408                         search_cmp_ftr_reg);
 409         if (ret)
 410                 return ret->reg;
 411         return NULL;
 412 }
 413
 414 static u64 arm64_ftr_set_value(const struct arm64_ftr_bits *ftrp, s64 reg,
 415                                s64 ftr_val)
 416 {
 417         u64 mask = arm64_ftr_mask(ftrp);
 418
 419         reg &= ~mask;
 420         reg |= (ftr_val << ftrp->shift) & mask;
 421         return reg;
 422 }
 423
 424 static s64 arm64_ftr_safe_value(const struct arm64_ftr_bits *ftrp, s64 new,
 425                                 s64 cur)
 426 {
 427         s64 ret = 0;
 428
 429         switch (ftrp->type) {
 430         case FTR_EXACT:
 431                 ret = ftrp->safe_val;
 432                 break;
 433         case FTR_LOWER_SAFE:
 434                 ret = new < cur ? new : cur;
 435                 break;
 436         case FTR_HIGHER_OR_ZERO_SAFE:
 437                 if (!cur || !new)
 438                         break;
 439                 /* Fallthrough */
 440         case FTR_HIGHER_SAFE:
 441                 ret = new > cur ? new : cur;
 442                 break;
 443         default:
 444                 BUG();
 445         }
 446
 447         return ret;
 448 }
 449
 450 static void __init sort_ftr_regs(void)
 451 {
 452         int i;
 453
 454         /* Check that the array is sorted so that we can do the binary search */
 455         for (i = 1; i < ARRAY_SIZE(arm64_ftr_regs); i++)
 456                 BUG_ON(arm64_ftr_regs[i].sys_id < arm64_ftr_regs[i - 1].sys_id);
 457 }
 458
 459 /*
 460  * Initialise the CPU feature register from Boot CPU values.
 461  * Also initiliases the strict_mask for the register.
 462  * Any bits that are not covered by an arm64_ftr_bits entry are considered
 463  * RES0 for the system-wide value, and must strictly match.
 464  */
 465 static void __init init_cpu_ftr_reg(u32 sys_reg, u64 new)
 466 {
 467         u64 val = 0;
 468         u64 strict_mask = ~0x0ULL;
 469         u64 user_mask = 0;
 470         u64 valid_mask = 0;
 471
 472         const struct arm64_ftr_bits *ftrp;
 473         struct arm64_ftr_reg *reg = get_arm64_ftr_reg(sys_reg);
 474
 475         BUG_ON(!reg);
 476
 477         for (ftrp  = reg->ftr_bits; ftrp->width; ftrp++) {
 478                 u64 ftr_mask = arm64_ftr_mask(ftrp);
 479                 s64 ftr_new = arm64_ftr_value(ftrp, new);
 480
 481                 val = arm64_ftr_set_value(ftrp, val, ftr_new);
 482
 483                 valid_mask |= ftr_mask;
 484                 if (!ftrp->strict)
 485                         strict_mask &= ~ftr_mask;
 486                 if (ftrp->visible)
 487                         user_mask |= ftr_mask;
 488                 else
 489                         reg->user_val = arm64_ftr_set_value(ftrp,
 490                                                             reg->user_val,
 491                                                             ftrp->safe_val);
 492         }
 493
 494         val &= valid_mask;
 495
 496         reg->sys_val = val;
 497         reg->strict_mask = strict_mask;
 498         reg->user_mask = user_mask;
 499 }
 500
 501 extern const struct arm64_cpu_capabilities arm64_errata[];
 502 static void __init setup_boot_cpu_capabilities(void);
 503
 504 void __init init_cpu_features(struct cpuinfo_arm64 *info)
 505 {
 506         /* Before we start using the tables, make sure it is sorted */
 507         sort_ftr_regs();
 508
 509         init_cpu_ftr_reg(SYS_CTR_EL0, info->reg_ctr);
 510         init_cpu_ftr_reg(SYS_DCZID_EL0, info->reg_dczid);
 511         init_cpu_ftr_reg(SYS_CNTFRQ_EL0, info->reg_cntfrq);
 512         init_cpu_ftr_reg(SYS_ID_AA64DFR0_EL1, info->reg_id_aa64dfr0);
 513         init_cpu_ftr_reg(SYS_ID_AA64DFR1_EL1, info->reg_id_aa64dfr1);
 514         init_cpu_ftr_reg(SYS_ID_AA64ISAR0_EL1, info->reg_id_aa64isar0);
 515         init_cpu_ftr_reg(SYS_ID_AA64ISAR1_EL1, info->reg_id_aa64isar1);
 516         init_cpu_ftr_reg(SYS_ID_AA64ISAR2_EL1, info->reg_id_aa64isar2);
 517         init_cpu_ftr_reg(SYS_ID_AA64MMFR0_EL1, info->reg_id_aa64mmfr0);
 518         init_cpu_ftr_reg(SYS_ID_AA64MMFR1_EL1, info->reg_id_aa64mmfr1);
 519         init_cpu_ftr_reg(SYS_ID_AA64MMFR2_EL1, info->reg_id_aa64mmfr2);
 520         init_cpu_ftr_reg(SYS_ID_AA64PFR0_EL1, info->reg_id_aa64pfr0);
 521         init_cpu_ftr_reg(SYS_ID_AA64PFR1_EL1, info->reg_id_aa64pfr1);
 522
 523         if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) {
 524                 init_cpu_ftr_reg(SYS_ID_DFR0_EL1, info->reg_id_dfr0);
 525                 init_cpu_ftr_reg(SYS_ID_ISAR0_EL1, info->reg_id_isar0);
 526                 init_cpu_ftr_reg(SYS_ID_ISAR1_EL1, info->reg_id_isar1);
 527                 init_cpu_ftr_reg(SYS_ID_ISAR2_EL1, info->reg_id_isar2);
 528                 init_cpu_ftr_reg(SYS_ID_ISAR3_EL1, info->reg_id_isar3);
 529                 init_cpu_ftr_reg(SYS_ID_ISAR4_EL1, info->reg_id_isar4);
 530                 init_cpu_ftr_reg(SYS_ID_ISAR5_EL1, info->reg_id_isar5);
 531                 init_cpu_ftr_reg(SYS_ID_MMFR0_EL1, info->reg_id_mmfr0);
 532                 init_cpu_ftr_reg(SYS_ID_MMFR1_EL1, info->reg_id_mmfr1);
 533                 init_cpu_ftr_reg(SYS_ID_MMFR2_EL1, info->reg_id_mmfr2);
 534                 init_cpu_ftr_reg(SYS_ID_MMFR3_EL1, info->reg_id_mmfr3);
 535                 init_cpu_ftr_reg(SYS_ID_PFR0_EL1, info->reg_id_pfr0);
 536                 init_cpu_ftr_reg(SYS_ID_PFR1_EL1, info->reg_id_pfr1);
 537                 init_cpu_ftr_reg(SYS_MVFR0_EL1, info->reg_mvfr0);
 538                 init_cpu_ftr_reg(SYS_MVFR1_EL1, info->reg_mvfr1);
 539                 init_cpu_ftr_reg(SYS_MVFR2_EL1, info->reg_mvfr2);
 540         }
 541
 542         /*
 543          * Detect and enable early CPU capabilities based on the boot CPU,
 544          * after we have initialised the CPU feature infrastructure.
 545          */
 546         setup_boot_cpu_capabilities();
 547 }
 548
 549 static void update_cpu_ftr_reg(struct arm64_ftr_reg *reg, u64 new)
 550 {
 551         const struct arm64_ftr_bits *ftrp;
 552
 553         for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) {
 554                 s64 ftr_cur = arm64_ftr_value(ftrp, reg->sys_val);
 555                 s64 ftr_new = arm64_ftr_value(ftrp, new);
 556
 557                 if (ftr_cur == ftr_new)
 558                         continue;
 559                 /* Find a safe value */
 560                 ftr_new = arm64_ftr_safe_value(ftrp, ftr_new, ftr_cur);
 561                 reg->sys_val = arm64_ftr_set_value(ftrp, reg->sys_val, ftr_new);
 562         }
 563
 564 }
 565
 566 static int check_update_ftr_reg(u32 sys_id, int cpu, u64 val, u64 boot)
 567 {
 568         struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id);
 569
 570         BUG_ON(!regp);
 571         update_cpu_ftr_reg(regp, val);
 572         if ((boot & regp->strict_mask) == (val & regp->strict_mask))
 573                 return 0;
 574         pr_warn("SANITY CHECK: Unexpected variation in %s. Boot CPU: %#016llx, CPU%d: %#016llx\n",
 575                         regp->name, boot, cpu, val);
 576         return 1;
 577 }
 578
 579 /*
 580  * Update system wide CPU feature registers with the values from a
 581  * non-boot CPU. Also performs SANITY checks to make sure that there
 582  * aren't any insane variations from that of the boot CPU.
 583  */
 584 void update_cpu_features(int cpu,
 585                          struct cpuinfo_arm64 *info,
 586                          struct cpuinfo_arm64 *boot)
 587 {
 588         int taint = 0;
 589
 590         /*
 591          * The kernel can handle differing I-cache policies, but otherwise
 592          * caches should look identical. Userspace JITs will make use of
 593          * *minLine.
 594          */
 595         taint |= check_update_ftr_reg(SYS_CTR_EL0, cpu,
 596                                       info->reg_ctr, boot->reg_ctr);
 597
 598         /*
 599          * Userspace may perform DC ZVA instructions. Mismatched block sizes
 600          * could result in too much or too little memory being zeroed if a
 601          * process is preempted and migrated between CPUs.
 602          */
 603         taint |= check_update_ftr_reg(SYS_DCZID_EL0, cpu,
 604                                       info->reg_dczid, boot->reg_dczid);
 605
 606         /* If different, timekeeping will be broken (especially with KVM) */
 607         taint |= check_update_ftr_reg(SYS_CNTFRQ_EL0, cpu,
 608                                       info->reg_cntfrq, boot->reg_cntfrq);
 609
 610         /*
 611          * The kernel uses self-hosted debug features and expects CPUs to
 612          * support identical debug features. We presently need CTX_CMPs, WRPs,
 613          * and BRPs to be identical.
 614          * ID_AA64DFR1 is currently RES0.
 615          */
 616         taint |= check_update_ftr_reg(SYS_ID_AA64DFR0_EL1, cpu,
 617                                       info->reg_id_aa64dfr0, boot->reg_id_aa64dfr0);
 618         taint |= check_update_ftr_reg(SYS_ID_AA64DFR1_EL1, cpu,
 619                                       info->reg_id_aa64dfr1, boot->reg_id_aa64dfr1);
 620         /*
 621          * Even in big.LITTLE, processors should be identical instruction-set
 622          * wise.
 623          */
 624         taint |= check_update_ftr_reg(SYS_ID_AA64ISAR0_EL1, cpu,
 625                                       info->reg_id_aa64isar0, boot->reg_id_aa64isar0);
 626         taint |= check_update_ftr_reg(SYS_ID_AA64ISAR1_EL1, cpu,
 627                                       info->reg_id_aa64isar1, boot->reg_id_aa64isar1);
 628         taint |= check_update_ftr_reg(SYS_ID_AA64ISAR2_EL1, cpu,
 629                                       info->reg_id_aa64isar2, boot->reg_id_aa64isar2);
 630
 631         /*
 632          * Differing PARange support is fine as long as all peripherals and
 633          * memory are mapped within the minimum PARange of all CPUs.
 634          * Linux should not care about secure memory.
 635          */
 636         taint |= check_update_ftr_reg(SYS_ID_AA64MMFR0_EL1, cpu,
 637                                       info->reg_id_aa64mmfr0, boot->reg_id_aa64mmfr0);
 638         taint |= check_update_ftr_reg(SYS_ID_AA64MMFR1_EL1, cpu,
 639                                       info->reg_id_aa64mmfr1, boot->reg_id_aa64mmfr1);
 640         taint |= check_update_ftr_reg(SYS_ID_AA64MMFR2_EL1, cpu,
 641                                       info->reg_id_aa64mmfr2, boot->reg_id_aa64mmfr2);
 642
 643         taint |= check_update_ftr_reg(SYS_ID_AA64PFR0_EL1, cpu,
 644                                       info->reg_id_aa64pfr0, boot->reg_id_aa64pfr0);
 645         taint |= check_update_ftr_reg(SYS_ID_AA64PFR1_EL1, cpu,
 646                                       info->reg_id_aa64pfr1, boot->reg_id_aa64pfr1);
 647
 648         /*
 649          * If we have AArch32, we care about 32-bit features for compat.
 650          * If the system doesn't support AArch32, don't update them.
 651          */
 652         if (id_aa64pfr0_32bit_el0(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1)) &&
 653                 id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) {
 654
 655                 taint |= check_update_ftr_reg(SYS_ID_DFR0_EL1, cpu,
 656                                         info->reg_id_dfr0, boot->reg_id_dfr0);
 657                 taint |= check_update_ftr_reg(SYS_ID_ISAR0_EL1, cpu,
 658                                         info->reg_id_isar0, boot->reg_id_isar0);
 659                 taint |= check_update_ftr_reg(SYS_ID_ISAR1_EL1, cpu,
 660                                         info->reg_id_isar1, boot->reg_id_isar1);
 661                 taint |= check_update_ftr_reg(SYS_ID_ISAR2_EL1, cpu,
 662                                         info->reg_id_isar2, boot->reg_id_isar2);
 663                 taint |= check_update_ftr_reg(SYS_ID_ISAR3_EL1, cpu,
 664                                         info->reg_id_isar3, boot->reg_id_isar3);
 665                 taint |= check_update_ftr_reg(SYS_ID_ISAR4_EL1, cpu,
 666                                         info->reg_id_isar4, boot->reg_id_isar4);
 667                 taint |= check_update_ftr_reg(SYS_ID_ISAR5_EL1, cpu,
 668                                         info->reg_id_isar5, boot->reg_id_isar5);
 669
 670                 /*
 671                  * Regardless of the value of the AuxReg field, the AIFSR, ADFSR, and
 672                  * ACTLR formats could differ across CPUs and therefore would have to
 673                  * be trapped for virtualization anyway.
 674                  */
 675                 taint |= check_update_ftr_reg(SYS_ID_MMFR0_EL1, cpu,
 676                                         info->reg_id_mmfr0, boot->reg_id_mmfr0);
 677                 taint |= check_update_ftr_reg(SYS_ID_MMFR1_EL1, cpu,
 678                                         info->reg_id_mmfr1, boot->reg_id_mmfr1);
 679                 taint |= check_update_ftr_reg(SYS_ID_MMFR2_EL1, cpu,
 680                                         info->reg_id_mmfr2, boot->reg_id_mmfr2);
 681                 taint |= check_update_ftr_reg(SYS_ID_MMFR3_EL1, cpu,
 682                                         info->reg_id_mmfr3, boot->reg_id_mmfr3);
 683                 taint |= check_update_ftr_reg(SYS_ID_PFR0_EL1, cpu,
 684                                         info->reg_id_pfr0, boot->reg_id_pfr0);
 685                 taint |= check_update_ftr_reg(SYS_ID_PFR1_EL1, cpu,
 686                                         info->reg_id_pfr1, boot->reg_id_pfr1);
 687                 taint |= check_update_ftr_reg(SYS_MVFR0_EL1, cpu,
 688                                         info->reg_mvfr0, boot->reg_mvfr0);
 689                 taint |= check_update_ftr_reg(SYS_MVFR1_EL1, cpu,
 690                                         info->reg_mvfr1, boot->reg_mvfr1);
 691                 taint |= check_update_ftr_reg(SYS_MVFR2_EL1, cpu,
 692                                         info->reg_mvfr2, boot->reg_mvfr2);
 693         }
 694
 695         /*
 696          * Mismatched CPU features are a recipe for disaster. Don't even
 697          * pretend to support them.
 698          */
 699         if (taint) {
 700                 pr_warn_once("Unsupported CPU feature variation detected.\n");
 701                 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK);
 702         }
 703 }
 704
 705 u64 read_sanitised_ftr_reg(u32 id)
 706 {
 707         struct arm64_ftr_reg *regp = get_arm64_ftr_reg(id);
 708
 709         /* We shouldn't get a request for an unsupported register */
 710         BUG_ON(!regp);
 711         return regp->sys_val;
 712 }
 713
 714 #define read_sysreg_case(r)     \
 715         case r:         return read_sysreg_s(r)
 716
 717 /*
 718  * __read_sysreg_by_encoding() - Used by a STARTING cpu before cpuinfo is populated.
 719  * Read the system register on the current CPU
 720  */
 721 static u64 __read_sysreg_by_encoding(u32 sys_id)
 722 {
 723         switch (sys_id) {
 724         read_sysreg_case(SYS_ID_PFR0_EL1);
 725         read_sysreg_case(SYS_ID_PFR1_EL1);
 726         read_sysreg_case(SYS_ID_DFR0_EL1);
 727         read_sysreg_case(SYS_ID_MMFR0_EL1);
 728         read_sysreg_case(SYS_ID_MMFR1_EL1);
 729         read_sysreg_case(SYS_ID_MMFR2_EL1);
 730         read_sysreg_case(SYS_ID_MMFR3_EL1);
 731         read_sysreg_case(SYS_ID_ISAR0_EL1);
 732         read_sysreg_case(SYS_ID_ISAR1_EL1);
 733         read_sysreg_case(SYS_ID_ISAR2_EL1);
 734         read_sysreg_case(SYS_ID_ISAR3_EL1);
 735         read_sysreg_case(SYS_ID_ISAR4_EL1);
 736         read_sysreg_case(SYS_ID_ISAR5_EL1);
 737         read_sysreg_case(SYS_MVFR0_EL1);
 738         read_sysreg_case(SYS_MVFR1_EL1);
 739         read_sysreg_case(SYS_MVFR2_EL1);
 740
 741         read_sysreg_case(SYS_ID_AA64PFR0_EL1);
 742         read_sysreg_case(SYS_ID_AA64PFR1_EL1);
 743         read_sysreg_case(SYS_ID_AA64DFR0_EL1);
 744         read_sysreg_case(SYS_ID_AA64DFR1_EL1);
 745         read_sysreg_case(SYS_ID_AA64MMFR0_EL1);
 746         read_sysreg_case(SYS_ID_AA64MMFR1_EL1);
 747         read_sysreg_case(SYS_ID_AA64MMFR2_EL1);
 748         read_sysreg_case(SYS_ID_AA64ISAR0_EL1);
 749         read_sysreg_case(SYS_ID_AA64ISAR1_EL1);
 750         read_sysreg_case(SYS_ID_AA64ISAR2_EL1);
 751
 752         read_sysreg_case(SYS_CNTFRQ_EL0);
 753         read_sysreg_case(SYS_CTR_EL0);
 754         read_sysreg_case(SYS_DCZID_EL0);
 755
 756         default:
 757                 BUG();
 758                 return 0;
 759         }
 760 }
 761
 762 #include <linux/irqchip/arm-gic-v3.h>
 763
 764 static bool
 765 feature_matches(u64 reg, const struct arm64_cpu_capabilities *entry)
 766 {
 767         int val = cpuid_feature_extract_field(reg, entry->field_pos, entry->sign);
 768
 769         return val >= entry->min_field_value;
 770 }
 771
 772 static bool
 773 has_cpuid_feature(const struct arm64_cpu_capabilities *entry, int scope)
 774 {
 775         u64 val;
 776
 777         WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible());
 778         if (scope == SCOPE_SYSTEM)
 779                 val = read_sanitised_ftr_reg(entry->sys_reg);
 780         else
 781                 val = __read_sysreg_by_encoding(entry->sys_reg);
 782
 783         return feature_matches(val, entry);
 784 }
 785
 786 static bool has_useable_gicv3_cpuif(const struct arm64_cpu_capabilities *entry, int scope)
 787 {
 788         bool has_sre;
 789
 790         if (!has_cpuid_feature(entry, scope))
 791                 return false;
 792
 793         has_sre = gic_enable_sre();
 794         if (!has_sre)
 795                 pr_warn_once("%s present but disabled by higher exception level\n",
 796                              entry->desc);
 797
 798         return has_sre;
 799 }
 800
 801 static bool has_no_hw_prefetch(const struct arm64_cpu_capabilities *entry, int __unused)
 802 {
 803         u32 midr = read_cpuid_id();
 804
 805         /* Cavium ThunderX pass 1.x and 2.x */
 806         return MIDR_IS_CPU_MODEL_RANGE(midr, MIDR_THUNDERX,
 807                 MIDR_CPU_VAR_REV(0, 0),
 808                 MIDR_CPU_VAR_REV(1, MIDR_REVISION_MASK));
 809 }
 810
 811 static bool hyp_offset_low(const struct arm64_cpu_capabilities *entry,
 812                            int __unused)
 813 {
 814         phys_addr_t idmap_addr = __pa_symbol(__hyp_idmap_text_start);
 815
 816         /*
 817          * Activate the lower HYP offset only if:
 818          * - the idmap doesn't clash with it,
 819          * - the kernel is not running at EL2.
 820          */
 821         return idmap_addr > GENMASK(VA_BITS - 2, 0) && !is_kernel_in_hyp_mode();
 822 }
 823
 824 static bool has_no_fpsimd(const struct arm64_cpu_capabilities *entry, int __unused)
 825 {
 826         u64 pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1);
 827
 828         return cpuid_feature_extract_signed_field(pfr0,
 829                                         ID_AA64PFR0_FP_SHIFT) < 0;
 830 }
 831
 832 static bool __meltdown_safe = true;
 833 static int __kpti_forced; /* 0: not forced, >0: forced on, <0: forced off */
 834
 835 static bool unmap_kernel_at_el0(const struct arm64_cpu_capabilities *entry,
 836                                 int scope)
 837 {
 838         /* List of CPUs that are not vulnerable and don't need KPTI */
 839         static const struct midr_range kpti_safe_list[] = {
 840                 MIDR_ALL_VERSIONS(MIDR_CAVIUM_THUNDERX2),
 841                 MIDR_ALL_VERSIONS(MIDR_BRCM_VULCAN),
 842                 MIDR_ALL_VERSIONS(MIDR_CORTEX_A35),
 843                 MIDR_ALL_VERSIONS(MIDR_CORTEX_A53),
 844                 MIDR_ALL_VERSIONS(MIDR_CORTEX_A55),
 845                 MIDR_ALL_VERSIONS(MIDR_CORTEX_A57),
 846                 MIDR_ALL_VERSIONS(MIDR_CORTEX_A72),
 847                 MIDR_ALL_VERSIONS(MIDR_CORTEX_A73),
 848                 { /* sentinel */ }
 849         };
 850         char const *str = "kpti command line option";
 851         bool meltdown_safe;
 852
 853         meltdown_safe = is_midr_in_range_list(read_cpuid_id(), kpti_safe_list);
 854
 855         /* Defer to CPU feature registers */
 856         if (has_cpuid_feature(entry, scope))
 857                 meltdown_safe = true;
 858
 859         if (!meltdown_safe)
 860                 __meltdown_safe = false;
 861
 862         /*
 863          * For reasons that aren't entirely clear, enabling KPTI on Cavium
 864          * ThunderX leads to apparent I-cache corruption of kernel text, which
 865          * ends as well as you might imagine. Don't even try.
 866          */
 867         if (cpus_have_const_cap(ARM64_WORKAROUND_CAVIUM_27456)) {
 868                 str = "ARM64_WORKAROUND_CAVIUM_27456";
 869                 __kpti_forced = -1;
 870         }
 871
 872         /* Useful for KASLR robustness */
 873         if (IS_ENABLED(CONFIG_RANDOMIZE_BASE) && kaslr_offset() > 0) {
 874                 if (!__kpti_forced) {
 875                         str = "KASLR";
 876                         __kpti_forced = 1;
 877                 }
 878         }
 879
 880         if (cpu_mitigations_off() && !__kpti_forced) {
 881                 str = "mitigations=off";
 882                 __kpti_forced = -1;
 883         }
 884
 885         if (!IS_ENABLED(CONFIG_UNMAP_KERNEL_AT_EL0)) {
 886                 pr_info_once("kernel page table isolation disabled by kernel configuration\n");
 887                 return false;
 888         }
 889
 890         /* Forced? */
 891         if (__kpti_forced) {
 892                 pr_info_once("kernel page table isolation forced %s by %s\n",
 893                              __kpti_forced > 0 ? "ON" : "OFF", str);
 894                 return __kpti_forced > 0;
 895         }
 896
 897         return !meltdown_safe;
 898 }
 899
 900 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0
 901 static void
 902 kpti_install_ng_mappings(const struct arm64_cpu_capabilities *__unused)
 903 {
 904         typedef void (kpti_remap_fn)(int, int, phys_addr_t);
 905         extern kpti_remap_fn idmap_kpti_install_ng_mappings;
 906         kpti_remap_fn *remap_fn;
 907
 908         static bool kpti_applied = false;
 909         int cpu = smp_processor_id();
 910
 911         if (__this_cpu_read(this_cpu_vector) == vectors) {
 912                 const char *v = arm64_get_bp_hardening_vector(EL1_VECTOR_KPTI);
 913
 914                 __this_cpu_write(this_cpu_vector, v);
 915         }
 916
 917         if (kpti_applied)
 918                 return;
 919
 920         remap_fn = (void *)__pa_symbol(idmap_kpti_install_ng_mappings);
 921
 922         cpu_install_idmap();
 923         remap_fn(cpu, num_online_cpus(), __pa_symbol(swapper_pg_dir));
 924         cpu_uninstall_idmap();
 925
 926         if (!cpu)
 927                 kpti_applied = true;
 928
 929         return;
 930 }
 931 #else
 932 static void
 933 kpti_install_ng_mappings(const struct arm64_cpu_capabilities *__unused)
 934 {
 935 }
 936 #endif  /* CONFIG_UNMAP_KERNEL_AT_EL0 */
 937
 938 static int __init parse_kpti(char *str)
 939 {
 940         bool enabled;
 941         int ret = strtobool(str, &enabled);
 942
 943         if (ret)
 944                 return ret;
 945
 946         __kpti_forced = enabled ? 1 : -1;
 947         return 0;
 948 }
 949 early_param("kpti", parse_kpti);
 950
 951 #ifdef CONFIG_ARM64_VHE
 952 static bool runs_at_el2(const struct arm64_cpu_capabilities *entry, int __unused)
 953 {
 954         return is_kernel_in_hyp_mode();
 955 }
 956
 957 static void cpu_copy_el2regs(const struct arm64_cpu_capabilities *__unused)
 958 {
 959         /*
 960          * Copy register values that aren't redirected by hardware.
 961          *
 962          * Before code patching, we only set tpidr_el1, all CPUs need to copy
 963          * this value to tpidr_el2 before we patch the code. Once we've done
 964          * that, freshly-onlined CPUs will set tpidr_el2, so we don't need to
 965          * do anything here.
 966          */
 967         if (!alternatives_applied)
 968                 write_sysreg(read_sysreg(tpidr_el1), tpidr_el2);
 969 }
 970 #endif
 971
 972 #ifdef CONFIG_ARM64_SSBD
 973 static int ssbs_emulation_handler(struct pt_regs *regs, u32 instr)
 974 {
 975         if (user_mode(regs))
 976                 return 1;
 977
 978         if (instr & BIT(CRm_shift))
 979                 regs->pstate |= PSR_SSBS_BIT;
 980         else
 981                 regs->pstate &= ~PSR_SSBS_BIT;
 982
 983         arm64_skip_faulting_instruction(regs, 4);
 984         return 0;
 985 }
 986
 987 static struct undef_hook ssbs_emulation_hook = {
 988         .instr_mask     = ~(1U << CRm_shift),
 989         .instr_val      = 0xd500001f | REG_PSTATE_SSBS_IMM,
 990         .fn             = ssbs_emulation_handler,
 991 };
 992
 993 static void cpu_enable_ssbs(const struct arm64_cpu_capabilities *__unused)
 994 {
 995         static bool undef_hook_registered = false;
 996         static DEFINE_SPINLOCK(hook_lock);
 997
 998         spin_lock(&hook_lock);
 999         if (!undef_hook_registered) {
1000                 register_undef_hook(&ssbs_emulation_hook);
1001                 undef_hook_registered = true;
1002         }
1003         spin_unlock(&hook_lock);
1004
1005         if (arm64_get_ssbd_state() == ARM64_SSBD_FORCE_DISABLE) {
1006                 sysreg_clear_set(sctlr_el1, 0, SCTLR_ELx_DSSBS);
1007                 arm64_set_ssbd_mitigation(false);
1008         } else {
1009                 arm64_set_ssbd_mitigation(true);
1010         }
1011 }
1012 #endif /* CONFIG_ARM64_SSBD */
1013
1014 static void elf_hwcap_fixup(void)
1015 {
1016 #ifdef CONFIG_ARM64_ERRATUM_1742098
1017         if (cpus_have_const_cap(ARM64_WORKAROUND_1742098))
1018                 compat_elf_hwcap2 &= ~COMPAT_HWCAP2_AES;
1019 #endif /* ARM64_ERRATUM_1742098 */
1020 }
1021
1022 static const struct arm64_cpu_capabilities arm64_features[] = {
1023         {
1024                 .desc = "GIC system register CPU interface",
1025                 .capability = ARM64_HAS_SYSREG_GIC_CPUIF,
1026                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1027                 .matches = has_useable_gicv3_cpuif,
1028                 .sys_reg = SYS_ID_AA64PFR0_EL1,
1029                 .field_pos = ID_AA64PFR0_GIC_SHIFT,
1030                 .sign = FTR_UNSIGNED,
1031                 .min_field_value = 1,
1032         },
1033 #ifdef CONFIG_ARM64_PAN
1034         {
1035                 .desc = "Privileged Access Never",
1036                 .capability = ARM64_HAS_PAN,
1037                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1038                 .matches = has_cpuid_feature,
1039                 .sys_reg = SYS_ID_AA64MMFR1_EL1,
1040                 .field_pos = ID_AA64MMFR1_PAN_SHIFT,
1041                 .sign = FTR_UNSIGNED,
1042                 .min_field_value = 1,
1043                 .cpu_enable = cpu_enable_pan,
1044         },
1045 #endif /* CONFIG_ARM64_PAN */
1046 #if defined(CONFIG_AS_LSE) && defined(CONFIG_ARM64_LSE_ATOMICS)
1047         {
1048                 .desc = "LSE atomic instructions",
1049                 .capability = ARM64_HAS_LSE_ATOMICS,
1050                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1051                 .matches = has_cpuid_feature,
1052                 .sys_reg = SYS_ID_AA64ISAR0_EL1,
1053                 .field_pos = ID_AA64ISAR0_ATOMICS_SHIFT,
1054                 .sign = FTR_UNSIGNED,
1055                 .min_field_value = 2,
1056         },
1057 #endif /* CONFIG_AS_LSE && CONFIG_ARM64_LSE_ATOMICS */
1058         {
1059                 .desc = "Software prefetching using PRFM",
1060                 .capability = ARM64_HAS_NO_HW_PREFETCH,
1061                 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
1062                 .matches = has_no_hw_prefetch,
1063         },
1064 #ifdef CONFIG_ARM64_UAO
1065         {
1066                 .desc = "User Access Override",
1067                 .capability = ARM64_HAS_UAO,
1068                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1069                 .matches = has_cpuid_feature,
1070                 .sys_reg = SYS_ID_AA64MMFR2_EL1,
1071                 .field_pos = ID_AA64MMFR2_UAO_SHIFT,
1072                 .min_field_value = 1,
1073                 /*
1074                  * We rely on stop_machine() calling uao_thread_switch() to set
1075                  * UAO immediately after patching.
1076                  */
1077         },
1078 #endif /* CONFIG_ARM64_UAO */
1079 #ifdef CONFIG_ARM64_PAN
1080         {
1081                 .capability = ARM64_ALT_PAN_NOT_UAO,
1082                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1083                 .matches = cpufeature_pan_not_uao,
1084         },
1085 #endif /* CONFIG_ARM64_PAN */
1086 #ifdef CONFIG_ARM64_VHE
1087         {
1088                 .desc = "Virtualization Host Extensions",
1089                 .capability = ARM64_HAS_VIRT_HOST_EXTN,
1090                 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE,
1091                 .matches = runs_at_el2,
1092                 .cpu_enable = cpu_copy_el2regs,
1093         },
1094 #endif  /* CONFIG_ARM64_VHE */
1095         {
1096                 .desc = "32-bit EL0 Support",
1097                 .capability = ARM64_HAS_32BIT_EL0,
1098                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1099                 .matches = has_cpuid_feature,
1100                 .sys_reg = SYS_ID_AA64PFR0_EL1,
1101                 .sign = FTR_UNSIGNED,
1102                 .field_pos = ID_AA64PFR0_EL0_SHIFT,
1103                 .min_field_value = ID_AA64PFR0_EL0_32BIT_64BIT,
1104         },
1105         {
1106                 .desc = "Reduced HYP mapping offset",
1107                 .capability = ARM64_HYP_OFFSET_LOW,
1108                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1109                 .matches = hyp_offset_low,
1110         },
1111         {
1112                 .desc = "Kernel page table isolation (KPTI)",
1113                 .capability = ARM64_UNMAP_KERNEL_AT_EL0,
1114                 .type = ARM64_CPUCAP_BOOT_RESTRICTED_CPU_LOCAL_FEATURE,
1115                 /*
1116                  * The ID feature fields below are used to indicate that
1117                  * the CPU doesn't need KPTI. See unmap_kernel_at_el0 for
1118                  * more details.
1119                  */
1120                 .sys_reg = SYS_ID_AA64PFR0_EL1,
1121                 .field_pos = ID_AA64PFR0_CSV3_SHIFT,
1122                 .min_field_value = 1,
1123                 .matches = unmap_kernel_at_el0,
1124                 .cpu_enable = kpti_install_ng_mappings,
1125         },
1126         {
1127                 /* FP/SIMD is not implemented */
1128                 .capability = ARM64_HAS_NO_FPSIMD,
1129                 .type = ARM64_CPUCAP_BOOT_RESTRICTED_CPU_LOCAL_FEATURE,
1130                 .min_field_value = 0,
1131                 .matches = has_no_fpsimd,
1132         },
1133 #ifdef CONFIG_ARM64_PMEM
1134         {
1135                 .desc = "Data cache clean to Point of Persistence",
1136                 .capability = ARM64_HAS_DCPOP,
1137                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1138                 .matches = has_cpuid_feature,
1139                 .sys_reg = SYS_ID_AA64ISAR1_EL1,
1140                 .field_pos = ID_AA64ISAR1_DPB_SHIFT,
1141                 .min_field_value = 1,
1142         },
1143 #endif
1144 #ifdef CONFIG_ARM64_SSBD
1145         {
1146                 .desc = "Speculative Store Bypassing Safe (SSBS)",
1147                 .capability = ARM64_SSBS,
1148                 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
1149                 .matches = has_cpuid_feature,
1150                 .sys_reg = SYS_ID_AA64PFR1_EL1,
1151                 .field_pos = ID_AA64PFR1_SSBS_SHIFT,
1152                 .sign = FTR_UNSIGNED,
1153                 .min_field_value = ID_AA64PFR1_SSBS_PSTATE_ONLY,
1154                 .cpu_enable = cpu_enable_ssbs,
1155         },
1156 #endif
1157         {},
1158 };
1159
1160
1161 #define HWCAP_CPUID_MATCH(reg, field, s, min_value)             \
1162                 .matches = has_cpuid_feature,                   \
1163                 .sys_reg = reg,                                 \
1164                 .field_pos = field,                             \
1165                 .sign = s,                                      \
1166                 .min_field_value = min_value,                   \
1167
1168 #define __HWCAP_CAP(name, cap_type, cap)                        \
1169                 .desc = name,                                   \
1170                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,            \
1171                 .hwcap_type = cap_type,                         \
1172                 .hwcap = cap,                                   \
1173
1174 #define HWCAP_CAP(reg, field, s, min_value, cap_type, cap)      \
1175         {                                                       \
1176                 __HWCAP_CAP(#cap, cap_type, cap)                \
1177                 HWCAP_CPUID_MATCH(reg, field, s, min_value)     \
1178         }
1179
1180 #define HWCAP_CAP_MATCH(match, cap_type, cap)                   \
1181         {                                                       \
1182                 __HWCAP_CAP(#cap, cap_type, cap)                \
1183                 .matches = match,                               \
1184         }
1185
1186 static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = {
1187         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, HWCAP_PMULL),
1188         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_AES),
1189         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA1_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_SHA1),
1190         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA2_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_SHA2),
1191         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA2_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, HWCAP_SHA512),
1192         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_CRC32_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_CRC32),
1193         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_ATOMICS_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, HWCAP_ATOMICS),
1194         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_RDM_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_ASIMDRDM),
1195         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA3_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_SHA3),
1196         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SM3_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_SM3),
1197         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SM4_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_SM4),
1198         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_DP_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_ASIMDDP),
1199         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_FHM_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_ASIMDFHM),
1200         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_TS_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_FLAGM),
1201         HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, FTR_SIGNED, 0, CAP_HWCAP, HWCAP_FP),
1202         HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, HWCAP_FPHP),
1203         HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, FTR_SIGNED, 0, CAP_HWCAP, HWCAP_ASIMD),
1204         HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, HWCAP_ASIMDHP),
1205         HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_DIT_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, HWCAP_DIT),
1206         HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_DPB_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_DCPOP),
1207         HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_JSCVT_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_JSCVT),
1208         HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_FCMA_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_FCMA),
1209         HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_LRCPC_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_LRCPC),
1210         HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_LRCPC_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, HWCAP_ILRCPC),
1211         HWCAP_CAP(SYS_ID_AA64MMFR2_EL1, ID_AA64MMFR2_AT_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_USCAT),
1212         HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_SSBS_SHIFT, FTR_UNSIGNED, ID_AA64PFR1_SSBS_PSTATE_INSNS, CAP_HWCAP, HWCAP_SSBS),
1213         {},
1214 };
1215
1216 #ifdef CONFIG_COMPAT
1217 static bool compat_has_neon(const struct arm64_cpu_capabilities *cap, int scope)
1218 {
1219         /*
1220          * Check that all of MVFR1_EL1.{SIMDSP, SIMDInt, SIMDLS} are available,
1221          * in line with that of arm32 as in vfp_init(). We make sure that the
1222          * check is future proof, by making sure value is non-zero.
1223          */
1224         u32 mvfr1;
1225
1226         WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible());
1227         if (scope == SCOPE_SYSTEM)
1228                 mvfr1 = read_sanitised_ftr_reg(SYS_MVFR1_EL1);
1229         else
1230                 mvfr1 = read_sysreg_s(SYS_MVFR1_EL1);
1231
1232         return cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_SIMDSP_SHIFT) &&
1233                 cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_SIMDINT_SHIFT) &&
1234                 cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_SIMDLS_SHIFT);
1235 }
1236 #endif
1237
1238 static const struct arm64_cpu_capabilities compat_elf_hwcaps[] = {
1239 #ifdef CONFIG_COMPAT
1240         HWCAP_CAP_MATCH(compat_has_neon, CAP_COMPAT_HWCAP, COMPAT_HWCAP_NEON),
1241         HWCAP_CAP(SYS_MVFR1_EL1, MVFR1_SIMDFMAC_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFPv4),
1242         /* Arm v8 mandates MVFR0.FPDP == {0, 2}. So, piggy back on this for the presence of VFP support */
1243         HWCAP_CAP(SYS_MVFR0_EL1, MVFR0_FPDP_SHIFT, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFP),
1244         HWCAP_CAP(SYS_MVFR0_EL1, MVFR0_FPDP_SHIFT, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFPv3),
1245         HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_PMULL),
1246         HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_AES),
1247         HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA1_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA1),
1248         HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA2_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA2),
1249         HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_CRC32_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_CRC32),
1250 #endif
1251         {},
1252 };
1253
1254 static void __init cap_set_elf_hwcap(const struct arm64_cpu_capabilities *cap)
1255 {
1256         switch (cap->hwcap_type) {
1257         case CAP_HWCAP:
1258                 elf_hwcap |= cap->hwcap;
1259                 break;
1260 #ifdef CONFIG_COMPAT
1261         case CAP_COMPAT_HWCAP:
1262                 compat_elf_hwcap |= (u32)cap->hwcap;
1263                 break;
1264         case CAP_COMPAT_HWCAP2:
1265                 compat_elf_hwcap2 |= (u32)cap->hwcap;
1266                 break;
1267 #endif
1268         default:
1269                 WARN_ON(1);
1270                 break;
1271         }
1272 }
1273
1274 /* Check if we have a particular HWCAP enabled */
1275 static bool cpus_have_elf_hwcap(const struct arm64_cpu_capabilities *cap)
1276 {
1277         bool rc;
1278
1279         switch (cap->hwcap_type) {
1280         case CAP_HWCAP:
1281                 rc = (elf_hwcap & cap->hwcap) != 0;
1282                 break;
1283 #ifdef CONFIG_COMPAT
1284         case CAP_COMPAT_HWCAP:
1285                 rc = (compat_elf_hwcap & (u32)cap->hwcap) != 0;
1286                 break;
1287         case CAP_COMPAT_HWCAP2:
1288                 rc = (compat_elf_hwcap2 & (u32)cap->hwcap) != 0;
1289                 break;
1290 #endif
1291         default:
1292                 WARN_ON(1);
1293                 rc = false;
1294         }
1295
1296         return rc;
1297 }
1298
1299 static void __init setup_elf_hwcaps(const struct arm64_cpu_capabilities *hwcaps)
1300 {
1301         /* We support emulation of accesses to CPU ID feature registers */
1302         elf_hwcap |= HWCAP_CPUID;
1303         for (; hwcaps->matches; hwcaps++)
1304                 if (hwcaps->matches(hwcaps, cpucap_default_scope(hwcaps)))
1305                         cap_set_elf_hwcap(hwcaps);
1306 }
1307
1308 /*
1309  * Check if the current CPU has a given feature capability.
1310  * Should be called from non-preemptible context.
1311  */
1312 static bool __this_cpu_has_cap(const struct arm64_cpu_capabilities *cap_array,
1313                                unsigned int cap)
1314 {
1315         const struct arm64_cpu_capabilities *caps;
1316
1317         if (WARN_ON(preemptible()))
1318                 return false;
1319
1320         for (caps = cap_array; caps->matches; caps++)
1321                 if (caps->capability == cap &&
1322                     caps->matches(caps, SCOPE_LOCAL_CPU))
1323                         return true;
1324         return false;
1325 }
1326
1327 static void __update_cpu_capabilities(const struct arm64_cpu_capabilities *caps,
1328                                       u16 scope_mask, const char *info)
1329 {
1330         scope_mask &= ARM64_CPUCAP_SCOPE_MASK;
1331         for (; caps->matches; caps++) {
1332                 if (!(caps->type & scope_mask) ||
1333                     !caps->matches(caps, cpucap_default_scope(caps)))
1334                         continue;
1335
1336                 if (!cpus_have_cap(caps->capability) && caps->desc)
1337                         pr_info("%s %s\n", info, caps->desc);
1338                 cpus_set_cap(caps->capability);
1339         }
1340 }
1341
1342 static void update_cpu_capabilities(u16 scope_mask)
1343 {
1344         __update_cpu_capabilities(arm64_errata, scope_mask,
1345                                   "enabling workaround for");
1346         __update_cpu_capabilities(arm64_features, scope_mask, "detected:");
1347 }
1348
1349 static int __enable_cpu_capability(void *arg)
1350 {
1351         const struct arm64_cpu_capabilities *cap = arg;
1352
1353         cap->cpu_enable(cap);
1354         return 0;
1355 }
1356
1357 /*
1358  * Run through the enabled capabilities and enable() it on all active
1359  * CPUs
1360  */
1361 static void __init
1362 __enable_cpu_capabilities(const struct arm64_cpu_capabilities *caps,
1363                           u16 scope_mask)
1364 {
1365         scope_mask &= ARM64_CPUCAP_SCOPE_MASK;
1366         for (; caps->matches; caps++) {
1367                 unsigned int num = caps->capability;
1368
1369                 if (!(caps->type & scope_mask) || !cpus_have_cap(num))
1370                         continue;
1371
1372                 /* Ensure cpus_have_const_cap(num) works */
1373                 static_branch_enable(&cpu_hwcap_keys[num]);
1374
1375                 if (caps->cpu_enable) {
1376                         /*
1377                          * Capabilities with SCOPE_BOOT_CPU scope are finalised
1378                          * before any secondary CPU boots. Thus, each secondary
1379                          * will enable the capability as appropriate via
1380                          * check_local_cpu_capabilities(). The only exception is
1381                          * the boot CPU, for which the capability must be
1382                          * enabled here. This approach avoids costly
1383                          * stop_machine() calls for this case.
1384                          *
1385                          * Otherwise, use stop_machine() as it schedules the
1386                          * work allowing us to modify PSTATE, instead of
1387                          * on_each_cpu() which uses an IPI, giving us a PSTATE
1388                          * that disappears when we return.
1389                          */
1390                         if (scope_mask & SCOPE_BOOT_CPU)
1391                                 caps->cpu_enable(caps);
1392                         else
1393                                 stop_machine(__enable_cpu_capability,
1394                                              (void *)caps, cpu_online_mask);
1395                 }
1396         }
1397 }
1398
1399 static void __init enable_cpu_capabilities(u16 scope_mask)
1400 {
1401         __enable_cpu_capabilities(arm64_errata, scope_mask);
1402         __enable_cpu_capabilities(arm64_features, scope_mask);
1403 }
1404
1405 /*
1406  * Flag to indicate if we have computed the system wide
1407  * capabilities based on the boot time active CPUs. This
1408  * will be used to determine if a new booting CPU should
1409  * go through the verification process to make sure that it
1410  * supports the system capabilities, without using a hotplug
1411  * notifier.
1412  */
1413 static bool sys_caps_initialised;
1414
1415 static inline void set_sys_caps_initialised(void)
1416 {
1417         sys_caps_initialised = true;
1418 }
1419
1420 /*
1421  * Run through the list of capabilities to check for conflicts.
1422  * If the system has already detected a capability, take necessary
1423  * action on this CPU.
1424  *
1425  * Returns "false" on conflicts.
1426  */
1427 static bool
1428 __verify_local_cpu_caps(const struct arm64_cpu_capabilities *caps_list,
1429                         u16 scope_mask)
1430 {
1431         bool cpu_has_cap, system_has_cap;
1432         const struct arm64_cpu_capabilities *caps;
1433
1434         scope_mask &= ARM64_CPUCAP_SCOPE_MASK;
1435
1436         for (caps = caps_list; caps->matches; caps++) {
1437                 if (!(caps->type & scope_mask))
1438                         continue;
1439
1440                 cpu_has_cap = __this_cpu_has_cap(caps_list, caps->capability);
1441                 system_has_cap = cpus_have_cap(caps->capability);
1442
1443                 if (system_has_cap) {
1444                         /*
1445                          * Check if the new CPU misses an advertised feature,
1446                          * which is not safe to miss.
1447                          */
1448                         if (!cpu_has_cap && !cpucap_late_cpu_optional(caps))
1449                                 break;
1450                         /*
1451                          * We have to issue cpu_enable() irrespective of
1452                          * whether the CPU has it or not, as it is enabeld
1453                          * system wide. It is upto the call back to take
1454                          * appropriate action on this CPU.
1455                          */
1456                         if (caps->cpu_enable)
1457                                 caps->cpu_enable(caps);
1458                 } else {
1459                         /*
1460                          * Check if the CPU has this capability if it isn't
1461                          * safe to have when the system doesn't.
1462                          */
1463                         if (cpu_has_cap && !cpucap_late_cpu_permitted(caps))
1464                                 break;
1465                 }
1466         }
1467
1468         if (caps->matches) {
1469                 pr_crit("CPU%d: Detected conflict for capability %d (%s), System: %d, CPU: %d\n",
1470                         smp_processor_id(), caps->capability,
1471                         caps->desc, system_has_cap, cpu_has_cap);
1472                 return false;
1473         }
1474
1475         return true;
1476 }
1477
1478 static bool verify_local_cpu_caps(u16 scope_mask)
1479 {
1480         return __verify_local_cpu_caps(arm64_errata, scope_mask) &&
1481                __verify_local_cpu_caps(arm64_features, scope_mask);
1482 }
1483
1484 /*
1485  * Check for CPU features that are used in early boot
1486  * based on the Boot CPU value.
1487  */
1488 static void check_early_cpu_features(void)
1489 {
1490         verify_cpu_asid_bits();
1491         /*
1492          * Early features are used by the kernel already. If there
1493          * is a conflict, we cannot proceed further.
1494          */
1495         if (!verify_local_cpu_caps(SCOPE_BOOT_CPU))
1496                 cpu_panic_kernel();
1497 }
1498
1499 static void
1500 verify_local_elf_hwcaps(const struct arm64_cpu_capabilities *caps)
1501 {
1502
1503         for (; caps->matches; caps++)
1504                 if (cpus_have_elf_hwcap(caps) && !caps->matches(caps, SCOPE_LOCAL_CPU)) {
1505                         pr_crit("CPU%d: missing HWCAP: %s\n",
1506                                         smp_processor_id(), caps->desc);
1507                         cpu_die_early();
1508                 }
1509 }
1510
1511
1512 /*
1513  * Run through the enabled system capabilities and enable() it on this CPU.
1514  * The capabilities were decided based on the available CPUs at the boot time.
1515  * Any new CPU should match the system wide status of the capability. If the
1516  * new CPU doesn't have a capability which the system now has enabled, we
1517  * cannot do anything to fix it up and could cause unexpected failures. So
1518  * we park the CPU.
1519  */
1520 static void verify_local_cpu_capabilities(void)
1521 {
1522         /*
1523          * The capabilities with SCOPE_BOOT_CPU are checked from
1524          * check_early_cpu_features(), as they need to be verified
1525          * on all secondary CPUs.
1526          */
1527         if (!verify_local_cpu_caps(SCOPE_ALL & ~SCOPE_BOOT_CPU))
1528                 cpu_die_early();
1529
1530         verify_local_elf_hwcaps(arm64_elf_hwcaps);
1531         if (system_supports_32bit_el0())
1532                 verify_local_elf_hwcaps(compat_elf_hwcaps);
1533 }
1534
1535 void check_local_cpu_capabilities(void)
1536 {
1537         /*
1538          * All secondary CPUs should conform to the early CPU features
1539          * in use by the kernel based on boot CPU.
1540          */
1541         check_early_cpu_features();
1542
1543         /*
1544          * If we haven't finalised the system capabilities, this CPU gets
1545          * a chance to update the errata work arounds and local features.
1546          * Otherwise, this CPU should verify that it has all the system
1547          * advertised capabilities.
1548          */
1549         if (!sys_caps_initialised)
1550                 update_cpu_capabilities(SCOPE_LOCAL_CPU);
1551         else
1552                 verify_local_cpu_capabilities();
1553 }
1554
1555 static void __init setup_boot_cpu_capabilities(void)
1556 {
1557         /* Detect capabilities with either SCOPE_BOOT_CPU or SCOPE_LOCAL_CPU */
1558         update_cpu_capabilities(SCOPE_BOOT_CPU | SCOPE_LOCAL_CPU);
1559         /* Enable the SCOPE_BOOT_CPU capabilities alone right away */
1560         enable_cpu_capabilities(SCOPE_BOOT_CPU);
1561 }
1562
1563 DEFINE_STATIC_KEY_FALSE(arm64_const_caps_ready);
1564 EXPORT_SYMBOL(arm64_const_caps_ready);
1565
1566 static void __init mark_const_caps_ready(void)
1567 {
1568         static_branch_enable(&arm64_const_caps_ready);
1569 }
1570
1571 extern const struct arm64_cpu_capabilities arm64_errata[];
1572
1573 bool this_cpu_has_cap(unsigned int cap)
1574 {
1575         return (__this_cpu_has_cap(arm64_features, cap) ||
1576                 __this_cpu_has_cap(arm64_errata, cap));
1577 }
1578
1579 static void __init setup_system_capabilities(void)
1580 {
1581         /*
1582          * We have finalised the system-wide safe feature
1583          * registers, finalise the capabilities that depend
1584          * on it. Also enable all the available capabilities,
1585          * that are not enabled already.
1586          */
1587         update_cpu_capabilities(SCOPE_SYSTEM);
1588         enable_cpu_capabilities(SCOPE_ALL & ~SCOPE_BOOT_CPU);
1589 }
1590
1591 void __init setup_cpu_features(void)
1592 {
1593         u32 cwg;
1594         int cls;
1595
1596         setup_system_capabilities();
1597         mark_const_caps_ready();
1598         setup_elf_hwcaps(arm64_elf_hwcaps);
1599
1600         if (system_supports_32bit_el0()) {
1601                 setup_elf_hwcaps(compat_elf_hwcaps);
1602                 elf_hwcap_fixup();
1603         }
1604
1605         /* Advertise that we have computed the system capabilities */
1606         set_sys_caps_initialised();
1607
1608         /*
1609          * Check for sane CTR_EL0.CWG value.
1610          */
1611         cwg = cache_type_cwg();
1612         cls = cache_line_size();
1613         if (!cwg)
1614                 pr_warn("No Cache Writeback Granule information, assuming cache line size %d\n",
1615                         cls);
1616         if (L1_CACHE_BYTES < cls)
1617                 pr_warn("L1_CACHE_BYTES smaller than the Cache Writeback Granule (%d < %d)\n",
1618                         L1_CACHE_BYTES, cls);
1619 }
1620
1621 static bool __maybe_unused
1622 cpufeature_pan_not_uao(const struct arm64_cpu_capabilities *entry, int __unused)
1623 {
1624         return (cpus_have_const_cap(ARM64_HAS_PAN) && !cpus_have_const_cap(ARM64_HAS_UAO));
1625 }
1626
1627 /*
1628  * We emulate only the following system register space.
1629  * Op0 = 0x3, CRn = 0x0, Op1 = 0x0, CRm = [0, 4 - 7]
1630  * See Table C5-6 System instruction encodings for System register accesses,
1631  * ARMv8 ARM(ARM DDI 0487A.f) for more details.
1632  */
1633 static inline bool __attribute_const__ is_emulated(u32 id)
1634 {
1635         return (sys_reg_Op0(id) == 0x3 &&
1636                 sys_reg_CRn(id) == 0x0 &&
1637                 sys_reg_Op1(id) == 0x0 &&
1638                 (sys_reg_CRm(id) == 0 ||
1639                  ((sys_reg_CRm(id) >= 4) && (sys_reg_CRm(id) <= 7))));
1640 }
1641
1642 /*
1643  * With CRm == 0, reg should be one of :
1644  * MIDR_EL1, MPIDR_EL1 or REVIDR_EL1.
1645  */
1646 static inline int emulate_id_reg(u32 id, u64 *valp)
1647 {
1648         switch (id) {
1649         case SYS_MIDR_EL1:
1650                 *valp = read_cpuid_id();
1651                 break;
1652         case SYS_MPIDR_EL1:
1653                 *valp = SYS_MPIDR_SAFE_VAL;
1654                 break;
1655         case SYS_REVIDR_EL1:
1656                 /* IMPLEMENTATION DEFINED values are emulated with 0 */
1657                 *valp = 0;
1658                 break;
1659         default:
1660                 return -EINVAL;
1661         }
1662
1663         return 0;
1664 }
1665
1666 static int emulate_sys_reg(u32 id, u64 *valp)
1667 {
1668         struct arm64_ftr_reg *regp;
1669
1670         if (!is_emulated(id))
1671                 return -EINVAL;
1672
1673         if (sys_reg_CRm(id) == 0)
1674                 return emulate_id_reg(id, valp);
1675
1676         regp = get_arm64_ftr_reg(id);
1677         if (regp)
1678                 *valp = arm64_ftr_reg_user_value(regp);
1679         else
1680                 /*
1681                  * The untracked registers are either IMPLEMENTATION DEFINED
1682                  * (e.g, ID_AFR0_EL1) or reserved RAZ.
1683                  */
1684                 *valp = 0;
1685         return 0;
1686 }
1687
1688 static int emulate_mrs(struct pt_regs *regs, u32 insn)
1689 {
1690         int rc;
1691         u32 sys_reg, dst;
1692         u64 val;
1693
1694         /*
1695          * sys_reg values are defined as used in mrs/msr instruction.
1696          * shift the imm value to get the encoding.
1697          */
1698         sys_reg = (u32)aarch64_insn_decode_immediate(AARCH64_INSN_IMM_16, insn) << 5;
1699         rc = emulate_sys_reg(sys_reg, &val);
1700         if (!rc) {
1701                 dst = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RT, insn);
1702                 pt_regs_write_reg(regs, dst, val);
1703                 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE);
1704         }
1705
1706         return rc;
1707 }
1708
1709 static struct undef_hook mrs_hook = {
1710         .instr_mask = 0xfff00000,
1711         .instr_val  = 0xd5300000,
1712         .pstate_mask = COMPAT_PSR_MODE_MASK,
1713         .pstate_val = PSR_MODE_EL0t,
1714         .fn = emulate_mrs,
1715 };
1716
1717 static int __init enable_mrs_emulation(void)
1718 {
1719         register_undef_hook(&mrs_hook);
1720         return 0;
1721 }
1722
1723 core_initcall(enable_mrs_emulation);
1724
1725 ssize_t cpu_show_meltdown(struct device *dev, struct device_attribute *attr,
1726                           char *buf)
1727 {
1728         if (__meltdown_safe)
1729                 return sprintf(buf, "Not affected\n");
1730
1731         if (arm64_kernel_unmapped_at_el0())
1732                 return sprintf(buf, "Mitigation: PTI\n");
1733
1734         return sprintf(buf, "Vulnerable\n");
1735 }