2 * Contains CPU feature definitions
4 * Copyright (C) 2015 ARM Ltd.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program. If not, see <http://www.gnu.org/licenses/>.
19 #define pr_fmt(fmt) "CPU features: " fmt
21 #include <linux/bsearch.h>
22 #include <linux/cpumask.h>
23 #include <linux/sort.h>
24 #include <linux/stop_machine.h>
25 #include <linux/types.h>
27 #include <asm/cpufeature.h>
28 #include <asm/cpu_ops.h>
29 #include <asm/mmu_context.h>
30 #include <asm/processor.h>
31 #include <asm/sysreg.h>
34 unsigned long elf_hwcap __read_mostly;
35 EXPORT_SYMBOL_GPL(elf_hwcap);
38 #define COMPAT_ELF_HWCAP_DEFAULT \
39 (COMPAT_HWCAP_HALF|COMPAT_HWCAP_THUMB|\
40 COMPAT_HWCAP_FAST_MULT|COMPAT_HWCAP_EDSP|\
41 COMPAT_HWCAP_TLS|COMPAT_HWCAP_VFP|\
42 COMPAT_HWCAP_VFPv3|COMPAT_HWCAP_VFPv4|\
43 COMPAT_HWCAP_NEON|COMPAT_HWCAP_IDIV|\
45 unsigned int compat_elf_hwcap __read_mostly = COMPAT_ELF_HWCAP_DEFAULT;
46 unsigned int compat_elf_hwcap2 __read_mostly;
49 DECLARE_BITMAP(cpu_hwcaps, ARM64_NCAPS);
50 EXPORT_SYMBOL(cpu_hwcaps);
52 DEFINE_STATIC_KEY_ARRAY_FALSE(cpu_hwcap_keys, ARM64_NCAPS);
53 EXPORT_SYMBOL(cpu_hwcap_keys);
55 #define __ARM64_FTR_BITS(SIGNED, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
62 .safe_val = SAFE_VAL, \
65 /* Define a feature with unsigned values */
66 #define ARM64_FTR_BITS(STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
67 __ARM64_FTR_BITS(FTR_UNSIGNED, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL)
69 /* Define a feature with a signed value */
70 #define S_ARM64_FTR_BITS(STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
71 __ARM64_FTR_BITS(FTR_SIGNED, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL)
73 #define ARM64_FTR_END \
78 /* meta feature for alternatives */
79 static bool __maybe_unused
80 cpufeature_pan_not_uao(const struct arm64_cpu_capabilities *entry, int __unused);
83 static const struct arm64_ftr_bits ftr_id_aa64isar0[] = {
84 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 32, 32, 0),
85 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64ISAR0_RDM_SHIFT, 4, 0),
86 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 24, 4, 0),
87 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_ATOMICS_SHIFT, 4, 0),
88 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_CRC32_SHIFT, 4, 0),
89 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA2_SHIFT, 4, 0),
90 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA1_SHIFT, 4, 0),
91 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_AES_SHIFT, 4, 0),
92 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 4, 0), /* RAZ */
96 static const struct arm64_ftr_bits ftr_id_aa64pfr0[] = {
97 ARM64_FTR_BITS(FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_CSV3_SHIFT, 4, 0),
98 ARM64_FTR_BITS(FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_CSV2_SHIFT, 4, 0),
99 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 32, 24, 0),
100 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 28, 4, 0),
101 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64PFR0_GIC_SHIFT, 4, 0),
102 S_ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_ASIMD_SHIFT, 4, ID_AA64PFR0_ASIMD_NI),
103 S_ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_FP_SHIFT, 4, ID_AA64PFR0_FP_NI),
104 /* Linux doesn't care about the EL3 */
105 ARM64_FTR_BITS(FTR_NONSTRICT, FTR_EXACT, ID_AA64PFR0_EL3_SHIFT, 4, 0),
106 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64PFR0_EL2_SHIFT, 4, 0),
107 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64PFR0_EL1_SHIFT, 4, ID_AA64PFR0_EL1_64BIT_ONLY),
108 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64PFR0_EL0_SHIFT, 4, ID_AA64PFR0_EL0_64BIT_ONLY),
112 static const struct arm64_ftr_bits ftr_id_aa64mmfr0[] = {
113 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 32, 32, 0),
114 S_ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_TGRAN4_SHIFT, 4, ID_AA64MMFR0_TGRAN4_NI),
115 S_ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_TGRAN64_SHIFT, 4, ID_AA64MMFR0_TGRAN64_NI),
116 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_TGRAN16_SHIFT, 4, ID_AA64MMFR0_TGRAN16_NI),
117 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_BIGENDEL0_SHIFT, 4, 0),
118 /* Linux shouldn't care about secure memory */
119 ARM64_FTR_BITS(FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_SNSMEM_SHIFT, 4, 0),
120 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_BIGENDEL_SHIFT, 4, 0),
121 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_ASID_SHIFT, 4, 0),
123 * Differing PARange is fine as long as all peripherals and memory are mapped
124 * within the minimum PARange of all CPUs
126 ARM64_FTR_BITS(FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_PARANGE_SHIFT, 4, 0),
130 static const struct arm64_ftr_bits ftr_id_aa64mmfr1[] = {
131 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 32, 32, 0),
132 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_PAN_SHIFT, 4, 0),
133 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR1_LOR_SHIFT, 4, 0),
134 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR1_HPD_SHIFT, 4, 0),
135 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR1_VHE_SHIFT, 4, 0),
136 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR1_VMIDBITS_SHIFT, 4, 0),
137 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR1_HADBS_SHIFT, 4, 0),
141 static const struct arm64_ftr_bits ftr_id_aa64mmfr2[] = {
142 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR2_LVA_SHIFT, 4, 0),
143 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR2_IESB_SHIFT, 4, 0),
144 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR2_LSM_SHIFT, 4, 0),
145 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR2_UAO_SHIFT, 4, 0),
146 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR2_CNP_SHIFT, 4, 0),
150 static const struct arm64_ftr_bits ftr_ctr[] = {
151 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 31, 1, 1), /* RES1 */
152 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 30, 1, 0),
153 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 29, 1, 1), /* DIC */
154 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 28, 1, 1), /* IDC */
155 ARM64_FTR_BITS(FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, 24, 4, 0), /* CWG */
156 ARM64_FTR_BITS(FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, 20, 4, 0), /* ERG */
157 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, CTR_DMINLINE_SHIFT, 4, 1),
159 * Linux can handle differing I-cache policies. Userspace JITs will
160 * make use of *minLine.
161 * If we have differing I-cache policies, report it as the weakest - AIVIVT.
163 ARM64_FTR_BITS(FTR_NONSTRICT, FTR_EXACT, 14, 2, ICACHE_POLICY_AIVIVT), /* L1Ip */
164 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 4, 10, 0), /* RAZ */
165 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, CTR_IMINLINE_SHIFT, 4, 0),
169 struct arm64_ftr_reg arm64_ftr_reg_ctrel0 = {
170 .name = "SYS_CTR_EL0",
174 static const struct arm64_ftr_bits ftr_id_mmfr0[] = {
175 S_ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 28, 4, 0xf), /* InnerShr */
176 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 24, 4, 0), /* FCSE */
177 ARM64_FTR_BITS(FTR_NONSTRICT, FTR_LOWER_SAFE, 20, 4, 0), /* AuxReg */
178 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 16, 4, 0), /* TCM */
179 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 12, 4, 0), /* ShareLvl */
180 S_ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 8, 4, 0xf), /* OuterShr */
181 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 4, 4, 0), /* PMSA */
182 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 4, 0), /* VMSA */
186 static const struct arm64_ftr_bits ftr_id_aa64dfr0[] = {
187 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 32, 32, 0),
188 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_CTX_CMPS_SHIFT, 4, 0),
189 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_WRPS_SHIFT, 4, 0),
190 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_BRPS_SHIFT, 4, 0),
191 S_ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64DFR0_PMUVER_SHIFT, 4, 0),
192 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64DFR0_TRACEVER_SHIFT, 4, 0),
193 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64DFR0_DEBUGVER_SHIFT, 4, 0x6),
197 static const struct arm64_ftr_bits ftr_mvfr2[] = {
198 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 8, 24, 0), /* RAZ */
199 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 4, 4, 0), /* FPMisc */
200 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 4, 0), /* SIMDMisc */
204 static const struct arm64_ftr_bits ftr_dczid[] = {
205 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 5, 27, 0), /* RAZ */
206 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 4, 1, 1), /* DZP */
207 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), /* BS */
212 static const struct arm64_ftr_bits ftr_id_isar5[] = {
213 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_ISAR5_RDM_SHIFT, 4, 0),
214 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 20, 4, 0), /* RAZ */
215 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_ISAR5_CRC32_SHIFT, 4, 0),
216 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_ISAR5_SHA2_SHIFT, 4, 0),
217 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_ISAR5_SHA1_SHIFT, 4, 0),
218 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_ISAR5_AES_SHIFT, 4, 0),
219 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_ISAR5_SEVL_SHIFT, 4, 0),
223 static const struct arm64_ftr_bits ftr_id_mmfr4[] = {
224 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 8, 24, 0), /* RAZ */
225 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 4, 4, 0), /* ac2 */
226 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 4, 0), /* RAZ */
230 static const struct arm64_ftr_bits ftr_id_pfr0[] = {
231 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 16, 16, 0), /* RAZ */
232 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 12, 4, 0), /* State3 */
233 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 8, 4, 0), /* State2 */
234 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 4, 4, 0), /* State1 */
235 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 4, 0), /* State0 */
239 static const struct arm64_ftr_bits ftr_id_dfr0[] = {
240 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0),
241 S_ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0xf), /* PerfMon */
242 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0),
243 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0),
244 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0),
245 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0),
246 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),
247 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),
252 * Common ftr bits for a 32bit register with all hidden, strict
253 * attributes, with 4bit feature fields and a default safe value of
254 * 0. Covers the following 32bit registers:
255 * id_isar[0-4], id_mmfr[1-3], id_pfr1, mvfr[0-1]
257 static const struct arm64_ftr_bits ftr_generic_32bits[] = {
258 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0),
259 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0),
260 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0),
261 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0),
262 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0),
263 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0),
264 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),
265 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),
269 static const struct arm64_ftr_bits ftr_generic[] = {
270 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 64, 0),
274 static const struct arm64_ftr_bits ftr_generic32[] = {
275 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 32, 0),
279 static const struct arm64_ftr_bits ftr_aa64raz[] = {
280 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 64, 0),
284 #define ARM64_FTR_REG(id, table) { \
286 .reg = &(struct arm64_ftr_reg){ \
288 .ftr_bits = &((table)[0]), \
291 static const struct __ftr_reg_entry {
293 struct arm64_ftr_reg *reg;
294 } arm64_ftr_regs[] = {
296 /* Op1 = 0, CRn = 0, CRm = 1 */
297 ARM64_FTR_REG(SYS_ID_PFR0_EL1, ftr_id_pfr0),
298 ARM64_FTR_REG(SYS_ID_PFR1_EL1, ftr_generic_32bits),
299 ARM64_FTR_REG(SYS_ID_DFR0_EL1, ftr_id_dfr0),
300 ARM64_FTR_REG(SYS_ID_MMFR0_EL1, ftr_id_mmfr0),
301 ARM64_FTR_REG(SYS_ID_MMFR1_EL1, ftr_generic_32bits),
302 ARM64_FTR_REG(SYS_ID_MMFR2_EL1, ftr_generic_32bits),
303 ARM64_FTR_REG(SYS_ID_MMFR3_EL1, ftr_generic_32bits),
305 /* Op1 = 0, CRn = 0, CRm = 2 */
306 ARM64_FTR_REG(SYS_ID_ISAR0_EL1, ftr_generic_32bits),
307 ARM64_FTR_REG(SYS_ID_ISAR1_EL1, ftr_generic_32bits),
308 ARM64_FTR_REG(SYS_ID_ISAR2_EL1, ftr_generic_32bits),
309 ARM64_FTR_REG(SYS_ID_ISAR3_EL1, ftr_generic_32bits),
310 ARM64_FTR_REG(SYS_ID_ISAR4_EL1, ftr_generic_32bits),
311 ARM64_FTR_REG(SYS_ID_ISAR5_EL1, ftr_id_isar5),
312 ARM64_FTR_REG(SYS_ID_MMFR4_EL1, ftr_id_mmfr4),
314 /* Op1 = 0, CRn = 0, CRm = 3 */
315 ARM64_FTR_REG(SYS_MVFR0_EL1, ftr_generic_32bits),
316 ARM64_FTR_REG(SYS_MVFR1_EL1, ftr_generic_32bits),
317 ARM64_FTR_REG(SYS_MVFR2_EL1, ftr_mvfr2),
319 /* Op1 = 0, CRn = 0, CRm = 4 */
320 ARM64_FTR_REG(SYS_ID_AA64PFR0_EL1, ftr_id_aa64pfr0),
321 ARM64_FTR_REG(SYS_ID_AA64PFR1_EL1, ftr_aa64raz),
323 /* Op1 = 0, CRn = 0, CRm = 5 */
324 ARM64_FTR_REG(SYS_ID_AA64DFR0_EL1, ftr_id_aa64dfr0),
325 ARM64_FTR_REG(SYS_ID_AA64DFR1_EL1, ftr_generic),
327 /* Op1 = 0, CRn = 0, CRm = 6 */
328 ARM64_FTR_REG(SYS_ID_AA64ISAR0_EL1, ftr_id_aa64isar0),
329 ARM64_FTR_REG(SYS_ID_AA64ISAR1_EL1, ftr_aa64raz),
331 /* Op1 = 0, CRn = 0, CRm = 7 */
332 ARM64_FTR_REG(SYS_ID_AA64MMFR0_EL1, ftr_id_aa64mmfr0),
333 ARM64_FTR_REG(SYS_ID_AA64MMFR1_EL1, ftr_id_aa64mmfr1),
334 ARM64_FTR_REG(SYS_ID_AA64MMFR2_EL1, ftr_id_aa64mmfr2),
336 /* Op1 = 3, CRn = 0, CRm = 0 */
337 { SYS_CTR_EL0, &arm64_ftr_reg_ctrel0 },
338 ARM64_FTR_REG(SYS_DCZID_EL0, ftr_dczid),
340 /* Op1 = 3, CRn = 14, CRm = 0 */
341 ARM64_FTR_REG(SYS_CNTFRQ_EL0, ftr_generic32),
344 static int search_cmp_ftr_reg(const void *id, const void *regp)
346 return (int)(unsigned long)id - (int)((const struct __ftr_reg_entry *)regp)->sys_id;
350 * get_arm64_ftr_reg - Lookup a feature register entry using its
351 * sys_reg() encoding. With the array arm64_ftr_regs sorted in the
352 * ascending order of sys_id , we use binary search to find a matching
355 * returns - Upon success, matching ftr_reg entry for id.
356 * - NULL on failure. It is upto the caller to decide
357 * the impact of a failure.
359 static struct arm64_ftr_reg *get_arm64_ftr_reg(u32 sys_id)
361 const struct __ftr_reg_entry *ret;
363 ret = bsearch((const void *)(unsigned long)sys_id,
365 ARRAY_SIZE(arm64_ftr_regs),
366 sizeof(arm64_ftr_regs[0]),
373 static u64 arm64_ftr_set_value(const struct arm64_ftr_bits *ftrp, s64 reg,
376 u64 mask = arm64_ftr_mask(ftrp);
379 reg |= (ftr_val << ftrp->shift) & mask;
383 static s64 arm64_ftr_safe_value(const struct arm64_ftr_bits *ftrp, s64 new,
388 switch (ftrp->type) {
390 ret = ftrp->safe_val;
393 ret = new < cur ? new : cur;
395 case FTR_HIGHER_OR_ZERO_SAFE:
399 case FTR_HIGHER_SAFE:
400 ret = new > cur ? new : cur;
409 static void __init sort_ftr_regs(void)
413 /* Check that the array is sorted so that we can do the binary search */
414 for (i = 1; i < ARRAY_SIZE(arm64_ftr_regs); i++)
415 BUG_ON(arm64_ftr_regs[i].sys_id < arm64_ftr_regs[i - 1].sys_id);
419 * Initialise the CPU feature register from Boot CPU values.
420 * Also initiliases the strict_mask for the register.
422 static void __init init_cpu_ftr_reg(u32 sys_reg, u64 new)
425 u64 strict_mask = ~0x0ULL;
426 const struct arm64_ftr_bits *ftrp;
427 struct arm64_ftr_reg *reg = get_arm64_ftr_reg(sys_reg);
431 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) {
432 s64 ftr_new = arm64_ftr_value(ftrp, new);
434 val = arm64_ftr_set_value(ftrp, val, ftr_new);
436 strict_mask &= ~arm64_ftr_mask(ftrp);
439 reg->strict_mask = strict_mask;
442 void __init init_cpu_features(struct cpuinfo_arm64 *info)
444 /* Before we start using the tables, make sure it is sorted */
447 init_cpu_ftr_reg(SYS_CTR_EL0, info->reg_ctr);
448 init_cpu_ftr_reg(SYS_DCZID_EL0, info->reg_dczid);
449 init_cpu_ftr_reg(SYS_CNTFRQ_EL0, info->reg_cntfrq);
450 init_cpu_ftr_reg(SYS_ID_AA64DFR0_EL1, info->reg_id_aa64dfr0);
451 init_cpu_ftr_reg(SYS_ID_AA64DFR1_EL1, info->reg_id_aa64dfr1);
452 init_cpu_ftr_reg(SYS_ID_AA64ISAR0_EL1, info->reg_id_aa64isar0);
453 init_cpu_ftr_reg(SYS_ID_AA64ISAR1_EL1, info->reg_id_aa64isar1);
454 init_cpu_ftr_reg(SYS_ID_AA64MMFR0_EL1, info->reg_id_aa64mmfr0);
455 init_cpu_ftr_reg(SYS_ID_AA64MMFR1_EL1, info->reg_id_aa64mmfr1);
456 init_cpu_ftr_reg(SYS_ID_AA64MMFR2_EL1, info->reg_id_aa64mmfr2);
457 init_cpu_ftr_reg(SYS_ID_AA64PFR0_EL1, info->reg_id_aa64pfr0);
458 init_cpu_ftr_reg(SYS_ID_AA64PFR1_EL1, info->reg_id_aa64pfr1);
460 if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) {
461 init_cpu_ftr_reg(SYS_ID_DFR0_EL1, info->reg_id_dfr0);
462 init_cpu_ftr_reg(SYS_ID_ISAR0_EL1, info->reg_id_isar0);
463 init_cpu_ftr_reg(SYS_ID_ISAR1_EL1, info->reg_id_isar1);
464 init_cpu_ftr_reg(SYS_ID_ISAR2_EL1, info->reg_id_isar2);
465 init_cpu_ftr_reg(SYS_ID_ISAR3_EL1, info->reg_id_isar3);
466 init_cpu_ftr_reg(SYS_ID_ISAR4_EL1, info->reg_id_isar4);
467 init_cpu_ftr_reg(SYS_ID_ISAR5_EL1, info->reg_id_isar5);
468 init_cpu_ftr_reg(SYS_ID_MMFR0_EL1, info->reg_id_mmfr0);
469 init_cpu_ftr_reg(SYS_ID_MMFR1_EL1, info->reg_id_mmfr1);
470 init_cpu_ftr_reg(SYS_ID_MMFR2_EL1, info->reg_id_mmfr2);
471 init_cpu_ftr_reg(SYS_ID_MMFR3_EL1, info->reg_id_mmfr3);
472 init_cpu_ftr_reg(SYS_ID_PFR0_EL1, info->reg_id_pfr0);
473 init_cpu_ftr_reg(SYS_ID_PFR1_EL1, info->reg_id_pfr1);
474 init_cpu_ftr_reg(SYS_MVFR0_EL1, info->reg_mvfr0);
475 init_cpu_ftr_reg(SYS_MVFR1_EL1, info->reg_mvfr1);
476 init_cpu_ftr_reg(SYS_MVFR2_EL1, info->reg_mvfr2);
481 static void update_cpu_ftr_reg(struct arm64_ftr_reg *reg, u64 new)
483 const struct arm64_ftr_bits *ftrp;
485 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) {
486 s64 ftr_cur = arm64_ftr_value(ftrp, reg->sys_val);
487 s64 ftr_new = arm64_ftr_value(ftrp, new);
489 if (ftr_cur == ftr_new)
491 /* Find a safe value */
492 ftr_new = arm64_ftr_safe_value(ftrp, ftr_new, ftr_cur);
493 reg->sys_val = arm64_ftr_set_value(ftrp, reg->sys_val, ftr_new);
498 static int check_update_ftr_reg(u32 sys_id, int cpu, u64 val, u64 boot)
500 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id);
503 update_cpu_ftr_reg(regp, val);
504 if ((boot & regp->strict_mask) == (val & regp->strict_mask))
506 pr_warn("SANITY CHECK: Unexpected variation in %s. Boot CPU: %#016llx, CPU%d: %#016llx\n",
507 regp->name, boot, cpu, val);
512 * Update system wide CPU feature registers with the values from a
513 * non-boot CPU. Also performs SANITY checks to make sure that there
514 * aren't any insane variations from that of the boot CPU.
516 void update_cpu_features(int cpu,
517 struct cpuinfo_arm64 *info,
518 struct cpuinfo_arm64 *boot)
523 * The kernel can handle differing I-cache policies, but otherwise
524 * caches should look identical. Userspace JITs will make use of
527 taint |= check_update_ftr_reg(SYS_CTR_EL0, cpu,
528 info->reg_ctr, boot->reg_ctr);
531 * Userspace may perform DC ZVA instructions. Mismatched block sizes
532 * could result in too much or too little memory being zeroed if a
533 * process is preempted and migrated between CPUs.
535 taint |= check_update_ftr_reg(SYS_DCZID_EL0, cpu,
536 info->reg_dczid, boot->reg_dczid);
538 /* If different, timekeeping will be broken (especially with KVM) */
539 taint |= check_update_ftr_reg(SYS_CNTFRQ_EL0, cpu,
540 info->reg_cntfrq, boot->reg_cntfrq);
543 * The kernel uses self-hosted debug features and expects CPUs to
544 * support identical debug features. We presently need CTX_CMPs, WRPs,
545 * and BRPs to be identical.
546 * ID_AA64DFR1 is currently RES0.
548 taint |= check_update_ftr_reg(SYS_ID_AA64DFR0_EL1, cpu,
549 info->reg_id_aa64dfr0, boot->reg_id_aa64dfr0);
550 taint |= check_update_ftr_reg(SYS_ID_AA64DFR1_EL1, cpu,
551 info->reg_id_aa64dfr1, boot->reg_id_aa64dfr1);
553 * Even in big.LITTLE, processors should be identical instruction-set
556 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR0_EL1, cpu,
557 info->reg_id_aa64isar0, boot->reg_id_aa64isar0);
558 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR1_EL1, cpu,
559 info->reg_id_aa64isar1, boot->reg_id_aa64isar1);
562 * Differing PARange support is fine as long as all peripherals and
563 * memory are mapped within the minimum PARange of all CPUs.
564 * Linux should not care about secure memory.
566 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR0_EL1, cpu,
567 info->reg_id_aa64mmfr0, boot->reg_id_aa64mmfr0);
568 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR1_EL1, cpu,
569 info->reg_id_aa64mmfr1, boot->reg_id_aa64mmfr1);
570 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR2_EL1, cpu,
571 info->reg_id_aa64mmfr2, boot->reg_id_aa64mmfr2);
574 * EL3 is not our concern.
575 * ID_AA64PFR1 is currently RES0.
577 taint |= check_update_ftr_reg(SYS_ID_AA64PFR0_EL1, cpu,
578 info->reg_id_aa64pfr0, boot->reg_id_aa64pfr0);
579 taint |= check_update_ftr_reg(SYS_ID_AA64PFR1_EL1, cpu,
580 info->reg_id_aa64pfr1, boot->reg_id_aa64pfr1);
583 * If we have AArch32, we care about 32-bit features for compat.
584 * If the system doesn't support AArch32, don't update them.
586 if (id_aa64pfr0_32bit_el0(read_system_reg(SYS_ID_AA64PFR0_EL1)) &&
587 id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) {
589 taint |= check_update_ftr_reg(SYS_ID_DFR0_EL1, cpu,
590 info->reg_id_dfr0, boot->reg_id_dfr0);
591 taint |= check_update_ftr_reg(SYS_ID_ISAR0_EL1, cpu,
592 info->reg_id_isar0, boot->reg_id_isar0);
593 taint |= check_update_ftr_reg(SYS_ID_ISAR1_EL1, cpu,
594 info->reg_id_isar1, boot->reg_id_isar1);
595 taint |= check_update_ftr_reg(SYS_ID_ISAR2_EL1, cpu,
596 info->reg_id_isar2, boot->reg_id_isar2);
597 taint |= check_update_ftr_reg(SYS_ID_ISAR3_EL1, cpu,
598 info->reg_id_isar3, boot->reg_id_isar3);
599 taint |= check_update_ftr_reg(SYS_ID_ISAR4_EL1, cpu,
600 info->reg_id_isar4, boot->reg_id_isar4);
601 taint |= check_update_ftr_reg(SYS_ID_ISAR5_EL1, cpu,
602 info->reg_id_isar5, boot->reg_id_isar5);
605 * Regardless of the value of the AuxReg field, the AIFSR, ADFSR, and
606 * ACTLR formats could differ across CPUs and therefore would have to
607 * be trapped for virtualization anyway.
609 taint |= check_update_ftr_reg(SYS_ID_MMFR0_EL1, cpu,
610 info->reg_id_mmfr0, boot->reg_id_mmfr0);
611 taint |= check_update_ftr_reg(SYS_ID_MMFR1_EL1, cpu,
612 info->reg_id_mmfr1, boot->reg_id_mmfr1);
613 taint |= check_update_ftr_reg(SYS_ID_MMFR2_EL1, cpu,
614 info->reg_id_mmfr2, boot->reg_id_mmfr2);
615 taint |= check_update_ftr_reg(SYS_ID_MMFR3_EL1, cpu,
616 info->reg_id_mmfr3, boot->reg_id_mmfr3);
617 taint |= check_update_ftr_reg(SYS_ID_PFR0_EL1, cpu,
618 info->reg_id_pfr0, boot->reg_id_pfr0);
619 taint |= check_update_ftr_reg(SYS_ID_PFR1_EL1, cpu,
620 info->reg_id_pfr1, boot->reg_id_pfr1);
621 taint |= check_update_ftr_reg(SYS_MVFR0_EL1, cpu,
622 info->reg_mvfr0, boot->reg_mvfr0);
623 taint |= check_update_ftr_reg(SYS_MVFR1_EL1, cpu,
624 info->reg_mvfr1, boot->reg_mvfr1);
625 taint |= check_update_ftr_reg(SYS_MVFR2_EL1, cpu,
626 info->reg_mvfr2, boot->reg_mvfr2);
630 * Mismatched CPU features are a recipe for disaster. Don't even
631 * pretend to support them.
633 WARN_TAINT_ONCE(taint, TAINT_CPU_OUT_OF_SPEC,
634 "Unsupported CPU feature variation.\n");
637 u64 read_system_reg(u32 id)
639 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(id);
641 /* We shouldn't get a request for an unsupported register */
643 return regp->sys_val;
647 * __raw_read_system_reg() - Used by a STARTING cpu before cpuinfo is populated.
648 * Read the system register on the current CPU
650 static u64 __raw_read_system_reg(u32 sys_id)
653 case SYS_ID_PFR0_EL1: return read_cpuid(ID_PFR0_EL1);
654 case SYS_ID_PFR1_EL1: return read_cpuid(ID_PFR1_EL1);
655 case SYS_ID_DFR0_EL1: return read_cpuid(ID_DFR0_EL1);
656 case SYS_ID_MMFR0_EL1: return read_cpuid(ID_MMFR0_EL1);
657 case SYS_ID_MMFR1_EL1: return read_cpuid(ID_MMFR1_EL1);
658 case SYS_ID_MMFR2_EL1: return read_cpuid(ID_MMFR2_EL1);
659 case SYS_ID_MMFR3_EL1: return read_cpuid(ID_MMFR3_EL1);
660 case SYS_ID_ISAR0_EL1: return read_cpuid(ID_ISAR0_EL1);
661 case SYS_ID_ISAR1_EL1: return read_cpuid(ID_ISAR1_EL1);
662 case SYS_ID_ISAR2_EL1: return read_cpuid(ID_ISAR2_EL1);
663 case SYS_ID_ISAR3_EL1: return read_cpuid(ID_ISAR3_EL1);
664 case SYS_ID_ISAR4_EL1: return read_cpuid(ID_ISAR4_EL1);
665 case SYS_ID_ISAR5_EL1: return read_cpuid(ID_ISAR5_EL1);
666 case SYS_MVFR0_EL1: return read_cpuid(MVFR0_EL1);
667 case SYS_MVFR1_EL1: return read_cpuid(MVFR1_EL1);
668 case SYS_MVFR2_EL1: return read_cpuid(MVFR2_EL1);
670 case SYS_ID_AA64PFR0_EL1: return read_cpuid(ID_AA64PFR0_EL1);
671 case SYS_ID_AA64PFR1_EL1: return read_cpuid(ID_AA64PFR1_EL1);
672 case SYS_ID_AA64DFR0_EL1: return read_cpuid(ID_AA64DFR0_EL1);
673 case SYS_ID_AA64DFR1_EL1: return read_cpuid(ID_AA64DFR1_EL1);
674 case SYS_ID_AA64MMFR0_EL1: return read_cpuid(ID_AA64MMFR0_EL1);
675 case SYS_ID_AA64MMFR1_EL1: return read_cpuid(ID_AA64MMFR1_EL1);
676 case SYS_ID_AA64MMFR2_EL1: return read_cpuid(ID_AA64MMFR2_EL1);
677 case SYS_ID_AA64ISAR0_EL1: return read_cpuid(ID_AA64ISAR0_EL1);
678 case SYS_ID_AA64ISAR1_EL1: return read_cpuid(ID_AA64ISAR1_EL1);
680 case SYS_CNTFRQ_EL0: return read_cpuid(CNTFRQ_EL0);
681 case SYS_CTR_EL0: return read_cpuid(CTR_EL0);
682 case SYS_DCZID_EL0: return read_cpuid(DCZID_EL0);
689 #include <linux/irqchip/arm-gic-v3.h>
692 feature_matches(u64 reg, const struct arm64_cpu_capabilities *entry)
694 int val = cpuid_feature_extract_field(reg, entry->field_pos, entry->sign);
696 return val >= entry->min_field_value;
700 has_cpuid_feature(const struct arm64_cpu_capabilities *entry, int scope)
704 WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible());
705 if (scope == SCOPE_SYSTEM)
706 val = read_system_reg(entry->sys_reg);
708 val = __raw_read_system_reg(entry->sys_reg);
710 return feature_matches(val, entry);
713 static bool has_useable_gicv3_cpuif(const struct arm64_cpu_capabilities *entry, int scope)
717 if (!has_cpuid_feature(entry, scope))
720 has_sre = gic_enable_sre();
722 pr_warn_once("%s present but disabled by higher exception level\n",
728 static bool has_no_hw_prefetch(const struct arm64_cpu_capabilities *entry, int __unused)
730 u32 midr = read_cpuid_id();
733 /* Cavium ThunderX pass 1.x and 2.x */
735 rv_max = (1 << MIDR_VARIANT_SHIFT) | MIDR_REVISION_MASK;
737 return MIDR_IS_CPU_MODEL_RANGE(midr, MIDR_THUNDERX, rv_min, rv_max);
740 static bool runs_at_el2(const struct arm64_cpu_capabilities *entry, int __unused)
742 return is_kernel_in_hyp_mode();
745 static bool hyp_offset_low(const struct arm64_cpu_capabilities *entry,
748 phys_addr_t idmap_addr = virt_to_phys(__hyp_idmap_text_start);
751 * Activate the lower HYP offset only if:
752 * - the idmap doesn't clash with it,
753 * - the kernel is not running at EL2.
755 return idmap_addr > GENMASK(VA_BITS - 2, 0) && !is_kernel_in_hyp_mode();
758 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0
759 static int __kpti_forced; /* 0: not forced, >0: forced on, <0: forced off */
761 static bool unmap_kernel_at_el0(const struct arm64_cpu_capabilities *entry,
764 char const *str = "command line option";
765 u64 pfr0 = read_system_reg(SYS_ID_AA64PFR0_EL1);
768 * For reasons that aren't entirely clear, enabling KPTI on Cavium
769 * ThunderX leads to apparent I-cache corruption of kernel text, which
770 * ends as well as you might imagine. Don't even try.
772 if (cpus_have_const_cap(ARM64_WORKAROUND_CAVIUM_27456)) {
773 str = "ARM64_WORKAROUND_CAVIUM_27456";
779 pr_info_once("kernel page table isolation forced %s by %s\n",
780 __kpti_forced > 0 ? "ON" : "OFF", str);
781 return __kpti_forced > 0;
784 /* Useful for KASLR robustness */
785 if (IS_ENABLED(CONFIG_RANDOMIZE_BASE))
788 /* Don't force KPTI for CPUs that are not vulnerable */
789 switch (read_cpuid_id() & MIDR_CPU_MODEL_MASK) {
790 case MIDR_CAVIUM_THUNDERX2:
791 case MIDR_BRCM_VULCAN:
792 case MIDR_CORTEX_A53:
793 case MIDR_CORTEX_A55:
794 case MIDR_CORTEX_A57:
795 case MIDR_CORTEX_A72:
796 case MIDR_CORTEX_A73:
800 /* Defer to CPU feature registers */
801 return !cpuid_feature_extract_unsigned_field(pfr0,
802 ID_AA64PFR0_CSV3_SHIFT);
805 static int kpti_install_ng_mappings(void *__unused)
807 typedef void (kpti_remap_fn)(int, int, phys_addr_t);
808 extern kpti_remap_fn idmap_kpti_install_ng_mappings;
809 kpti_remap_fn *remap_fn;
811 static bool kpti_applied = false;
812 int cpu = smp_processor_id();
817 remap_fn = (void *)__pa_symbol(idmap_kpti_install_ng_mappings);
820 remap_fn(cpu, num_online_cpus(), __pa_symbol(swapper_pg_dir));
821 cpu_uninstall_idmap();
829 static int __init parse_kpti(char *str)
832 int ret = strtobool(str, &enabled);
837 __kpti_forced = enabled ? 1 : -1;
840 early_param("kpti", parse_kpti);
841 #endif /* CONFIG_UNMAP_KERNEL_AT_EL0 */
843 static int cpu_copy_el2regs(void *__unused)
846 * Copy register values that aren't redirected by hardware.
848 * Before code patching, we only set tpidr_el1, all CPUs need to copy
849 * this value to tpidr_el2 before we patch the code. Once we've done
850 * that, freshly-onlined CPUs will set tpidr_el2, so we don't need to
853 if (!alternatives_applied)
854 write_sysreg(read_sysreg(tpidr_el1), tpidr_el2);
859 static const struct arm64_cpu_capabilities arm64_features[] = {
861 .desc = "GIC system register CPU interface",
862 .capability = ARM64_HAS_SYSREG_GIC_CPUIF,
863 .def_scope = SCOPE_SYSTEM,
864 .matches = has_useable_gicv3_cpuif,
865 .sys_reg = SYS_ID_AA64PFR0_EL1,
866 .field_pos = ID_AA64PFR0_GIC_SHIFT,
867 .sign = FTR_UNSIGNED,
868 .min_field_value = 1,
870 #ifdef CONFIG_ARM64_PAN
872 .desc = "Privileged Access Never",
873 .capability = ARM64_HAS_PAN,
874 .def_scope = SCOPE_SYSTEM,
875 .matches = has_cpuid_feature,
876 .sys_reg = SYS_ID_AA64MMFR1_EL1,
877 .field_pos = ID_AA64MMFR1_PAN_SHIFT,
878 .sign = FTR_UNSIGNED,
879 .min_field_value = 1,
880 .enable = cpu_enable_pan,
882 #endif /* CONFIG_ARM64_PAN */
883 #if defined(CONFIG_AS_LSE) && defined(CONFIG_ARM64_LSE_ATOMICS)
885 .desc = "LSE atomic instructions",
886 .capability = ARM64_HAS_LSE_ATOMICS,
887 .def_scope = SCOPE_SYSTEM,
888 .matches = has_cpuid_feature,
889 .sys_reg = SYS_ID_AA64ISAR0_EL1,
890 .field_pos = ID_AA64ISAR0_ATOMICS_SHIFT,
891 .sign = FTR_UNSIGNED,
892 .min_field_value = 2,
894 #endif /* CONFIG_AS_LSE && CONFIG_ARM64_LSE_ATOMICS */
896 .desc = "Software prefetching using PRFM",
897 .capability = ARM64_HAS_NO_HW_PREFETCH,
898 .def_scope = SCOPE_SYSTEM,
899 .matches = has_no_hw_prefetch,
901 #ifdef CONFIG_ARM64_UAO
903 .desc = "User Access Override",
904 .capability = ARM64_HAS_UAO,
905 .def_scope = SCOPE_SYSTEM,
906 .matches = has_cpuid_feature,
907 .sys_reg = SYS_ID_AA64MMFR2_EL1,
908 .field_pos = ID_AA64MMFR2_UAO_SHIFT,
909 .min_field_value = 1,
910 .enable = cpu_enable_uao,
912 #endif /* CONFIG_ARM64_UAO */
913 #ifdef CONFIG_ARM64_PAN
915 .capability = ARM64_ALT_PAN_NOT_UAO,
916 .def_scope = SCOPE_SYSTEM,
917 .matches = cpufeature_pan_not_uao,
919 #endif /* CONFIG_ARM64_PAN */
921 .desc = "Virtualization Host Extensions",
922 .capability = ARM64_HAS_VIRT_HOST_EXTN,
923 .def_scope = SCOPE_SYSTEM,
924 .matches = runs_at_el2,
925 .enable = cpu_copy_el2regs,
928 .desc = "32-bit EL0 Support",
929 .capability = ARM64_HAS_32BIT_EL0,
930 .def_scope = SCOPE_SYSTEM,
931 .matches = has_cpuid_feature,
932 .sys_reg = SYS_ID_AA64PFR0_EL1,
933 .sign = FTR_UNSIGNED,
934 .field_pos = ID_AA64PFR0_EL0_SHIFT,
935 .min_field_value = ID_AA64PFR0_EL0_32BIT_64BIT,
938 .desc = "Reduced HYP mapping offset",
939 .capability = ARM64_HYP_OFFSET_LOW,
940 .def_scope = SCOPE_SYSTEM,
941 .matches = hyp_offset_low,
943 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0
945 .desc = "Kernel page table isolation (KPTI)",
946 .capability = ARM64_UNMAP_KERNEL_AT_EL0,
947 .def_scope = SCOPE_SYSTEM,
948 .matches = unmap_kernel_at_el0,
949 .enable = kpti_install_ng_mappings,
955 #define HWCAP_CAP(reg, field, s, min_value, type, cap) \
958 .def_scope = SCOPE_SYSTEM, \
959 .matches = has_cpuid_feature, \
961 .field_pos = field, \
963 .min_field_value = min_value, \
964 .hwcap_type = type, \
968 static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = {
969 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, HWCAP_PMULL),
970 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_AES),
971 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA1_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_SHA1),
972 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA2_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_SHA2),
973 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_CRC32_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_CRC32),
974 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_ATOMICS_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, HWCAP_ATOMICS),
975 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, FTR_SIGNED, 0, CAP_HWCAP, HWCAP_FP),
976 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, HWCAP_FPHP),
977 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, FTR_SIGNED, 0, CAP_HWCAP, HWCAP_ASIMD),
978 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, HWCAP_ASIMDHP),
982 static const struct arm64_cpu_capabilities compat_elf_hwcaps[] = {
984 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_PMULL),
985 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_AES),
986 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA1_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA1),
987 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA2_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA2),
988 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_CRC32_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_CRC32),
993 static void __init cap_set_elf_hwcap(const struct arm64_cpu_capabilities *cap)
995 switch (cap->hwcap_type) {
997 elf_hwcap |= cap->hwcap;
1000 case CAP_COMPAT_HWCAP:
1001 compat_elf_hwcap |= (u32)cap->hwcap;
1003 case CAP_COMPAT_HWCAP2:
1004 compat_elf_hwcap2 |= (u32)cap->hwcap;
1013 /* Check if we have a particular HWCAP enabled */
1014 static bool cpus_have_elf_hwcap(const struct arm64_cpu_capabilities *cap)
1018 switch (cap->hwcap_type) {
1020 rc = (elf_hwcap & cap->hwcap) != 0;
1022 #ifdef CONFIG_COMPAT
1023 case CAP_COMPAT_HWCAP:
1024 rc = (compat_elf_hwcap & (u32)cap->hwcap) != 0;
1026 case CAP_COMPAT_HWCAP2:
1027 rc = (compat_elf_hwcap2 & (u32)cap->hwcap) != 0;
1038 static void __init setup_elf_hwcaps(const struct arm64_cpu_capabilities *hwcaps)
1040 for (; hwcaps->matches; hwcaps++)
1041 if (hwcaps->matches(hwcaps, hwcaps->def_scope))
1042 cap_set_elf_hwcap(hwcaps);
1046 * Check if the current CPU has a given feature capability.
1047 * Should be called from non-preemptible context.
1049 static bool __this_cpu_has_cap(const struct arm64_cpu_capabilities *cap_array,
1052 const struct arm64_cpu_capabilities *caps;
1054 if (WARN_ON(preemptible()))
1057 for (caps = cap_array; caps->matches; caps++)
1058 if (caps->capability == cap &&
1059 caps->matches(caps, SCOPE_LOCAL_CPU))
1064 void update_cpu_capabilities(const struct arm64_cpu_capabilities *caps,
1067 for (; caps->matches; caps++) {
1068 if (!caps->matches(caps, caps->def_scope))
1071 if (!cpus_have_cap(caps->capability) && caps->desc)
1072 pr_info("%s %s\n", info, caps->desc);
1073 cpus_set_cap(caps->capability);
1078 * Run through the enabled capabilities and enable() it on all active
1081 void __init enable_cpu_capabilities(const struct arm64_cpu_capabilities *caps)
1083 for (; caps->matches; caps++) {
1084 unsigned int num = caps->capability;
1086 if (!cpus_have_cap(num))
1089 /* Ensure cpus_have_const_cap(num) works */
1090 static_branch_enable(&cpu_hwcap_keys[num]);
1094 * Use stop_machine() as it schedules the work allowing
1095 * us to modify PSTATE, instead of on_each_cpu() which
1096 * uses an IPI, giving us a PSTATE that disappears when
1099 stop_machine(caps->enable, (void *)caps, cpu_online_mask);
1105 * Flag to indicate if we have computed the system wide
1106 * capabilities based on the boot time active CPUs. This
1107 * will be used to determine if a new booting CPU should
1108 * go through the verification process to make sure that it
1109 * supports the system capabilities, without using a hotplug
1112 static bool sys_caps_initialised;
1114 static inline void set_sys_caps_initialised(void)
1116 sys_caps_initialised = true;
1120 * Check for CPU features that are used in early boot
1121 * based on the Boot CPU value.
1123 static void check_early_cpu_features(void)
1125 verify_cpu_run_el();
1126 verify_cpu_asid_bits();
1130 verify_local_elf_hwcaps(const struct arm64_cpu_capabilities *caps)
1133 for (; caps->matches; caps++)
1134 if (cpus_have_elf_hwcap(caps) && !caps->matches(caps, SCOPE_LOCAL_CPU)) {
1135 pr_crit("CPU%d: missing HWCAP: %s\n",
1136 smp_processor_id(), caps->desc);
1142 verify_local_cpu_features(const struct arm64_cpu_capabilities *caps_list)
1144 const struct arm64_cpu_capabilities *caps = caps_list;
1145 for (; caps->matches; caps++) {
1146 if (!cpus_have_cap(caps->capability))
1149 * If the new CPU misses an advertised feature, we cannot proceed
1150 * further, park the cpu.
1152 if (!__this_cpu_has_cap(caps_list, caps->capability)) {
1153 pr_crit("CPU%d: missing feature: %s\n",
1154 smp_processor_id(), caps->desc);
1158 caps->enable((void *)caps);
1163 * Run through the enabled system capabilities and enable() it on this CPU.
1164 * The capabilities were decided based on the available CPUs at the boot time.
1165 * Any new CPU should match the system wide status of the capability. If the
1166 * new CPU doesn't have a capability which the system now has enabled, we
1167 * cannot do anything to fix it up and could cause unexpected failures. So
1170 static void verify_local_cpu_capabilities(void)
1172 verify_local_cpu_errata_workarounds();
1173 verify_local_cpu_features(arm64_features);
1174 verify_local_elf_hwcaps(arm64_elf_hwcaps);
1175 if (system_supports_32bit_el0())
1176 verify_local_elf_hwcaps(compat_elf_hwcaps);
1179 void check_local_cpu_capabilities(void)
1182 * All secondary CPUs should conform to the early CPU features
1183 * in use by the kernel based on boot CPU.
1185 check_early_cpu_features();
1188 * If we haven't finalised the system capabilities, this CPU gets
1189 * a chance to update the errata work arounds.
1190 * Otherwise, this CPU should verify that it has all the system
1191 * advertised capabilities.
1193 if (!sys_caps_initialised)
1194 update_cpu_errata_workarounds();
1196 verify_local_cpu_capabilities();
1199 static void __init setup_feature_capabilities(void)
1201 update_cpu_capabilities(arm64_features, "detected feature:");
1202 enable_cpu_capabilities(arm64_features);
1205 DEFINE_STATIC_KEY_FALSE(arm64_const_caps_ready);
1206 EXPORT_SYMBOL(arm64_const_caps_ready);
1208 static void __init mark_const_caps_ready(void)
1210 static_branch_enable(&arm64_const_caps_ready);
1213 extern const struct arm64_cpu_capabilities arm64_errata[];
1215 bool this_cpu_has_cap(unsigned int cap)
1217 return (__this_cpu_has_cap(arm64_features, cap) ||
1218 __this_cpu_has_cap(arm64_errata, cap));
1221 void __init setup_cpu_features(void)
1226 /* Set the CPU feature capabilies */
1227 setup_feature_capabilities();
1228 enable_errata_workarounds();
1229 mark_const_caps_ready();
1230 setup_elf_hwcaps(arm64_elf_hwcaps);
1232 if (system_supports_32bit_el0())
1233 setup_elf_hwcaps(compat_elf_hwcaps);
1235 /* Advertise that we have computed the system capabilities */
1236 set_sys_caps_initialised();
1239 * Check for sane CTR_EL0.CWG value.
1241 cwg = cache_type_cwg();
1242 cls = cache_line_size();
1244 pr_warn("No Cache Writeback Granule information, assuming cache line size %d\n",
1246 if (L1_CACHE_BYTES < cls)
1247 pr_warn("L1_CACHE_BYTES smaller than the Cache Writeback Granule (%d < %d)\n",
1248 L1_CACHE_BYTES, cls);
1251 static bool __maybe_unused
1252 cpufeature_pan_not_uao(const struct arm64_cpu_capabilities *entry, int __unused)
1254 return (cpus_have_const_cap(ARM64_HAS_PAN) && !cpus_have_const_cap(ARM64_HAS_UAO));