arch/arm64/kernel/cpufeature.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Contains CPU feature definitions
   4  *
   5  * Copyright (C) 2015 ARM Ltd.
   6  */
   7
   8 #define pr_fmt(fmt) "CPU features: " fmt
   9
  10 #include <linux/bsearch.h>
  11 #include <linux/cpumask.h>
  12 #include <linux/crash_dump.h>
  13 #include <linux/percpu.h>
  14 #include <linux/sort.h>
  15 #include <linux/stop_machine.h>
  16 #include <linux/types.h>
  17 #include <linux/mm.h>
  18 #include <linux/cpu.h>
  19
  20 #include <asm/cpu.h>
  21 #include <asm/cpufeature.h>
  22 #include <asm/cpu_ops.h>
  23 #include <asm/fpsimd.h>
  24 #include <asm/hwcap.h>
  25 #include <asm/mmu_context.h>
  26 #include <asm/processor.h>
  27 #include <asm/sysreg.h>
  28 #include <asm/traps.h>
  29 #include <asm/vectors.h>
  30 #include <asm/virt.h>
  31
  32 /* Kernel representation of AT_HWCAP and AT_HWCAP2 */
  33 static unsigned long elf_hwcap __read_mostly;
  34
  35 #ifdef CONFIG_COMPAT
  36 #define COMPAT_ELF_HWCAP_DEFAULT        \
  37                                 (COMPAT_HWCAP_HALF|COMPAT_HWCAP_THUMB|\
  38                                  COMPAT_HWCAP_FAST_MULT|COMPAT_HWCAP_EDSP|\
  39                                  COMPAT_HWCAP_TLS|COMPAT_HWCAP_IDIV|\
  40                                  COMPAT_HWCAP_LPAE)
  41 unsigned int compat_elf_hwcap __read_mostly = COMPAT_ELF_HWCAP_DEFAULT;
  42 unsigned int compat_elf_hwcap2 __read_mostly;
  43 #endif
  44
  45 DECLARE_BITMAP(cpu_hwcaps, ARM64_NCAPS);
  46 EXPORT_SYMBOL(cpu_hwcaps);
  47 static struct arm64_cpu_capabilities const __ro_after_init *cpu_hwcaps_ptrs[ARM64_NCAPS];
  48
  49 /* Need also bit for ARM64_CB_PATCH */
  50 DECLARE_BITMAP(boot_capabilities, ARM64_NPATCHABLE);
  51
  52 DEFINE_PER_CPU_READ_MOSTLY(const char *, this_cpu_vector) = vectors;
  53
  54 /*
  55  * Flag to indicate if we have computed the system wide
  56  * capabilities based on the boot time active CPUs. This
  57  * will be used to determine if a new booting CPU should
  58  * go through the verification process to make sure that it
  59  * supports the system capabilities, without using a hotplug
  60  * notifier.
  61  */
  62 static bool sys_caps_initialised;
  63
  64 static inline void set_sys_caps_initialised(void)
  65 {
  66         sys_caps_initialised = true;
  67 }
  68
  69 static int dump_cpu_hwcaps(struct notifier_block *self, unsigned long v, void *p)
  70 {
  71         /* file-wide pr_fmt adds "CPU features: " prefix */
  72         pr_emerg("0x%*pb\n", ARM64_NCAPS, &cpu_hwcaps);
  73         return 0;
  74 }
  75
  76 static struct notifier_block cpu_hwcaps_notifier = {
  77         .notifier_call = dump_cpu_hwcaps
  78 };
  79
  80 static int __init register_cpu_hwcaps_dumper(void)
  81 {
  82         atomic_notifier_chain_register(&panic_notifier_list,
  83                                        &cpu_hwcaps_notifier);
  84         return 0;
  85 }
  86 __initcall(register_cpu_hwcaps_dumper);
  87
  88 DEFINE_STATIC_KEY_ARRAY_FALSE(cpu_hwcap_keys, ARM64_NCAPS);
  89 EXPORT_SYMBOL(cpu_hwcap_keys);
  90
  91 #define __ARM64_FTR_BITS(SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
  92         {                                               \
  93                 .sign = SIGNED,                         \
  94                 .visible = VISIBLE,                     \
  95                 .strict = STRICT,                       \
  96                 .type = TYPE,                           \
  97                 .shift = SHIFT,                         \
  98                 .width = WIDTH,                         \
  99                 .safe_val = SAFE_VAL,                   \
 100         }
 101
 102 /* Define a feature with unsigned values */
 103 #define ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
 104         __ARM64_FTR_BITS(FTR_UNSIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL)
 105
 106 /* Define a feature with a signed value */
 107 #define S_ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
 108         __ARM64_FTR_BITS(FTR_SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL)
 109
 110 #define ARM64_FTR_END                                   \
 111         {                                               \
 112                 .width = 0,                             \
 113         }
 114
 115 /* meta feature for alternatives */
 116 static bool __maybe_unused
 117 cpufeature_pan_not_uao(const struct arm64_cpu_capabilities *entry, int __unused);
 118
 119 static void cpu_enable_cnp(struct arm64_cpu_capabilities const *cap);
 120
 121 /*
 122  * NOTE: Any changes to the visibility of features should be kept in
 123  * sync with the documentation of the CPU feature register ABI.
 124  */
 125 static const struct arm64_ftr_bits ftr_id_aa64isar0[] = {
 126         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_TS_SHIFT, 4, 0),
 127         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_FHM_SHIFT, 4, 0),
 128         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_DP_SHIFT, 4, 0),
 129         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SM4_SHIFT, 4, 0),
 130         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SM3_SHIFT, 4, 0),
 131         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA3_SHIFT, 4, 0),
 132         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_RDM_SHIFT, 4, 0),
 133         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_ATOMICS_SHIFT, 4, 0),
 134         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_CRC32_SHIFT, 4, 0),
 135         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA2_SHIFT, 4, 0),
 136         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA1_SHIFT, 4, 0),
 137         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_AES_SHIFT, 4, 0),
 138         ARM64_FTR_END,
 139 };
 140
 141 static const struct arm64_ftr_bits ftr_id_aa64isar1[] = {
 142         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_SB_SHIFT, 4, 0),
 143         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_FRINTTS_SHIFT, 4, 0),
 144         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
 145                        FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_GPI_SHIFT, 4, 0),
 146         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
 147                        FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_GPA_SHIFT, 4, 0),
 148         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_LRCPC_SHIFT, 4, 0),
 149         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_FCMA_SHIFT, 4, 0),
 150         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_JSCVT_SHIFT, 4, 0),
 151         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
 152                        FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_API_SHIFT, 4, 0),
 153         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
 154                        FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_APA_SHIFT, 4, 0),
 155         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_DPB_SHIFT, 4, 0),
 156         ARM64_FTR_END,
 157 };
 158
 159 static const struct arm64_ftr_bits ftr_id_aa64isar2[] = {
 160         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_AA64ISAR2_CLEARBHB_SHIFT, 4, 0),
 161         ARM64_FTR_END,
 162 };
 163
 164 static const struct arm64_ftr_bits ftr_id_aa64pfr0[] = {
 165         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_CSV3_SHIFT, 4, 0),
 166         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_CSV2_SHIFT, 4, 0),
 167         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_DIT_SHIFT, 4, 0),
 168         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
 169                                    FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_SVE_SHIFT, 4, 0),
 170         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_RAS_SHIFT, 4, 0),
 171         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_GIC_SHIFT, 4, 0),
 172         S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_ASIMD_SHIFT, 4, ID_AA64PFR0_ASIMD_NI),
 173         S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_FP_SHIFT, 4, ID_AA64PFR0_FP_NI),
 174         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL3_SHIFT, 4, 0),
 175         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL2_SHIFT, 4, 0),
 176         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_SHIFT, 4, ID_AA64PFR0_EL1_64BIT_ONLY),
 177         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL0_SHIFT, 4, ID_AA64PFR0_EL0_64BIT_ONLY),
 178         ARM64_FTR_END,
 179 };
 180
 181 static const struct arm64_ftr_bits ftr_id_aa64pfr1[] = {
 182         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_SSBS_SHIFT, 4, ID_AA64PFR1_SSBS_PSTATE_NI),
 183         ARM64_FTR_END,
 184 };
 185
 186 static const struct arm64_ftr_bits ftr_id_aa64zfr0[] = {
 187         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
 188                        FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_SM4_SHIFT, 4, 0),
 189         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
 190                        FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_SHA3_SHIFT, 4, 0),
 191         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
 192                        FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_BITPERM_SHIFT, 4, 0),
 193         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
 194                        FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_AES_SHIFT, 4, 0),
 195         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
 196                        FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_SVEVER_SHIFT, 4, 0),
 197         ARM64_FTR_END,
 198 };
 199
 200 static const struct arm64_ftr_bits ftr_id_aa64mmfr0[] = {
 201         /*
 202          * We already refuse to boot CPUs that don't support our configured
 203          * page size, so we can only detect mismatches for a page size other
 204          * than the one we're currently using. Unfortunately, SoCs like this
 205          * exist in the wild so, even though we don't like it, we'll have to go
 206          * along with it and treat them as non-strict.
 207          */
 208         S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN4_SHIFT, 4, ID_AA64MMFR0_TGRAN4_NI),
 209         S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN64_SHIFT, 4, ID_AA64MMFR0_TGRAN64_NI),
 210         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN16_SHIFT, 4, ID_AA64MMFR0_TGRAN16_NI),
 211
 212         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_BIGENDEL0_SHIFT, 4, 0),
 213         /* Linux shouldn't care about secure memory */
 214         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_SNSMEM_SHIFT, 4, 0),
 215         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_BIGENDEL_SHIFT, 4, 0),
 216         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_ASID_SHIFT, 4, 0),
 217         /*
 218          * Differing PARange is fine as long as all peripherals and memory are mapped
 219          * within the minimum PARange of all CPUs
 220          */
 221         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_PARANGE_SHIFT, 4, 0),
 222         ARM64_FTR_END,
 223 };
 224
 225 static const struct arm64_ftr_bits ftr_id_aa64mmfr1[] = {
 226         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_PAN_SHIFT, 4, 0),
 227         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_LOR_SHIFT, 4, 0),
 228         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_HPD_SHIFT, 4, 0),
 229         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_VHE_SHIFT, 4, 0),
 230         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_VMIDBITS_SHIFT, 4, 0),
 231         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_HADBS_SHIFT, 4, 0),
 232         ARM64_FTR_END,
 233 };
 234
 235 static const struct arm64_ftr_bits ftr_id_aa64mmfr2[] = {
 236         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_FWB_SHIFT, 4, 0),
 237         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_AT_SHIFT, 4, 0),
 238         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_LVA_SHIFT, 4, 0),
 239         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_IESB_SHIFT, 4, 0),
 240         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_LSM_SHIFT, 4, 0),
 241         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_UAO_SHIFT, 4, 0),
 242         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_CNP_SHIFT, 4, 0),
 243         ARM64_FTR_END,
 244 };
 245
 246 static const struct arm64_ftr_bits ftr_ctr[] = {
 247         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, 31, 1, 1), /* RES1 */
 248         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_DIC_SHIFT, 1, 1),
 249         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_IDC_SHIFT, 1, 1),
 250         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, CTR_CWG_SHIFT, 4, 0),
 251         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, CTR_ERG_SHIFT, 4, 0),
 252         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_DMINLINE_SHIFT, 4, 1),
 253         /*
 254          * Linux can handle differing I-cache policies. Userspace JITs will
 255          * make use of *minLine.
 256          * If we have differing I-cache policies, report it as the weakest - VIPT.
 257          */
 258         ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_EXACT, 14, 2, ICACHE_POLICY_VIPT),       /* L1Ip */
 259         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_IMINLINE_SHIFT, 4, 0),
 260         ARM64_FTR_END,
 261 };
 262
 263 struct arm64_ftr_reg arm64_ftr_reg_ctrel0 = {
 264         .name           = "SYS_CTR_EL0",
 265         .ftr_bits       = ftr_ctr
 266 };
 267
 268 static const struct arm64_ftr_bits ftr_id_mmfr0[] = {
 269         S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0xf),   /* InnerShr */
 270         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0),       /* FCSE */
 271         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, 20, 4, 0),    /* AuxReg */
 272         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0),       /* TCM */
 273         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0),       /* ShareLvl */
 274         S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0xf),    /* OuterShr */
 275         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),        /* PMSA */
 276         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),        /* VMSA */
 277         ARM64_FTR_END,
 278 };
 279
 280 static const struct arm64_ftr_bits ftr_id_aa64dfr0[] = {
 281         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 36, 28, 0),
 282         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64DFR0_PMSVER_SHIFT, 4, 0),
 283         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_CTX_CMPS_SHIFT, 4, 0),
 284         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_WRPS_SHIFT, 4, 0),
 285         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_BRPS_SHIFT, 4, 0),
 286         /*
 287          * We can instantiate multiple PMU instances with different levels
 288          * of support.
 289          */
 290         S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64DFR0_PMUVER_SHIFT, 4, 0),
 291         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64DFR0_DEBUGVER_SHIFT, 4, 0x6),
 292         ARM64_FTR_END,
 293 };
 294
 295 static const struct arm64_ftr_bits ftr_mvfr2[] = {
 296         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),                /* FPMisc */
 297         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),                /* SIMDMisc */
 298         ARM64_FTR_END,
 299 };
 300
 301 static const struct arm64_ftr_bits ftr_dczid[] = {
 302         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, 4, 1, 1),            /* DZP */
 303         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),       /* BS */
 304         ARM64_FTR_END,
 305 };
 306
 307
 308 static const struct arm64_ftr_bits ftr_id_isar5[] = {
 309         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_RDM_SHIFT, 4, 0),
 310         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_CRC32_SHIFT, 4, 0),
 311         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SHA2_SHIFT, 4, 0),
 312         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SHA1_SHIFT, 4, 0),
 313         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_AES_SHIFT, 4, 0),
 314         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SEVL_SHIFT, 4, 0),
 315         ARM64_FTR_END,
 316 };
 317
 318 static const struct arm64_ftr_bits ftr_id_mmfr4[] = {
 319         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),        /* ac2 */
 320         ARM64_FTR_END,
 321 };
 322
 323 static const struct arm64_ftr_bits ftr_id_pfr0[] = {
 324         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0),               /* State3 */
 325         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0),                /* State2 */
 326         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),                /* State1 */
 327         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),                /* State0 */
 328         ARM64_FTR_END,
 329 };
 330
 331 static const struct arm64_ftr_bits ftr_id_dfr0[] = {
 332         /* [31:28] TraceFilt */
 333         S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0xf),   /* PerfMon */
 334         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0),
 335         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0),
 336         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0),
 337         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0),
 338         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),
 339         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),
 340         ARM64_FTR_END,
 341 };
 342
 343 static const struct arm64_ftr_bits ftr_zcr[] = {
 344         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE,
 345                 ZCR_ELx_LEN_SHIFT, ZCR_ELx_LEN_SIZE, 0),        /* LEN */
 346         ARM64_FTR_END,
 347 };
 348
 349 /*
 350  * Common ftr bits for a 32bit register with all hidden, strict
 351  * attributes, with 4bit feature fields and a default safe value of
 352  * 0. Covers the following 32bit registers:
 353  * id_isar[0-4], id_mmfr[1-3], id_pfr1, mvfr[0-1]
 354  */
 355 static const struct arm64_ftr_bits ftr_generic_32bits[] = {
 356         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0),
 357         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0),
 358         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0),
 359         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0),
 360         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0),
 361         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0),
 362         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),
 363         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),
 364         ARM64_FTR_END,
 365 };
 366
 367 /* Table for a single 32bit feature value */
 368 static const struct arm64_ftr_bits ftr_single32[] = {
 369         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 0, 32, 0),
 370         ARM64_FTR_END,
 371 };
 372
 373 static const struct arm64_ftr_bits ftr_raz[] = {
 374         ARM64_FTR_END,
 375 };
 376
 377 #define ARM64_FTR_REG(id, table) {              \
 378         .sys_id = id,                           \
 379         .reg =  &(struct arm64_ftr_reg){        \
 380                 .name = #id,                    \
 381                 .ftr_bits = &((table)[0]),      \
 382         }}
 383
 384 static const struct __ftr_reg_entry {
 385         u32                     sys_id;
 386         struct arm64_ftr_reg    *reg;
 387 } arm64_ftr_regs[] = {
 388
 389         /* Op1 = 0, CRn = 0, CRm = 1 */
 390         ARM64_FTR_REG(SYS_ID_PFR0_EL1, ftr_id_pfr0),
 391         ARM64_FTR_REG(SYS_ID_PFR1_EL1, ftr_generic_32bits),
 392         ARM64_FTR_REG(SYS_ID_DFR0_EL1, ftr_id_dfr0),
 393         ARM64_FTR_REG(SYS_ID_MMFR0_EL1, ftr_id_mmfr0),
 394         ARM64_FTR_REG(SYS_ID_MMFR1_EL1, ftr_generic_32bits),
 395         ARM64_FTR_REG(SYS_ID_MMFR2_EL1, ftr_generic_32bits),
 396         ARM64_FTR_REG(SYS_ID_MMFR3_EL1, ftr_generic_32bits),
 397
 398         /* Op1 = 0, CRn = 0, CRm = 2 */
 399         ARM64_FTR_REG(SYS_ID_ISAR0_EL1, ftr_generic_32bits),
 400         ARM64_FTR_REG(SYS_ID_ISAR1_EL1, ftr_generic_32bits),
 401         ARM64_FTR_REG(SYS_ID_ISAR2_EL1, ftr_generic_32bits),
 402         ARM64_FTR_REG(SYS_ID_ISAR3_EL1, ftr_generic_32bits),
 403         ARM64_FTR_REG(SYS_ID_ISAR4_EL1, ftr_generic_32bits),
 404         ARM64_FTR_REG(SYS_ID_ISAR5_EL1, ftr_id_isar5),
 405         ARM64_FTR_REG(SYS_ID_MMFR4_EL1, ftr_id_mmfr4),
 406
 407         /* Op1 = 0, CRn = 0, CRm = 3 */
 408         ARM64_FTR_REG(SYS_MVFR0_EL1, ftr_generic_32bits),
 409         ARM64_FTR_REG(SYS_MVFR1_EL1, ftr_generic_32bits),
 410         ARM64_FTR_REG(SYS_MVFR2_EL1, ftr_mvfr2),
 411
 412         /* Op1 = 0, CRn = 0, CRm = 4 */
 413         ARM64_FTR_REG(SYS_ID_AA64PFR0_EL1, ftr_id_aa64pfr0),
 414         ARM64_FTR_REG(SYS_ID_AA64PFR1_EL1, ftr_id_aa64pfr1),
 415         ARM64_FTR_REG(SYS_ID_AA64ZFR0_EL1, ftr_id_aa64zfr0),
 416
 417         /* Op1 = 0, CRn = 0, CRm = 5 */
 418         ARM64_FTR_REG(SYS_ID_AA64DFR0_EL1, ftr_id_aa64dfr0),
 419         ARM64_FTR_REG(SYS_ID_AA64DFR1_EL1, ftr_raz),
 420
 421         /* Op1 = 0, CRn = 0, CRm = 6 */
 422         ARM64_FTR_REG(SYS_ID_AA64ISAR0_EL1, ftr_id_aa64isar0),
 423         ARM64_FTR_REG(SYS_ID_AA64ISAR1_EL1, ftr_id_aa64isar1),
 424         ARM64_FTR_REG(SYS_ID_AA64ISAR2_EL1, ftr_id_aa64isar2),
 425
 426         /* Op1 = 0, CRn = 0, CRm = 7 */
 427         ARM64_FTR_REG(SYS_ID_AA64MMFR0_EL1, ftr_id_aa64mmfr0),
 428         ARM64_FTR_REG(SYS_ID_AA64MMFR1_EL1, ftr_id_aa64mmfr1),
 429         ARM64_FTR_REG(SYS_ID_AA64MMFR2_EL1, ftr_id_aa64mmfr2),
 430
 431         /* Op1 = 0, CRn = 1, CRm = 2 */
 432         ARM64_FTR_REG(SYS_ZCR_EL1, ftr_zcr),
 433
 434         /* Op1 = 3, CRn = 0, CRm = 0 */
 435         { SYS_CTR_EL0, &arm64_ftr_reg_ctrel0 },
 436         ARM64_FTR_REG(SYS_DCZID_EL0, ftr_dczid),
 437
 438         /* Op1 = 3, CRn = 14, CRm = 0 */
 439         ARM64_FTR_REG(SYS_CNTFRQ_EL0, ftr_single32),
 440 };
 441
 442 static int search_cmp_ftr_reg(const void *id, const void *regp)
 443 {
 444         return (int)(unsigned long)id - (int)((const struct __ftr_reg_entry *)regp)->sys_id;
 445 }
 446
 447 /*
 448  * get_arm64_ftr_reg - Lookup a feature register entry using its
 449  * sys_reg() encoding. With the array arm64_ftr_regs sorted in the
 450  * ascending order of sys_id , we use binary search to find a matching
 451  * entry.
 452  *
 453  * returns - Upon success,  matching ftr_reg entry for id.
 454  *         - NULL on failure. It is upto the caller to decide
 455  *           the impact of a failure.
 456  */
 457 static struct arm64_ftr_reg *get_arm64_ftr_reg(u32 sys_id)
 458 {
 459         const struct __ftr_reg_entry *ret;
 460
 461         ret = bsearch((const void *)(unsigned long)sys_id,
 462                         arm64_ftr_regs,
 463                         ARRAY_SIZE(arm64_ftr_regs),
 464                         sizeof(arm64_ftr_regs[0]),
 465                         search_cmp_ftr_reg);
 466         if (ret)
 467                 return ret->reg;
 468         return NULL;
 469 }
 470
 471 static u64 arm64_ftr_set_value(const struct arm64_ftr_bits *ftrp, s64 reg,
 472                                s64 ftr_val)
 473 {
 474         u64 mask = arm64_ftr_mask(ftrp);
 475
 476         reg &= ~mask;
 477         reg |= (ftr_val << ftrp->shift) & mask;
 478         return reg;
 479 }
 480
 481 static s64 arm64_ftr_safe_value(const struct arm64_ftr_bits *ftrp, s64 new,
 482                                 s64 cur)
 483 {
 484         s64 ret = 0;
 485
 486         switch (ftrp->type) {
 487         case FTR_EXACT:
 488                 ret = ftrp->safe_val;
 489                 break;
 490         case FTR_LOWER_SAFE:
 491                 ret = new < cur ? new : cur;
 492                 break;
 493         case FTR_HIGHER_OR_ZERO_SAFE:
 494                 if (!cur || !new)
 495                         break;
 496                 /* Fallthrough */
 497         case FTR_HIGHER_SAFE:
 498                 ret = new > cur ? new : cur;
 499                 break;
 500         default:
 501                 BUG();
 502         }
 503
 504         return ret;
 505 }
 506
 507 static void __init sort_ftr_regs(void)
 508 {
 509         int i;
 510
 511         /* Check that the array is sorted so that we can do the binary search */
 512         for (i = 1; i < ARRAY_SIZE(arm64_ftr_regs); i++)
 513                 BUG_ON(arm64_ftr_regs[i].sys_id < arm64_ftr_regs[i - 1].sys_id);
 514 }
 515
 516 /*
 517  * Initialise the CPU feature register from Boot CPU values.
 518  * Also initiliases the strict_mask for the register.
 519  * Any bits that are not covered by an arm64_ftr_bits entry are considered
 520  * RES0 for the system-wide value, and must strictly match.
 521  */
 522 static void __init init_cpu_ftr_reg(u32 sys_reg, u64 new)
 523 {
 524         u64 val = 0;
 525         u64 strict_mask = ~0x0ULL;
 526         u64 user_mask = 0;
 527         u64 valid_mask = 0;
 528
 529         const struct arm64_ftr_bits *ftrp;
 530         struct arm64_ftr_reg *reg = get_arm64_ftr_reg(sys_reg);
 531
 532         BUG_ON(!reg);
 533
 534         for (ftrp  = reg->ftr_bits; ftrp->width; ftrp++) {
 535                 u64 ftr_mask = arm64_ftr_mask(ftrp);
 536                 s64 ftr_new = arm64_ftr_value(ftrp, new);
 537
 538                 val = arm64_ftr_set_value(ftrp, val, ftr_new);
 539
 540                 valid_mask |= ftr_mask;
 541                 if (!ftrp->strict)
 542                         strict_mask &= ~ftr_mask;
 543                 if (ftrp->visible)
 544                         user_mask |= ftr_mask;
 545                 else
 546                         reg->user_val = arm64_ftr_set_value(ftrp,
 547                                                             reg->user_val,
 548                                                             ftrp->safe_val);
 549         }
 550
 551         val &= valid_mask;
 552
 553         reg->sys_val = val;
 554         reg->strict_mask = strict_mask;
 555         reg->user_mask = user_mask;
 556 }
 557
 558 extern const struct arm64_cpu_capabilities arm64_errata[];
 559 static const struct arm64_cpu_capabilities arm64_features[];
 560
 561 static void __init
 562 init_cpu_hwcaps_indirect_list_from_array(const struct arm64_cpu_capabilities *caps)
 563 {
 564         for (; caps->matches; caps++) {
 565                 if (WARN(caps->capability >= ARM64_NCAPS,
 566                         "Invalid capability %d\n", caps->capability))
 567                         continue;
 568                 if (WARN(cpu_hwcaps_ptrs[caps->capability],
 569                         "Duplicate entry for capability %d\n",
 570                         caps->capability))
 571                         continue;
 572                 cpu_hwcaps_ptrs[caps->capability] = caps;
 573         }
 574 }
 575
 576 static void __init init_cpu_hwcaps_indirect_list(void)
 577 {
 578         init_cpu_hwcaps_indirect_list_from_array(arm64_features);
 579         init_cpu_hwcaps_indirect_list_from_array(arm64_errata);
 580 }
 581
 582 static void __init setup_boot_cpu_capabilities(void);
 583
 584 void __init init_cpu_features(struct cpuinfo_arm64 *info)
 585 {
 586         /* Before we start using the tables, make sure it is sorted */
 587         sort_ftr_regs();
 588
 589         init_cpu_ftr_reg(SYS_CTR_EL0, info->reg_ctr);
 590         init_cpu_ftr_reg(SYS_DCZID_EL0, info->reg_dczid);
 591         init_cpu_ftr_reg(SYS_CNTFRQ_EL0, info->reg_cntfrq);
 592         init_cpu_ftr_reg(SYS_ID_AA64DFR0_EL1, info->reg_id_aa64dfr0);
 593         init_cpu_ftr_reg(SYS_ID_AA64DFR1_EL1, info->reg_id_aa64dfr1);
 594         init_cpu_ftr_reg(SYS_ID_AA64ISAR0_EL1, info->reg_id_aa64isar0);
 595         init_cpu_ftr_reg(SYS_ID_AA64ISAR1_EL1, info->reg_id_aa64isar1);
 596         init_cpu_ftr_reg(SYS_ID_AA64ISAR2_EL1, info->reg_id_aa64isar2);
 597         init_cpu_ftr_reg(SYS_ID_AA64MMFR0_EL1, info->reg_id_aa64mmfr0);
 598         init_cpu_ftr_reg(SYS_ID_AA64MMFR1_EL1, info->reg_id_aa64mmfr1);
 599         init_cpu_ftr_reg(SYS_ID_AA64MMFR2_EL1, info->reg_id_aa64mmfr2);
 600         init_cpu_ftr_reg(SYS_ID_AA64PFR0_EL1, info->reg_id_aa64pfr0);
 601         init_cpu_ftr_reg(SYS_ID_AA64PFR1_EL1, info->reg_id_aa64pfr1);
 602         init_cpu_ftr_reg(SYS_ID_AA64ZFR0_EL1, info->reg_id_aa64zfr0);
 603
 604         if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) {
 605                 init_cpu_ftr_reg(SYS_ID_DFR0_EL1, info->reg_id_dfr0);
 606                 init_cpu_ftr_reg(SYS_ID_ISAR0_EL1, info->reg_id_isar0);
 607                 init_cpu_ftr_reg(SYS_ID_ISAR1_EL1, info->reg_id_isar1);
 608                 init_cpu_ftr_reg(SYS_ID_ISAR2_EL1, info->reg_id_isar2);
 609                 init_cpu_ftr_reg(SYS_ID_ISAR3_EL1, info->reg_id_isar3);
 610                 init_cpu_ftr_reg(SYS_ID_ISAR4_EL1, info->reg_id_isar4);
 611                 init_cpu_ftr_reg(SYS_ID_ISAR5_EL1, info->reg_id_isar5);
 612                 init_cpu_ftr_reg(SYS_ID_MMFR0_EL1, info->reg_id_mmfr0);
 613                 init_cpu_ftr_reg(SYS_ID_MMFR1_EL1, info->reg_id_mmfr1);
 614                 init_cpu_ftr_reg(SYS_ID_MMFR2_EL1, info->reg_id_mmfr2);
 615                 init_cpu_ftr_reg(SYS_ID_MMFR3_EL1, info->reg_id_mmfr3);
 616                 init_cpu_ftr_reg(SYS_ID_PFR0_EL1, info->reg_id_pfr0);
 617                 init_cpu_ftr_reg(SYS_ID_PFR1_EL1, info->reg_id_pfr1);
 618                 init_cpu_ftr_reg(SYS_MVFR0_EL1, info->reg_mvfr0);
 619                 init_cpu_ftr_reg(SYS_MVFR1_EL1, info->reg_mvfr1);
 620                 init_cpu_ftr_reg(SYS_MVFR2_EL1, info->reg_mvfr2);
 621         }
 622
 623         if (id_aa64pfr0_sve(info->reg_id_aa64pfr0)) {
 624                 init_cpu_ftr_reg(SYS_ZCR_EL1, info->reg_zcr);
 625                 sve_init_vq_map();
 626         }
 627
 628         /*
 629          * Initialize the indirect array of CPU hwcaps capabilities pointers
 630          * before we handle the boot CPU below.
 631          */
 632         init_cpu_hwcaps_indirect_list();
 633
 634         /*
 635          * Detect and enable early CPU capabilities based on the boot CPU,
 636          * after we have initialised the CPU feature infrastructure.
 637          */
 638         setup_boot_cpu_capabilities();
 639 }
 640
 641 static void update_cpu_ftr_reg(struct arm64_ftr_reg *reg, u64 new)
 642 {
 643         const struct arm64_ftr_bits *ftrp;
 644
 645         for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) {
 646                 s64 ftr_cur = arm64_ftr_value(ftrp, reg->sys_val);
 647                 s64 ftr_new = arm64_ftr_value(ftrp, new);
 648
 649                 if (ftr_cur == ftr_new)
 650                         continue;
 651                 /* Find a safe value */
 652                 ftr_new = arm64_ftr_safe_value(ftrp, ftr_new, ftr_cur);
 653                 reg->sys_val = arm64_ftr_set_value(ftrp, reg->sys_val, ftr_new);
 654         }
 655
 656 }
 657
 658 static int check_update_ftr_reg(u32 sys_id, int cpu, u64 val, u64 boot)
 659 {
 660         struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id);
 661
 662         BUG_ON(!regp);
 663         update_cpu_ftr_reg(regp, val);
 664         if ((boot & regp->strict_mask) == (val & regp->strict_mask))
 665                 return 0;
 666         pr_warn("SANITY CHECK: Unexpected variation in %s. Boot CPU: %#016llx, CPU%d: %#016llx\n",
 667                         regp->name, boot, cpu, val);
 668         return 1;
 669 }
 670
 671 /*
 672  * Update system wide CPU feature registers with the values from a
 673  * non-boot CPU. Also performs SANITY checks to make sure that there
 674  * aren't any insane variations from that of the boot CPU.
 675  */
 676 void update_cpu_features(int cpu,
 677                          struct cpuinfo_arm64 *info,
 678                          struct cpuinfo_arm64 *boot)
 679 {
 680         int taint = 0;
 681
 682         /*
 683          * The kernel can handle differing I-cache policies, but otherwise
 684          * caches should look identical. Userspace JITs will make use of
 685          * *minLine.
 686          */
 687         taint |= check_update_ftr_reg(SYS_CTR_EL0, cpu,
 688                                       info->reg_ctr, boot->reg_ctr);
 689
 690         /*
 691          * Userspace may perform DC ZVA instructions. Mismatched block sizes
 692          * could result in too much or too little memory being zeroed if a
 693          * process is preempted and migrated between CPUs.
 694          */
 695         taint |= check_update_ftr_reg(SYS_DCZID_EL0, cpu,
 696                                       info->reg_dczid, boot->reg_dczid);
 697
 698         /* If different, timekeeping will be broken (especially with KVM) */
 699         taint |= check_update_ftr_reg(SYS_CNTFRQ_EL0, cpu,
 700                                       info->reg_cntfrq, boot->reg_cntfrq);
 701
 702         /*
 703          * The kernel uses self-hosted debug features and expects CPUs to
 704          * support identical debug features. We presently need CTX_CMPs, WRPs,
 705          * and BRPs to be identical.
 706          * ID_AA64DFR1 is currently RES0.
 707          */
 708         taint |= check_update_ftr_reg(SYS_ID_AA64DFR0_EL1, cpu,
 709                                       info->reg_id_aa64dfr0, boot->reg_id_aa64dfr0);
 710         taint |= check_update_ftr_reg(SYS_ID_AA64DFR1_EL1, cpu,
 711                                       info->reg_id_aa64dfr1, boot->reg_id_aa64dfr1);
 712         /*
 713          * Even in big.LITTLE, processors should be identical instruction-set
 714          * wise.
 715          */
 716         taint |= check_update_ftr_reg(SYS_ID_AA64ISAR0_EL1, cpu,
 717                                       info->reg_id_aa64isar0, boot->reg_id_aa64isar0);
 718         taint |= check_update_ftr_reg(SYS_ID_AA64ISAR1_EL1, cpu,
 719                                       info->reg_id_aa64isar1, boot->reg_id_aa64isar1);
 720         taint |= check_update_ftr_reg(SYS_ID_AA64ISAR2_EL1, cpu,
 721                                       info->reg_id_aa64isar2, boot->reg_id_aa64isar2);
 722
 723         /*
 724          * Differing PARange support is fine as long as all peripherals and
 725          * memory are mapped within the minimum PARange of all CPUs.
 726          * Linux should not care about secure memory.
 727          */
 728         taint |= check_update_ftr_reg(SYS_ID_AA64MMFR0_EL1, cpu,
 729                                       info->reg_id_aa64mmfr0, boot->reg_id_aa64mmfr0);
 730         taint |= check_update_ftr_reg(SYS_ID_AA64MMFR1_EL1, cpu,
 731                                       info->reg_id_aa64mmfr1, boot->reg_id_aa64mmfr1);
 732         taint |= check_update_ftr_reg(SYS_ID_AA64MMFR2_EL1, cpu,
 733                                       info->reg_id_aa64mmfr2, boot->reg_id_aa64mmfr2);
 734
 735         taint |= check_update_ftr_reg(SYS_ID_AA64PFR0_EL1, cpu,
 736                                       info->reg_id_aa64pfr0, boot->reg_id_aa64pfr0);
 737         taint |= check_update_ftr_reg(SYS_ID_AA64PFR1_EL1, cpu,
 738                                       info->reg_id_aa64pfr1, boot->reg_id_aa64pfr1);
 739
 740         taint |= check_update_ftr_reg(SYS_ID_AA64ZFR0_EL1, cpu,
 741                                       info->reg_id_aa64zfr0, boot->reg_id_aa64zfr0);
 742
 743         /*
 744          * If we have AArch32, we care about 32-bit features for compat.
 745          * If the system doesn't support AArch32, don't update them.
 746          */
 747         if (id_aa64pfr0_32bit_el0(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1)) &&
 748                 id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) {
 749
 750                 taint |= check_update_ftr_reg(SYS_ID_DFR0_EL1, cpu,
 751                                         info->reg_id_dfr0, boot->reg_id_dfr0);
 752                 taint |= check_update_ftr_reg(SYS_ID_ISAR0_EL1, cpu,
 753                                         info->reg_id_isar0, boot->reg_id_isar0);
 754                 taint |= check_update_ftr_reg(SYS_ID_ISAR1_EL1, cpu,
 755                                         info->reg_id_isar1, boot->reg_id_isar1);
 756                 taint |= check_update_ftr_reg(SYS_ID_ISAR2_EL1, cpu,
 757                                         info->reg_id_isar2, boot->reg_id_isar2);
 758                 taint |= check_update_ftr_reg(SYS_ID_ISAR3_EL1, cpu,
 759                                         info->reg_id_isar3, boot->reg_id_isar3);
 760                 taint |= check_update_ftr_reg(SYS_ID_ISAR4_EL1, cpu,
 761                                         info->reg_id_isar4, boot->reg_id_isar4);
 762                 taint |= check_update_ftr_reg(SYS_ID_ISAR5_EL1, cpu,
 763                                         info->reg_id_isar5, boot->reg_id_isar5);
 764
 765                 /*
 766                  * Regardless of the value of the AuxReg field, the AIFSR, ADFSR, and
 767                  * ACTLR formats could differ across CPUs and therefore would have to
 768                  * be trapped for virtualization anyway.
 769                  */
 770                 taint |= check_update_ftr_reg(SYS_ID_MMFR0_EL1, cpu,
 771                                         info->reg_id_mmfr0, boot->reg_id_mmfr0);
 772                 taint |= check_update_ftr_reg(SYS_ID_MMFR1_EL1, cpu,
 773                                         info->reg_id_mmfr1, boot->reg_id_mmfr1);
 774                 taint |= check_update_ftr_reg(SYS_ID_MMFR2_EL1, cpu,
 775                                         info->reg_id_mmfr2, boot->reg_id_mmfr2);
 776                 taint |= check_update_ftr_reg(SYS_ID_MMFR3_EL1, cpu,
 777                                         info->reg_id_mmfr3, boot->reg_id_mmfr3);
 778                 taint |= check_update_ftr_reg(SYS_ID_PFR0_EL1, cpu,
 779                                         info->reg_id_pfr0, boot->reg_id_pfr0);
 780                 taint |= check_update_ftr_reg(SYS_ID_PFR1_EL1, cpu,
 781                                         info->reg_id_pfr1, boot->reg_id_pfr1);
 782                 taint |= check_update_ftr_reg(SYS_MVFR0_EL1, cpu,
 783                                         info->reg_mvfr0, boot->reg_mvfr0);
 784                 taint |= check_update_ftr_reg(SYS_MVFR1_EL1, cpu,
 785                                         info->reg_mvfr1, boot->reg_mvfr1);
 786                 taint |= check_update_ftr_reg(SYS_MVFR2_EL1, cpu,
 787                                         info->reg_mvfr2, boot->reg_mvfr2);
 788         }
 789
 790         if (id_aa64pfr0_sve(info->reg_id_aa64pfr0)) {
 791                 taint |= check_update_ftr_reg(SYS_ZCR_EL1, cpu,
 792                                         info->reg_zcr, boot->reg_zcr);
 793
 794                 /* Probe vector lengths, unless we already gave up on SVE */
 795                 if (id_aa64pfr0_sve(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1)) &&
 796                     !sys_caps_initialised)
 797                         sve_update_vq_map();
 798         }
 799
 800         /*
 801          * Mismatched CPU features are a recipe for disaster. Don't even
 802          * pretend to support them.
 803          */
 804         if (taint) {
 805                 pr_warn_once("Unsupported CPU feature variation detected.\n");
 806                 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK);
 807         }
 808 }
 809
 810 u64 read_sanitised_ftr_reg(u32 id)
 811 {
 812         struct arm64_ftr_reg *regp = get_arm64_ftr_reg(id);
 813
 814         /* We shouldn't get a request for an unsupported register */
 815         BUG_ON(!regp);
 816         return regp->sys_val;
 817 }
 818
 819 #define read_sysreg_case(r)     \
 820         case r:         return read_sysreg_s(r)
 821
 822 /*
 823  * __read_sysreg_by_encoding() - Used by a STARTING cpu before cpuinfo is populated.
 824  * Read the system register on the current CPU
 825  */
 826 static u64 __read_sysreg_by_encoding(u32 sys_id)
 827 {
 828         switch (sys_id) {
 829         read_sysreg_case(SYS_ID_PFR0_EL1);
 830         read_sysreg_case(SYS_ID_PFR1_EL1);
 831         read_sysreg_case(SYS_ID_DFR0_EL1);
 832         read_sysreg_case(SYS_ID_MMFR0_EL1);
 833         read_sysreg_case(SYS_ID_MMFR1_EL1);
 834         read_sysreg_case(SYS_ID_MMFR2_EL1);
 835         read_sysreg_case(SYS_ID_MMFR3_EL1);
 836         read_sysreg_case(SYS_ID_ISAR0_EL1);
 837         read_sysreg_case(SYS_ID_ISAR1_EL1);
 838         read_sysreg_case(SYS_ID_ISAR2_EL1);
 839         read_sysreg_case(SYS_ID_ISAR3_EL1);
 840         read_sysreg_case(SYS_ID_ISAR4_EL1);
 841         read_sysreg_case(SYS_ID_ISAR5_EL1);
 842         read_sysreg_case(SYS_MVFR0_EL1);
 843         read_sysreg_case(SYS_MVFR1_EL1);
 844         read_sysreg_case(SYS_MVFR2_EL1);
 845
 846         read_sysreg_case(SYS_ID_AA64PFR0_EL1);
 847         read_sysreg_case(SYS_ID_AA64PFR1_EL1);
 848         read_sysreg_case(SYS_ID_AA64ZFR0_EL1);
 849         read_sysreg_case(SYS_ID_AA64DFR0_EL1);
 850         read_sysreg_case(SYS_ID_AA64DFR1_EL1);
 851         read_sysreg_case(SYS_ID_AA64MMFR0_EL1);
 852         read_sysreg_case(SYS_ID_AA64MMFR1_EL1);
 853         read_sysreg_case(SYS_ID_AA64MMFR2_EL1);
 854         read_sysreg_case(SYS_ID_AA64ISAR0_EL1);
 855         read_sysreg_case(SYS_ID_AA64ISAR1_EL1);
 856         read_sysreg_case(SYS_ID_AA64ISAR2_EL1);
 857
 858         read_sysreg_case(SYS_CNTFRQ_EL0);
 859         read_sysreg_case(SYS_CTR_EL0);
 860         read_sysreg_case(SYS_DCZID_EL0);
 861
 862         default:
 863                 BUG();
 864                 return 0;
 865         }
 866 }
 867
 868 #include <linux/irqchip/arm-gic-v3.h>
 869
 870 static bool
 871 feature_matches(u64 reg, const struct arm64_cpu_capabilities *entry)
 872 {
 873         int val = cpuid_feature_extract_field(reg, entry->field_pos, entry->sign);
 874
 875         return val >= entry->min_field_value;
 876 }
 877
 878 static bool
 879 has_cpuid_feature(const struct arm64_cpu_capabilities *entry, int scope)
 880 {
 881         u64 val;
 882
 883         WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible());
 884         if (scope == SCOPE_SYSTEM)
 885                 val = read_sanitised_ftr_reg(entry->sys_reg);
 886         else
 887                 val = __read_sysreg_by_encoding(entry->sys_reg);
 888
 889         return feature_matches(val, entry);
 890 }
 891
 892 static bool has_useable_gicv3_cpuif(const struct arm64_cpu_capabilities *entry, int scope)
 893 {
 894         bool has_sre;
 895
 896         if (!has_cpuid_feature(entry, scope))
 897                 return false;
 898
 899         has_sre = gic_enable_sre();
 900         if (!has_sre)
 901                 pr_warn_once("%s present but disabled by higher exception level\n",
 902                              entry->desc);
 903
 904         return has_sre;
 905 }
 906
 907 static bool has_no_hw_prefetch(const struct arm64_cpu_capabilities *entry, int __unused)
 908 {
 909         u32 midr = read_cpuid_id();
 910
 911         /* Cavium ThunderX pass 1.x and 2.x */
 912         return midr_is_cpu_model_range(midr, MIDR_THUNDERX,
 913                 MIDR_CPU_VAR_REV(0, 0),
 914                 MIDR_CPU_VAR_REV(1, MIDR_REVISION_MASK));
 915 }
 916
 917 static bool has_no_fpsimd(const struct arm64_cpu_capabilities *entry, int __unused)
 918 {
 919         u64 pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1);
 920
 921         return cpuid_feature_extract_signed_field(pfr0,
 922                                         ID_AA64PFR0_FP_SHIFT) < 0;
 923 }
 924
 925 static bool has_cache_idc(const struct arm64_cpu_capabilities *entry,
 926                           int scope)
 927 {
 928         u64 ctr;
 929
 930         if (scope == SCOPE_SYSTEM)
 931                 ctr = arm64_ftr_reg_ctrel0.sys_val;
 932         else
 933                 ctr = read_cpuid_effective_cachetype();
 934
 935         return ctr & BIT(CTR_IDC_SHIFT);
 936 }
 937
 938 static void cpu_emulate_effective_ctr(const struct arm64_cpu_capabilities *__unused)
 939 {
 940         /*
 941          * If the CPU exposes raw CTR_EL0.IDC = 0, while effectively
 942          * CTR_EL0.IDC = 1 (from CLIDR values), we need to trap accesses
 943          * to the CTR_EL0 on this CPU and emulate it with the real/safe
 944          * value.
 945          */
 946         if (!(read_cpuid_cachetype() & BIT(CTR_IDC_SHIFT)))
 947                 sysreg_clear_set(sctlr_el1, SCTLR_EL1_UCT, 0);
 948 }
 949
 950 static bool has_cache_dic(const struct arm64_cpu_capabilities *entry,
 951                           int scope)
 952 {
 953         u64 ctr;
 954
 955         if (scope == SCOPE_SYSTEM)
 956                 ctr = arm64_ftr_reg_ctrel0.sys_val;
 957         else
 958                 ctr = read_cpuid_cachetype();
 959
 960         return ctr & BIT(CTR_DIC_SHIFT);
 961 }
 962
 963 static bool __maybe_unused
 964 has_useable_cnp(const struct arm64_cpu_capabilities *entry, int scope)
 965 {
 966         /*
 967          * Kdump isn't guaranteed to power-off all secondary CPUs, CNP
 968          * may share TLB entries with a CPU stuck in the crashed
 969          * kernel.
 970          */
 971          if (is_kdump_kernel())
 972                 return false;
 973
 974         return has_cpuid_feature(entry, scope);
 975 }
 976
 977 static bool __meltdown_safe = true;
 978 static int __kpti_forced; /* 0: not forced, >0: forced on, <0: forced off */
 979
 980 static bool unmap_kernel_at_el0(const struct arm64_cpu_capabilities *entry,
 981                                 int scope)
 982 {
 983         /* List of CPUs that are not vulnerable and don't need KPTI */
 984         static const struct midr_range kpti_safe_list[] = {
 985                 MIDR_ALL_VERSIONS(MIDR_CAVIUM_THUNDERX2),
 986                 MIDR_ALL_VERSIONS(MIDR_BRCM_VULCAN),
 987                 MIDR_ALL_VERSIONS(MIDR_CORTEX_A35),
 988                 MIDR_ALL_VERSIONS(MIDR_CORTEX_A53),
 989                 MIDR_ALL_VERSIONS(MIDR_CORTEX_A55),
 990                 MIDR_ALL_VERSIONS(MIDR_CORTEX_A57),
 991                 MIDR_ALL_VERSIONS(MIDR_CORTEX_A72),
 992                 MIDR_ALL_VERSIONS(MIDR_CORTEX_A73),
 993                 MIDR_ALL_VERSIONS(MIDR_HISI_TSV110),
 994                 { /* sentinel */ }
 995         };
 996         char const *str = "kpti command line option";
 997         bool meltdown_safe;
 998
 999         meltdown_safe = is_midr_in_range_list(read_cpuid_id(), kpti_safe_list);
1000
1001         /* Defer to CPU feature registers */
1002         if (has_cpuid_feature(entry, scope))
1003                 meltdown_safe = true;
1004
1005         if (!meltdown_safe)
1006                 __meltdown_safe = false;
1007
1008         /*
1009          * For reasons that aren't entirely clear, enabling KPTI on Cavium
1010          * ThunderX leads to apparent I-cache corruption of kernel text, which
1011          * ends as well as you might imagine. Don't even try.
1012          */
1013         if (cpus_have_const_cap(ARM64_WORKAROUND_CAVIUM_27456)) {
1014                 str = "ARM64_WORKAROUND_CAVIUM_27456";
1015                 __kpti_forced = -1;
1016         }
1017
1018         /* Useful for KASLR robustness */
1019         if (IS_ENABLED(CONFIG_RANDOMIZE_BASE) && kaslr_offset() > 0) {
1020                 if (!__kpti_forced) {
1021                         str = "KASLR";
1022                         __kpti_forced = 1;
1023                 }
1024         }
1025
1026         if (cpu_mitigations_off() && !__kpti_forced) {
1027                 str = "mitigations=off";
1028                 __kpti_forced = -1;
1029         }
1030
1031         if (!IS_ENABLED(CONFIG_UNMAP_KERNEL_AT_EL0)) {
1032                 pr_info_once("kernel page table isolation disabled by kernel configuration\n");
1033                 return false;
1034         }
1035
1036         /* Forced? */
1037         if (__kpti_forced) {
1038                 pr_info_once("kernel page table isolation forced %s by %s\n",
1039                              __kpti_forced > 0 ? "ON" : "OFF", str);
1040                 return __kpti_forced > 0;
1041         }
1042
1043         return !meltdown_safe;
1044 }
1045
1046 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0
1047 static void
1048 kpti_install_ng_mappings(const struct arm64_cpu_capabilities *__unused)
1049 {
1050         typedef void (kpti_remap_fn)(int, int, phys_addr_t);
1051         extern kpti_remap_fn idmap_kpti_install_ng_mappings;
1052         kpti_remap_fn *remap_fn;
1053
1054         static bool kpti_applied = false;
1055         int cpu = smp_processor_id();
1056
1057         if (__this_cpu_read(this_cpu_vector) == vectors) {
1058                 const char *v = arm64_get_bp_hardening_vector(EL1_VECTOR_KPTI);
1059
1060                 __this_cpu_write(this_cpu_vector, v);
1061         }
1062
1063         /*
1064          * We don't need to rewrite the page-tables if either we've done
1065          * it already or we have KASLR enabled and therefore have not
1066          * created any global mappings at all.
1067          */
1068         if (kpti_applied || kaslr_offset() > 0)
1069                 return;
1070
1071         remap_fn = (void *)__pa_symbol(idmap_kpti_install_ng_mappings);
1072
1073         cpu_install_idmap();
1074         remap_fn(cpu, num_online_cpus(), __pa_symbol(swapper_pg_dir));
1075         cpu_uninstall_idmap();
1076
1077         if (!cpu)
1078                 kpti_applied = true;
1079
1080         return;
1081 }
1082 #else
1083 static void
1084 kpti_install_ng_mappings(const struct arm64_cpu_capabilities *__unused)
1085 {
1086 }
1087 #endif  /* CONFIG_UNMAP_KERNEL_AT_EL0 */
1088
1089 static int __init parse_kpti(char *str)
1090 {
1091         bool enabled;
1092         int ret = strtobool(str, &enabled);
1093
1094         if (ret)
1095                 return ret;
1096
1097         __kpti_forced = enabled ? 1 : -1;
1098         return 0;
1099 }
1100 early_param("kpti", parse_kpti);
1101
1102 #ifdef CONFIG_ARM64_HW_AFDBM
1103 static inline void __cpu_enable_hw_dbm(void)
1104 {
1105         u64 tcr = read_sysreg(tcr_el1) | TCR_HD;
1106
1107         write_sysreg(tcr, tcr_el1);
1108         isb();
1109 }
1110
1111 static bool cpu_has_broken_dbm(void)
1112 {
1113         /* List of CPUs which have broken DBM support. */
1114         static const struct midr_range cpus[] = {
1115 #ifdef CONFIG_ARM64_ERRATUM_1024718
1116                 MIDR_ALL_VERSIONS(MIDR_CORTEX_A55),
1117 #endif
1118                 {},
1119         };
1120
1121         return is_midr_in_range_list(read_cpuid_id(), cpus);
1122 }
1123
1124 static bool cpu_can_use_dbm(const struct arm64_cpu_capabilities *cap)
1125 {
1126         return has_cpuid_feature(cap, SCOPE_LOCAL_CPU) &&
1127                !cpu_has_broken_dbm();
1128 }
1129
1130 static void cpu_enable_hw_dbm(struct arm64_cpu_capabilities const *cap)
1131 {
1132         if (cpu_can_use_dbm(cap))
1133                 __cpu_enable_hw_dbm();
1134 }
1135
1136 static bool has_hw_dbm(const struct arm64_cpu_capabilities *cap,
1137                        int __unused)
1138 {
1139         static bool detected = false;
1140         /*
1141          * DBM is a non-conflicting feature. i.e, the kernel can safely
1142          * run a mix of CPUs with and without the feature. So, we
1143          * unconditionally enable the capability to allow any late CPU
1144          * to use the feature. We only enable the control bits on the
1145          * CPU, if it actually supports.
1146          *
1147          * We have to make sure we print the "feature" detection only
1148          * when at least one CPU actually uses it. So check if this CPU
1149          * can actually use it and print the message exactly once.
1150          *
1151          * This is safe as all CPUs (including secondary CPUs - due to the
1152          * LOCAL_CPU scope - and the hotplugged CPUs - via verification)
1153          * goes through the "matches" check exactly once. Also if a CPU
1154          * matches the criteria, it is guaranteed that the CPU will turn
1155          * the DBM on, as the capability is unconditionally enabled.
1156          */
1157         if (!detected && cpu_can_use_dbm(cap)) {
1158                 detected = true;
1159                 pr_info("detected: Hardware dirty bit management\n");
1160         }
1161
1162         return true;
1163 }
1164
1165 #endif
1166
1167 #ifdef CONFIG_ARM64_VHE
1168 static bool runs_at_el2(const struct arm64_cpu_capabilities *entry, int __unused)
1169 {
1170         return is_kernel_in_hyp_mode();
1171 }
1172
1173 static void cpu_copy_el2regs(const struct arm64_cpu_capabilities *__unused)
1174 {
1175         /*
1176          * Copy register values that aren't redirected by hardware.
1177          *
1178          * Before code patching, we only set tpidr_el1, all CPUs need to copy
1179          * this value to tpidr_el2 before we patch the code. Once we've done
1180          * that, freshly-onlined CPUs will set tpidr_el2, so we don't need to
1181          * do anything here.
1182          */
1183         if (!alternative_is_applied(ARM64_HAS_VIRT_HOST_EXTN))
1184                 write_sysreg(read_sysreg(tpidr_el1), tpidr_el2);
1185 }
1186 #endif
1187
1188 static void cpu_has_fwb(const struct arm64_cpu_capabilities *__unused)
1189 {
1190         u64 val = read_sysreg_s(SYS_CLIDR_EL1);
1191
1192         /* Check that CLIDR_EL1.LOU{U,IS} are both 0 */
1193         WARN_ON(val & (7 << 27 | 7 << 21));
1194 }
1195
1196 #ifdef CONFIG_ARM64_SSBD
1197 static int ssbs_emulation_handler(struct pt_regs *regs, u32 instr)
1198 {
1199         if (user_mode(regs))
1200                 return 1;
1201
1202         if (instr & BIT(PSTATE_Imm_shift))
1203                 regs->pstate |= PSR_SSBS_BIT;
1204         else
1205                 regs->pstate &= ~PSR_SSBS_BIT;
1206
1207         arm64_skip_faulting_instruction(regs, 4);
1208         return 0;
1209 }
1210
1211 static struct undef_hook ssbs_emulation_hook = {
1212         .instr_mask     = ~(1U << PSTATE_Imm_shift),
1213         .instr_val      = 0xd500401f | PSTATE_SSBS,
1214         .fn             = ssbs_emulation_handler,
1215 };
1216
1217 static void cpu_enable_ssbs(const struct arm64_cpu_capabilities *__unused)
1218 {
1219         static bool undef_hook_registered = false;
1220         static DEFINE_RAW_SPINLOCK(hook_lock);
1221
1222         raw_spin_lock(&hook_lock);
1223         if (!undef_hook_registered) {
1224                 register_undef_hook(&ssbs_emulation_hook);
1225                 undef_hook_registered = true;
1226         }
1227         raw_spin_unlock(&hook_lock);
1228
1229         if (arm64_get_ssbd_state() == ARM64_SSBD_FORCE_DISABLE) {
1230                 sysreg_clear_set(sctlr_el1, 0, SCTLR_ELx_DSSBS);
1231                 arm64_set_ssbd_mitigation(false);
1232         } else {
1233                 arm64_set_ssbd_mitigation(true);
1234         }
1235 }
1236 #endif /* CONFIG_ARM64_SSBD */
1237
1238 #ifdef CONFIG_ARM64_PAN
1239 static void cpu_enable_pan(const struct arm64_cpu_capabilities *__unused)
1240 {
1241         /*
1242          * We modify PSTATE. This won't work from irq context as the PSTATE
1243          * is discarded once we return from the exception.
1244          */
1245         WARN_ON_ONCE(in_interrupt());
1246
1247         sysreg_clear_set(sctlr_el1, SCTLR_EL1_SPAN, 0);
1248         asm(SET_PSTATE_PAN(1));
1249 }
1250 #endif /* CONFIG_ARM64_PAN */
1251
1252 #ifdef CONFIG_ARM64_RAS_EXTN
1253 static void cpu_clear_disr(const struct arm64_cpu_capabilities *__unused)
1254 {
1255         /* Firmware may have left a deferred SError in this register. */
1256         write_sysreg_s(0, SYS_DISR_EL1);
1257 }
1258 #endif /* CONFIG_ARM64_RAS_EXTN */
1259
1260 #ifdef CONFIG_ARM64_PTR_AUTH
1261 static void cpu_enable_address_auth(struct arm64_cpu_capabilities const *cap)
1262 {
1263         sysreg_clear_set(sctlr_el1, 0, SCTLR_ELx_ENIA | SCTLR_ELx_ENIB |
1264                                        SCTLR_ELx_ENDA | SCTLR_ELx_ENDB);
1265 }
1266 #endif /* CONFIG_ARM64_PTR_AUTH */
1267
1268 #ifdef CONFIG_ARM64_PSEUDO_NMI
1269 static bool enable_pseudo_nmi;
1270
1271 static int __init early_enable_pseudo_nmi(char *p)
1272 {
1273         return strtobool(p, &enable_pseudo_nmi);
1274 }
1275 early_param("irqchip.gicv3_pseudo_nmi", early_enable_pseudo_nmi);
1276
1277 static bool can_use_gic_priorities(const struct arm64_cpu_capabilities *entry,
1278                                    int scope)
1279 {
1280         return enable_pseudo_nmi && has_useable_gicv3_cpuif(entry, scope);
1281 }
1282 #endif
1283
1284 static void elf_hwcap_fixup(void)
1285 {
1286 #ifdef CONFIG_ARM64_ERRATUM_1742098
1287         if (cpus_have_const_cap(ARM64_WORKAROUND_1742098))
1288                 compat_elf_hwcap2 &= ~COMPAT_HWCAP2_AES;
1289 #endif /* ARM64_ERRATUM_1742098 */
1290 }
1291
1292 static const struct arm64_cpu_capabilities arm64_features[] = {
1293         {
1294                 .desc = "GIC system register CPU interface",
1295                 .capability = ARM64_HAS_SYSREG_GIC_CPUIF,
1296                 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE,
1297                 .matches = has_useable_gicv3_cpuif,
1298                 .sys_reg = SYS_ID_AA64PFR0_EL1,
1299                 .field_pos = ID_AA64PFR0_GIC_SHIFT,
1300                 .sign = FTR_UNSIGNED,
1301                 .min_field_value = 1,
1302         },
1303 #ifdef CONFIG_ARM64_PAN
1304         {
1305                 .desc = "Privileged Access Never",
1306                 .capability = ARM64_HAS_PAN,
1307                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1308                 .matches = has_cpuid_feature,
1309                 .sys_reg = SYS_ID_AA64MMFR1_EL1,
1310                 .field_pos = ID_AA64MMFR1_PAN_SHIFT,
1311                 .sign = FTR_UNSIGNED,
1312                 .min_field_value = 1,
1313                 .cpu_enable = cpu_enable_pan,
1314         },
1315 #endif /* CONFIG_ARM64_PAN */
1316 #if defined(CONFIG_AS_LSE) && defined(CONFIG_ARM64_LSE_ATOMICS)
1317         {
1318                 .desc = "LSE atomic instructions",
1319                 .capability = ARM64_HAS_LSE_ATOMICS,
1320                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1321                 .matches = has_cpuid_feature,
1322                 .sys_reg = SYS_ID_AA64ISAR0_EL1,
1323                 .field_pos = ID_AA64ISAR0_ATOMICS_SHIFT,
1324                 .sign = FTR_UNSIGNED,
1325                 .min_field_value = 2,
1326         },
1327 #endif /* CONFIG_AS_LSE && CONFIG_ARM64_LSE_ATOMICS */
1328         {
1329                 .desc = "Software prefetching using PRFM",
1330                 .capability = ARM64_HAS_NO_HW_PREFETCH,
1331                 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
1332                 .matches = has_no_hw_prefetch,
1333         },
1334 #ifdef CONFIG_ARM64_UAO
1335         {
1336                 .desc = "User Access Override",
1337                 .capability = ARM64_HAS_UAO,
1338                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1339                 .matches = has_cpuid_feature,
1340                 .sys_reg = SYS_ID_AA64MMFR2_EL1,
1341                 .field_pos = ID_AA64MMFR2_UAO_SHIFT,
1342                 .min_field_value = 1,
1343                 /*
1344                  * We rely on stop_machine() calling uao_thread_switch() to set
1345                  * UAO immediately after patching.
1346                  */
1347         },
1348 #endif /* CONFIG_ARM64_UAO */
1349 #ifdef CONFIG_ARM64_PAN
1350         {
1351                 .capability = ARM64_ALT_PAN_NOT_UAO,
1352                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1353                 .matches = cpufeature_pan_not_uao,
1354         },
1355 #endif /* CONFIG_ARM64_PAN */
1356 #ifdef CONFIG_ARM64_VHE
1357         {
1358                 .desc = "Virtualization Host Extensions",
1359                 .capability = ARM64_HAS_VIRT_HOST_EXTN,
1360                 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE,
1361                 .matches = runs_at_el2,
1362                 .cpu_enable = cpu_copy_el2regs,
1363         },
1364 #endif  /* CONFIG_ARM64_VHE */
1365         {
1366                 .desc = "32-bit EL0 Support",
1367                 .capability = ARM64_HAS_32BIT_EL0,
1368                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1369                 .matches = has_cpuid_feature,
1370                 .sys_reg = SYS_ID_AA64PFR0_EL1,
1371                 .sign = FTR_UNSIGNED,
1372                 .field_pos = ID_AA64PFR0_EL0_SHIFT,
1373                 .min_field_value = ID_AA64PFR0_EL0_32BIT_64BIT,
1374         },
1375         {
1376                 .desc = "Kernel page table isolation (KPTI)",
1377                 .capability = ARM64_UNMAP_KERNEL_AT_EL0,
1378                 .type = ARM64_CPUCAP_BOOT_RESTRICTED_CPU_LOCAL_FEATURE,
1379                 /*
1380                  * The ID feature fields below are used to indicate that
1381                  * the CPU doesn't need KPTI. See unmap_kernel_at_el0 for
1382                  * more details.
1383                  */
1384                 .sys_reg = SYS_ID_AA64PFR0_EL1,
1385                 .field_pos = ID_AA64PFR0_CSV3_SHIFT,
1386                 .min_field_value = 1,
1387                 .matches = unmap_kernel_at_el0,
1388                 .cpu_enable = kpti_install_ng_mappings,
1389         },
1390         {
1391                 /* FP/SIMD is not implemented */
1392                 .capability = ARM64_HAS_NO_FPSIMD,
1393                 .type = ARM64_CPUCAP_BOOT_RESTRICTED_CPU_LOCAL_FEATURE,
1394                 .min_field_value = 0,
1395                 .matches = has_no_fpsimd,
1396         },
1397 #ifdef CONFIG_ARM64_PMEM
1398         {
1399                 .desc = "Data cache clean to Point of Persistence",
1400                 .capability = ARM64_HAS_DCPOP,
1401                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1402                 .matches = has_cpuid_feature,
1403                 .sys_reg = SYS_ID_AA64ISAR1_EL1,
1404                 .field_pos = ID_AA64ISAR1_DPB_SHIFT,
1405                 .min_field_value = 1,
1406         },
1407         {
1408                 .desc = "Data cache clean to Point of Deep Persistence",
1409                 .capability = ARM64_HAS_DCPODP,
1410                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1411                 .matches = has_cpuid_feature,
1412                 .sys_reg = SYS_ID_AA64ISAR1_EL1,
1413                 .sign = FTR_UNSIGNED,
1414                 .field_pos = ID_AA64ISAR1_DPB_SHIFT,
1415                 .min_field_value = 2,
1416         },
1417 #endif
1418 #ifdef CONFIG_ARM64_SVE
1419         {
1420                 .desc = "Scalable Vector Extension",
1421                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1422                 .capability = ARM64_SVE,
1423                 .sys_reg = SYS_ID_AA64PFR0_EL1,
1424                 .sign = FTR_UNSIGNED,
1425                 .field_pos = ID_AA64PFR0_SVE_SHIFT,
1426                 .min_field_value = ID_AA64PFR0_SVE,
1427                 .matches = has_cpuid_feature,
1428                 .cpu_enable = sve_kernel_enable,
1429         },
1430 #endif /* CONFIG_ARM64_SVE */
1431 #ifdef CONFIG_ARM64_RAS_EXTN
1432         {
1433                 .desc = "RAS Extension Support",
1434                 .capability = ARM64_HAS_RAS_EXTN,
1435                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1436                 .matches = has_cpuid_feature,
1437                 .sys_reg = SYS_ID_AA64PFR0_EL1,
1438                 .sign = FTR_UNSIGNED,
1439                 .field_pos = ID_AA64PFR0_RAS_SHIFT,
1440                 .min_field_value = ID_AA64PFR0_RAS_V1,
1441                 .cpu_enable = cpu_clear_disr,
1442         },
1443 #endif /* CONFIG_ARM64_RAS_EXTN */
1444         {
1445                 .desc = "Data cache clean to the PoU not required for I/D coherence",
1446                 .capability = ARM64_HAS_CACHE_IDC,
1447                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1448                 .matches = has_cache_idc,
1449                 .cpu_enable = cpu_emulate_effective_ctr,
1450         },
1451         {
1452                 .desc = "Instruction cache invalidation not required for I/D coherence",
1453                 .capability = ARM64_HAS_CACHE_DIC,
1454                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1455                 .matches = has_cache_dic,
1456         },
1457         {
1458                 .desc = "Stage-2 Force Write-Back",
1459                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1460                 .capability = ARM64_HAS_STAGE2_FWB,
1461                 .sys_reg = SYS_ID_AA64MMFR2_EL1,
1462                 .sign = FTR_UNSIGNED,
1463                 .field_pos = ID_AA64MMFR2_FWB_SHIFT,
1464                 .min_field_value = 1,
1465                 .matches = has_cpuid_feature,
1466                 .cpu_enable = cpu_has_fwb,
1467         },
1468 #ifdef CONFIG_ARM64_HW_AFDBM
1469         {
1470                 /*
1471                  * Since we turn this on always, we don't want the user to
1472                  * think that the feature is available when it may not be.
1473                  * So hide the description.
1474                  *
1475                  * .desc = "Hardware pagetable Dirty Bit Management",
1476                  *
1477                  */
1478                 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
1479                 .capability = ARM64_HW_DBM,
1480                 .sys_reg = SYS_ID_AA64MMFR1_EL1,
1481                 .sign = FTR_UNSIGNED,
1482                 .field_pos = ID_AA64MMFR1_HADBS_SHIFT,
1483                 .min_field_value = 2,
1484                 .matches = has_hw_dbm,
1485                 .cpu_enable = cpu_enable_hw_dbm,
1486         },
1487 #endif
1488         {
1489                 .desc = "CRC32 instructions",
1490                 .capability = ARM64_HAS_CRC32,
1491                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1492                 .matches = has_cpuid_feature,
1493                 .sys_reg = SYS_ID_AA64ISAR0_EL1,
1494                 .field_pos = ID_AA64ISAR0_CRC32_SHIFT,
1495                 .min_field_value = 1,
1496         },
1497 #ifdef CONFIG_ARM64_SSBD
1498         {
1499                 .desc = "Speculative Store Bypassing Safe (SSBS)",
1500                 .capability = ARM64_SSBS,
1501                 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
1502                 .matches = has_cpuid_feature,
1503                 .sys_reg = SYS_ID_AA64PFR1_EL1,
1504                 .field_pos = ID_AA64PFR1_SSBS_SHIFT,
1505                 .sign = FTR_UNSIGNED,
1506                 .min_field_value = ID_AA64PFR1_SSBS_PSTATE_ONLY,
1507                 .cpu_enable = cpu_enable_ssbs,
1508         },
1509 #endif
1510 #ifdef CONFIG_ARM64_CNP
1511         {
1512                 .desc = "Common not Private translations",
1513                 .capability = ARM64_HAS_CNP,
1514                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1515                 .matches = has_useable_cnp,
1516                 .sys_reg = SYS_ID_AA64MMFR2_EL1,
1517                 .sign = FTR_UNSIGNED,
1518                 .field_pos = ID_AA64MMFR2_CNP_SHIFT,
1519                 .min_field_value = 1,
1520                 .cpu_enable = cpu_enable_cnp,
1521         },
1522 #endif
1523         {
1524                 .desc = "Speculation barrier (SB)",
1525                 .capability = ARM64_HAS_SB,
1526                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1527                 .matches = has_cpuid_feature,
1528                 .sys_reg = SYS_ID_AA64ISAR1_EL1,
1529                 .field_pos = ID_AA64ISAR1_SB_SHIFT,
1530                 .sign = FTR_UNSIGNED,
1531                 .min_field_value = 1,
1532         },
1533 #ifdef CONFIG_ARM64_PTR_AUTH
1534         {
1535                 .desc = "Address authentication (architected algorithm)",
1536                 .capability = ARM64_HAS_ADDRESS_AUTH_ARCH,
1537                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1538                 .sys_reg = SYS_ID_AA64ISAR1_EL1,
1539                 .sign = FTR_UNSIGNED,
1540                 .field_pos = ID_AA64ISAR1_APA_SHIFT,
1541                 .min_field_value = ID_AA64ISAR1_APA_ARCHITECTED,
1542                 .matches = has_cpuid_feature,
1543                 .cpu_enable = cpu_enable_address_auth,
1544         },
1545         {
1546                 .desc = "Address authentication (IMP DEF algorithm)",
1547                 .capability = ARM64_HAS_ADDRESS_AUTH_IMP_DEF,
1548                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1549                 .sys_reg = SYS_ID_AA64ISAR1_EL1,
1550                 .sign = FTR_UNSIGNED,
1551                 .field_pos = ID_AA64ISAR1_API_SHIFT,
1552                 .min_field_value = ID_AA64ISAR1_API_IMP_DEF,
1553                 .matches = has_cpuid_feature,
1554                 .cpu_enable = cpu_enable_address_auth,
1555         },
1556         {
1557                 .desc = "Generic authentication (architected algorithm)",
1558                 .capability = ARM64_HAS_GENERIC_AUTH_ARCH,
1559                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1560                 .sys_reg = SYS_ID_AA64ISAR1_EL1,
1561                 .sign = FTR_UNSIGNED,
1562                 .field_pos = ID_AA64ISAR1_GPA_SHIFT,
1563                 .min_field_value = ID_AA64ISAR1_GPA_ARCHITECTED,
1564                 .matches = has_cpuid_feature,
1565         },
1566         {
1567                 .desc = "Generic authentication (IMP DEF algorithm)",
1568                 .capability = ARM64_HAS_GENERIC_AUTH_IMP_DEF,
1569                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1570                 .sys_reg = SYS_ID_AA64ISAR1_EL1,
1571                 .sign = FTR_UNSIGNED,
1572                 .field_pos = ID_AA64ISAR1_GPI_SHIFT,
1573                 .min_field_value = ID_AA64ISAR1_GPI_IMP_DEF,
1574                 .matches = has_cpuid_feature,
1575         },
1576 #endif /* CONFIG_ARM64_PTR_AUTH */
1577 #ifdef CONFIG_ARM64_PSEUDO_NMI
1578         {
1579                 /*
1580                  * Depends on having GICv3
1581                  */
1582                 .desc = "IRQ priority masking",
1583                 .capability = ARM64_HAS_IRQ_PRIO_MASKING,
1584                 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE,
1585                 .matches = can_use_gic_priorities,
1586                 .sys_reg = SYS_ID_AA64PFR0_EL1,
1587                 .field_pos = ID_AA64PFR0_GIC_SHIFT,
1588                 .sign = FTR_UNSIGNED,
1589                 .min_field_value = 1,
1590         },
1591 #endif
1592         {},
1593 };
1594
1595 #define HWCAP_CPUID_MATCH(reg, field, s, min_value)                             \
1596                 .matches = has_cpuid_feature,                                   \
1597                 .sys_reg = reg,                                                 \
1598                 .field_pos = field,                                             \
1599                 .sign = s,                                                      \
1600                 .min_field_value = min_value,
1601
1602 #define __HWCAP_CAP(name, cap_type, cap)                                        \
1603                 .desc = name,                                                   \
1604                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,                            \
1605                 .hwcap_type = cap_type,                                         \
1606                 .hwcap = cap,                                                   \
1607
1608 #define HWCAP_CAP(reg, field, s, min_value, cap_type, cap)                      \
1609         {                                                                       \
1610                 __HWCAP_CAP(#cap, cap_type, cap)                                \
1611                 HWCAP_CPUID_MATCH(reg, field, s, min_value)                     \
1612         }
1613
1614 #define HWCAP_MULTI_CAP(list, cap_type, cap)                                    \
1615         {                                                                       \
1616                 __HWCAP_CAP(#cap, cap_type, cap)                                \
1617                 .matches = cpucap_multi_entry_cap_matches,                      \
1618                 .match_list = list,                                             \
1619         }
1620
1621 #define HWCAP_CAP_MATCH(match, cap_type, cap)                                   \
1622         {                                                                       \
1623                 __HWCAP_CAP(#cap, cap_type, cap)                                \
1624                 .matches = match,                                               \
1625         }
1626
1627 #ifdef CONFIG_ARM64_PTR_AUTH
1628 static const struct arm64_cpu_capabilities ptr_auth_hwcap_addr_matches[] = {
1629         {
1630                 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_APA_SHIFT,
1631                                   FTR_UNSIGNED, ID_AA64ISAR1_APA_ARCHITECTED)
1632         },
1633         {
1634                 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_API_SHIFT,
1635                                   FTR_UNSIGNED, ID_AA64ISAR1_API_IMP_DEF)
1636         },
1637         {},
1638 };
1639
1640 static const struct arm64_cpu_capabilities ptr_auth_hwcap_gen_matches[] = {
1641         {
1642                 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_GPA_SHIFT,
1643                                   FTR_UNSIGNED, ID_AA64ISAR1_GPA_ARCHITECTED)
1644         },
1645         {
1646                 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_GPI_SHIFT,
1647                                   FTR_UNSIGNED, ID_AA64ISAR1_GPI_IMP_DEF)
1648         },
1649         {},
1650 };
1651 #endif
1652
1653 static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = {
1654         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_PMULL),
1655         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_AES),
1656         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA1_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SHA1),
1657         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA2_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SHA2),
1658         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA2_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_SHA512),
1659         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_CRC32_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_CRC32),
1660         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_ATOMICS_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_ATOMICS),
1661         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_RDM_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDRDM),
1662         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA3_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SHA3),
1663         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SM3_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SM3),
1664         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SM4_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SM4),
1665         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_DP_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDDP),
1666         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_FHM_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDFHM),
1667         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_TS_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FLAGM),
1668         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_TS_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_FLAGM2),
1669         HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, FTR_SIGNED, 0, CAP_HWCAP, KERNEL_HWCAP_FP),
1670         HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FPHP),
1671         HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, FTR_SIGNED, 0, CAP_HWCAP, KERNEL_HWCAP_ASIMD),
1672         HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDHP),
1673         HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_DIT_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_DIT),
1674         HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_DPB_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_DCPOP),
1675         HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_DPB_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_DCPODP),
1676         HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_JSCVT_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_JSCVT),
1677         HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_FCMA_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FCMA),
1678         HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_LRCPC_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_LRCPC),
1679         HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_LRCPC_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_ILRCPC),
1680         HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_FRINTTS_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FRINT),
1681         HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_SB_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SB),
1682         HWCAP_CAP(SYS_ID_AA64MMFR2_EL1, ID_AA64MMFR2_AT_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_USCAT),
1683 #ifdef CONFIG_ARM64_SVE
1684         HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_SVE_SHIFT, FTR_UNSIGNED, ID_AA64PFR0_SVE, CAP_HWCAP, KERNEL_HWCAP_SVE),
1685         HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_SVEVER_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_SVEVER_SVE2, CAP_HWCAP, KERNEL_HWCAP_SVE2),
1686         HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_AES_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_AES, CAP_HWCAP, KERNEL_HWCAP_SVEAES),
1687         HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_AES_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_AES_PMULL, CAP_HWCAP, KERNEL_HWCAP_SVEPMULL),
1688         HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_BITPERM_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_BITPERM, CAP_HWCAP, KERNEL_HWCAP_SVEBITPERM),
1689         HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_SHA3_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_SHA3, CAP_HWCAP, KERNEL_HWCAP_SVESHA3),
1690         HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_SM4_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_SM4, CAP_HWCAP, KERNEL_HWCAP_SVESM4),
1691 #endif
1692         HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_SSBS_SHIFT, FTR_UNSIGNED, ID_AA64PFR1_SSBS_PSTATE_INSNS, CAP_HWCAP, KERNEL_HWCAP_SSBS),
1693 #ifdef CONFIG_ARM64_PTR_AUTH
1694         HWCAP_MULTI_CAP(ptr_auth_hwcap_addr_matches, CAP_HWCAP, KERNEL_HWCAP_PACA),
1695         HWCAP_MULTI_CAP(ptr_auth_hwcap_gen_matches, CAP_HWCAP, KERNEL_HWCAP_PACG),
1696 #endif
1697         {},
1698 };
1699
1700 #ifdef CONFIG_COMPAT
1701 static bool compat_has_neon(const struct arm64_cpu_capabilities *cap, int scope)
1702 {
1703         /*
1704          * Check that all of MVFR1_EL1.{SIMDSP, SIMDInt, SIMDLS} are available,
1705          * in line with that of arm32 as in vfp_init(). We make sure that the
1706          * check is future proof, by making sure value is non-zero.
1707          */
1708         u32 mvfr1;
1709
1710         WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible());
1711         if (scope == SCOPE_SYSTEM)
1712                 mvfr1 = read_sanitised_ftr_reg(SYS_MVFR1_EL1);
1713         else
1714                 mvfr1 = read_sysreg_s(SYS_MVFR1_EL1);
1715
1716         return cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_SIMDSP_SHIFT) &&
1717                 cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_SIMDINT_SHIFT) &&
1718                 cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_SIMDLS_SHIFT);
1719 }
1720 #endif
1721
1722 static const struct arm64_cpu_capabilities compat_elf_hwcaps[] = {
1723 #ifdef CONFIG_COMPAT
1724         HWCAP_CAP_MATCH(compat_has_neon, CAP_COMPAT_HWCAP, COMPAT_HWCAP_NEON),
1725         HWCAP_CAP(SYS_MVFR1_EL1, MVFR1_SIMDFMAC_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFPv4),
1726         /* Arm v8 mandates MVFR0.FPDP == {0, 2}. So, piggy back on this for the presence of VFP support */
1727         HWCAP_CAP(SYS_MVFR0_EL1, MVFR0_FPDP_SHIFT, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFP),
1728         HWCAP_CAP(SYS_MVFR0_EL1, MVFR0_FPDP_SHIFT, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFPv3),
1729         HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_PMULL),
1730         HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_AES),
1731         HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA1_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA1),
1732         HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA2_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA2),
1733         HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_CRC32_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_CRC32),
1734 #endif
1735         {},
1736 };
1737
1738 static void __init cap_set_elf_hwcap(const struct arm64_cpu_capabilities *cap)
1739 {
1740         switch (cap->hwcap_type) {
1741         case CAP_HWCAP:
1742                 cpu_set_feature(cap->hwcap);
1743                 break;
1744 #ifdef CONFIG_COMPAT
1745         case CAP_COMPAT_HWCAP:
1746                 compat_elf_hwcap |= (u32)cap->hwcap;
1747                 break;
1748         case CAP_COMPAT_HWCAP2:
1749                 compat_elf_hwcap2 |= (u32)cap->hwcap;
1750                 break;
1751 #endif
1752         default:
1753                 WARN_ON(1);
1754                 break;
1755         }
1756 }
1757
1758 /* Check if we have a particular HWCAP enabled */
1759 static bool cpus_have_elf_hwcap(const struct arm64_cpu_capabilities *cap)
1760 {
1761         bool rc;
1762
1763         switch (cap->hwcap_type) {
1764         case CAP_HWCAP:
1765                 rc = cpu_have_feature(cap->hwcap);
1766                 break;
1767 #ifdef CONFIG_COMPAT
1768         case CAP_COMPAT_HWCAP:
1769                 rc = (compat_elf_hwcap & (u32)cap->hwcap) != 0;
1770                 break;
1771         case CAP_COMPAT_HWCAP2:
1772                 rc = (compat_elf_hwcap2 & (u32)cap->hwcap) != 0;
1773                 break;
1774 #endif
1775         default:
1776                 WARN_ON(1);
1777                 rc = false;
1778         }
1779
1780         return rc;
1781 }
1782
1783 static void __init setup_elf_hwcaps(const struct arm64_cpu_capabilities *hwcaps)
1784 {
1785         /* We support emulation of accesses to CPU ID feature registers */
1786         cpu_set_named_feature(CPUID);
1787         for (; hwcaps->matches; hwcaps++)
1788                 if (hwcaps->matches(hwcaps, cpucap_default_scope(hwcaps)))
1789                         cap_set_elf_hwcap(hwcaps);
1790 }
1791
1792 static void update_cpu_capabilities(u16 scope_mask)
1793 {
1794         int i;
1795         const struct arm64_cpu_capabilities *caps;
1796
1797         scope_mask &= ARM64_CPUCAP_SCOPE_MASK;
1798         for (i = 0; i < ARM64_NCAPS; i++) {
1799                 caps = cpu_hwcaps_ptrs[i];
1800                 if (!caps || !(caps->type & scope_mask) ||
1801                     cpus_have_cap(caps->capability) ||
1802                     !caps->matches(caps, cpucap_default_scope(caps)))
1803                         continue;
1804
1805                 if (caps->desc)
1806                         pr_info("detected: %s\n", caps->desc);
1807                 cpus_set_cap(caps->capability);
1808
1809                 if ((scope_mask & SCOPE_BOOT_CPU) && (caps->type & SCOPE_BOOT_CPU))
1810                         set_bit(caps->capability, boot_capabilities);
1811         }
1812 }
1813
1814 /*
1815  * Enable all the available capabilities on this CPU. The capabilities
1816  * with BOOT_CPU scope are handled separately and hence skipped here.
1817  */
1818 static int cpu_enable_non_boot_scope_capabilities(void *__unused)
1819 {
1820         int i;
1821         u16 non_boot_scope = SCOPE_ALL & ~SCOPE_BOOT_CPU;
1822
1823         for_each_available_cap(i) {
1824                 const struct arm64_cpu_capabilities *cap = cpu_hwcaps_ptrs[i];
1825
1826                 if (WARN_ON(!cap))
1827                         continue;
1828
1829                 if (!(cap->type & non_boot_scope))
1830                         continue;
1831
1832                 if (cap->cpu_enable)
1833                         cap->cpu_enable(cap);
1834         }
1835         return 0;
1836 }
1837
1838 /*
1839  * Run through the enabled capabilities and enable() it on all active
1840  * CPUs
1841  */
1842 static void __init enable_cpu_capabilities(u16 scope_mask)
1843 {
1844         int i;
1845         const struct arm64_cpu_capabilities *caps;
1846         bool boot_scope;
1847
1848         scope_mask &= ARM64_CPUCAP_SCOPE_MASK;
1849         boot_scope = !!(scope_mask & SCOPE_BOOT_CPU);
1850
1851         for (i = 0; i < ARM64_NCAPS; i++) {
1852                 unsigned int num;
1853
1854                 caps = cpu_hwcaps_ptrs[i];
1855                 if (!caps || !(caps->type & scope_mask))
1856                         continue;
1857                 num = caps->capability;
1858                 if (!cpus_have_cap(num))
1859                         continue;
1860
1861                 /* Ensure cpus_have_const_cap(num) works */
1862                 static_branch_enable(&cpu_hwcap_keys[num]);
1863
1864                 if (boot_scope && caps->cpu_enable)
1865                         /*
1866                          * Capabilities with SCOPE_BOOT_CPU scope are finalised
1867                          * before any secondary CPU boots. Thus, each secondary
1868                          * will enable the capability as appropriate via
1869                          * check_local_cpu_capabilities(). The only exception is
1870                          * the boot CPU, for which the capability must be
1871                          * enabled here. This approach avoids costly
1872                          * stop_machine() calls for this case.
1873                          */
1874                         caps->cpu_enable(caps);
1875         }
1876
1877         /*
1878          * For all non-boot scope capabilities, use stop_machine()
1879          * as it schedules the work allowing us to modify PSTATE,
1880          * instead of on_each_cpu() which uses an IPI, giving us a
1881          * PSTATE that disappears when we return.
1882          */
1883         if (!boot_scope)
1884                 stop_machine(cpu_enable_non_boot_scope_capabilities,
1885                              NULL, cpu_online_mask);
1886 }
1887
1888 /*
1889  * Run through the list of capabilities to check for conflicts.
1890  * If the system has already detected a capability, take necessary
1891  * action on this CPU.
1892  *
1893  * Returns "false" on conflicts.
1894  */
1895 static bool verify_local_cpu_caps(u16 scope_mask)
1896 {
1897         int i;
1898         bool cpu_has_cap, system_has_cap;
1899         const struct arm64_cpu_capabilities *caps;
1900
1901         scope_mask &= ARM64_CPUCAP_SCOPE_MASK;
1902
1903         for (i = 0; i < ARM64_NCAPS; i++) {
1904                 caps = cpu_hwcaps_ptrs[i];
1905                 if (!caps || !(caps->type & scope_mask))
1906                         continue;
1907
1908                 cpu_has_cap = caps->matches(caps, SCOPE_LOCAL_CPU);
1909                 system_has_cap = cpus_have_cap(caps->capability);
1910
1911                 if (system_has_cap) {
1912                         /*
1913                          * Check if the new CPU misses an advertised feature,
1914                          * which is not safe to miss.
1915                          */
1916                         if (!cpu_has_cap && !cpucap_late_cpu_optional(caps))
1917                                 break;
1918                         /*
1919                          * We have to issue cpu_enable() irrespective of
1920                          * whether the CPU has it or not, as it is enabeld
1921                          * system wide. It is upto the call back to take
1922                          * appropriate action on this CPU.
1923                          */
1924                         if (caps->cpu_enable)
1925                                 caps->cpu_enable(caps);
1926                 } else {
1927                         /*
1928                          * Check if the CPU has this capability if it isn't
1929                          * safe to have when the system doesn't.
1930                          */
1931                         if (cpu_has_cap && !cpucap_late_cpu_permitted(caps))
1932                                 break;
1933                 }
1934         }
1935
1936         if (i < ARM64_NCAPS) {
1937                 pr_crit("CPU%d: Detected conflict for capability %d (%s), System: %d, CPU: %d\n",
1938                         smp_processor_id(), caps->capability,
1939                         caps->desc, system_has_cap, cpu_has_cap);
1940                 return false;
1941         }
1942
1943         return true;
1944 }
1945
1946 /*
1947  * Check for CPU features that are used in early boot
1948  * based on the Boot CPU value.
1949  */
1950 static void check_early_cpu_features(void)
1951 {
1952         verify_cpu_asid_bits();
1953         /*
1954          * Early features are used by the kernel already. If there
1955          * is a conflict, we cannot proceed further.
1956          */
1957         if (!verify_local_cpu_caps(SCOPE_BOOT_CPU))
1958                 cpu_panic_kernel();
1959 }
1960
1961 static void
1962 verify_local_elf_hwcaps(const struct arm64_cpu_capabilities *caps)
1963 {
1964
1965         for (; caps->matches; caps++)
1966                 if (cpus_have_elf_hwcap(caps) && !caps->matches(caps, SCOPE_LOCAL_CPU)) {
1967                         pr_crit("CPU%d: missing HWCAP: %s\n",
1968                                         smp_processor_id(), caps->desc);
1969                         cpu_die_early();
1970                 }
1971 }
1972
1973 static void verify_sve_features(void)
1974 {
1975         u64 safe_zcr = read_sanitised_ftr_reg(SYS_ZCR_EL1);
1976         u64 zcr = read_zcr_features();
1977
1978         unsigned int safe_len = safe_zcr & ZCR_ELx_LEN_MASK;
1979         unsigned int len = zcr & ZCR_ELx_LEN_MASK;
1980
1981         if (len < safe_len || sve_verify_vq_map()) {
1982                 pr_crit("CPU%d: SVE: vector length support mismatch\n",
1983                         smp_processor_id());
1984                 cpu_die_early();
1985         }
1986
1987         /* Add checks on other ZCR bits here if necessary */
1988 }
1989
1990
1991 /*
1992  * Run through the enabled system capabilities and enable() it on this CPU.
1993  * The capabilities were decided based on the available CPUs at the boot time.
1994  * Any new CPU should match the system wide status of the capability. If the
1995  * new CPU doesn't have a capability which the system now has enabled, we
1996  * cannot do anything to fix it up and could cause unexpected failures. So
1997  * we park the CPU.
1998  */
1999 static void verify_local_cpu_capabilities(void)
2000 {
2001         /*
2002          * The capabilities with SCOPE_BOOT_CPU are checked from
2003          * check_early_cpu_features(), as they need to be verified
2004          * on all secondary CPUs.
2005          */
2006         if (!verify_local_cpu_caps(SCOPE_ALL & ~SCOPE_BOOT_CPU))
2007                 cpu_die_early();
2008
2009         verify_local_elf_hwcaps(arm64_elf_hwcaps);
2010
2011         if (system_supports_32bit_el0())
2012                 verify_local_elf_hwcaps(compat_elf_hwcaps);
2013
2014         if (system_supports_sve())
2015                 verify_sve_features();
2016 }
2017
2018 void check_local_cpu_capabilities(void)
2019 {
2020         /*
2021          * All secondary CPUs should conform to the early CPU features
2022          * in use by the kernel based on boot CPU.
2023          */
2024         check_early_cpu_features();
2025
2026         /*
2027          * If we haven't finalised the system capabilities, this CPU gets
2028          * a chance to update the errata work arounds and local features.
2029          * Otherwise, this CPU should verify that it has all the system
2030          * advertised capabilities.
2031          */
2032         if (!sys_caps_initialised)
2033                 update_cpu_capabilities(SCOPE_LOCAL_CPU);
2034         else
2035                 verify_local_cpu_capabilities();
2036 }
2037
2038 static void __init setup_boot_cpu_capabilities(void)
2039 {
2040         /* Detect capabilities with either SCOPE_BOOT_CPU or SCOPE_LOCAL_CPU */
2041         update_cpu_capabilities(SCOPE_BOOT_CPU | SCOPE_LOCAL_CPU);
2042         /* Enable the SCOPE_BOOT_CPU capabilities alone right away */
2043         enable_cpu_capabilities(SCOPE_BOOT_CPU);
2044 }
2045
2046 DEFINE_STATIC_KEY_FALSE(arm64_const_caps_ready);
2047 EXPORT_SYMBOL(arm64_const_caps_ready);
2048
2049 static void __init mark_const_caps_ready(void)
2050 {
2051         static_branch_enable(&arm64_const_caps_ready);
2052 }
2053
2054 bool this_cpu_has_cap(unsigned int n)
2055 {
2056         if (!WARN_ON(preemptible()) && n < ARM64_NCAPS) {
2057                 const struct arm64_cpu_capabilities *cap = cpu_hwcaps_ptrs[n];
2058
2059                 if (cap)
2060                         return cap->matches(cap, SCOPE_LOCAL_CPU);
2061         }
2062
2063         return false;
2064 }
2065
2066 void cpu_set_feature(unsigned int num)
2067 {
2068         WARN_ON(num >= MAX_CPU_FEATURES);
2069         elf_hwcap |= BIT(num);
2070 }
2071 EXPORT_SYMBOL_GPL(cpu_set_feature);
2072
2073 bool cpu_have_feature(unsigned int num)
2074 {
2075         WARN_ON(num >= MAX_CPU_FEATURES);
2076         return elf_hwcap & BIT(num);
2077 }
2078 EXPORT_SYMBOL_GPL(cpu_have_feature);
2079
2080 unsigned long cpu_get_elf_hwcap(void)
2081 {
2082         /*
2083          * We currently only populate the first 32 bits of AT_HWCAP. Please
2084          * note that for userspace compatibility we guarantee that bits 62
2085          * and 63 will always be returned as 0.
2086          */
2087         return lower_32_bits(elf_hwcap);
2088 }
2089
2090 unsigned long cpu_get_elf_hwcap2(void)
2091 {
2092         return upper_32_bits(elf_hwcap);
2093 }
2094
2095 static void __init setup_system_capabilities(void)
2096 {
2097         /*
2098          * We have finalised the system-wide safe feature
2099          * registers, finalise the capabilities that depend
2100          * on it. Also enable all the available capabilities,
2101          * that are not enabled already.
2102          */
2103         update_cpu_capabilities(SCOPE_SYSTEM);
2104         enable_cpu_capabilities(SCOPE_ALL & ~SCOPE_BOOT_CPU);
2105 }
2106
2107 void __init setup_cpu_features(void)
2108 {
2109         u32 cwg;
2110
2111         setup_system_capabilities();
2112         mark_const_caps_ready();
2113         setup_elf_hwcaps(arm64_elf_hwcaps);
2114
2115         if (system_supports_32bit_el0()) {
2116                 setup_elf_hwcaps(compat_elf_hwcaps);
2117                 elf_hwcap_fixup();
2118         }
2119
2120         if (system_uses_ttbr0_pan())
2121                 pr_info("emulated: Privileged Access Never (PAN) using TTBR0_EL1 switching\n");
2122
2123         sve_setup();
2124         minsigstksz_setup();
2125
2126         /* Advertise that we have computed the system capabilities */
2127         set_sys_caps_initialised();
2128
2129         /*
2130          * Check for sane CTR_EL0.CWG value.
2131          */
2132         cwg = cache_type_cwg();
2133         if (!cwg)
2134                 pr_warn("No Cache Writeback Granule information, assuming %d\n",
2135                         ARCH_DMA_MINALIGN);
2136 }
2137
2138 static bool __maybe_unused
2139 cpufeature_pan_not_uao(const struct arm64_cpu_capabilities *entry, int __unused)
2140 {
2141         return (cpus_have_const_cap(ARM64_HAS_PAN) && !cpus_have_const_cap(ARM64_HAS_UAO));
2142 }
2143
2144 static void __maybe_unused cpu_enable_cnp(struct arm64_cpu_capabilities const *cap)
2145 {
2146         cpu_replace_ttbr1(lm_alias(swapper_pg_dir));
2147 }
2148
2149 /*
2150  * We emulate only the following system register space.
2151  * Op0 = 0x3, CRn = 0x0, Op1 = 0x0, CRm = [0, 4 - 7]
2152  * See Table C5-6 System instruction encodings for System register accesses,
2153  * ARMv8 ARM(ARM DDI 0487A.f) for more details.
2154  */
2155 static inline bool __attribute_const__ is_emulated(u32 id)
2156 {
2157         return (sys_reg_Op0(id) == 0x3 &&
2158                 sys_reg_CRn(id) == 0x0 &&
2159                 sys_reg_Op1(id) == 0x0 &&
2160                 (sys_reg_CRm(id) == 0 ||
2161                  ((sys_reg_CRm(id) >= 4) && (sys_reg_CRm(id) <= 7))));
2162 }
2163
2164 /*
2165  * With CRm == 0, reg should be one of :
2166  * MIDR_EL1, MPIDR_EL1 or REVIDR_EL1.
2167  */
2168 static inline int emulate_id_reg(u32 id, u64 *valp)
2169 {
2170         switch (id) {
2171         case SYS_MIDR_EL1:
2172                 *valp = read_cpuid_id();
2173                 break;
2174         case SYS_MPIDR_EL1:
2175                 *valp = SYS_MPIDR_SAFE_VAL;
2176                 break;
2177         case SYS_REVIDR_EL1:
2178                 /* IMPLEMENTATION DEFINED values are emulated with 0 */
2179                 *valp = 0;
2180                 break;
2181         default:
2182                 return -EINVAL;
2183         }
2184
2185         return 0;
2186 }
2187
2188 static int emulate_sys_reg(u32 id, u64 *valp)
2189 {
2190         struct arm64_ftr_reg *regp;
2191
2192         if (!is_emulated(id))
2193                 return -EINVAL;
2194
2195         if (sys_reg_CRm(id) == 0)
2196                 return emulate_id_reg(id, valp);
2197
2198         regp = get_arm64_ftr_reg(id);
2199         if (regp)
2200                 *valp = arm64_ftr_reg_user_value(regp);
2201         else
2202                 /*
2203                  * The untracked registers are either IMPLEMENTATION DEFINED
2204                  * (e.g, ID_AFR0_EL1) or reserved RAZ.
2205                  */
2206                 *valp = 0;
2207         return 0;
2208 }
2209
2210 int do_emulate_mrs(struct pt_regs *regs, u32 sys_reg, u32 rt)
2211 {
2212         int rc;
2213         u64 val;
2214
2215         rc = emulate_sys_reg(sys_reg, &val);
2216         if (!rc) {
2217                 pt_regs_write_reg(regs, rt, val);
2218                 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE);
2219         }
2220         return rc;
2221 }
2222
2223 static int emulate_mrs(struct pt_regs *regs, u32 insn)
2224 {
2225         u32 sys_reg, rt;
2226
2227         /*
2228          * sys_reg values are defined as used in mrs/msr instruction.
2229          * shift the imm value to get the encoding.
2230          */
2231         sys_reg = (u32)aarch64_insn_decode_immediate(AARCH64_INSN_IMM_16, insn) << 5;
2232         rt = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RT, insn);
2233         return do_emulate_mrs(regs, sys_reg, rt);
2234 }
2235
2236 static struct undef_hook mrs_hook = {
2237         .instr_mask = 0xfff00000,
2238         .instr_val  = 0xd5300000,
2239         .pstate_mask = PSR_AA32_MODE_MASK,
2240         .pstate_val = PSR_MODE_EL0t,
2241         .fn = emulate_mrs,
2242 };
2243
2244 static int __init enable_mrs_emulation(void)
2245 {
2246         register_undef_hook(&mrs_hook);
2247         return 0;
2248 }
2249
2250 core_initcall(enable_mrs_emulation);
2251
2252 ssize_t cpu_show_meltdown(struct device *dev, struct device_attribute *attr,
2253                           char *buf)
2254 {
2255         if (__meltdown_safe)
2256                 return sprintf(buf, "Not affected\n");
2257
2258         if (arm64_kernel_unmapped_at_el0())
2259                 return sprintf(buf, "Mitigation: PTI\n");
2260
2261         return sprintf(buf, "Vulnerable\n");
2262 }