2 * Contains CPU feature definitions
4 * Copyright (C) 2015 ARM Ltd.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program. If not, see <http://www.gnu.org/licenses/>.
19 #define pr_fmt(fmt) "CPU features: " fmt
21 #include <linux/bsearch.h>
22 #include <linux/cpumask.h>
23 #include <linux/sort.h>
24 #include <linux/stop_machine.h>
25 #include <linux/types.h>
27 #include <linux/cpu.h>
29 #include <asm/cpufeature.h>
30 #include <asm/cpu_ops.h>
31 #include <asm/mmu_context.h>
32 #include <asm/processor.h>
33 #include <asm/sysreg.h>
34 #include <asm/traps.h>
37 unsigned long elf_hwcap __read_mostly;
38 EXPORT_SYMBOL_GPL(elf_hwcap);
41 #define COMPAT_ELF_HWCAP_DEFAULT \
42 (COMPAT_HWCAP_HALF|COMPAT_HWCAP_THUMB|\
43 COMPAT_HWCAP_FAST_MULT|COMPAT_HWCAP_EDSP|\
44 COMPAT_HWCAP_TLS|COMPAT_HWCAP_IDIV|\
46 unsigned int compat_elf_hwcap __read_mostly = COMPAT_ELF_HWCAP_DEFAULT;
47 unsigned int compat_elf_hwcap2 __read_mostly;
50 DECLARE_BITMAP(cpu_hwcaps, ARM64_NCAPS);
51 EXPORT_SYMBOL(cpu_hwcaps);
53 static int dump_cpu_hwcaps(struct notifier_block *self, unsigned long v, void *p)
55 /* file-wide pr_fmt adds "CPU features: " prefix */
56 pr_emerg("0x%*pb\n", ARM64_NCAPS, &cpu_hwcaps);
60 static struct notifier_block cpu_hwcaps_notifier = {
61 .notifier_call = dump_cpu_hwcaps
64 static int __init register_cpu_hwcaps_dumper(void)
66 atomic_notifier_chain_register(&panic_notifier_list,
67 &cpu_hwcaps_notifier);
70 __initcall(register_cpu_hwcaps_dumper);
72 DEFINE_STATIC_KEY_ARRAY_FALSE(cpu_hwcap_keys, ARM64_NCAPS);
73 EXPORT_SYMBOL(cpu_hwcap_keys);
75 #define __ARM64_FTR_BITS(SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
83 .safe_val = SAFE_VAL, \
86 /* Define a feature with unsigned values */
87 #define ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
88 __ARM64_FTR_BITS(FTR_UNSIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL)
90 /* Define a feature with a signed value */
91 #define S_ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
92 __ARM64_FTR_BITS(FTR_SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL)
94 #define ARM64_FTR_END \
99 /* meta feature for alternatives */
100 static bool __maybe_unused
101 cpufeature_pan_not_uao(const struct arm64_cpu_capabilities *entry, int __unused);
105 * NOTE: Any changes to the visibility of features should be kept in
106 * sync with the documentation of the CPU feature register ABI.
108 static const struct arm64_ftr_bits ftr_id_aa64isar0[] = {
109 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_TS_SHIFT, 4, 0),
110 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_FHM_SHIFT, 4, 0),
111 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_DP_SHIFT, 4, 0),
112 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SM4_SHIFT, 4, 0),
113 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SM3_SHIFT, 4, 0),
114 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA3_SHIFT, 4, 0),
115 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_RDM_SHIFT, 4, 0),
116 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_ATOMICS_SHIFT, 4, 0),
117 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_CRC32_SHIFT, 4, 0),
118 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA2_SHIFT, 4, 0),
119 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA1_SHIFT, 4, 0),
120 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_AES_SHIFT, 4, 0),
124 static const struct arm64_ftr_bits ftr_id_aa64isar1[] = {
125 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_LRCPC_SHIFT, 4, 0),
126 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_FCMA_SHIFT, 4, 0),
127 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_JSCVT_SHIFT, 4, 0),
128 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_DPB_SHIFT, 4, 0),
132 static const struct arm64_ftr_bits ftr_id_aa64pfr0[] = {
133 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_CSV3_SHIFT, 4, 0),
134 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_CSV2_SHIFT, 4, 0),
135 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_DIT_SHIFT, 4, 0),
136 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_GIC_SHIFT, 4, 0),
137 S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_ASIMD_SHIFT, 4, ID_AA64PFR0_ASIMD_NI),
138 S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_FP_SHIFT, 4, ID_AA64PFR0_FP_NI),
139 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL3_SHIFT, 4, 0),
140 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL2_SHIFT, 4, 0),
141 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_SHIFT, 4, ID_AA64PFR0_EL1_64BIT_ONLY),
142 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL0_SHIFT, 4, ID_AA64PFR0_EL0_64BIT_ONLY),
146 static const struct arm64_ftr_bits ftr_id_aa64pfr1[] = {
147 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_SSBS_SHIFT, 4, ID_AA64PFR1_SSBS_PSTATE_NI),
151 static const struct arm64_ftr_bits ftr_id_aa64mmfr0[] = {
152 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN4_SHIFT, 4, ID_AA64MMFR0_TGRAN4_NI),
153 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN64_SHIFT, 4, ID_AA64MMFR0_TGRAN64_NI),
154 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN16_SHIFT, 4, ID_AA64MMFR0_TGRAN16_NI),
155 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_BIGENDEL0_SHIFT, 4, 0),
156 /* Linux shouldn't care about secure memory */
157 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_SNSMEM_SHIFT, 4, 0),
158 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_BIGENDEL_SHIFT, 4, 0),
159 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_ASID_SHIFT, 4, 0),
161 * Differing PARange is fine as long as all peripherals and memory are mapped
162 * within the minimum PARange of all CPUs
164 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_PARANGE_SHIFT, 4, 0),
168 static const struct arm64_ftr_bits ftr_id_aa64mmfr1[] = {
169 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_PAN_SHIFT, 4, 0),
170 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_LOR_SHIFT, 4, 0),
171 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_HPD_SHIFT, 4, 0),
172 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_VHE_SHIFT, 4, 0),
173 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_VMIDBITS_SHIFT, 4, 0),
174 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_HADBS_SHIFT, 4, 0),
178 static const struct arm64_ftr_bits ftr_id_aa64mmfr2[] = {
179 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_AT_SHIFT, 4, 0),
180 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_LVA_SHIFT, 4, 0),
181 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_IESB_SHIFT, 4, 0),
182 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_LSM_SHIFT, 4, 0),
183 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_UAO_SHIFT, 4, 0),
184 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_CNP_SHIFT, 4, 0),
188 static const struct arm64_ftr_bits ftr_ctr[] = {
189 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, 31, 1, 1), /* RES1 */
190 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, 29, 1, 1), /* DIC */
191 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, 28, 1, 1), /* IDC */
192 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, 24, 4, 0), /* CWG */
193 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, 20, 4, 0), /* ERG */
194 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_DMINLINE_SHIFT, 4, 1),
196 * Linux can handle differing I-cache policies. Userspace JITs will
197 * make use of *minLine.
198 * If we have differing I-cache policies, report it as the weakest - VIPT.
200 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_EXACT, 14, 2, ICACHE_POLICY_VIPT), /* L1Ip */
201 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_IMINLINE_SHIFT, 4, 0),
205 struct arm64_ftr_reg arm64_ftr_reg_ctrel0 = {
206 .name = "SYS_CTR_EL0",
210 static const struct arm64_ftr_bits ftr_id_mmfr0[] = {
211 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0xf), /* InnerShr */
212 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0), /* FCSE */
213 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, 20, 4, 0), /* AuxReg */
214 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0), /* TCM */
215 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0), /* ShareLvl */
216 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0xf), /* OuterShr */
217 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0), /* PMSA */
218 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), /* VMSA */
222 static const struct arm64_ftr_bits ftr_id_aa64dfr0[] = {
223 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 36, 28, 0),
224 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64DFR0_PMSVER_SHIFT, 4, 0),
225 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_CTX_CMPS_SHIFT, 4, 0),
226 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_WRPS_SHIFT, 4, 0),
227 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_BRPS_SHIFT, 4, 0),
229 * We can instantiate multiple PMU instances with different levels
232 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64DFR0_PMUVER_SHIFT, 4, 0),
233 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64DFR0_DEBUGVER_SHIFT, 4, 0x6),
237 static const struct arm64_ftr_bits ftr_mvfr2[] = {
238 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0), /* FPMisc */
239 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), /* SIMDMisc */
243 static const struct arm64_ftr_bits ftr_dczid[] = {
244 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, 4, 1, 1), /* DZP */
245 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), /* BS */
250 static const struct arm64_ftr_bits ftr_id_isar5[] = {
251 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_RDM_SHIFT, 4, 0),
252 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_CRC32_SHIFT, 4, 0),
253 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SHA2_SHIFT, 4, 0),
254 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SHA1_SHIFT, 4, 0),
255 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_AES_SHIFT, 4, 0),
256 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SEVL_SHIFT, 4, 0),
260 static const struct arm64_ftr_bits ftr_id_mmfr4[] = {
261 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0), /* ac2 */
265 static const struct arm64_ftr_bits ftr_id_pfr0[] = {
266 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0), /* State3 */
267 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0), /* State2 */
268 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0), /* State1 */
269 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), /* State0 */
273 static const struct arm64_ftr_bits ftr_id_dfr0[] = {
274 /* [31:28] TraceFilt */
275 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0xf), /* PerfMon */
276 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0),
277 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0),
278 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0),
279 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0),
280 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),
281 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),
286 * Common ftr bits for a 32bit register with all hidden, strict
287 * attributes, with 4bit feature fields and a default safe value of
288 * 0. Covers the following 32bit registers:
289 * id_isar[0-4], id_mmfr[1-3], id_pfr1, mvfr[0-1]
291 static const struct arm64_ftr_bits ftr_generic_32bits[] = {
292 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0),
293 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0),
294 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0),
295 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0),
296 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0),
297 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0),
298 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),
299 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),
303 /* Table for a single 32bit feature value */
304 static const struct arm64_ftr_bits ftr_single32[] = {
305 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 0, 32, 0),
309 static const struct arm64_ftr_bits ftr_raz[] = {
313 #define ARM64_FTR_REG(id, table) { \
315 .reg = &(struct arm64_ftr_reg){ \
317 .ftr_bits = &((table)[0]), \
320 static const struct __ftr_reg_entry {
322 struct arm64_ftr_reg *reg;
323 } arm64_ftr_regs[] = {
325 /* Op1 = 0, CRn = 0, CRm = 1 */
326 ARM64_FTR_REG(SYS_ID_PFR0_EL1, ftr_id_pfr0),
327 ARM64_FTR_REG(SYS_ID_PFR1_EL1, ftr_generic_32bits),
328 ARM64_FTR_REG(SYS_ID_DFR0_EL1, ftr_id_dfr0),
329 ARM64_FTR_REG(SYS_ID_MMFR0_EL1, ftr_id_mmfr0),
330 ARM64_FTR_REG(SYS_ID_MMFR1_EL1, ftr_generic_32bits),
331 ARM64_FTR_REG(SYS_ID_MMFR2_EL1, ftr_generic_32bits),
332 ARM64_FTR_REG(SYS_ID_MMFR3_EL1, ftr_generic_32bits),
334 /* Op1 = 0, CRn = 0, CRm = 2 */
335 ARM64_FTR_REG(SYS_ID_ISAR0_EL1, ftr_generic_32bits),
336 ARM64_FTR_REG(SYS_ID_ISAR1_EL1, ftr_generic_32bits),
337 ARM64_FTR_REG(SYS_ID_ISAR2_EL1, ftr_generic_32bits),
338 ARM64_FTR_REG(SYS_ID_ISAR3_EL1, ftr_generic_32bits),
339 ARM64_FTR_REG(SYS_ID_ISAR4_EL1, ftr_generic_32bits),
340 ARM64_FTR_REG(SYS_ID_ISAR5_EL1, ftr_id_isar5),
341 ARM64_FTR_REG(SYS_ID_MMFR4_EL1, ftr_id_mmfr4),
343 /* Op1 = 0, CRn = 0, CRm = 3 */
344 ARM64_FTR_REG(SYS_MVFR0_EL1, ftr_generic_32bits),
345 ARM64_FTR_REG(SYS_MVFR1_EL1, ftr_generic_32bits),
346 ARM64_FTR_REG(SYS_MVFR2_EL1, ftr_mvfr2),
348 /* Op1 = 0, CRn = 0, CRm = 4 */
349 ARM64_FTR_REG(SYS_ID_AA64PFR0_EL1, ftr_id_aa64pfr0),
350 ARM64_FTR_REG(SYS_ID_AA64PFR1_EL1, ftr_id_aa64pfr1),
352 /* Op1 = 0, CRn = 0, CRm = 5 */
353 ARM64_FTR_REG(SYS_ID_AA64DFR0_EL1, ftr_id_aa64dfr0),
354 ARM64_FTR_REG(SYS_ID_AA64DFR1_EL1, ftr_raz),
356 /* Op1 = 0, CRn = 0, CRm = 6 */
357 ARM64_FTR_REG(SYS_ID_AA64ISAR0_EL1, ftr_id_aa64isar0),
358 ARM64_FTR_REG(SYS_ID_AA64ISAR1_EL1, ftr_id_aa64isar1),
360 /* Op1 = 0, CRn = 0, CRm = 7 */
361 ARM64_FTR_REG(SYS_ID_AA64MMFR0_EL1, ftr_id_aa64mmfr0),
362 ARM64_FTR_REG(SYS_ID_AA64MMFR1_EL1, ftr_id_aa64mmfr1),
363 ARM64_FTR_REG(SYS_ID_AA64MMFR2_EL1, ftr_id_aa64mmfr2),
365 /* Op1 = 3, CRn = 0, CRm = 0 */
366 { SYS_CTR_EL0, &arm64_ftr_reg_ctrel0 },
367 ARM64_FTR_REG(SYS_DCZID_EL0, ftr_dczid),
369 /* Op1 = 3, CRn = 14, CRm = 0 */
370 ARM64_FTR_REG(SYS_CNTFRQ_EL0, ftr_single32),
373 static int search_cmp_ftr_reg(const void *id, const void *regp)
375 return (int)(unsigned long)id - (int)((const struct __ftr_reg_entry *)regp)->sys_id;
379 * get_arm64_ftr_reg - Lookup a feature register entry using its
380 * sys_reg() encoding. With the array arm64_ftr_regs sorted in the
381 * ascending order of sys_id , we use binary search to find a matching
384 * returns - Upon success, matching ftr_reg entry for id.
385 * - NULL on failure. It is upto the caller to decide
386 * the impact of a failure.
388 static struct arm64_ftr_reg *get_arm64_ftr_reg(u32 sys_id)
390 const struct __ftr_reg_entry *ret;
392 ret = bsearch((const void *)(unsigned long)sys_id,
394 ARRAY_SIZE(arm64_ftr_regs),
395 sizeof(arm64_ftr_regs[0]),
402 static u64 arm64_ftr_set_value(const struct arm64_ftr_bits *ftrp, s64 reg,
405 u64 mask = arm64_ftr_mask(ftrp);
408 reg |= (ftr_val << ftrp->shift) & mask;
412 static s64 arm64_ftr_safe_value(const struct arm64_ftr_bits *ftrp, s64 new,
417 switch (ftrp->type) {
419 ret = ftrp->safe_val;
422 ret = new < cur ? new : cur;
424 case FTR_HIGHER_OR_ZERO_SAFE:
428 case FTR_HIGHER_SAFE:
429 ret = new > cur ? new : cur;
438 static void __init sort_ftr_regs(void)
442 /* Check that the array is sorted so that we can do the binary search */
443 for (i = 1; i < ARRAY_SIZE(arm64_ftr_regs); i++)
444 BUG_ON(arm64_ftr_regs[i].sys_id < arm64_ftr_regs[i - 1].sys_id);
448 * Initialise the CPU feature register from Boot CPU values.
449 * Also initiliases the strict_mask for the register.
450 * Any bits that are not covered by an arm64_ftr_bits entry are considered
451 * RES0 for the system-wide value, and must strictly match.
453 static void __init init_cpu_ftr_reg(u32 sys_reg, u64 new)
456 u64 strict_mask = ~0x0ULL;
460 const struct arm64_ftr_bits *ftrp;
461 struct arm64_ftr_reg *reg = get_arm64_ftr_reg(sys_reg);
465 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) {
466 u64 ftr_mask = arm64_ftr_mask(ftrp);
467 s64 ftr_new = arm64_ftr_value(ftrp, new);
469 val = arm64_ftr_set_value(ftrp, val, ftr_new);
471 valid_mask |= ftr_mask;
473 strict_mask &= ~ftr_mask;
475 user_mask |= ftr_mask;
477 reg->user_val = arm64_ftr_set_value(ftrp,
485 reg->strict_mask = strict_mask;
486 reg->user_mask = user_mask;
489 extern const struct arm64_cpu_capabilities arm64_errata[];
490 static void __init setup_boot_cpu_capabilities(void);
492 void __init init_cpu_features(struct cpuinfo_arm64 *info)
494 /* Before we start using the tables, make sure it is sorted */
497 init_cpu_ftr_reg(SYS_CTR_EL0, info->reg_ctr);
498 init_cpu_ftr_reg(SYS_DCZID_EL0, info->reg_dczid);
499 init_cpu_ftr_reg(SYS_CNTFRQ_EL0, info->reg_cntfrq);
500 init_cpu_ftr_reg(SYS_ID_AA64DFR0_EL1, info->reg_id_aa64dfr0);
501 init_cpu_ftr_reg(SYS_ID_AA64DFR1_EL1, info->reg_id_aa64dfr1);
502 init_cpu_ftr_reg(SYS_ID_AA64ISAR0_EL1, info->reg_id_aa64isar0);
503 init_cpu_ftr_reg(SYS_ID_AA64ISAR1_EL1, info->reg_id_aa64isar1);
504 init_cpu_ftr_reg(SYS_ID_AA64MMFR0_EL1, info->reg_id_aa64mmfr0);
505 init_cpu_ftr_reg(SYS_ID_AA64MMFR1_EL1, info->reg_id_aa64mmfr1);
506 init_cpu_ftr_reg(SYS_ID_AA64MMFR2_EL1, info->reg_id_aa64mmfr2);
507 init_cpu_ftr_reg(SYS_ID_AA64PFR0_EL1, info->reg_id_aa64pfr0);
508 init_cpu_ftr_reg(SYS_ID_AA64PFR1_EL1, info->reg_id_aa64pfr1);
510 if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) {
511 init_cpu_ftr_reg(SYS_ID_DFR0_EL1, info->reg_id_dfr0);
512 init_cpu_ftr_reg(SYS_ID_ISAR0_EL1, info->reg_id_isar0);
513 init_cpu_ftr_reg(SYS_ID_ISAR1_EL1, info->reg_id_isar1);
514 init_cpu_ftr_reg(SYS_ID_ISAR2_EL1, info->reg_id_isar2);
515 init_cpu_ftr_reg(SYS_ID_ISAR3_EL1, info->reg_id_isar3);
516 init_cpu_ftr_reg(SYS_ID_ISAR4_EL1, info->reg_id_isar4);
517 init_cpu_ftr_reg(SYS_ID_ISAR5_EL1, info->reg_id_isar5);
518 init_cpu_ftr_reg(SYS_ID_MMFR0_EL1, info->reg_id_mmfr0);
519 init_cpu_ftr_reg(SYS_ID_MMFR1_EL1, info->reg_id_mmfr1);
520 init_cpu_ftr_reg(SYS_ID_MMFR2_EL1, info->reg_id_mmfr2);
521 init_cpu_ftr_reg(SYS_ID_MMFR3_EL1, info->reg_id_mmfr3);
522 init_cpu_ftr_reg(SYS_ID_PFR0_EL1, info->reg_id_pfr0);
523 init_cpu_ftr_reg(SYS_ID_PFR1_EL1, info->reg_id_pfr1);
524 init_cpu_ftr_reg(SYS_MVFR0_EL1, info->reg_mvfr0);
525 init_cpu_ftr_reg(SYS_MVFR1_EL1, info->reg_mvfr1);
526 init_cpu_ftr_reg(SYS_MVFR2_EL1, info->reg_mvfr2);
530 * Detect and enable early CPU capabilities based on the boot CPU,
531 * after we have initialised the CPU feature infrastructure.
533 setup_boot_cpu_capabilities();
536 static void update_cpu_ftr_reg(struct arm64_ftr_reg *reg, u64 new)
538 const struct arm64_ftr_bits *ftrp;
540 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) {
541 s64 ftr_cur = arm64_ftr_value(ftrp, reg->sys_val);
542 s64 ftr_new = arm64_ftr_value(ftrp, new);
544 if (ftr_cur == ftr_new)
546 /* Find a safe value */
547 ftr_new = arm64_ftr_safe_value(ftrp, ftr_new, ftr_cur);
548 reg->sys_val = arm64_ftr_set_value(ftrp, reg->sys_val, ftr_new);
553 static int check_update_ftr_reg(u32 sys_id, int cpu, u64 val, u64 boot)
555 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id);
558 update_cpu_ftr_reg(regp, val);
559 if ((boot & regp->strict_mask) == (val & regp->strict_mask))
561 pr_warn("SANITY CHECK: Unexpected variation in %s. Boot CPU: %#016llx, CPU%d: %#016llx\n",
562 regp->name, boot, cpu, val);
567 * Update system wide CPU feature registers with the values from a
568 * non-boot CPU. Also performs SANITY checks to make sure that there
569 * aren't any insane variations from that of the boot CPU.
571 void update_cpu_features(int cpu,
572 struct cpuinfo_arm64 *info,
573 struct cpuinfo_arm64 *boot)
578 * The kernel can handle differing I-cache policies, but otherwise
579 * caches should look identical. Userspace JITs will make use of
582 taint |= check_update_ftr_reg(SYS_CTR_EL0, cpu,
583 info->reg_ctr, boot->reg_ctr);
586 * Userspace may perform DC ZVA instructions. Mismatched block sizes
587 * could result in too much or too little memory being zeroed if a
588 * process is preempted and migrated between CPUs.
590 taint |= check_update_ftr_reg(SYS_DCZID_EL0, cpu,
591 info->reg_dczid, boot->reg_dczid);
593 /* If different, timekeeping will be broken (especially with KVM) */
594 taint |= check_update_ftr_reg(SYS_CNTFRQ_EL0, cpu,
595 info->reg_cntfrq, boot->reg_cntfrq);
598 * The kernel uses self-hosted debug features and expects CPUs to
599 * support identical debug features. We presently need CTX_CMPs, WRPs,
600 * and BRPs to be identical.
601 * ID_AA64DFR1 is currently RES0.
603 taint |= check_update_ftr_reg(SYS_ID_AA64DFR0_EL1, cpu,
604 info->reg_id_aa64dfr0, boot->reg_id_aa64dfr0);
605 taint |= check_update_ftr_reg(SYS_ID_AA64DFR1_EL1, cpu,
606 info->reg_id_aa64dfr1, boot->reg_id_aa64dfr1);
608 * Even in big.LITTLE, processors should be identical instruction-set
611 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR0_EL1, cpu,
612 info->reg_id_aa64isar0, boot->reg_id_aa64isar0);
613 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR1_EL1, cpu,
614 info->reg_id_aa64isar1, boot->reg_id_aa64isar1);
617 * Differing PARange support is fine as long as all peripherals and
618 * memory are mapped within the minimum PARange of all CPUs.
619 * Linux should not care about secure memory.
621 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR0_EL1, cpu,
622 info->reg_id_aa64mmfr0, boot->reg_id_aa64mmfr0);
623 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR1_EL1, cpu,
624 info->reg_id_aa64mmfr1, boot->reg_id_aa64mmfr1);
625 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR2_EL1, cpu,
626 info->reg_id_aa64mmfr2, boot->reg_id_aa64mmfr2);
628 taint |= check_update_ftr_reg(SYS_ID_AA64PFR0_EL1, cpu,
629 info->reg_id_aa64pfr0, boot->reg_id_aa64pfr0);
630 taint |= check_update_ftr_reg(SYS_ID_AA64PFR1_EL1, cpu,
631 info->reg_id_aa64pfr1, boot->reg_id_aa64pfr1);
634 * If we have AArch32, we care about 32-bit features for compat.
635 * If the system doesn't support AArch32, don't update them.
637 if (id_aa64pfr0_32bit_el0(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1)) &&
638 id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) {
640 taint |= check_update_ftr_reg(SYS_ID_DFR0_EL1, cpu,
641 info->reg_id_dfr0, boot->reg_id_dfr0);
642 taint |= check_update_ftr_reg(SYS_ID_ISAR0_EL1, cpu,
643 info->reg_id_isar0, boot->reg_id_isar0);
644 taint |= check_update_ftr_reg(SYS_ID_ISAR1_EL1, cpu,
645 info->reg_id_isar1, boot->reg_id_isar1);
646 taint |= check_update_ftr_reg(SYS_ID_ISAR2_EL1, cpu,
647 info->reg_id_isar2, boot->reg_id_isar2);
648 taint |= check_update_ftr_reg(SYS_ID_ISAR3_EL1, cpu,
649 info->reg_id_isar3, boot->reg_id_isar3);
650 taint |= check_update_ftr_reg(SYS_ID_ISAR4_EL1, cpu,
651 info->reg_id_isar4, boot->reg_id_isar4);
652 taint |= check_update_ftr_reg(SYS_ID_ISAR5_EL1, cpu,
653 info->reg_id_isar5, boot->reg_id_isar5);
656 * Regardless of the value of the AuxReg field, the AIFSR, ADFSR, and
657 * ACTLR formats could differ across CPUs and therefore would have to
658 * be trapped for virtualization anyway.
660 taint |= check_update_ftr_reg(SYS_ID_MMFR0_EL1, cpu,
661 info->reg_id_mmfr0, boot->reg_id_mmfr0);
662 taint |= check_update_ftr_reg(SYS_ID_MMFR1_EL1, cpu,
663 info->reg_id_mmfr1, boot->reg_id_mmfr1);
664 taint |= check_update_ftr_reg(SYS_ID_MMFR2_EL1, cpu,
665 info->reg_id_mmfr2, boot->reg_id_mmfr2);
666 taint |= check_update_ftr_reg(SYS_ID_MMFR3_EL1, cpu,
667 info->reg_id_mmfr3, boot->reg_id_mmfr3);
668 taint |= check_update_ftr_reg(SYS_ID_PFR0_EL1, cpu,
669 info->reg_id_pfr0, boot->reg_id_pfr0);
670 taint |= check_update_ftr_reg(SYS_ID_PFR1_EL1, cpu,
671 info->reg_id_pfr1, boot->reg_id_pfr1);
672 taint |= check_update_ftr_reg(SYS_MVFR0_EL1, cpu,
673 info->reg_mvfr0, boot->reg_mvfr0);
674 taint |= check_update_ftr_reg(SYS_MVFR1_EL1, cpu,
675 info->reg_mvfr1, boot->reg_mvfr1);
676 taint |= check_update_ftr_reg(SYS_MVFR2_EL1, cpu,
677 info->reg_mvfr2, boot->reg_mvfr2);
681 * Mismatched CPU features are a recipe for disaster. Don't even
682 * pretend to support them.
685 pr_warn_once("Unsupported CPU feature variation detected.\n");
686 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK);
690 u64 read_sanitised_ftr_reg(u32 id)
692 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(id);
694 /* We shouldn't get a request for an unsupported register */
696 return regp->sys_val;
699 #define read_sysreg_case(r) \
700 case r: return read_sysreg_s(r)
703 * __read_sysreg_by_encoding() - Used by a STARTING cpu before cpuinfo is populated.
704 * Read the system register on the current CPU
706 static u64 __read_sysreg_by_encoding(u32 sys_id)
709 read_sysreg_case(SYS_ID_PFR0_EL1);
710 read_sysreg_case(SYS_ID_PFR1_EL1);
711 read_sysreg_case(SYS_ID_DFR0_EL1);
712 read_sysreg_case(SYS_ID_MMFR0_EL1);
713 read_sysreg_case(SYS_ID_MMFR1_EL1);
714 read_sysreg_case(SYS_ID_MMFR2_EL1);
715 read_sysreg_case(SYS_ID_MMFR3_EL1);
716 read_sysreg_case(SYS_ID_ISAR0_EL1);
717 read_sysreg_case(SYS_ID_ISAR1_EL1);
718 read_sysreg_case(SYS_ID_ISAR2_EL1);
719 read_sysreg_case(SYS_ID_ISAR3_EL1);
720 read_sysreg_case(SYS_ID_ISAR4_EL1);
721 read_sysreg_case(SYS_ID_ISAR5_EL1);
722 read_sysreg_case(SYS_MVFR0_EL1);
723 read_sysreg_case(SYS_MVFR1_EL1);
724 read_sysreg_case(SYS_MVFR2_EL1);
726 read_sysreg_case(SYS_ID_AA64PFR0_EL1);
727 read_sysreg_case(SYS_ID_AA64PFR1_EL1);
728 read_sysreg_case(SYS_ID_AA64DFR0_EL1);
729 read_sysreg_case(SYS_ID_AA64DFR1_EL1);
730 read_sysreg_case(SYS_ID_AA64MMFR0_EL1);
731 read_sysreg_case(SYS_ID_AA64MMFR1_EL1);
732 read_sysreg_case(SYS_ID_AA64MMFR2_EL1);
733 read_sysreg_case(SYS_ID_AA64ISAR0_EL1);
734 read_sysreg_case(SYS_ID_AA64ISAR1_EL1);
736 read_sysreg_case(SYS_CNTFRQ_EL0);
737 read_sysreg_case(SYS_CTR_EL0);
738 read_sysreg_case(SYS_DCZID_EL0);
746 #include <linux/irqchip/arm-gic-v3.h>
749 feature_matches(u64 reg, const struct arm64_cpu_capabilities *entry)
751 int val = cpuid_feature_extract_field(reg, entry->field_pos, entry->sign);
753 return val >= entry->min_field_value;
757 has_cpuid_feature(const struct arm64_cpu_capabilities *entry, int scope)
761 WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible());
762 if (scope == SCOPE_SYSTEM)
763 val = read_sanitised_ftr_reg(entry->sys_reg);
765 val = __read_sysreg_by_encoding(entry->sys_reg);
767 return feature_matches(val, entry);
770 static bool has_useable_gicv3_cpuif(const struct arm64_cpu_capabilities *entry, int scope)
774 if (!has_cpuid_feature(entry, scope))
777 has_sre = gic_enable_sre();
779 pr_warn_once("%s present but disabled by higher exception level\n",
785 static bool has_no_hw_prefetch(const struct arm64_cpu_capabilities *entry, int __unused)
787 u32 midr = read_cpuid_id();
789 /* Cavium ThunderX pass 1.x and 2.x */
790 return MIDR_IS_CPU_MODEL_RANGE(midr, MIDR_THUNDERX,
791 MIDR_CPU_VAR_REV(0, 0),
792 MIDR_CPU_VAR_REV(1, MIDR_REVISION_MASK));
795 static bool hyp_offset_low(const struct arm64_cpu_capabilities *entry,
798 phys_addr_t idmap_addr = __pa_symbol(__hyp_idmap_text_start);
801 * Activate the lower HYP offset only if:
802 * - the idmap doesn't clash with it,
803 * - the kernel is not running at EL2.
805 return idmap_addr > GENMASK(VA_BITS - 2, 0) && !is_kernel_in_hyp_mode();
808 static bool has_no_fpsimd(const struct arm64_cpu_capabilities *entry, int __unused)
810 u64 pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1);
812 return cpuid_feature_extract_signed_field(pfr0,
813 ID_AA64PFR0_FP_SHIFT) < 0;
816 static bool __meltdown_safe = true;
817 static int __kpti_forced; /* 0: not forced, >0: forced on, <0: forced off */
819 static bool unmap_kernel_at_el0(const struct arm64_cpu_capabilities *entry,
822 /* List of CPUs that are not vulnerable and don't need KPTI */
823 static const struct midr_range kpti_safe_list[] = {
824 MIDR_ALL_VERSIONS(MIDR_CAVIUM_THUNDERX2),
825 MIDR_ALL_VERSIONS(MIDR_BRCM_VULCAN),
826 MIDR_ALL_VERSIONS(MIDR_CORTEX_A35),
827 MIDR_ALL_VERSIONS(MIDR_CORTEX_A53),
828 MIDR_ALL_VERSIONS(MIDR_CORTEX_A55),
829 MIDR_ALL_VERSIONS(MIDR_CORTEX_A57),
830 MIDR_ALL_VERSIONS(MIDR_CORTEX_A72),
831 MIDR_ALL_VERSIONS(MIDR_CORTEX_A73),
834 char const *str = "kpti command line option";
837 meltdown_safe = is_midr_in_range_list(read_cpuid_id(), kpti_safe_list);
839 /* Defer to CPU feature registers */
840 if (has_cpuid_feature(entry, scope))
841 meltdown_safe = true;
844 __meltdown_safe = false;
847 * For reasons that aren't entirely clear, enabling KPTI on Cavium
848 * ThunderX leads to apparent I-cache corruption of kernel text, which
849 * ends as well as you might imagine. Don't even try.
851 if (cpus_have_const_cap(ARM64_WORKAROUND_CAVIUM_27456)) {
852 str = "ARM64_WORKAROUND_CAVIUM_27456";
856 /* Useful for KASLR robustness */
857 if (IS_ENABLED(CONFIG_RANDOMIZE_BASE) && kaslr_offset() > 0) {
858 if (!__kpti_forced) {
864 if (cpu_mitigations_off() && !__kpti_forced) {
865 str = "mitigations=off";
869 if (!IS_ENABLED(CONFIG_UNMAP_KERNEL_AT_EL0)) {
870 pr_info_once("kernel page table isolation disabled by kernel configuration\n");
876 pr_info_once("kernel page table isolation forced %s by %s\n",
877 __kpti_forced > 0 ? "ON" : "OFF", str);
878 return __kpti_forced > 0;
881 return !meltdown_safe;
884 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0
886 kpti_install_ng_mappings(const struct arm64_cpu_capabilities *__unused)
888 typedef void (kpti_remap_fn)(int, int, phys_addr_t);
889 extern kpti_remap_fn idmap_kpti_install_ng_mappings;
890 kpti_remap_fn *remap_fn;
892 static bool kpti_applied = false;
893 int cpu = smp_processor_id();
898 remap_fn = (void *)__pa_symbol(idmap_kpti_install_ng_mappings);
901 remap_fn(cpu, num_online_cpus(), __pa_symbol(swapper_pg_dir));
902 cpu_uninstall_idmap();
911 kpti_install_ng_mappings(const struct arm64_cpu_capabilities *__unused)
914 #endif /* CONFIG_UNMAP_KERNEL_AT_EL0 */
916 static int __init parse_kpti(char *str)
919 int ret = strtobool(str, &enabled);
924 __kpti_forced = enabled ? 1 : -1;
927 early_param("kpti", parse_kpti);
929 #ifdef CONFIG_ARM64_VHE
930 static bool runs_at_el2(const struct arm64_cpu_capabilities *entry, int __unused)
932 return is_kernel_in_hyp_mode();
935 static void cpu_copy_el2regs(const struct arm64_cpu_capabilities *__unused)
938 * Copy register values that aren't redirected by hardware.
940 * Before code patching, we only set tpidr_el1, all CPUs need to copy
941 * this value to tpidr_el2 before we patch the code. Once we've done
942 * that, freshly-onlined CPUs will set tpidr_el2, so we don't need to
945 if (!alternatives_applied)
946 write_sysreg(read_sysreg(tpidr_el1), tpidr_el2);
950 #ifdef CONFIG_ARM64_SSBD
951 static int ssbs_emulation_handler(struct pt_regs *regs, u32 instr)
956 if (instr & BIT(CRm_shift))
957 regs->pstate |= PSR_SSBS_BIT;
959 regs->pstate &= ~PSR_SSBS_BIT;
961 arm64_skip_faulting_instruction(regs, 4);
965 static struct undef_hook ssbs_emulation_hook = {
966 .instr_mask = ~(1U << CRm_shift),
967 .instr_val = 0xd500001f | REG_PSTATE_SSBS_IMM,
968 .fn = ssbs_emulation_handler,
971 static void cpu_enable_ssbs(const struct arm64_cpu_capabilities *__unused)
973 static bool undef_hook_registered = false;
974 static DEFINE_SPINLOCK(hook_lock);
976 spin_lock(&hook_lock);
977 if (!undef_hook_registered) {
978 register_undef_hook(&ssbs_emulation_hook);
979 undef_hook_registered = true;
981 spin_unlock(&hook_lock);
983 if (arm64_get_ssbd_state() == ARM64_SSBD_FORCE_DISABLE) {
984 sysreg_clear_set(sctlr_el1, 0, SCTLR_ELx_DSSBS);
985 arm64_set_ssbd_mitigation(false);
987 arm64_set_ssbd_mitigation(true);
990 #endif /* CONFIG_ARM64_SSBD */
992 static const struct arm64_cpu_capabilities arm64_features[] = {
994 .desc = "GIC system register CPU interface",
995 .capability = ARM64_HAS_SYSREG_GIC_CPUIF,
996 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
997 .matches = has_useable_gicv3_cpuif,
998 .sys_reg = SYS_ID_AA64PFR0_EL1,
999 .field_pos = ID_AA64PFR0_GIC_SHIFT,
1000 .sign = FTR_UNSIGNED,
1001 .min_field_value = 1,
1003 #ifdef CONFIG_ARM64_PAN
1005 .desc = "Privileged Access Never",
1006 .capability = ARM64_HAS_PAN,
1007 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1008 .matches = has_cpuid_feature,
1009 .sys_reg = SYS_ID_AA64MMFR1_EL1,
1010 .field_pos = ID_AA64MMFR1_PAN_SHIFT,
1011 .sign = FTR_UNSIGNED,
1012 .min_field_value = 1,
1013 .cpu_enable = cpu_enable_pan,
1015 #endif /* CONFIG_ARM64_PAN */
1016 #if defined(CONFIG_AS_LSE) && defined(CONFIG_ARM64_LSE_ATOMICS)
1018 .desc = "LSE atomic instructions",
1019 .capability = ARM64_HAS_LSE_ATOMICS,
1020 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1021 .matches = has_cpuid_feature,
1022 .sys_reg = SYS_ID_AA64ISAR0_EL1,
1023 .field_pos = ID_AA64ISAR0_ATOMICS_SHIFT,
1024 .sign = FTR_UNSIGNED,
1025 .min_field_value = 2,
1027 #endif /* CONFIG_AS_LSE && CONFIG_ARM64_LSE_ATOMICS */
1029 .desc = "Software prefetching using PRFM",
1030 .capability = ARM64_HAS_NO_HW_PREFETCH,
1031 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
1032 .matches = has_no_hw_prefetch,
1034 #ifdef CONFIG_ARM64_UAO
1036 .desc = "User Access Override",
1037 .capability = ARM64_HAS_UAO,
1038 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1039 .matches = has_cpuid_feature,
1040 .sys_reg = SYS_ID_AA64MMFR2_EL1,
1041 .field_pos = ID_AA64MMFR2_UAO_SHIFT,
1042 .min_field_value = 1,
1044 * We rely on stop_machine() calling uao_thread_switch() to set
1045 * UAO immediately after patching.
1048 #endif /* CONFIG_ARM64_UAO */
1049 #ifdef CONFIG_ARM64_PAN
1051 .capability = ARM64_ALT_PAN_NOT_UAO,
1052 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1053 .matches = cpufeature_pan_not_uao,
1055 #endif /* CONFIG_ARM64_PAN */
1056 #ifdef CONFIG_ARM64_VHE
1058 .desc = "Virtualization Host Extensions",
1059 .capability = ARM64_HAS_VIRT_HOST_EXTN,
1060 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE,
1061 .matches = runs_at_el2,
1062 .cpu_enable = cpu_copy_el2regs,
1064 #endif /* CONFIG_ARM64_VHE */
1066 .desc = "32-bit EL0 Support",
1067 .capability = ARM64_HAS_32BIT_EL0,
1068 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1069 .matches = has_cpuid_feature,
1070 .sys_reg = SYS_ID_AA64PFR0_EL1,
1071 .sign = FTR_UNSIGNED,
1072 .field_pos = ID_AA64PFR0_EL0_SHIFT,
1073 .min_field_value = ID_AA64PFR0_EL0_32BIT_64BIT,
1076 .desc = "Reduced HYP mapping offset",
1077 .capability = ARM64_HYP_OFFSET_LOW,
1078 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1079 .matches = hyp_offset_low,
1082 .desc = "Kernel page table isolation (KPTI)",
1083 .capability = ARM64_UNMAP_KERNEL_AT_EL0,
1084 .type = ARM64_CPUCAP_BOOT_RESTRICTED_CPU_LOCAL_FEATURE,
1086 * The ID feature fields below are used to indicate that
1087 * the CPU doesn't need KPTI. See unmap_kernel_at_el0 for
1090 .sys_reg = SYS_ID_AA64PFR0_EL1,
1091 .field_pos = ID_AA64PFR0_CSV3_SHIFT,
1092 .min_field_value = 1,
1093 .matches = unmap_kernel_at_el0,
1094 .cpu_enable = kpti_install_ng_mappings,
1097 /* FP/SIMD is not implemented */
1098 .capability = ARM64_HAS_NO_FPSIMD,
1099 .type = ARM64_CPUCAP_BOOT_RESTRICTED_CPU_LOCAL_FEATURE,
1100 .min_field_value = 0,
1101 .matches = has_no_fpsimd,
1103 #ifdef CONFIG_ARM64_PMEM
1105 .desc = "Data cache clean to Point of Persistence",
1106 .capability = ARM64_HAS_DCPOP,
1107 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1108 .matches = has_cpuid_feature,
1109 .sys_reg = SYS_ID_AA64ISAR1_EL1,
1110 .field_pos = ID_AA64ISAR1_DPB_SHIFT,
1111 .min_field_value = 1,
1114 #ifdef CONFIG_ARM64_SSBD
1116 .desc = "Speculative Store Bypassing Safe (SSBS)",
1117 .capability = ARM64_SSBS,
1118 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
1119 .matches = has_cpuid_feature,
1120 .sys_reg = SYS_ID_AA64PFR1_EL1,
1121 .field_pos = ID_AA64PFR1_SSBS_SHIFT,
1122 .sign = FTR_UNSIGNED,
1123 .min_field_value = ID_AA64PFR1_SSBS_PSTATE_ONLY,
1124 .cpu_enable = cpu_enable_ssbs,
1131 #define HWCAP_CPUID_MATCH(reg, field, s, min_value) \
1132 .matches = has_cpuid_feature, \
1134 .field_pos = field, \
1136 .min_field_value = min_value, \
1138 #define __HWCAP_CAP(name, cap_type, cap) \
1140 .type = ARM64_CPUCAP_SYSTEM_FEATURE, \
1141 .hwcap_type = cap_type, \
1144 #define HWCAP_CAP(reg, field, s, min_value, cap_type, cap) \
1146 __HWCAP_CAP(#cap, cap_type, cap) \
1147 HWCAP_CPUID_MATCH(reg, field, s, min_value) \
1150 #define HWCAP_CAP_MATCH(match, cap_type, cap) \
1152 __HWCAP_CAP(#cap, cap_type, cap) \
1156 static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = {
1157 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, HWCAP_PMULL),
1158 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_AES),
1159 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA1_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_SHA1),
1160 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA2_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_SHA2),
1161 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA2_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, HWCAP_SHA512),
1162 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_CRC32_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_CRC32),
1163 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_ATOMICS_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, HWCAP_ATOMICS),
1164 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_RDM_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_ASIMDRDM),
1165 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA3_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_SHA3),
1166 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SM3_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_SM3),
1167 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SM4_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_SM4),
1168 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_DP_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_ASIMDDP),
1169 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_FHM_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_ASIMDFHM),
1170 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_TS_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_FLAGM),
1171 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, FTR_SIGNED, 0, CAP_HWCAP, HWCAP_FP),
1172 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, HWCAP_FPHP),
1173 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, FTR_SIGNED, 0, CAP_HWCAP, HWCAP_ASIMD),
1174 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, HWCAP_ASIMDHP),
1175 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_DIT_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, HWCAP_DIT),
1176 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_DPB_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_DCPOP),
1177 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_JSCVT_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_JSCVT),
1178 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_FCMA_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_FCMA),
1179 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_LRCPC_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_LRCPC),
1180 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_LRCPC_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, HWCAP_ILRCPC),
1181 HWCAP_CAP(SYS_ID_AA64MMFR2_EL1, ID_AA64MMFR2_AT_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_USCAT),
1182 HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_SSBS_SHIFT, FTR_UNSIGNED, ID_AA64PFR1_SSBS_PSTATE_INSNS, CAP_HWCAP, HWCAP_SSBS),
1186 #ifdef CONFIG_COMPAT
1187 static bool compat_has_neon(const struct arm64_cpu_capabilities *cap, int scope)
1190 * Check that all of MVFR1_EL1.{SIMDSP, SIMDInt, SIMDLS} are available,
1191 * in line with that of arm32 as in vfp_init(). We make sure that the
1192 * check is future proof, by making sure value is non-zero.
1196 WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible());
1197 if (scope == SCOPE_SYSTEM)
1198 mvfr1 = read_sanitised_ftr_reg(SYS_MVFR1_EL1);
1200 mvfr1 = read_sysreg_s(SYS_MVFR1_EL1);
1202 return cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_SIMDSP_SHIFT) &&
1203 cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_SIMDINT_SHIFT) &&
1204 cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_SIMDLS_SHIFT);
1208 static const struct arm64_cpu_capabilities compat_elf_hwcaps[] = {
1209 #ifdef CONFIG_COMPAT
1210 HWCAP_CAP_MATCH(compat_has_neon, CAP_COMPAT_HWCAP, COMPAT_HWCAP_NEON),
1211 HWCAP_CAP(SYS_MVFR1_EL1, MVFR1_SIMDFMAC_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFPv4),
1212 /* Arm v8 mandates MVFR0.FPDP == {0, 2}. So, piggy back on this for the presence of VFP support */
1213 HWCAP_CAP(SYS_MVFR0_EL1, MVFR0_FPDP_SHIFT, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFP),
1214 HWCAP_CAP(SYS_MVFR0_EL1, MVFR0_FPDP_SHIFT, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFPv3),
1215 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_PMULL),
1216 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_AES),
1217 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA1_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA1),
1218 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA2_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA2),
1219 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_CRC32_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_CRC32),
1224 static void __init cap_set_elf_hwcap(const struct arm64_cpu_capabilities *cap)
1226 switch (cap->hwcap_type) {
1228 elf_hwcap |= cap->hwcap;
1230 #ifdef CONFIG_COMPAT
1231 case CAP_COMPAT_HWCAP:
1232 compat_elf_hwcap |= (u32)cap->hwcap;
1234 case CAP_COMPAT_HWCAP2:
1235 compat_elf_hwcap2 |= (u32)cap->hwcap;
1244 /* Check if we have a particular HWCAP enabled */
1245 static bool cpus_have_elf_hwcap(const struct arm64_cpu_capabilities *cap)
1249 switch (cap->hwcap_type) {
1251 rc = (elf_hwcap & cap->hwcap) != 0;
1253 #ifdef CONFIG_COMPAT
1254 case CAP_COMPAT_HWCAP:
1255 rc = (compat_elf_hwcap & (u32)cap->hwcap) != 0;
1257 case CAP_COMPAT_HWCAP2:
1258 rc = (compat_elf_hwcap2 & (u32)cap->hwcap) != 0;
1269 static void __init setup_elf_hwcaps(const struct arm64_cpu_capabilities *hwcaps)
1271 /* We support emulation of accesses to CPU ID feature registers */
1272 elf_hwcap |= HWCAP_CPUID;
1273 for (; hwcaps->matches; hwcaps++)
1274 if (hwcaps->matches(hwcaps, cpucap_default_scope(hwcaps)))
1275 cap_set_elf_hwcap(hwcaps);
1279 * Check if the current CPU has a given feature capability.
1280 * Should be called from non-preemptible context.
1282 static bool __this_cpu_has_cap(const struct arm64_cpu_capabilities *cap_array,
1285 const struct arm64_cpu_capabilities *caps;
1287 if (WARN_ON(preemptible()))
1290 for (caps = cap_array; caps->matches; caps++)
1291 if (caps->capability == cap &&
1292 caps->matches(caps, SCOPE_LOCAL_CPU))
1297 static void __update_cpu_capabilities(const struct arm64_cpu_capabilities *caps,
1298 u16 scope_mask, const char *info)
1300 scope_mask &= ARM64_CPUCAP_SCOPE_MASK;
1301 for (; caps->matches; caps++) {
1302 if (!(caps->type & scope_mask) ||
1303 !caps->matches(caps, cpucap_default_scope(caps)))
1306 if (!cpus_have_cap(caps->capability) && caps->desc)
1307 pr_info("%s %s\n", info, caps->desc);
1308 cpus_set_cap(caps->capability);
1312 static void update_cpu_capabilities(u16 scope_mask)
1314 __update_cpu_capabilities(arm64_errata, scope_mask,
1315 "enabling workaround for");
1316 __update_cpu_capabilities(arm64_features, scope_mask, "detected:");
1319 static int __enable_cpu_capability(void *arg)
1321 const struct arm64_cpu_capabilities *cap = arg;
1323 cap->cpu_enable(cap);
1328 * Run through the enabled capabilities and enable() it on all active
1332 __enable_cpu_capabilities(const struct arm64_cpu_capabilities *caps,
1335 scope_mask &= ARM64_CPUCAP_SCOPE_MASK;
1336 for (; caps->matches; caps++) {
1337 unsigned int num = caps->capability;
1339 if (!(caps->type & scope_mask) || !cpus_have_cap(num))
1342 /* Ensure cpus_have_const_cap(num) works */
1343 static_branch_enable(&cpu_hwcap_keys[num]);
1345 if (caps->cpu_enable) {
1347 * Capabilities with SCOPE_BOOT_CPU scope are finalised
1348 * before any secondary CPU boots. Thus, each secondary
1349 * will enable the capability as appropriate via
1350 * check_local_cpu_capabilities(). The only exception is
1351 * the boot CPU, for which the capability must be
1352 * enabled here. This approach avoids costly
1353 * stop_machine() calls for this case.
1355 * Otherwise, use stop_machine() as it schedules the
1356 * work allowing us to modify PSTATE, instead of
1357 * on_each_cpu() which uses an IPI, giving us a PSTATE
1358 * that disappears when we return.
1360 if (scope_mask & SCOPE_BOOT_CPU)
1361 caps->cpu_enable(caps);
1363 stop_machine(__enable_cpu_capability,
1364 (void *)caps, cpu_online_mask);
1369 static void __init enable_cpu_capabilities(u16 scope_mask)
1371 __enable_cpu_capabilities(arm64_errata, scope_mask);
1372 __enable_cpu_capabilities(arm64_features, scope_mask);
1376 * Flag to indicate if we have computed the system wide
1377 * capabilities based on the boot time active CPUs. This
1378 * will be used to determine if a new booting CPU should
1379 * go through the verification process to make sure that it
1380 * supports the system capabilities, without using a hotplug
1383 static bool sys_caps_initialised;
1385 static inline void set_sys_caps_initialised(void)
1387 sys_caps_initialised = true;
1391 * Run through the list of capabilities to check for conflicts.
1392 * If the system has already detected a capability, take necessary
1393 * action on this CPU.
1395 * Returns "false" on conflicts.
1398 __verify_local_cpu_caps(const struct arm64_cpu_capabilities *caps_list,
1401 bool cpu_has_cap, system_has_cap;
1402 const struct arm64_cpu_capabilities *caps;
1404 scope_mask &= ARM64_CPUCAP_SCOPE_MASK;
1406 for (caps = caps_list; caps->matches; caps++) {
1407 if (!(caps->type & scope_mask))
1410 cpu_has_cap = __this_cpu_has_cap(caps_list, caps->capability);
1411 system_has_cap = cpus_have_cap(caps->capability);
1413 if (system_has_cap) {
1415 * Check if the new CPU misses an advertised feature,
1416 * which is not safe to miss.
1418 if (!cpu_has_cap && !cpucap_late_cpu_optional(caps))
1421 * We have to issue cpu_enable() irrespective of
1422 * whether the CPU has it or not, as it is enabeld
1423 * system wide. It is upto the call back to take
1424 * appropriate action on this CPU.
1426 if (caps->cpu_enable)
1427 caps->cpu_enable(caps);
1430 * Check if the CPU has this capability if it isn't
1431 * safe to have when the system doesn't.
1433 if (cpu_has_cap && !cpucap_late_cpu_permitted(caps))
1438 if (caps->matches) {
1439 pr_crit("CPU%d: Detected conflict for capability %d (%s), System: %d, CPU: %d\n",
1440 smp_processor_id(), caps->capability,
1441 caps->desc, system_has_cap, cpu_has_cap);
1448 static bool verify_local_cpu_caps(u16 scope_mask)
1450 return __verify_local_cpu_caps(arm64_errata, scope_mask) &&
1451 __verify_local_cpu_caps(arm64_features, scope_mask);
1455 * Check for CPU features that are used in early boot
1456 * based on the Boot CPU value.
1458 static void check_early_cpu_features(void)
1460 verify_cpu_asid_bits();
1462 * Early features are used by the kernel already. If there
1463 * is a conflict, we cannot proceed further.
1465 if (!verify_local_cpu_caps(SCOPE_BOOT_CPU))
1470 verify_local_elf_hwcaps(const struct arm64_cpu_capabilities *caps)
1473 for (; caps->matches; caps++)
1474 if (cpus_have_elf_hwcap(caps) && !caps->matches(caps, SCOPE_LOCAL_CPU)) {
1475 pr_crit("CPU%d: missing HWCAP: %s\n",
1476 smp_processor_id(), caps->desc);
1483 * Run through the enabled system capabilities and enable() it on this CPU.
1484 * The capabilities were decided based on the available CPUs at the boot time.
1485 * Any new CPU should match the system wide status of the capability. If the
1486 * new CPU doesn't have a capability which the system now has enabled, we
1487 * cannot do anything to fix it up and could cause unexpected failures. So
1490 static void verify_local_cpu_capabilities(void)
1493 * The capabilities with SCOPE_BOOT_CPU are checked from
1494 * check_early_cpu_features(), as they need to be verified
1495 * on all secondary CPUs.
1497 if (!verify_local_cpu_caps(SCOPE_ALL & ~SCOPE_BOOT_CPU))
1500 verify_local_elf_hwcaps(arm64_elf_hwcaps);
1501 if (system_supports_32bit_el0())
1502 verify_local_elf_hwcaps(compat_elf_hwcaps);
1505 void check_local_cpu_capabilities(void)
1508 * All secondary CPUs should conform to the early CPU features
1509 * in use by the kernel based on boot CPU.
1511 check_early_cpu_features();
1514 * If we haven't finalised the system capabilities, this CPU gets
1515 * a chance to update the errata work arounds and local features.
1516 * Otherwise, this CPU should verify that it has all the system
1517 * advertised capabilities.
1519 if (!sys_caps_initialised)
1520 update_cpu_capabilities(SCOPE_LOCAL_CPU);
1522 verify_local_cpu_capabilities();
1525 static void __init setup_boot_cpu_capabilities(void)
1527 /* Detect capabilities with either SCOPE_BOOT_CPU or SCOPE_LOCAL_CPU */
1528 update_cpu_capabilities(SCOPE_BOOT_CPU | SCOPE_LOCAL_CPU);
1529 /* Enable the SCOPE_BOOT_CPU capabilities alone right away */
1530 enable_cpu_capabilities(SCOPE_BOOT_CPU);
1533 DEFINE_STATIC_KEY_FALSE(arm64_const_caps_ready);
1534 EXPORT_SYMBOL(arm64_const_caps_ready);
1536 static void __init mark_const_caps_ready(void)
1538 static_branch_enable(&arm64_const_caps_ready);
1541 extern const struct arm64_cpu_capabilities arm64_errata[];
1543 bool this_cpu_has_cap(unsigned int cap)
1545 return (__this_cpu_has_cap(arm64_features, cap) ||
1546 __this_cpu_has_cap(arm64_errata, cap));
1549 static void __init setup_system_capabilities(void)
1552 * We have finalised the system-wide safe feature
1553 * registers, finalise the capabilities that depend
1554 * on it. Also enable all the available capabilities,
1555 * that are not enabled already.
1557 update_cpu_capabilities(SCOPE_SYSTEM);
1558 enable_cpu_capabilities(SCOPE_ALL & ~SCOPE_BOOT_CPU);
1561 void __init setup_cpu_features(void)
1566 setup_system_capabilities();
1567 mark_const_caps_ready();
1568 setup_elf_hwcaps(arm64_elf_hwcaps);
1570 if (system_supports_32bit_el0())
1571 setup_elf_hwcaps(compat_elf_hwcaps);
1573 /* Advertise that we have computed the system capabilities */
1574 set_sys_caps_initialised();
1577 * Check for sane CTR_EL0.CWG value.
1579 cwg = cache_type_cwg();
1580 cls = cache_line_size();
1582 pr_warn("No Cache Writeback Granule information, assuming cache line size %d\n",
1584 if (L1_CACHE_BYTES < cls)
1585 pr_warn("L1_CACHE_BYTES smaller than the Cache Writeback Granule (%d < %d)\n",
1586 L1_CACHE_BYTES, cls);
1589 static bool __maybe_unused
1590 cpufeature_pan_not_uao(const struct arm64_cpu_capabilities *entry, int __unused)
1592 return (cpus_have_const_cap(ARM64_HAS_PAN) && !cpus_have_const_cap(ARM64_HAS_UAO));
1596 * We emulate only the following system register space.
1597 * Op0 = 0x3, CRn = 0x0, Op1 = 0x0, CRm = [0, 4 - 7]
1598 * See Table C5-6 System instruction encodings for System register accesses,
1599 * ARMv8 ARM(ARM DDI 0487A.f) for more details.
1601 static inline bool __attribute_const__ is_emulated(u32 id)
1603 return (sys_reg_Op0(id) == 0x3 &&
1604 sys_reg_CRn(id) == 0x0 &&
1605 sys_reg_Op1(id) == 0x0 &&
1606 (sys_reg_CRm(id) == 0 ||
1607 ((sys_reg_CRm(id) >= 4) && (sys_reg_CRm(id) <= 7))));
1611 * With CRm == 0, reg should be one of :
1612 * MIDR_EL1, MPIDR_EL1 or REVIDR_EL1.
1614 static inline int emulate_id_reg(u32 id, u64 *valp)
1618 *valp = read_cpuid_id();
1621 *valp = SYS_MPIDR_SAFE_VAL;
1623 case SYS_REVIDR_EL1:
1624 /* IMPLEMENTATION DEFINED values are emulated with 0 */
1634 static int emulate_sys_reg(u32 id, u64 *valp)
1636 struct arm64_ftr_reg *regp;
1638 if (!is_emulated(id))
1641 if (sys_reg_CRm(id) == 0)
1642 return emulate_id_reg(id, valp);
1644 regp = get_arm64_ftr_reg(id);
1646 *valp = arm64_ftr_reg_user_value(regp);
1649 * The untracked registers are either IMPLEMENTATION DEFINED
1650 * (e.g, ID_AFR0_EL1) or reserved RAZ.
1656 static int emulate_mrs(struct pt_regs *regs, u32 insn)
1663 * sys_reg values are defined as used in mrs/msr instruction.
1664 * shift the imm value to get the encoding.
1666 sys_reg = (u32)aarch64_insn_decode_immediate(AARCH64_INSN_IMM_16, insn) << 5;
1667 rc = emulate_sys_reg(sys_reg, &val);
1669 dst = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RT, insn);
1670 pt_regs_write_reg(regs, dst, val);
1671 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE);
1677 static struct undef_hook mrs_hook = {
1678 .instr_mask = 0xfff00000,
1679 .instr_val = 0xd5300000,
1680 .pstate_mask = COMPAT_PSR_MODE_MASK,
1681 .pstate_val = PSR_MODE_EL0t,
1685 static int __init enable_mrs_emulation(void)
1687 register_undef_hook(&mrs_hook);
1691 core_initcall(enable_mrs_emulation);
1693 ssize_t cpu_show_meltdown(struct device *dev, struct device_attribute *attr,
1696 if (__meltdown_safe)
1697 return sprintf(buf, "Not affected\n");
1699 if (arm64_kernel_unmapped_at_el0())
1700 return sprintf(buf, "Mitigation: PTI\n");
1702 return sprintf(buf, "Vulnerable\n");