arch/arm64/kernel/cpufeature.c

   1 /*
   2  * Contains CPU feature definitions
   3  *
   4  * Copyright (C) 2015 ARM Ltd.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  17  */
  18
  19 #define pr_fmt(fmt) "CPU features: " fmt
  20
  21 #include <linux/bsearch.h>
  22 #include <linux/cpumask.h>
  23 #include <linux/percpu.h>
  24 #include <linux/sort.h>
  25 #include <linux/stop_machine.h>
  26 #include <linux/types.h>
  27 #include <linux/mm.h>
  28 #include <linux/cpu.h>
  29
  30 #include <asm/cpu.h>
  31 #include <asm/cpufeature.h>
  32 #include <asm/cpu_ops.h>
  33 #include <asm/fpsimd.h>
  34 #include <asm/mmu_context.h>
  35 #include <asm/processor.h>
  36 #include <asm/sysreg.h>
  37 #include <asm/traps.h>
  38 #include <asm/vectors.h>
  39 #include <asm/virt.h>
  40
  41 unsigned long elf_hwcap __read_mostly;
  42 EXPORT_SYMBOL_GPL(elf_hwcap);
  43
  44 #ifdef CONFIG_COMPAT
  45 #define COMPAT_ELF_HWCAP_DEFAULT        \
  46                                 (COMPAT_HWCAP_HALF|COMPAT_HWCAP_THUMB|\
  47                                  COMPAT_HWCAP_FAST_MULT|COMPAT_HWCAP_EDSP|\
  48                                  COMPAT_HWCAP_TLS|COMPAT_HWCAP_IDIV|\
  49                                  COMPAT_HWCAP_LPAE)
  50 unsigned int compat_elf_hwcap __read_mostly = COMPAT_ELF_HWCAP_DEFAULT;
  51 unsigned int compat_elf_hwcap2 __read_mostly;
  52 #endif
  53
  54 DECLARE_BITMAP(cpu_hwcaps, ARM64_NCAPS);
  55 EXPORT_SYMBOL(cpu_hwcaps);
  56
  57 DEFINE_PER_CPU_READ_MOSTLY(const char *, this_cpu_vector) = vectors;
  58
  59 /*
  60  * Flag to indicate if we have computed the system wide
  61  * capabilities based on the boot time active CPUs. This
  62  * will be used to determine if a new booting CPU should
  63  * go through the verification process to make sure that it
  64  * supports the system capabilities, without using a hotplug
  65  * notifier.
  66  */
  67 static bool sys_caps_initialised;
  68
  69 static inline void set_sys_caps_initialised(void)
  70 {
  71         sys_caps_initialised = true;
  72 }
  73
  74 static int dump_cpu_hwcaps(struct notifier_block *self, unsigned long v, void *p)
  75 {
  76         /* file-wide pr_fmt adds "CPU features: " prefix */
  77         pr_emerg("0x%*pb\n", ARM64_NCAPS, &cpu_hwcaps);
  78         return 0;
  79 }
  80
  81 static struct notifier_block cpu_hwcaps_notifier = {
  82         .notifier_call = dump_cpu_hwcaps
  83 };
  84
  85 static int __init register_cpu_hwcaps_dumper(void)
  86 {
  87         atomic_notifier_chain_register(&panic_notifier_list,
  88                                        &cpu_hwcaps_notifier);
  89         return 0;
  90 }
  91 __initcall(register_cpu_hwcaps_dumper);
  92
  93 DEFINE_STATIC_KEY_ARRAY_FALSE(cpu_hwcap_keys, ARM64_NCAPS);
  94 EXPORT_SYMBOL(cpu_hwcap_keys);
  95
  96 #define __ARM64_FTR_BITS(SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
  97         {                                               \
  98                 .sign = SIGNED,                         \
  99                 .visible = VISIBLE,                     \
 100                 .strict = STRICT,                       \
 101                 .type = TYPE,                           \
 102                 .shift = SHIFT,                         \
 103                 .width = WIDTH,                         \
 104                 .safe_val = SAFE_VAL,                   \
 105         }
 106
 107 /* Define a feature with unsigned values */
 108 #define ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
 109         __ARM64_FTR_BITS(FTR_UNSIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL)
 110
 111 /* Define a feature with a signed value */
 112 #define S_ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
 113         __ARM64_FTR_BITS(FTR_SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL)
 114
 115 #define ARM64_FTR_END                                   \
 116         {                                               \
 117                 .width = 0,                             \
 118         }
 119
 120 /* meta feature for alternatives */
 121 static bool __maybe_unused
 122 cpufeature_pan_not_uao(const struct arm64_cpu_capabilities *entry, int __unused);
 123
 124
 125 /*
 126  * NOTE: Any changes to the visibility of features should be kept in
 127  * sync with the documentation of the CPU feature register ABI.
 128  */
 129 static const struct arm64_ftr_bits ftr_id_aa64isar0[] = {
 130         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_TS_SHIFT, 4, 0),
 131         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_FHM_SHIFT, 4, 0),
 132         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_DP_SHIFT, 4, 0),
 133         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SM4_SHIFT, 4, 0),
 134         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SM3_SHIFT, 4, 0),
 135         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA3_SHIFT, 4, 0),
 136         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_RDM_SHIFT, 4, 0),
 137         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_ATOMICS_SHIFT, 4, 0),
 138         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_CRC32_SHIFT, 4, 0),
 139         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA2_SHIFT, 4, 0),
 140         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA1_SHIFT, 4, 0),
 141         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_AES_SHIFT, 4, 0),
 142         ARM64_FTR_END,
 143 };
 144
 145 static const struct arm64_ftr_bits ftr_id_aa64isar1[] = {
 146         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_LRCPC_SHIFT, 4, 0),
 147         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_FCMA_SHIFT, 4, 0),
 148         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_JSCVT_SHIFT, 4, 0),
 149         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_DPB_SHIFT, 4, 0),
 150         ARM64_FTR_END,
 151 };
 152
 153 static const struct arm64_ftr_bits ftr_id_aa64isar2[] = {
 154         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_AA64ISAR2_CLEARBHB_SHIFT, 4, 0),
 155         ARM64_FTR_END,
 156 };
 157
 158 static const struct arm64_ftr_bits ftr_id_aa64pfr0[] = {
 159         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_CSV3_SHIFT, 4, 0),
 160         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_CSV2_SHIFT, 4, 0),
 161         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_DIT_SHIFT, 4, 0),
 162         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
 163                                    FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_SVE_SHIFT, 4, 0),
 164         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_RAS_SHIFT, 4, 0),
 165         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_GIC_SHIFT, 4, 0),
 166         S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_ASIMD_SHIFT, 4, ID_AA64PFR0_ASIMD_NI),
 167         S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_FP_SHIFT, 4, ID_AA64PFR0_FP_NI),
 168         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL3_SHIFT, 4, 0),
 169         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL2_SHIFT, 4, 0),
 170         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_SHIFT, 4, ID_AA64PFR0_EL1_64BIT_ONLY),
 171         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL0_SHIFT, 4, ID_AA64PFR0_EL0_64BIT_ONLY),
 172         ARM64_FTR_END,
 173 };
 174
 175 static const struct arm64_ftr_bits ftr_id_aa64pfr1[] = {
 176         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_SSBS_SHIFT, 4, ID_AA64PFR1_SSBS_PSTATE_NI),
 177         ARM64_FTR_END,
 178 };
 179
 180 static const struct arm64_ftr_bits ftr_id_aa64mmfr0[] = {
 181         /*
 182          * We already refuse to boot CPUs that don't support our configured
 183          * page size, so we can only detect mismatches for a page size other
 184          * than the one we're currently using. Unfortunately, SoCs like this
 185          * exist in the wild so, even though we don't like it, we'll have to go
 186          * along with it and treat them as non-strict.
 187          */
 188         S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN4_SHIFT, 4, ID_AA64MMFR0_TGRAN4_NI),
 189         S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN64_SHIFT, 4, ID_AA64MMFR0_TGRAN64_NI),
 190         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN16_SHIFT, 4, ID_AA64MMFR0_TGRAN16_NI),
 191
 192         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_BIGENDEL0_SHIFT, 4, 0),
 193         /* Linux shouldn't care about secure memory */
 194         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_SNSMEM_SHIFT, 4, 0),
 195         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_BIGENDEL_SHIFT, 4, 0),
 196         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_ASID_SHIFT, 4, 0),
 197         /*
 198          * Differing PARange is fine as long as all peripherals and memory are mapped
 199          * within the minimum PARange of all CPUs
 200          */
 201         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_PARANGE_SHIFT, 4, 0),
 202         ARM64_FTR_END,
 203 };
 204
 205 static const struct arm64_ftr_bits ftr_id_aa64mmfr1[] = {
 206         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_PAN_SHIFT, 4, 0),
 207         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_LOR_SHIFT, 4, 0),
 208         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_HPD_SHIFT, 4, 0),
 209         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_VHE_SHIFT, 4, 0),
 210         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_VMIDBITS_SHIFT, 4, 0),
 211         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_HADBS_SHIFT, 4, 0),
 212         ARM64_FTR_END,
 213 };
 214
 215 static const struct arm64_ftr_bits ftr_id_aa64mmfr2[] = {
 216         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_FWB_SHIFT, 4, 0),
 217         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_AT_SHIFT, 4, 0),
 218         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_LVA_SHIFT, 4, 0),
 219         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_IESB_SHIFT, 4, 0),
 220         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_LSM_SHIFT, 4, 0),
 221         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_UAO_SHIFT, 4, 0),
 222         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_CNP_SHIFT, 4, 0),
 223         ARM64_FTR_END,
 224 };
 225
 226 static const struct arm64_ftr_bits ftr_ctr[] = {
 227         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, 31, 1, 1), /* RES1 */
 228         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_DIC_SHIFT, 1, 1),
 229         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_IDC_SHIFT, 1, 1),
 230         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, CTR_CWG_SHIFT, 4, 0),
 231         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, CTR_ERG_SHIFT, 4, 0),
 232         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_DMINLINE_SHIFT, 4, 1),
 233         /*
 234          * Linux can handle differing I-cache policies. Userspace JITs will
 235          * make use of *minLine.
 236          * If we have differing I-cache policies, report it as the weakest - VIPT.
 237          */
 238         ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_EXACT, 14, 2, ICACHE_POLICY_VIPT),       /* L1Ip */
 239         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_IMINLINE_SHIFT, 4, 0),
 240         ARM64_FTR_END,
 241 };
 242
 243 struct arm64_ftr_reg arm64_ftr_reg_ctrel0 = {
 244         .name           = "SYS_CTR_EL0",
 245         .ftr_bits       = ftr_ctr
 246 };
 247
 248 static const struct arm64_ftr_bits ftr_id_mmfr0[] = {
 249         S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0xf),   /* InnerShr */
 250         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0),       /* FCSE */
 251         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, 20, 4, 0),    /* AuxReg */
 252         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0),       /* TCM */
 253         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0),       /* ShareLvl */
 254         S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0xf),    /* OuterShr */
 255         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),        /* PMSA */
 256         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),        /* VMSA */
 257         ARM64_FTR_END,
 258 };
 259
 260 static const struct arm64_ftr_bits ftr_id_aa64dfr0[] = {
 261         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 36, 28, 0),
 262         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64DFR0_PMSVER_SHIFT, 4, 0),
 263         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_CTX_CMPS_SHIFT, 4, 0),
 264         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_WRPS_SHIFT, 4, 0),
 265         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_BRPS_SHIFT, 4, 0),
 266         /*
 267          * We can instantiate multiple PMU instances with different levels
 268          * of support.
 269          */
 270         S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64DFR0_PMUVER_SHIFT, 4, 0),
 271         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64DFR0_DEBUGVER_SHIFT, 4, 0x6),
 272         ARM64_FTR_END,
 273 };
 274
 275 static const struct arm64_ftr_bits ftr_mvfr2[] = {
 276         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),                /* FPMisc */
 277         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),                /* SIMDMisc */
 278         ARM64_FTR_END,
 279 };
 280
 281 static const struct arm64_ftr_bits ftr_dczid[] = {
 282         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, 4, 1, 1),            /* DZP */
 283         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),       /* BS */
 284         ARM64_FTR_END,
 285 };
 286
 287
 288 static const struct arm64_ftr_bits ftr_id_isar5[] = {
 289         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_RDM_SHIFT, 4, 0),
 290         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_CRC32_SHIFT, 4, 0),
 291         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SHA2_SHIFT, 4, 0),
 292         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SHA1_SHIFT, 4, 0),
 293         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_AES_SHIFT, 4, 0),
 294         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SEVL_SHIFT, 4, 0),
 295         ARM64_FTR_END,
 296 };
 297
 298 static const struct arm64_ftr_bits ftr_id_mmfr4[] = {
 299         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),        /* ac2 */
 300         ARM64_FTR_END,
 301 };
 302
 303 static const struct arm64_ftr_bits ftr_id_pfr0[] = {
 304         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0),               /* State3 */
 305         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0),                /* State2 */
 306         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),                /* State1 */
 307         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),                /* State0 */
 308         ARM64_FTR_END,
 309 };
 310
 311 static const struct arm64_ftr_bits ftr_id_dfr0[] = {
 312         /* [31:28] TraceFilt */
 313         S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0xf),   /* PerfMon */
 314         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0),
 315         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0),
 316         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0),
 317         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0),
 318         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),
 319         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),
 320         ARM64_FTR_END,
 321 };
 322
 323 static const struct arm64_ftr_bits ftr_zcr[] = {
 324         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE,
 325                 ZCR_ELx_LEN_SHIFT, ZCR_ELx_LEN_SIZE, 0),        /* LEN */
 326         ARM64_FTR_END,
 327 };
 328
 329 /*
 330  * Common ftr bits for a 32bit register with all hidden, strict
 331  * attributes, with 4bit feature fields and a default safe value of
 332  * 0. Covers the following 32bit registers:
 333  * id_isar[0-4], id_mmfr[1-3], id_pfr1, mvfr[0-1]
 334  */
 335 static const struct arm64_ftr_bits ftr_generic_32bits[] = {
 336         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0),
 337         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0),
 338         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0),
 339         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0),
 340         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0),
 341         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0),
 342         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),
 343         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),
 344         ARM64_FTR_END,
 345 };
 346
 347 /* Table for a single 32bit feature value */
 348 static const struct arm64_ftr_bits ftr_single32[] = {
 349         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 0, 32, 0),
 350         ARM64_FTR_END,
 351 };
 352
 353 static const struct arm64_ftr_bits ftr_raz[] = {
 354         ARM64_FTR_END,
 355 };
 356
 357 #define ARM64_FTR_REG(id, table) {              \
 358         .sys_id = id,                           \
 359         .reg =  &(struct arm64_ftr_reg){        \
 360                 .name = #id,                    \
 361                 .ftr_bits = &((table)[0]),      \
 362         }}
 363
 364 static const struct __ftr_reg_entry {
 365         u32                     sys_id;
 366         struct arm64_ftr_reg    *reg;
 367 } arm64_ftr_regs[] = {
 368
 369         /* Op1 = 0, CRn = 0, CRm = 1 */
 370         ARM64_FTR_REG(SYS_ID_PFR0_EL1, ftr_id_pfr0),
 371         ARM64_FTR_REG(SYS_ID_PFR1_EL1, ftr_generic_32bits),
 372         ARM64_FTR_REG(SYS_ID_DFR0_EL1, ftr_id_dfr0),
 373         ARM64_FTR_REG(SYS_ID_MMFR0_EL1, ftr_id_mmfr0),
 374         ARM64_FTR_REG(SYS_ID_MMFR1_EL1, ftr_generic_32bits),
 375         ARM64_FTR_REG(SYS_ID_MMFR2_EL1, ftr_generic_32bits),
 376         ARM64_FTR_REG(SYS_ID_MMFR3_EL1, ftr_generic_32bits),
 377
 378         /* Op1 = 0, CRn = 0, CRm = 2 */
 379         ARM64_FTR_REG(SYS_ID_ISAR0_EL1, ftr_generic_32bits),
 380         ARM64_FTR_REG(SYS_ID_ISAR1_EL1, ftr_generic_32bits),
 381         ARM64_FTR_REG(SYS_ID_ISAR2_EL1, ftr_generic_32bits),
 382         ARM64_FTR_REG(SYS_ID_ISAR3_EL1, ftr_generic_32bits),
 383         ARM64_FTR_REG(SYS_ID_ISAR4_EL1, ftr_generic_32bits),
 384         ARM64_FTR_REG(SYS_ID_ISAR5_EL1, ftr_id_isar5),
 385         ARM64_FTR_REG(SYS_ID_MMFR4_EL1, ftr_id_mmfr4),
 386
 387         /* Op1 = 0, CRn = 0, CRm = 3 */
 388         ARM64_FTR_REG(SYS_MVFR0_EL1, ftr_generic_32bits),
 389         ARM64_FTR_REG(SYS_MVFR1_EL1, ftr_generic_32bits),
 390         ARM64_FTR_REG(SYS_MVFR2_EL1, ftr_mvfr2),
 391
 392         /* Op1 = 0, CRn = 0, CRm = 4 */
 393         ARM64_FTR_REG(SYS_ID_AA64PFR0_EL1, ftr_id_aa64pfr0),
 394         ARM64_FTR_REG(SYS_ID_AA64PFR1_EL1, ftr_id_aa64pfr1),
 395         ARM64_FTR_REG(SYS_ID_AA64ZFR0_EL1, ftr_raz),
 396
 397         /* Op1 = 0, CRn = 0, CRm = 5 */
 398         ARM64_FTR_REG(SYS_ID_AA64DFR0_EL1, ftr_id_aa64dfr0),
 399         ARM64_FTR_REG(SYS_ID_AA64DFR1_EL1, ftr_raz),
 400
 401         /* Op1 = 0, CRn = 0, CRm = 6 */
 402         ARM64_FTR_REG(SYS_ID_AA64ISAR0_EL1, ftr_id_aa64isar0),
 403         ARM64_FTR_REG(SYS_ID_AA64ISAR1_EL1, ftr_id_aa64isar1),
 404         ARM64_FTR_REG(SYS_ID_AA64ISAR2_EL1, ftr_id_aa64isar2),
 405
 406         /* Op1 = 0, CRn = 0, CRm = 7 */
 407         ARM64_FTR_REG(SYS_ID_AA64MMFR0_EL1, ftr_id_aa64mmfr0),
 408         ARM64_FTR_REG(SYS_ID_AA64MMFR1_EL1, ftr_id_aa64mmfr1),
 409         ARM64_FTR_REG(SYS_ID_AA64MMFR2_EL1, ftr_id_aa64mmfr2),
 410
 411         /* Op1 = 0, CRn = 1, CRm = 2 */
 412         ARM64_FTR_REG(SYS_ZCR_EL1, ftr_zcr),
 413
 414         /* Op1 = 3, CRn = 0, CRm = 0 */
 415         { SYS_CTR_EL0, &arm64_ftr_reg_ctrel0 },
 416         ARM64_FTR_REG(SYS_DCZID_EL0, ftr_dczid),
 417
 418         /* Op1 = 3, CRn = 14, CRm = 0 */
 419         ARM64_FTR_REG(SYS_CNTFRQ_EL0, ftr_single32),
 420 };
 421
 422 static int search_cmp_ftr_reg(const void *id, const void *regp)
 423 {
 424         return (int)(unsigned long)id - (int)((const struct __ftr_reg_entry *)regp)->sys_id;
 425 }
 426
 427 /*
 428  * get_arm64_ftr_reg - Lookup a feature register entry using its
 429  * sys_reg() encoding. With the array arm64_ftr_regs sorted in the
 430  * ascending order of sys_id , we use binary search to find a matching
 431  * entry.
 432  *
 433  * returns - Upon success,  matching ftr_reg entry for id.
 434  *         - NULL on failure. It is upto the caller to decide
 435  *           the impact of a failure.
 436  */
 437 static struct arm64_ftr_reg *get_arm64_ftr_reg(u32 sys_id)
 438 {
 439         const struct __ftr_reg_entry *ret;
 440
 441         ret = bsearch((const void *)(unsigned long)sys_id,
 442                         arm64_ftr_regs,
 443                         ARRAY_SIZE(arm64_ftr_regs),
 444                         sizeof(arm64_ftr_regs[0]),
 445                         search_cmp_ftr_reg);
 446         if (ret)
 447                 return ret->reg;
 448         return NULL;
 449 }
 450
 451 static u64 arm64_ftr_set_value(const struct arm64_ftr_bits *ftrp, s64 reg,
 452                                s64 ftr_val)
 453 {
 454         u64 mask = arm64_ftr_mask(ftrp);
 455
 456         reg &= ~mask;
 457         reg |= (ftr_val << ftrp->shift) & mask;
 458         return reg;
 459 }
 460
 461 static s64 arm64_ftr_safe_value(const struct arm64_ftr_bits *ftrp, s64 new,
 462                                 s64 cur)
 463 {
 464         s64 ret = 0;
 465
 466         switch (ftrp->type) {
 467         case FTR_EXACT:
 468                 ret = ftrp->safe_val;
 469                 break;
 470         case FTR_LOWER_SAFE:
 471                 ret = new < cur ? new : cur;
 472                 break;
 473         case FTR_HIGHER_OR_ZERO_SAFE:
 474                 if (!cur || !new)
 475                         break;
 476                 /* Fallthrough */
 477         case FTR_HIGHER_SAFE:
 478                 ret = new > cur ? new : cur;
 479                 break;
 480         default:
 481                 BUG();
 482         }
 483
 484         return ret;
 485 }
 486
 487 static void __init sort_ftr_regs(void)
 488 {
 489         int i;
 490
 491         /* Check that the array is sorted so that we can do the binary search */
 492         for (i = 1; i < ARRAY_SIZE(arm64_ftr_regs); i++)
 493                 BUG_ON(arm64_ftr_regs[i].sys_id < arm64_ftr_regs[i - 1].sys_id);
 494 }
 495
 496 /*
 497  * Initialise the CPU feature register from Boot CPU values.
 498  * Also initiliases the strict_mask for the register.
 499  * Any bits that are not covered by an arm64_ftr_bits entry are considered
 500  * RES0 for the system-wide value, and must strictly match.
 501  */
 502 static void __init init_cpu_ftr_reg(u32 sys_reg, u64 new)
 503 {
 504         u64 val = 0;
 505         u64 strict_mask = ~0x0ULL;
 506         u64 user_mask = 0;
 507         u64 valid_mask = 0;
 508
 509         const struct arm64_ftr_bits *ftrp;
 510         struct arm64_ftr_reg *reg = get_arm64_ftr_reg(sys_reg);
 511
 512         BUG_ON(!reg);
 513
 514         for (ftrp  = reg->ftr_bits; ftrp->width; ftrp++) {
 515                 u64 ftr_mask = arm64_ftr_mask(ftrp);
 516                 s64 ftr_new = arm64_ftr_value(ftrp, new);
 517
 518                 val = arm64_ftr_set_value(ftrp, val, ftr_new);
 519
 520                 valid_mask |= ftr_mask;
 521                 if (!ftrp->strict)
 522                         strict_mask &= ~ftr_mask;
 523                 if (ftrp->visible)
 524                         user_mask |= ftr_mask;
 525                 else
 526                         reg->user_val = arm64_ftr_set_value(ftrp,
 527                                                             reg->user_val,
 528                                                             ftrp->safe_val);
 529         }
 530
 531         val &= valid_mask;
 532
 533         reg->sys_val = val;
 534         reg->strict_mask = strict_mask;
 535         reg->user_mask = user_mask;
 536 }
 537
 538 extern const struct arm64_cpu_capabilities arm64_errata[];
 539 static void __init setup_boot_cpu_capabilities(void);
 540
 541 void __init init_cpu_features(struct cpuinfo_arm64 *info)
 542 {
 543         /* Before we start using the tables, make sure it is sorted */
 544         sort_ftr_regs();
 545
 546         init_cpu_ftr_reg(SYS_CTR_EL0, info->reg_ctr);
 547         init_cpu_ftr_reg(SYS_DCZID_EL0, info->reg_dczid);
 548         init_cpu_ftr_reg(SYS_CNTFRQ_EL0, info->reg_cntfrq);
 549         init_cpu_ftr_reg(SYS_ID_AA64DFR0_EL1, info->reg_id_aa64dfr0);
 550         init_cpu_ftr_reg(SYS_ID_AA64DFR1_EL1, info->reg_id_aa64dfr1);
 551         init_cpu_ftr_reg(SYS_ID_AA64ISAR0_EL1, info->reg_id_aa64isar0);
 552         init_cpu_ftr_reg(SYS_ID_AA64ISAR1_EL1, info->reg_id_aa64isar1);
 553         init_cpu_ftr_reg(SYS_ID_AA64ISAR2_EL1, info->reg_id_aa64isar2);
 554         init_cpu_ftr_reg(SYS_ID_AA64MMFR0_EL1, info->reg_id_aa64mmfr0);
 555         init_cpu_ftr_reg(SYS_ID_AA64MMFR1_EL1, info->reg_id_aa64mmfr1);
 556         init_cpu_ftr_reg(SYS_ID_AA64MMFR2_EL1, info->reg_id_aa64mmfr2);
 557         init_cpu_ftr_reg(SYS_ID_AA64PFR0_EL1, info->reg_id_aa64pfr0);
 558         init_cpu_ftr_reg(SYS_ID_AA64PFR1_EL1, info->reg_id_aa64pfr1);
 559         init_cpu_ftr_reg(SYS_ID_AA64ZFR0_EL1, info->reg_id_aa64zfr0);
 560
 561         if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) {
 562                 init_cpu_ftr_reg(SYS_ID_DFR0_EL1, info->reg_id_dfr0);
 563                 init_cpu_ftr_reg(SYS_ID_ISAR0_EL1, info->reg_id_isar0);
 564                 init_cpu_ftr_reg(SYS_ID_ISAR1_EL1, info->reg_id_isar1);
 565                 init_cpu_ftr_reg(SYS_ID_ISAR2_EL1, info->reg_id_isar2);
 566                 init_cpu_ftr_reg(SYS_ID_ISAR3_EL1, info->reg_id_isar3);
 567                 init_cpu_ftr_reg(SYS_ID_ISAR4_EL1, info->reg_id_isar4);
 568                 init_cpu_ftr_reg(SYS_ID_ISAR5_EL1, info->reg_id_isar5);
 569                 init_cpu_ftr_reg(SYS_ID_MMFR0_EL1, info->reg_id_mmfr0);
 570                 init_cpu_ftr_reg(SYS_ID_MMFR1_EL1, info->reg_id_mmfr1);
 571                 init_cpu_ftr_reg(SYS_ID_MMFR2_EL1, info->reg_id_mmfr2);
 572                 init_cpu_ftr_reg(SYS_ID_MMFR3_EL1, info->reg_id_mmfr3);
 573                 init_cpu_ftr_reg(SYS_ID_PFR0_EL1, info->reg_id_pfr0);
 574                 init_cpu_ftr_reg(SYS_ID_PFR1_EL1, info->reg_id_pfr1);
 575                 init_cpu_ftr_reg(SYS_MVFR0_EL1, info->reg_mvfr0);
 576                 init_cpu_ftr_reg(SYS_MVFR1_EL1, info->reg_mvfr1);
 577                 init_cpu_ftr_reg(SYS_MVFR2_EL1, info->reg_mvfr2);
 578         }
 579
 580         if (id_aa64pfr0_sve(info->reg_id_aa64pfr0)) {
 581                 init_cpu_ftr_reg(SYS_ZCR_EL1, info->reg_zcr);
 582                 sve_init_vq_map();
 583         }
 584
 585         /*
 586          * Detect and enable early CPU capabilities based on the boot CPU,
 587          * after we have initialised the CPU feature infrastructure.
 588          */
 589         setup_boot_cpu_capabilities();
 590 }
 591
 592 static void update_cpu_ftr_reg(struct arm64_ftr_reg *reg, u64 new)
 593 {
 594         const struct arm64_ftr_bits *ftrp;
 595
 596         for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) {
 597                 s64 ftr_cur = arm64_ftr_value(ftrp, reg->sys_val);
 598                 s64 ftr_new = arm64_ftr_value(ftrp, new);
 599
 600                 if (ftr_cur == ftr_new)
 601                         continue;
 602                 /* Find a safe value */
 603                 ftr_new = arm64_ftr_safe_value(ftrp, ftr_new, ftr_cur);
 604                 reg->sys_val = arm64_ftr_set_value(ftrp, reg->sys_val, ftr_new);
 605         }
 606
 607 }
 608
 609 static int check_update_ftr_reg(u32 sys_id, int cpu, u64 val, u64 boot)
 610 {
 611         struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id);
 612
 613         BUG_ON(!regp);
 614         update_cpu_ftr_reg(regp, val);
 615         if ((boot & regp->strict_mask) == (val & regp->strict_mask))
 616                 return 0;
 617         pr_warn("SANITY CHECK: Unexpected variation in %s. Boot CPU: %#016llx, CPU%d: %#016llx\n",
 618                         regp->name, boot, cpu, val);
 619         return 1;
 620 }
 621
 622 /*
 623  * Update system wide CPU feature registers with the values from a
 624  * non-boot CPU. Also performs SANITY checks to make sure that there
 625  * aren't any insane variations from that of the boot CPU.
 626  */
 627 void update_cpu_features(int cpu,
 628                          struct cpuinfo_arm64 *info,
 629                          struct cpuinfo_arm64 *boot)
 630 {
 631         int taint = 0;
 632
 633         /*
 634          * The kernel can handle differing I-cache policies, but otherwise
 635          * caches should look identical. Userspace JITs will make use of
 636          * *minLine.
 637          */
 638         taint |= check_update_ftr_reg(SYS_CTR_EL0, cpu,
 639                                       info->reg_ctr, boot->reg_ctr);
 640
 641         /*
 642          * Userspace may perform DC ZVA instructions. Mismatched block sizes
 643          * could result in too much or too little memory being zeroed if a
 644          * process is preempted and migrated between CPUs.
 645          */
 646         taint |= check_update_ftr_reg(SYS_DCZID_EL0, cpu,
 647                                       info->reg_dczid, boot->reg_dczid);
 648
 649         /* If different, timekeeping will be broken (especially with KVM) */
 650         taint |= check_update_ftr_reg(SYS_CNTFRQ_EL0, cpu,
 651                                       info->reg_cntfrq, boot->reg_cntfrq);
 652
 653         /*
 654          * The kernel uses self-hosted debug features and expects CPUs to
 655          * support identical debug features. We presently need CTX_CMPs, WRPs,
 656          * and BRPs to be identical.
 657          * ID_AA64DFR1 is currently RES0.
 658          */
 659         taint |= check_update_ftr_reg(SYS_ID_AA64DFR0_EL1, cpu,
 660                                       info->reg_id_aa64dfr0, boot->reg_id_aa64dfr0);
 661         taint |= check_update_ftr_reg(SYS_ID_AA64DFR1_EL1, cpu,
 662                                       info->reg_id_aa64dfr1, boot->reg_id_aa64dfr1);
 663         /*
 664          * Even in big.LITTLE, processors should be identical instruction-set
 665          * wise.
 666          */
 667         taint |= check_update_ftr_reg(SYS_ID_AA64ISAR0_EL1, cpu,
 668                                       info->reg_id_aa64isar0, boot->reg_id_aa64isar0);
 669         taint |= check_update_ftr_reg(SYS_ID_AA64ISAR1_EL1, cpu,
 670                                       info->reg_id_aa64isar1, boot->reg_id_aa64isar1);
 671         taint |= check_update_ftr_reg(SYS_ID_AA64ISAR2_EL1, cpu,
 672                                       info->reg_id_aa64isar2, boot->reg_id_aa64isar2);
 673
 674         /*
 675          * Differing PARange support is fine as long as all peripherals and
 676          * memory are mapped within the minimum PARange of all CPUs.
 677          * Linux should not care about secure memory.
 678          */
 679         taint |= check_update_ftr_reg(SYS_ID_AA64MMFR0_EL1, cpu,
 680                                       info->reg_id_aa64mmfr0, boot->reg_id_aa64mmfr0);
 681         taint |= check_update_ftr_reg(SYS_ID_AA64MMFR1_EL1, cpu,
 682                                       info->reg_id_aa64mmfr1, boot->reg_id_aa64mmfr1);
 683         taint |= check_update_ftr_reg(SYS_ID_AA64MMFR2_EL1, cpu,
 684                                       info->reg_id_aa64mmfr2, boot->reg_id_aa64mmfr2);
 685
 686         taint |= check_update_ftr_reg(SYS_ID_AA64PFR0_EL1, cpu,
 687                                       info->reg_id_aa64pfr0, boot->reg_id_aa64pfr0);
 688         taint |= check_update_ftr_reg(SYS_ID_AA64PFR1_EL1, cpu,
 689                                       info->reg_id_aa64pfr1, boot->reg_id_aa64pfr1);
 690
 691         taint |= check_update_ftr_reg(SYS_ID_AA64ZFR0_EL1, cpu,
 692                                       info->reg_id_aa64zfr0, boot->reg_id_aa64zfr0);
 693
 694         /*
 695          * If we have AArch32, we care about 32-bit features for compat.
 696          * If the system doesn't support AArch32, don't update them.
 697          */
 698         if (id_aa64pfr0_32bit_el0(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1)) &&
 699                 id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) {
 700
 701                 taint |= check_update_ftr_reg(SYS_ID_DFR0_EL1, cpu,
 702                                         info->reg_id_dfr0, boot->reg_id_dfr0);
 703                 taint |= check_update_ftr_reg(SYS_ID_ISAR0_EL1, cpu,
 704                                         info->reg_id_isar0, boot->reg_id_isar0);
 705                 taint |= check_update_ftr_reg(SYS_ID_ISAR1_EL1, cpu,
 706                                         info->reg_id_isar1, boot->reg_id_isar1);
 707                 taint |= check_update_ftr_reg(SYS_ID_ISAR2_EL1, cpu,
 708                                         info->reg_id_isar2, boot->reg_id_isar2);
 709                 taint |= check_update_ftr_reg(SYS_ID_ISAR3_EL1, cpu,
 710                                         info->reg_id_isar3, boot->reg_id_isar3);
 711                 taint |= check_update_ftr_reg(SYS_ID_ISAR4_EL1, cpu,
 712                                         info->reg_id_isar4, boot->reg_id_isar4);
 713                 taint |= check_update_ftr_reg(SYS_ID_ISAR5_EL1, cpu,
 714                                         info->reg_id_isar5, boot->reg_id_isar5);
 715
 716                 /*
 717                  * Regardless of the value of the AuxReg field, the AIFSR, ADFSR, and
 718                  * ACTLR formats could differ across CPUs and therefore would have to
 719                  * be trapped for virtualization anyway.
 720                  */
 721                 taint |= check_update_ftr_reg(SYS_ID_MMFR0_EL1, cpu,
 722                                         info->reg_id_mmfr0, boot->reg_id_mmfr0);
 723                 taint |= check_update_ftr_reg(SYS_ID_MMFR1_EL1, cpu,
 724                                         info->reg_id_mmfr1, boot->reg_id_mmfr1);
 725                 taint |= check_update_ftr_reg(SYS_ID_MMFR2_EL1, cpu,
 726                                         info->reg_id_mmfr2, boot->reg_id_mmfr2);
 727                 taint |= check_update_ftr_reg(SYS_ID_MMFR3_EL1, cpu,
 728                                         info->reg_id_mmfr3, boot->reg_id_mmfr3);
 729                 taint |= check_update_ftr_reg(SYS_ID_PFR0_EL1, cpu,
 730                                         info->reg_id_pfr0, boot->reg_id_pfr0);
 731                 taint |= check_update_ftr_reg(SYS_ID_PFR1_EL1, cpu,
 732                                         info->reg_id_pfr1, boot->reg_id_pfr1);
 733                 taint |= check_update_ftr_reg(SYS_MVFR0_EL1, cpu,
 734                                         info->reg_mvfr0, boot->reg_mvfr0);
 735                 taint |= check_update_ftr_reg(SYS_MVFR1_EL1, cpu,
 736                                         info->reg_mvfr1, boot->reg_mvfr1);
 737                 taint |= check_update_ftr_reg(SYS_MVFR2_EL1, cpu,
 738                                         info->reg_mvfr2, boot->reg_mvfr2);
 739         }
 740
 741         if (id_aa64pfr0_sve(info->reg_id_aa64pfr0)) {
 742                 taint |= check_update_ftr_reg(SYS_ZCR_EL1, cpu,
 743                                         info->reg_zcr, boot->reg_zcr);
 744
 745                 /* Probe vector lengths, unless we already gave up on SVE */
 746                 if (id_aa64pfr0_sve(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1)) &&
 747                     !sys_caps_initialised)
 748                         sve_update_vq_map();
 749         }
 750
 751         /*
 752          * Mismatched CPU features are a recipe for disaster. Don't even
 753          * pretend to support them.
 754          */
 755         if (taint) {
 756                 pr_warn_once("Unsupported CPU feature variation detected.\n");
 757                 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK);
 758         }
 759 }
 760
 761 u64 read_sanitised_ftr_reg(u32 id)
 762 {
 763         struct arm64_ftr_reg *regp = get_arm64_ftr_reg(id);
 764
 765         /* We shouldn't get a request for an unsupported register */
 766         BUG_ON(!regp);
 767         return regp->sys_val;
 768 }
 769
 770 #define read_sysreg_case(r)     \
 771         case r:         return read_sysreg_s(r)
 772
 773 /*
 774  * __read_sysreg_by_encoding() - Used by a STARTING cpu before cpuinfo is populated.
 775  * Read the system register on the current CPU
 776  */
 777 static u64 __read_sysreg_by_encoding(u32 sys_id)
 778 {
 779         switch (sys_id) {
 780         read_sysreg_case(SYS_ID_PFR0_EL1);
 781         read_sysreg_case(SYS_ID_PFR1_EL1);
 782         read_sysreg_case(SYS_ID_DFR0_EL1);
 783         read_sysreg_case(SYS_ID_MMFR0_EL1);
 784         read_sysreg_case(SYS_ID_MMFR1_EL1);
 785         read_sysreg_case(SYS_ID_MMFR2_EL1);
 786         read_sysreg_case(SYS_ID_MMFR3_EL1);
 787         read_sysreg_case(SYS_ID_ISAR0_EL1);
 788         read_sysreg_case(SYS_ID_ISAR1_EL1);
 789         read_sysreg_case(SYS_ID_ISAR2_EL1);
 790         read_sysreg_case(SYS_ID_ISAR3_EL1);
 791         read_sysreg_case(SYS_ID_ISAR4_EL1);
 792         read_sysreg_case(SYS_ID_ISAR5_EL1);
 793         read_sysreg_case(SYS_MVFR0_EL1);
 794         read_sysreg_case(SYS_MVFR1_EL1);
 795         read_sysreg_case(SYS_MVFR2_EL1);
 796
 797         read_sysreg_case(SYS_ID_AA64PFR0_EL1);
 798         read_sysreg_case(SYS_ID_AA64PFR1_EL1);
 799         read_sysreg_case(SYS_ID_AA64DFR0_EL1);
 800         read_sysreg_case(SYS_ID_AA64DFR1_EL1);
 801         read_sysreg_case(SYS_ID_AA64MMFR0_EL1);
 802         read_sysreg_case(SYS_ID_AA64MMFR1_EL1);
 803         read_sysreg_case(SYS_ID_AA64MMFR2_EL1);
 804         read_sysreg_case(SYS_ID_AA64ISAR0_EL1);
 805         read_sysreg_case(SYS_ID_AA64ISAR1_EL1);
 806         read_sysreg_case(SYS_ID_AA64ISAR2_EL1);
 807
 808         read_sysreg_case(SYS_CNTFRQ_EL0);
 809         read_sysreg_case(SYS_CTR_EL0);
 810         read_sysreg_case(SYS_DCZID_EL0);
 811
 812         default:
 813                 BUG();
 814                 return 0;
 815         }
 816 }
 817
 818 #include <linux/irqchip/arm-gic-v3.h>
 819
 820 static bool
 821 feature_matches(u64 reg, const struct arm64_cpu_capabilities *entry)
 822 {
 823         int val = cpuid_feature_extract_field(reg, entry->field_pos, entry->sign);
 824
 825         return val >= entry->min_field_value;
 826 }
 827
 828 static bool
 829 has_cpuid_feature(const struct arm64_cpu_capabilities *entry, int scope)
 830 {
 831         u64 val;
 832
 833         WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible());
 834         if (scope == SCOPE_SYSTEM)
 835                 val = read_sanitised_ftr_reg(entry->sys_reg);
 836         else
 837                 val = __read_sysreg_by_encoding(entry->sys_reg);
 838
 839         return feature_matches(val, entry);
 840 }
 841
 842 static bool has_useable_gicv3_cpuif(const struct arm64_cpu_capabilities *entry, int scope)
 843 {
 844         bool has_sre;
 845
 846         if (!has_cpuid_feature(entry, scope))
 847                 return false;
 848
 849         has_sre = gic_enable_sre();
 850         if (!has_sre)
 851                 pr_warn_once("%s present but disabled by higher exception level\n",
 852                              entry->desc);
 853
 854         return has_sre;
 855 }
 856
 857 static bool has_no_hw_prefetch(const struct arm64_cpu_capabilities *entry, int __unused)
 858 {
 859         u32 midr = read_cpuid_id();
 860
 861         /* Cavium ThunderX pass 1.x and 2.x */
 862         return midr_is_cpu_model_range(midr, MIDR_THUNDERX,
 863                 MIDR_CPU_VAR_REV(0, 0),
 864                 MIDR_CPU_VAR_REV(1, MIDR_REVISION_MASK));
 865 }
 866
 867 static bool has_no_fpsimd(const struct arm64_cpu_capabilities *entry, int __unused)
 868 {
 869         u64 pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1);
 870
 871         return cpuid_feature_extract_signed_field(pfr0,
 872                                         ID_AA64PFR0_FP_SHIFT) < 0;
 873 }
 874
 875 static bool has_cache_idc(const struct arm64_cpu_capabilities *entry,
 876                           int scope)
 877 {
 878         u64 ctr;
 879
 880         if (scope == SCOPE_SYSTEM)
 881                 ctr = arm64_ftr_reg_ctrel0.sys_val;
 882         else
 883                 ctr = read_cpuid_cachetype();
 884
 885         return ctr & BIT(CTR_IDC_SHIFT);
 886 }
 887
 888 static bool has_cache_dic(const struct arm64_cpu_capabilities *entry,
 889                           int scope)
 890 {
 891         u64 ctr;
 892
 893         if (scope == SCOPE_SYSTEM)
 894                 ctr = arm64_ftr_reg_ctrel0.sys_val;
 895         else
 896                 ctr = read_cpuid_cachetype();
 897
 898         return ctr & BIT(CTR_DIC_SHIFT);
 899 }
 900
 901 static bool __meltdown_safe = true;
 902 static int __kpti_forced; /* 0: not forced, >0: forced on, <0: forced off */
 903
 904 static bool unmap_kernel_at_el0(const struct arm64_cpu_capabilities *entry,
 905                                 int scope)
 906 {
 907         /* List of CPUs that are not vulnerable and don't need KPTI */
 908         static const struct midr_range kpti_safe_list[] = {
 909                 MIDR_ALL_VERSIONS(MIDR_CAVIUM_THUNDERX2),
 910                 MIDR_ALL_VERSIONS(MIDR_BRCM_VULCAN),
 911                 MIDR_ALL_VERSIONS(MIDR_CORTEX_A35),
 912                 MIDR_ALL_VERSIONS(MIDR_CORTEX_A53),
 913                 MIDR_ALL_VERSIONS(MIDR_CORTEX_A55),
 914                 MIDR_ALL_VERSIONS(MIDR_CORTEX_A57),
 915                 MIDR_ALL_VERSIONS(MIDR_CORTEX_A72),
 916                 MIDR_ALL_VERSIONS(MIDR_CORTEX_A73),
 917                 MIDR_ALL_VERSIONS(MIDR_HISI_TSV110),
 918                 { /* sentinel */ }
 919         };
 920         char const *str = "kpti command line option";
 921         bool meltdown_safe;
 922
 923         meltdown_safe = is_midr_in_range_list(read_cpuid_id(), kpti_safe_list);
 924
 925         /* Defer to CPU feature registers */
 926         if (has_cpuid_feature(entry, scope))
 927                 meltdown_safe = true;
 928
 929         if (!meltdown_safe)
 930                 __meltdown_safe = false;
 931
 932         /*
 933          * For reasons that aren't entirely clear, enabling KPTI on Cavium
 934          * ThunderX leads to apparent I-cache corruption of kernel text, which
 935          * ends as well as you might imagine. Don't even try.
 936          */
 937         if (cpus_have_const_cap(ARM64_WORKAROUND_CAVIUM_27456)) {
 938                 str = "ARM64_WORKAROUND_CAVIUM_27456";
 939                 __kpti_forced = -1;
 940         }
 941
 942         /* Useful for KASLR robustness */
 943         if (IS_ENABLED(CONFIG_RANDOMIZE_BASE) && kaslr_offset() > 0) {
 944                 if (!__kpti_forced) {
 945                         str = "KASLR";
 946                         __kpti_forced = 1;
 947                 }
 948         }
 949
 950         if (cpu_mitigations_off() && !__kpti_forced) {
 951                 str = "mitigations=off";
 952                 __kpti_forced = -1;
 953         }
 954
 955         if (!IS_ENABLED(CONFIG_UNMAP_KERNEL_AT_EL0)) {
 956                 pr_info_once("kernel page table isolation disabled by kernel configuration\n");
 957                 return false;
 958         }
 959
 960         /* Forced? */
 961         if (__kpti_forced) {
 962                 pr_info_once("kernel page table isolation forced %s by %s\n",
 963                              __kpti_forced > 0 ? "ON" : "OFF", str);
 964                 return __kpti_forced > 0;
 965         }
 966
 967         return !meltdown_safe;
 968 }
 969
 970 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0
 971 static void
 972 kpti_install_ng_mappings(const struct arm64_cpu_capabilities *__unused)
 973 {
 974         typedef void (kpti_remap_fn)(int, int, phys_addr_t);
 975         extern kpti_remap_fn idmap_kpti_install_ng_mappings;
 976         kpti_remap_fn *remap_fn;
 977
 978         static bool kpti_applied = false;
 979         int cpu = smp_processor_id();
 980
 981         if (__this_cpu_read(this_cpu_vector) == vectors) {
 982                 const char *v = arm64_get_bp_hardening_vector(EL1_VECTOR_KPTI);
 983
 984                 __this_cpu_write(this_cpu_vector, v);
 985         }
 986
 987         if (kpti_applied)
 988                 return;
 989
 990         remap_fn = (void *)__pa_symbol(idmap_kpti_install_ng_mappings);
 991
 992         cpu_install_idmap();
 993         remap_fn(cpu, num_online_cpus(), __pa_symbol(swapper_pg_dir));
 994         cpu_uninstall_idmap();
 995
 996         if (!cpu)
 997                 kpti_applied = true;
 998
 999         return;
1000 }
1001 #else
1002 static void
1003 kpti_install_ng_mappings(const struct arm64_cpu_capabilities *__unused)
1004 {
1005 }
1006 #endif  /* CONFIG_UNMAP_KERNEL_AT_EL0 */
1007
1008 static int __init parse_kpti(char *str)
1009 {
1010         bool enabled;
1011         int ret = strtobool(str, &enabled);
1012
1013         if (ret)
1014                 return ret;
1015
1016         __kpti_forced = enabled ? 1 : -1;
1017         return 0;
1018 }
1019 early_param("kpti", parse_kpti);
1020
1021 #ifdef CONFIG_ARM64_HW_AFDBM
1022 static inline void __cpu_enable_hw_dbm(void)
1023 {
1024         u64 tcr = read_sysreg(tcr_el1) | TCR_HD;
1025
1026         write_sysreg(tcr, tcr_el1);
1027         isb();
1028 }
1029
1030 static bool cpu_has_broken_dbm(void)
1031 {
1032         /* List of CPUs which have broken DBM support. */
1033         static const struct midr_range cpus[] = {
1034 #ifdef CONFIG_ARM64_ERRATUM_1024718
1035                 MIDR_ALL_VERSIONS(MIDR_CORTEX_A55),
1036 #endif
1037                 {},
1038         };
1039
1040         return is_midr_in_range_list(read_cpuid_id(), cpus);
1041 }
1042
1043 static bool cpu_can_use_dbm(const struct arm64_cpu_capabilities *cap)
1044 {
1045         return has_cpuid_feature(cap, SCOPE_LOCAL_CPU) &&
1046                !cpu_has_broken_dbm();
1047 }
1048
1049 static void cpu_enable_hw_dbm(struct arm64_cpu_capabilities const *cap)
1050 {
1051         if (cpu_can_use_dbm(cap))
1052                 __cpu_enable_hw_dbm();
1053 }
1054
1055 static bool has_hw_dbm(const struct arm64_cpu_capabilities *cap,
1056                        int __unused)
1057 {
1058         static bool detected = false;
1059         /*
1060          * DBM is a non-conflicting feature. i.e, the kernel can safely
1061          * run a mix of CPUs with and without the feature. So, we
1062          * unconditionally enable the capability to allow any late CPU
1063          * to use the feature. We only enable the control bits on the
1064          * CPU, if it actually supports.
1065          *
1066          * We have to make sure we print the "feature" detection only
1067          * when at least one CPU actually uses it. So check if this CPU
1068          * can actually use it and print the message exactly once.
1069          *
1070          * This is safe as all CPUs (including secondary CPUs - due to the
1071          * LOCAL_CPU scope - and the hotplugged CPUs - via verification)
1072          * goes through the "matches" check exactly once. Also if a CPU
1073          * matches the criteria, it is guaranteed that the CPU will turn
1074          * the DBM on, as the capability is unconditionally enabled.
1075          */
1076         if (!detected && cpu_can_use_dbm(cap)) {
1077                 detected = true;
1078                 pr_info("detected: Hardware dirty bit management\n");
1079         }
1080
1081         return true;
1082 }
1083
1084 #endif
1085
1086 #ifdef CONFIG_ARM64_VHE
1087 static bool runs_at_el2(const struct arm64_cpu_capabilities *entry, int __unused)
1088 {
1089         return is_kernel_in_hyp_mode();
1090 }
1091
1092 static void cpu_copy_el2regs(const struct arm64_cpu_capabilities *__unused)
1093 {
1094         /*
1095          * Copy register values that aren't redirected by hardware.
1096          *
1097          * Before code patching, we only set tpidr_el1, all CPUs need to copy
1098          * this value to tpidr_el2 before we patch the code. Once we've done
1099          * that, freshly-onlined CPUs will set tpidr_el2, so we don't need to
1100          * do anything here.
1101          */
1102         if (!alternatives_applied)
1103                 write_sysreg(read_sysreg(tpidr_el1), tpidr_el2);
1104 }
1105 #endif
1106
1107 static void cpu_has_fwb(const struct arm64_cpu_capabilities *__unused)
1108 {
1109         u64 val = read_sysreg_s(SYS_CLIDR_EL1);
1110
1111         /* Check that CLIDR_EL1.LOU{U,IS} are both 0 */
1112         WARN_ON(val & (7 << 27 | 7 << 21));
1113 }
1114
1115 #ifdef CONFIG_ARM64_SSBD
1116 static int ssbs_emulation_handler(struct pt_regs *regs, u32 instr)
1117 {
1118         if (user_mode(regs))
1119                 return 1;
1120
1121         if (instr & BIT(CRm_shift))
1122                 regs->pstate |= PSR_SSBS_BIT;
1123         else
1124                 regs->pstate &= ~PSR_SSBS_BIT;
1125
1126         arm64_skip_faulting_instruction(regs, 4);
1127         return 0;
1128 }
1129
1130 static struct undef_hook ssbs_emulation_hook = {
1131         .instr_mask     = ~(1U << CRm_shift),
1132         .instr_val      = 0xd500001f | REG_PSTATE_SSBS_IMM,
1133         .fn             = ssbs_emulation_handler,
1134 };
1135
1136 static void cpu_enable_ssbs(const struct arm64_cpu_capabilities *__unused)
1137 {
1138         static bool undef_hook_registered = false;
1139         static DEFINE_SPINLOCK(hook_lock);
1140
1141         spin_lock(&hook_lock);
1142         if (!undef_hook_registered) {
1143                 register_undef_hook(&ssbs_emulation_hook);
1144                 undef_hook_registered = true;
1145         }
1146         spin_unlock(&hook_lock);
1147
1148         if (arm64_get_ssbd_state() == ARM64_SSBD_FORCE_DISABLE) {
1149                 sysreg_clear_set(sctlr_el1, 0, SCTLR_ELx_DSSBS);
1150                 arm64_set_ssbd_mitigation(false);
1151         } else {
1152                 arm64_set_ssbd_mitigation(true);
1153         }
1154 }
1155 #endif /* CONFIG_ARM64_SSBD */
1156
1157 static const struct arm64_cpu_capabilities arm64_features[] = {
1158         {
1159                 .desc = "GIC system register CPU interface",
1160                 .capability = ARM64_HAS_SYSREG_GIC_CPUIF,
1161                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1162                 .matches = has_useable_gicv3_cpuif,
1163                 .sys_reg = SYS_ID_AA64PFR0_EL1,
1164                 .field_pos = ID_AA64PFR0_GIC_SHIFT,
1165                 .sign = FTR_UNSIGNED,
1166                 .min_field_value = 1,
1167         },
1168 #ifdef CONFIG_ARM64_PAN
1169         {
1170                 .desc = "Privileged Access Never",
1171                 .capability = ARM64_HAS_PAN,
1172                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1173                 .matches = has_cpuid_feature,
1174                 .sys_reg = SYS_ID_AA64MMFR1_EL1,
1175                 .field_pos = ID_AA64MMFR1_PAN_SHIFT,
1176                 .sign = FTR_UNSIGNED,
1177                 .min_field_value = 1,
1178                 .cpu_enable = cpu_enable_pan,
1179         },
1180 #endif /* CONFIG_ARM64_PAN */
1181 #if defined(CONFIG_AS_LSE) && defined(CONFIG_ARM64_LSE_ATOMICS)
1182         {
1183                 .desc = "LSE atomic instructions",
1184                 .capability = ARM64_HAS_LSE_ATOMICS,
1185                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1186                 .matches = has_cpuid_feature,
1187                 .sys_reg = SYS_ID_AA64ISAR0_EL1,
1188                 .field_pos = ID_AA64ISAR0_ATOMICS_SHIFT,
1189                 .sign = FTR_UNSIGNED,
1190                 .min_field_value = 2,
1191         },
1192 #endif /* CONFIG_AS_LSE && CONFIG_ARM64_LSE_ATOMICS */
1193         {
1194                 .desc = "Software prefetching using PRFM",
1195                 .capability = ARM64_HAS_NO_HW_PREFETCH,
1196                 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
1197                 .matches = has_no_hw_prefetch,
1198         },
1199 #ifdef CONFIG_ARM64_UAO
1200         {
1201                 .desc = "User Access Override",
1202                 .capability = ARM64_HAS_UAO,
1203                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1204                 .matches = has_cpuid_feature,
1205                 .sys_reg = SYS_ID_AA64MMFR2_EL1,
1206                 .field_pos = ID_AA64MMFR2_UAO_SHIFT,
1207                 .min_field_value = 1,
1208                 /*
1209                  * We rely on stop_machine() calling uao_thread_switch() to set
1210                  * UAO immediately after patching.
1211                  */
1212         },
1213 #endif /* CONFIG_ARM64_UAO */
1214 #ifdef CONFIG_ARM64_PAN
1215         {
1216                 .capability = ARM64_ALT_PAN_NOT_UAO,
1217                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1218                 .matches = cpufeature_pan_not_uao,
1219         },
1220 #endif /* CONFIG_ARM64_PAN */
1221 #ifdef CONFIG_ARM64_VHE
1222         {
1223                 .desc = "Virtualization Host Extensions",
1224                 .capability = ARM64_HAS_VIRT_HOST_EXTN,
1225                 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE,
1226                 .matches = runs_at_el2,
1227                 .cpu_enable = cpu_copy_el2regs,
1228         },
1229 #endif  /* CONFIG_ARM64_VHE */
1230         {
1231                 .desc = "32-bit EL0 Support",
1232                 .capability = ARM64_HAS_32BIT_EL0,
1233                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1234                 .matches = has_cpuid_feature,
1235                 .sys_reg = SYS_ID_AA64PFR0_EL1,
1236                 .sign = FTR_UNSIGNED,
1237                 .field_pos = ID_AA64PFR0_EL0_SHIFT,
1238                 .min_field_value = ID_AA64PFR0_EL0_32BIT_64BIT,
1239         },
1240         {
1241                 .desc = "Kernel page table isolation (KPTI)",
1242                 .capability = ARM64_UNMAP_KERNEL_AT_EL0,
1243                 .type = ARM64_CPUCAP_BOOT_RESTRICTED_CPU_LOCAL_FEATURE,
1244                 /*
1245                  * The ID feature fields below are used to indicate that
1246                  * the CPU doesn't need KPTI. See unmap_kernel_at_el0 for
1247                  * more details.
1248                  */
1249                 .sys_reg = SYS_ID_AA64PFR0_EL1,
1250                 .field_pos = ID_AA64PFR0_CSV3_SHIFT,
1251                 .min_field_value = 1,
1252                 .matches = unmap_kernel_at_el0,
1253                 .cpu_enable = kpti_install_ng_mappings,
1254         },
1255         {
1256                 /* FP/SIMD is not implemented */
1257                 .capability = ARM64_HAS_NO_FPSIMD,
1258                 .type = ARM64_CPUCAP_BOOT_RESTRICTED_CPU_LOCAL_FEATURE,
1259                 .min_field_value = 0,
1260                 .matches = has_no_fpsimd,
1261         },
1262 #ifdef CONFIG_ARM64_PMEM
1263         {
1264                 .desc = "Data cache clean to Point of Persistence",
1265                 .capability = ARM64_HAS_DCPOP,
1266                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1267                 .matches = has_cpuid_feature,
1268                 .sys_reg = SYS_ID_AA64ISAR1_EL1,
1269                 .field_pos = ID_AA64ISAR1_DPB_SHIFT,
1270                 .min_field_value = 1,
1271         },
1272 #endif
1273 #ifdef CONFIG_ARM64_SVE
1274         {
1275                 .desc = "Scalable Vector Extension",
1276                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1277                 .capability = ARM64_SVE,
1278                 .sys_reg = SYS_ID_AA64PFR0_EL1,
1279                 .sign = FTR_UNSIGNED,
1280                 .field_pos = ID_AA64PFR0_SVE_SHIFT,
1281                 .min_field_value = ID_AA64PFR0_SVE,
1282                 .matches = has_cpuid_feature,
1283                 .cpu_enable = sve_kernel_enable,
1284         },
1285 #endif /* CONFIG_ARM64_SVE */
1286 #ifdef CONFIG_ARM64_RAS_EXTN
1287         {
1288                 .desc = "RAS Extension Support",
1289                 .capability = ARM64_HAS_RAS_EXTN,
1290                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1291                 .matches = has_cpuid_feature,
1292                 .sys_reg = SYS_ID_AA64PFR0_EL1,
1293                 .sign = FTR_UNSIGNED,
1294                 .field_pos = ID_AA64PFR0_RAS_SHIFT,
1295                 .min_field_value = ID_AA64PFR0_RAS_V1,
1296                 .cpu_enable = cpu_clear_disr,
1297         },
1298 #endif /* CONFIG_ARM64_RAS_EXTN */
1299         {
1300                 .desc = "Data cache clean to the PoU not required for I/D coherence",
1301                 .capability = ARM64_HAS_CACHE_IDC,
1302                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1303                 .matches = has_cache_idc,
1304         },
1305         {
1306                 .desc = "Instruction cache invalidation not required for I/D coherence",
1307                 .capability = ARM64_HAS_CACHE_DIC,
1308                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1309                 .matches = has_cache_dic,
1310         },
1311         {
1312                 .desc = "Stage-2 Force Write-Back",
1313                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1314                 .capability = ARM64_HAS_STAGE2_FWB,
1315                 .sys_reg = SYS_ID_AA64MMFR2_EL1,
1316                 .sign = FTR_UNSIGNED,
1317                 .field_pos = ID_AA64MMFR2_FWB_SHIFT,
1318                 .min_field_value = 1,
1319                 .matches = has_cpuid_feature,
1320                 .cpu_enable = cpu_has_fwb,
1321         },
1322 #ifdef CONFIG_ARM64_HW_AFDBM
1323         {
1324                 /*
1325                  * Since we turn this on always, we don't want the user to
1326                  * think that the feature is available when it may not be.
1327                  * So hide the description.
1328                  *
1329                  * .desc = "Hardware pagetable Dirty Bit Management",
1330                  *
1331                  */
1332                 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
1333                 .capability = ARM64_HW_DBM,
1334                 .sys_reg = SYS_ID_AA64MMFR1_EL1,
1335                 .sign = FTR_UNSIGNED,
1336                 .field_pos = ID_AA64MMFR1_HADBS_SHIFT,
1337                 .min_field_value = 2,
1338                 .matches = has_hw_dbm,
1339                 .cpu_enable = cpu_enable_hw_dbm,
1340         },
1341 #endif
1342 #ifdef CONFIG_ARM64_SSBD
1343         {
1344                 .desc = "Speculative Store Bypassing Safe (SSBS)",
1345                 .capability = ARM64_SSBS,
1346                 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
1347                 .matches = has_cpuid_feature,
1348                 .sys_reg = SYS_ID_AA64PFR1_EL1,
1349                 .field_pos = ID_AA64PFR1_SSBS_SHIFT,
1350                 .sign = FTR_UNSIGNED,
1351                 .min_field_value = ID_AA64PFR1_SSBS_PSTATE_ONLY,
1352                 .cpu_enable = cpu_enable_ssbs,
1353         },
1354 #endif
1355         {},
1356 };
1357
1358
1359 #define HWCAP_CPUID_MATCH(reg, field, s, min_value)             \
1360                 .matches = has_cpuid_feature,                   \
1361                 .sys_reg = reg,                                 \
1362                 .field_pos = field,                             \
1363                 .sign = s,                                      \
1364                 .min_field_value = min_value,                   \
1365
1366 #define __HWCAP_CAP(name, cap_type, cap)                        \
1367                 .desc = name,                                   \
1368                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,            \
1369                 .hwcap_type = cap_type,                         \
1370                 .hwcap = cap,                                   \
1371
1372 #define HWCAP_CAP(reg, field, s, min_value, cap_type, cap)      \
1373         {                                                       \
1374                 __HWCAP_CAP(#cap, cap_type, cap)                \
1375                 HWCAP_CPUID_MATCH(reg, field, s, min_value)     \
1376         }
1377
1378 #define HWCAP_CAP_MATCH(match, cap_type, cap)                   \
1379         {                                                       \
1380                 __HWCAP_CAP(#cap, cap_type, cap)                \
1381                 .matches = match,                               \
1382         }
1383
1384 static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = {
1385         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, HWCAP_PMULL),
1386         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_AES),
1387         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA1_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_SHA1),
1388         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA2_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_SHA2),
1389         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA2_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, HWCAP_SHA512),
1390         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_CRC32_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_CRC32),
1391         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_ATOMICS_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, HWCAP_ATOMICS),
1392         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_RDM_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_ASIMDRDM),
1393         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA3_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_SHA3),
1394         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SM3_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_SM3),
1395         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SM4_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_SM4),
1396         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_DP_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_ASIMDDP),
1397         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_FHM_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_ASIMDFHM),
1398         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_TS_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_FLAGM),
1399         HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, FTR_SIGNED, 0, CAP_HWCAP, HWCAP_FP),
1400         HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, HWCAP_FPHP),
1401         HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, FTR_SIGNED, 0, CAP_HWCAP, HWCAP_ASIMD),
1402         HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, HWCAP_ASIMDHP),
1403         HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_DIT_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, HWCAP_DIT),
1404         HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_DPB_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_DCPOP),
1405         HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_JSCVT_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_JSCVT),
1406         HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_FCMA_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_FCMA),
1407         HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_LRCPC_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_LRCPC),
1408         HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_LRCPC_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, HWCAP_ILRCPC),
1409         HWCAP_CAP(SYS_ID_AA64MMFR2_EL1, ID_AA64MMFR2_AT_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_USCAT),
1410 #ifdef CONFIG_ARM64_SVE
1411         HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_SVE_SHIFT, FTR_UNSIGNED, ID_AA64PFR0_SVE, CAP_HWCAP, HWCAP_SVE),
1412 #endif
1413         HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_SSBS_SHIFT, FTR_UNSIGNED, ID_AA64PFR1_SSBS_PSTATE_INSNS, CAP_HWCAP, HWCAP_SSBS),
1414         {},
1415 };
1416
1417 #ifdef CONFIG_COMPAT
1418 static bool compat_has_neon(const struct arm64_cpu_capabilities *cap, int scope)
1419 {
1420         /*
1421          * Check that all of MVFR1_EL1.{SIMDSP, SIMDInt, SIMDLS} are available,
1422          * in line with that of arm32 as in vfp_init(). We make sure that the
1423          * check is future proof, by making sure value is non-zero.
1424          */
1425         u32 mvfr1;
1426
1427         WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible());
1428         if (scope == SCOPE_SYSTEM)
1429                 mvfr1 = read_sanitised_ftr_reg(SYS_MVFR1_EL1);
1430         else
1431                 mvfr1 = read_sysreg_s(SYS_MVFR1_EL1);
1432
1433         return cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_SIMDSP_SHIFT) &&
1434                 cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_SIMDINT_SHIFT) &&
1435                 cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_SIMDLS_SHIFT);
1436 }
1437 #endif
1438
1439 static const struct arm64_cpu_capabilities compat_elf_hwcaps[] = {
1440 #ifdef CONFIG_COMPAT
1441         HWCAP_CAP_MATCH(compat_has_neon, CAP_COMPAT_HWCAP, COMPAT_HWCAP_NEON),
1442         HWCAP_CAP(SYS_MVFR1_EL1, MVFR1_SIMDFMAC_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFPv4),
1443         /* Arm v8 mandates MVFR0.FPDP == {0, 2}. So, piggy back on this for the presence of VFP support */
1444         HWCAP_CAP(SYS_MVFR0_EL1, MVFR0_FPDP_SHIFT, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFP),
1445         HWCAP_CAP(SYS_MVFR0_EL1, MVFR0_FPDP_SHIFT, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFPv3),
1446         HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_PMULL),
1447         HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_AES),
1448         HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA1_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA1),
1449         HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA2_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA2),
1450         HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_CRC32_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_CRC32),
1451 #endif
1452         {},
1453 };
1454
1455 static void __init cap_set_elf_hwcap(const struct arm64_cpu_capabilities *cap)
1456 {
1457         switch (cap->hwcap_type) {
1458         case CAP_HWCAP:
1459                 elf_hwcap |= cap->hwcap;
1460                 break;
1461 #ifdef CONFIG_COMPAT
1462         case CAP_COMPAT_HWCAP:
1463                 compat_elf_hwcap |= (u32)cap->hwcap;
1464                 break;
1465         case CAP_COMPAT_HWCAP2:
1466                 compat_elf_hwcap2 |= (u32)cap->hwcap;
1467                 break;
1468 #endif
1469         default:
1470                 WARN_ON(1);
1471                 break;
1472         }
1473 }
1474
1475 /* Check if we have a particular HWCAP enabled */
1476 static bool cpus_have_elf_hwcap(const struct arm64_cpu_capabilities *cap)
1477 {
1478         bool rc;
1479
1480         switch (cap->hwcap_type) {
1481         case CAP_HWCAP:
1482                 rc = (elf_hwcap & cap->hwcap) != 0;
1483                 break;
1484 #ifdef CONFIG_COMPAT
1485         case CAP_COMPAT_HWCAP:
1486                 rc = (compat_elf_hwcap & (u32)cap->hwcap) != 0;
1487                 break;
1488         case CAP_COMPAT_HWCAP2:
1489                 rc = (compat_elf_hwcap2 & (u32)cap->hwcap) != 0;
1490                 break;
1491 #endif
1492         default:
1493                 WARN_ON(1);
1494                 rc = false;
1495         }
1496
1497         return rc;
1498 }
1499
1500 static void __init setup_elf_hwcaps(const struct arm64_cpu_capabilities *hwcaps)
1501 {
1502         /* We support emulation of accesses to CPU ID feature registers */
1503         elf_hwcap |= HWCAP_CPUID;
1504         for (; hwcaps->matches; hwcaps++)
1505                 if (hwcaps->matches(hwcaps, cpucap_default_scope(hwcaps)))
1506                         cap_set_elf_hwcap(hwcaps);
1507 }
1508
1509 /*
1510  * Check if the current CPU has a given feature capability.
1511  * Should be called from non-preemptible context.
1512  */
1513 static bool __this_cpu_has_cap(const struct arm64_cpu_capabilities *cap_array,
1514                                unsigned int cap)
1515 {
1516         const struct arm64_cpu_capabilities *caps;
1517
1518         if (WARN_ON(preemptible()))
1519                 return false;
1520
1521         for (caps = cap_array; caps->matches; caps++)
1522                 if (caps->capability == cap)
1523                         return caps->matches(caps, SCOPE_LOCAL_CPU);
1524
1525         return false;
1526 }
1527
1528 static void __update_cpu_capabilities(const struct arm64_cpu_capabilities *caps,
1529                                       u16 scope_mask, const char *info)
1530 {
1531         scope_mask &= ARM64_CPUCAP_SCOPE_MASK;
1532         for (; caps->matches; caps++) {
1533                 if (!(caps->type & scope_mask) ||
1534                     !caps->matches(caps, cpucap_default_scope(caps)))
1535                         continue;
1536
1537                 if (!cpus_have_cap(caps->capability) && caps->desc)
1538                         pr_info("%s %s\n", info, caps->desc);
1539                 cpus_set_cap(caps->capability);
1540         }
1541 }
1542
1543 static void update_cpu_capabilities(u16 scope_mask)
1544 {
1545         __update_cpu_capabilities(arm64_errata, scope_mask,
1546                                   "enabling workaround for");
1547         __update_cpu_capabilities(arm64_features, scope_mask, "detected:");
1548 }
1549
1550 static int __enable_cpu_capability(void *arg)
1551 {
1552         const struct arm64_cpu_capabilities *cap = arg;
1553
1554         cap->cpu_enable(cap);
1555         return 0;
1556 }
1557
1558 /*
1559  * Run through the enabled capabilities and enable() it on all active
1560  * CPUs
1561  */
1562 static void __init
1563 __enable_cpu_capabilities(const struct arm64_cpu_capabilities *caps,
1564                           u16 scope_mask)
1565 {
1566         scope_mask &= ARM64_CPUCAP_SCOPE_MASK;
1567         for (; caps->matches; caps++) {
1568                 unsigned int num = caps->capability;
1569
1570                 if (!(caps->type & scope_mask) || !cpus_have_cap(num))
1571                         continue;
1572
1573                 /* Ensure cpus_have_const_cap(num) works */
1574                 static_branch_enable(&cpu_hwcap_keys[num]);
1575
1576                 if (caps->cpu_enable) {
1577                         /*
1578                          * Capabilities with SCOPE_BOOT_CPU scope are finalised
1579                          * before any secondary CPU boots. Thus, each secondary
1580                          * will enable the capability as appropriate via
1581                          * check_local_cpu_capabilities(). The only exception is
1582                          * the boot CPU, for which the capability must be
1583                          * enabled here. This approach avoids costly
1584                          * stop_machine() calls for this case.
1585                          *
1586                          * Otherwise, use stop_machine() as it schedules the
1587                          * work allowing us to modify PSTATE, instead of
1588                          * on_each_cpu() which uses an IPI, giving us a PSTATE
1589                          * that disappears when we return.
1590                          */
1591                         if (scope_mask & SCOPE_BOOT_CPU)
1592                                 caps->cpu_enable(caps);
1593                         else
1594                                 stop_machine(__enable_cpu_capability,
1595                                              (void *)caps, cpu_online_mask);
1596                 }
1597         }
1598 }
1599
1600 static void __init enable_cpu_capabilities(u16 scope_mask)
1601 {
1602         __enable_cpu_capabilities(arm64_errata, scope_mask);
1603         __enable_cpu_capabilities(arm64_features, scope_mask);
1604 }
1605
1606 /*
1607  * Run through the list of capabilities to check for conflicts.
1608  * If the system has already detected a capability, take necessary
1609  * action on this CPU.
1610  *
1611  * Returns "false" on conflicts.
1612  */
1613 static bool
1614 __verify_local_cpu_caps(const struct arm64_cpu_capabilities *caps,
1615                         u16 scope_mask)
1616 {
1617         bool cpu_has_cap, system_has_cap;
1618
1619         scope_mask &= ARM64_CPUCAP_SCOPE_MASK;
1620
1621         for (; caps->matches; caps++) {
1622                 if (!(caps->type & scope_mask))
1623                         continue;
1624
1625                 cpu_has_cap = caps->matches(caps, SCOPE_LOCAL_CPU);
1626                 system_has_cap = cpus_have_cap(caps->capability);
1627
1628                 if (system_has_cap) {
1629                         /*
1630                          * Check if the new CPU misses an advertised feature,
1631                          * which is not safe to miss.
1632                          */
1633                         if (!cpu_has_cap && !cpucap_late_cpu_optional(caps))
1634                                 break;
1635                         /*
1636                          * We have to issue cpu_enable() irrespective of
1637                          * whether the CPU has it or not, as it is enabeld
1638                          * system wide. It is upto the call back to take
1639                          * appropriate action on this CPU.
1640                          */
1641                         if (caps->cpu_enable)
1642                                 caps->cpu_enable(caps);
1643                 } else {
1644                         /*
1645                          * Check if the CPU has this capability if it isn't
1646                          * safe to have when the system doesn't.
1647                          */
1648                         if (cpu_has_cap && !cpucap_late_cpu_permitted(caps))
1649                                 break;
1650                 }
1651         }
1652
1653         if (caps->matches) {
1654                 pr_crit("CPU%d: Detected conflict for capability %d (%s), System: %d, CPU: %d\n",
1655                         smp_processor_id(), caps->capability,
1656                         caps->desc, system_has_cap, cpu_has_cap);
1657                 return false;
1658         }
1659
1660         return true;
1661 }
1662
1663 static bool verify_local_cpu_caps(u16 scope_mask)
1664 {
1665         return __verify_local_cpu_caps(arm64_errata, scope_mask) &&
1666                __verify_local_cpu_caps(arm64_features, scope_mask);
1667 }
1668
1669 /*
1670  * Check for CPU features that are used in early boot
1671  * based on the Boot CPU value.
1672  */
1673 static void check_early_cpu_features(void)
1674 {
1675         verify_cpu_asid_bits();
1676         /*
1677          * Early features are used by the kernel already. If there
1678          * is a conflict, we cannot proceed further.
1679          */
1680         if (!verify_local_cpu_caps(SCOPE_BOOT_CPU))
1681                 cpu_panic_kernel();
1682 }
1683
1684 static void
1685 verify_local_elf_hwcaps(const struct arm64_cpu_capabilities *caps)
1686 {
1687
1688         for (; caps->matches; caps++)
1689                 if (cpus_have_elf_hwcap(caps) && !caps->matches(caps, SCOPE_LOCAL_CPU)) {
1690                         pr_crit("CPU%d: missing HWCAP: %s\n",
1691                                         smp_processor_id(), caps->desc);
1692                         cpu_die_early();
1693                 }
1694 }
1695
1696 static void verify_sve_features(void)
1697 {
1698         u64 safe_zcr = read_sanitised_ftr_reg(SYS_ZCR_EL1);
1699         u64 zcr = read_zcr_features();
1700
1701         unsigned int safe_len = safe_zcr & ZCR_ELx_LEN_MASK;
1702         unsigned int len = zcr & ZCR_ELx_LEN_MASK;
1703
1704         if (len < safe_len || sve_verify_vq_map()) {
1705                 pr_crit("CPU%d: SVE: required vector length(s) missing\n",
1706                         smp_processor_id());
1707                 cpu_die_early();
1708         }
1709
1710         /* Add checks on other ZCR bits here if necessary */
1711 }
1712
1713
1714 /*
1715  * Run through the enabled system capabilities and enable() it on this CPU.
1716  * The capabilities were decided based on the available CPUs at the boot time.
1717  * Any new CPU should match the system wide status of the capability. If the
1718  * new CPU doesn't have a capability which the system now has enabled, we
1719  * cannot do anything to fix it up and could cause unexpected failures. So
1720  * we park the CPU.
1721  */
1722 static void verify_local_cpu_capabilities(void)
1723 {
1724         /*
1725          * The capabilities with SCOPE_BOOT_CPU are checked from
1726          * check_early_cpu_features(), as they need to be verified
1727          * on all secondary CPUs.
1728          */
1729         if (!verify_local_cpu_caps(SCOPE_ALL & ~SCOPE_BOOT_CPU))
1730                 cpu_die_early();
1731
1732         verify_local_elf_hwcaps(arm64_elf_hwcaps);
1733
1734         if (system_supports_32bit_el0())
1735                 verify_local_elf_hwcaps(compat_elf_hwcaps);
1736
1737         if (system_supports_sve())
1738                 verify_sve_features();
1739 }
1740
1741 void check_local_cpu_capabilities(void)
1742 {
1743         /*
1744          * All secondary CPUs should conform to the early CPU features
1745          * in use by the kernel based on boot CPU.
1746          */
1747         check_early_cpu_features();
1748
1749         /*
1750          * If we haven't finalised the system capabilities, this CPU gets
1751          * a chance to update the errata work arounds and local features.
1752          * Otherwise, this CPU should verify that it has all the system
1753          * advertised capabilities.
1754          */
1755         if (!sys_caps_initialised)
1756                 update_cpu_capabilities(SCOPE_LOCAL_CPU);
1757         else
1758                 verify_local_cpu_capabilities();
1759 }
1760
1761 static void __init setup_boot_cpu_capabilities(void)
1762 {
1763         /* Detect capabilities with either SCOPE_BOOT_CPU or SCOPE_LOCAL_CPU */
1764         update_cpu_capabilities(SCOPE_BOOT_CPU | SCOPE_LOCAL_CPU);
1765         /* Enable the SCOPE_BOOT_CPU capabilities alone right away */
1766         enable_cpu_capabilities(SCOPE_BOOT_CPU);
1767 }
1768
1769 DEFINE_STATIC_KEY_FALSE(arm64_const_caps_ready);
1770 EXPORT_SYMBOL(arm64_const_caps_ready);
1771
1772 static void __init mark_const_caps_ready(void)
1773 {
1774         static_branch_enable(&arm64_const_caps_ready);
1775 }
1776
1777 extern const struct arm64_cpu_capabilities arm64_errata[];
1778
1779 bool this_cpu_has_cap(unsigned int cap)
1780 {
1781         return (__this_cpu_has_cap(arm64_features, cap) ||
1782                 __this_cpu_has_cap(arm64_errata, cap));
1783 }
1784
1785 static void __init setup_system_capabilities(void)
1786 {
1787         /*
1788          * We have finalised the system-wide safe feature
1789          * registers, finalise the capabilities that depend
1790          * on it. Also enable all the available capabilities,
1791          * that are not enabled already.
1792          */
1793         update_cpu_capabilities(SCOPE_SYSTEM);
1794         enable_cpu_capabilities(SCOPE_ALL & ~SCOPE_BOOT_CPU);
1795 }
1796
1797 void __init setup_cpu_features(void)
1798 {
1799         u32 cwg;
1800
1801         setup_system_capabilities();
1802         mark_const_caps_ready();
1803         setup_elf_hwcaps(arm64_elf_hwcaps);
1804
1805         if (system_supports_32bit_el0())
1806                 setup_elf_hwcaps(compat_elf_hwcaps);
1807
1808         if (system_uses_ttbr0_pan())
1809                 pr_info("emulated: Privileged Access Never (PAN) using TTBR0_EL1 switching\n");
1810
1811         sve_setup();
1812         minsigstksz_setup();
1813
1814         /* Advertise that we have computed the system capabilities */
1815         set_sys_caps_initialised();
1816
1817         /*
1818          * Check for sane CTR_EL0.CWG value.
1819          */
1820         cwg = cache_type_cwg();
1821         if (!cwg)
1822                 pr_warn("No Cache Writeback Granule information, assuming %d\n",
1823                         ARCH_DMA_MINALIGN);
1824 }
1825
1826 static bool __maybe_unused
1827 cpufeature_pan_not_uao(const struct arm64_cpu_capabilities *entry, int __unused)
1828 {
1829         return (cpus_have_const_cap(ARM64_HAS_PAN) && !cpus_have_const_cap(ARM64_HAS_UAO));
1830 }
1831
1832 /*
1833  * We emulate only the following system register space.
1834  * Op0 = 0x3, CRn = 0x0, Op1 = 0x0, CRm = [0, 4 - 7]
1835  * See Table C5-6 System instruction encodings for System register accesses,
1836  * ARMv8 ARM(ARM DDI 0487A.f) for more details.
1837  */
1838 static inline bool __attribute_const__ is_emulated(u32 id)
1839 {
1840         return (sys_reg_Op0(id) == 0x3 &&
1841                 sys_reg_CRn(id) == 0x0 &&
1842                 sys_reg_Op1(id) == 0x0 &&
1843                 (sys_reg_CRm(id) == 0 ||
1844                  ((sys_reg_CRm(id) >= 4) && (sys_reg_CRm(id) <= 7))));
1845 }
1846
1847 /*
1848  * With CRm == 0, reg should be one of :
1849  * MIDR_EL1, MPIDR_EL1 or REVIDR_EL1.
1850  */
1851 static inline int emulate_id_reg(u32 id, u64 *valp)
1852 {
1853         switch (id) {
1854         case SYS_MIDR_EL1:
1855                 *valp = read_cpuid_id();
1856                 break;
1857         case SYS_MPIDR_EL1:
1858                 *valp = SYS_MPIDR_SAFE_VAL;
1859                 break;
1860         case SYS_REVIDR_EL1:
1861                 /* IMPLEMENTATION DEFINED values are emulated with 0 */
1862                 *valp = 0;
1863                 break;
1864         default:
1865                 return -EINVAL;
1866         }
1867
1868         return 0;
1869 }
1870
1871 static int emulate_sys_reg(u32 id, u64 *valp)
1872 {
1873         struct arm64_ftr_reg *regp;
1874
1875         if (!is_emulated(id))
1876                 return -EINVAL;
1877
1878         if (sys_reg_CRm(id) == 0)
1879                 return emulate_id_reg(id, valp);
1880
1881         regp = get_arm64_ftr_reg(id);
1882         if (regp)
1883                 *valp = arm64_ftr_reg_user_value(regp);
1884         else
1885                 /*
1886                  * The untracked registers are either IMPLEMENTATION DEFINED
1887                  * (e.g, ID_AFR0_EL1) or reserved RAZ.
1888                  */
1889                 *valp = 0;
1890         return 0;
1891 }
1892
1893 static int emulate_mrs(struct pt_regs *regs, u32 insn)
1894 {
1895         int rc;
1896         u32 sys_reg, dst;
1897         u64 val;
1898
1899         /*
1900          * sys_reg values are defined as used in mrs/msr instruction.
1901          * shift the imm value to get the encoding.
1902          */
1903         sys_reg = (u32)aarch64_insn_decode_immediate(AARCH64_INSN_IMM_16, insn) << 5;
1904         rc = emulate_sys_reg(sys_reg, &val);
1905         if (!rc) {
1906                 dst = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RT, insn);
1907                 pt_regs_write_reg(regs, dst, val);
1908                 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE);
1909         }
1910
1911         return rc;
1912 }
1913
1914 static struct undef_hook mrs_hook = {
1915         .instr_mask = 0xfff00000,
1916         .instr_val  = 0xd5300000,
1917         .pstate_mask = PSR_AA32_MODE_MASK,
1918         .pstate_val = PSR_MODE_EL0t,
1919         .fn = emulate_mrs,
1920 };
1921
1922 static int __init enable_mrs_emulation(void)
1923 {
1924         register_undef_hook(&mrs_hook);
1925         return 0;
1926 }
1927
1928 core_initcall(enable_mrs_emulation);
1929
1930 void cpu_clear_disr(const struct arm64_cpu_capabilities *__unused)
1931 {
1932         /* Firmware may have left a deferred SError in this register. */
1933         write_sysreg_s(0, SYS_DISR_EL1);
1934 }
1935
1936 ssize_t cpu_show_meltdown(struct device *dev, struct device_attribute *attr,
1937                           char *buf)
1938 {
1939         if (__meltdown_safe)
1940                 return sprintf(buf, "Not affected\n");
1941
1942         if (arm64_kernel_unmapped_at_el0())
1943                 return sprintf(buf, "Mitigation: PTI\n");
1944
1945         return sprintf(buf, "Vulnerable\n");
1946 }