arch/arm64/kernel/cpu_errata.c

   1 /*
   2  * Contains CPU specific errata definitions
   3  *
   4  * Copyright (C) 2014 ARM Ltd.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  17  */
  18
  19 #include <linux/arm-smccc.h>
  20 #include <linux/psci.h>
  21 #include <linux/types.h>
  22 #include <linux/cpu.h>
  23 #include <asm/cpu.h>
  24 #include <asm/cputype.h>
  25 #include <asm/cpufeature.h>
  26 #include <asm/smp_plat.h>
  27
  28 static bool __maybe_unused
  29 is_affected_midr_range(const struct arm64_cpu_capabilities *entry, int scope)
  30 {
  31         const struct arm64_midr_revidr *fix;
  32         u32 midr = read_cpuid_id(), revidr;
  33
  34         WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible());
  35         if (!is_midr_in_range(midr, &entry->midr_range))
  36                 return false;
  37
  38         midr &= MIDR_REVISION_MASK | MIDR_VARIANT_MASK;
  39         revidr = read_cpuid(REVIDR_EL1);
  40         for (fix = entry->fixed_revs; fix && fix->revidr_mask; fix++)
  41                 if (midr == fix->midr_rv && (revidr & fix->revidr_mask))
  42                         return false;
  43
  44         return true;
  45 }
  46
  47 static bool __maybe_unused
  48 is_affected_midr_range_list(const struct arm64_cpu_capabilities *entry,
  49                             int scope)
  50 {
  51         WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible());
  52         return is_midr_in_range_list(read_cpuid_id(), entry->midr_range_list);
  53 }
  54
  55 static bool __maybe_unused
  56 is_kryo_midr(const struct arm64_cpu_capabilities *entry, int scope)
  57 {
  58         u32 model;
  59
  60         WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible());
  61
  62         model = read_cpuid_id();
  63         model &= MIDR_IMPLEMENTOR_MASK | (0xf00 << MIDR_PARTNUM_SHIFT) |
  64                  MIDR_ARCHITECTURE_MASK;
  65
  66         return model == entry->midr_range.model;
  67 }
  68
  69 static bool
  70 has_mismatched_cache_type(const struct arm64_cpu_capabilities *entry,
  71                           int scope)
  72 {
  73         u64 mask = CTR_CACHE_MINLINE_MASK;
  74
  75         /* Skip matching the min line sizes for cache type check */
  76         if (entry->capability == ARM64_MISMATCHED_CACHE_TYPE)
  77                 mask ^= arm64_ftr_reg_ctrel0.strict_mask;
  78
  79         WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible());
  80         return (read_cpuid_cachetype() & mask) !=
  81                (arm64_ftr_reg_ctrel0.sys_val & mask);
  82 }
  83
  84 static void
  85 cpu_enable_trap_ctr_access(const struct arm64_cpu_capabilities *__unused)
  86 {
  87         sysreg_clear_set(sctlr_el1, SCTLR_EL1_UCT, 0);
  88 }
  89
  90 atomic_t arm64_el2_vector_last_slot = ATOMIC_INIT(-1);
  91
  92 #include <asm/mmu_context.h>
  93 #include <asm/cacheflush.h>
  94
  95 DEFINE_PER_CPU_READ_MOSTLY(struct bp_hardening_data, bp_hardening_data);
  96
  97 #ifdef CONFIG_KVM_INDIRECT_VECTORS
  98 extern char __smccc_workaround_1_smc_start[];
  99 extern char __smccc_workaround_1_smc_end[];
 100
 101 static void __copy_hyp_vect_bpi(int slot, const char *hyp_vecs_start,
 102                                 const char *hyp_vecs_end)
 103 {
 104         void *dst = lm_alias(__bp_harden_hyp_vecs_start + slot * SZ_2K);
 105         int i;
 106
 107         for (i = 0; i < SZ_2K; i += 0x80)
 108                 memcpy(dst + i, hyp_vecs_start, hyp_vecs_end - hyp_vecs_start);
 109
 110         __flush_icache_range((uintptr_t)dst, (uintptr_t)dst + SZ_2K);
 111 }
 112
 113 static void install_bp_hardening_cb(bp_hardening_cb_t fn,
 114                                     const char *hyp_vecs_start,
 115                                     const char *hyp_vecs_end)
 116 {
 117         static DEFINE_SPINLOCK(bp_lock);
 118         int cpu, slot = -1;
 119
 120         spin_lock(&bp_lock);
 121         for_each_possible_cpu(cpu) {
 122                 if (per_cpu(bp_hardening_data.fn, cpu) == fn) {
 123                         slot = per_cpu(bp_hardening_data.hyp_vectors_slot, cpu);
 124                         break;
 125                 }
 126         }
 127
 128         if (slot == -1) {
 129                 slot = atomic_inc_return(&arm64_el2_vector_last_slot);
 130                 BUG_ON(slot >= BP_HARDEN_EL2_SLOTS);
 131                 __copy_hyp_vect_bpi(slot, hyp_vecs_start, hyp_vecs_end);
 132         }
 133
 134         __this_cpu_write(bp_hardening_data.hyp_vectors_slot, slot);
 135         __this_cpu_write(bp_hardening_data.fn, fn);
 136         spin_unlock(&bp_lock);
 137 }
 138 #else
 139 #define __smccc_workaround_1_smc_start          NULL
 140 #define __smccc_workaround_1_smc_end            NULL
 141
 142 static void install_bp_hardening_cb(bp_hardening_cb_t fn,
 143                                       const char *hyp_vecs_start,
 144                                       const char *hyp_vecs_end)
 145 {
 146         __this_cpu_write(bp_hardening_data.fn, fn);
 147 }
 148 #endif  /* CONFIG_KVM_INDIRECT_VECTORS */
 149
 150 #include <uapi/linux/psci.h>
 151 #include <linux/arm-smccc.h>
 152 #include <linux/psci.h>
 153
 154 static void call_smc_arch_workaround_1(void)
 155 {
 156         arm_smccc_1_1_smc(ARM_SMCCC_ARCH_WORKAROUND_1, NULL);
 157 }
 158
 159 static void call_hvc_arch_workaround_1(void)
 160 {
 161         arm_smccc_1_1_hvc(ARM_SMCCC_ARCH_WORKAROUND_1, NULL);
 162 }
 163
 164 static void qcom_link_stack_sanitization(void)
 165 {
 166         u64 tmp;
 167
 168         asm volatile("mov       %0, x30         \n"
 169                      ".rept     16              \n"
 170                      "bl        . + 4           \n"
 171                      ".endr                     \n"
 172                      "mov       x30, %0         \n"
 173                      : "=&r" (tmp));
 174 }
 175
 176 static bool __nospectre_v2;
 177 static int __init parse_nospectre_v2(char *str)
 178 {
 179         __nospectre_v2 = true;
 180         return 0;
 181 }
 182 early_param("nospectre_v2", parse_nospectre_v2);
 183
 184 /*
 185  * -1: No workaround
 186  *  0: No workaround required
 187  *  1: Workaround installed
 188  */
 189 static int detect_harden_bp_fw(void)
 190 {
 191         bp_hardening_cb_t cb;
 192         void *smccc_start, *smccc_end;
 193         struct arm_smccc_res res;
 194         u32 midr = read_cpuid_id();
 195
 196         if (psci_ops.smccc_version == SMCCC_VERSION_1_0)
 197                 return -1;
 198
 199         switch (psci_ops.conduit) {
 200         case PSCI_CONDUIT_HVC:
 201                 arm_smccc_1_1_hvc(ARM_SMCCC_ARCH_FEATURES_FUNC_ID,
 202                                   ARM_SMCCC_ARCH_WORKAROUND_1, &res);
 203                 switch ((int)res.a0) {
 204                 case 1:
 205                         /* Firmware says we're just fine */
 206                         return 0;
 207                 case 0:
 208                         cb = call_hvc_arch_workaround_1;
 209                         /* This is a guest, no need to patch KVM vectors */
 210                         smccc_start = NULL;
 211                         smccc_end = NULL;
 212                         break;
 213                 default:
 214                         return -1;
 215                 }
 216                 break;
 217
 218         case PSCI_CONDUIT_SMC:
 219                 arm_smccc_1_1_smc(ARM_SMCCC_ARCH_FEATURES_FUNC_ID,
 220                                   ARM_SMCCC_ARCH_WORKAROUND_1, &res);
 221                 switch ((int)res.a0) {
 222                 case 1:
 223                         /* Firmware says we're just fine */
 224                         return 0;
 225                 case 0:
 226                         cb = call_smc_arch_workaround_1;
 227                         smccc_start = __smccc_workaround_1_smc_start;
 228                         smccc_end = __smccc_workaround_1_smc_end;
 229                         break;
 230                 default:
 231                         return -1;
 232                 }
 233                 break;
 234
 235         default:
 236                 return -1;
 237         }
 238
 239         if (((midr & MIDR_CPU_MODEL_MASK) == MIDR_QCOM_FALKOR) ||
 240             ((midr & MIDR_CPU_MODEL_MASK) == MIDR_QCOM_FALKOR_V1))
 241                 cb = qcom_link_stack_sanitization;
 242
 243         if (IS_ENABLED(CONFIG_HARDEN_BRANCH_PREDICTOR))
 244                 install_bp_hardening_cb(cb, smccc_start, smccc_end);
 245
 246         return 1;
 247 }
 248
 249 DEFINE_PER_CPU_READ_MOSTLY(u64, arm64_ssbd_callback_required);
 250
 251 int ssbd_state __read_mostly = ARM64_SSBD_KERNEL;
 252 static bool __ssb_safe = true;
 253
 254 static const struct ssbd_options {
 255         const char      *str;
 256         int             state;
 257 } ssbd_options[] = {
 258         { "force-on",   ARM64_SSBD_FORCE_ENABLE, },
 259         { "force-off",  ARM64_SSBD_FORCE_DISABLE, },
 260         { "kernel",     ARM64_SSBD_KERNEL, },
 261 };
 262
 263 static int __init ssbd_cfg(char *buf)
 264 {
 265         int i;
 266
 267         if (!buf || !buf[0])
 268                 return -EINVAL;
 269
 270         for (i = 0; i < ARRAY_SIZE(ssbd_options); i++) {
 271                 int len = strlen(ssbd_options[i].str);
 272
 273                 if (strncmp(buf, ssbd_options[i].str, len))
 274                         continue;
 275
 276                 ssbd_state = ssbd_options[i].state;
 277                 return 0;
 278         }
 279
 280         return -EINVAL;
 281 }
 282 early_param("ssbd", ssbd_cfg);
 283
 284 void __init arm64_update_smccc_conduit(struct alt_instr *alt,
 285                                        __le32 *origptr, __le32 *updptr,
 286                                        int nr_inst)
 287 {
 288         u32 insn;
 289
 290         BUG_ON(nr_inst != 1);
 291
 292         switch (psci_ops.conduit) {
 293         case PSCI_CONDUIT_HVC:
 294                 insn = aarch64_insn_get_hvc_value();
 295                 break;
 296         case PSCI_CONDUIT_SMC:
 297                 insn = aarch64_insn_get_smc_value();
 298                 break;
 299         default:
 300                 return;
 301         }
 302
 303         *updptr = cpu_to_le32(insn);
 304 }
 305
 306 void __init arm64_enable_wa2_handling(struct alt_instr *alt,
 307                                       __le32 *origptr, __le32 *updptr,
 308                                       int nr_inst)
 309 {
 310         BUG_ON(nr_inst != 1);
 311         /*
 312          * Only allow mitigation on EL1 entry/exit and guest
 313          * ARCH_WORKAROUND_2 handling if the SSBD state allows it to
 314          * be flipped.
 315          */
 316         if (arm64_get_ssbd_state() == ARM64_SSBD_KERNEL)
 317                 *updptr = cpu_to_le32(aarch64_insn_gen_nop());
 318 }
 319
 320 void arm64_set_ssbd_mitigation(bool state)
 321 {
 322         if (!IS_ENABLED(CONFIG_ARM64_SSBD)) {
 323                 pr_info_once("SSBD disabled by kernel configuration\n");
 324                 return;
 325         }
 326
 327         if (this_cpu_has_cap(ARM64_SSBS)) {
 328                 if (state)
 329                         asm volatile(SET_PSTATE_SSBS(0));
 330                 else
 331                         asm volatile(SET_PSTATE_SSBS(1));
 332                 return;
 333         }
 334
 335         switch (psci_ops.conduit) {
 336         case PSCI_CONDUIT_HVC:
 337                 arm_smccc_1_1_hvc(ARM_SMCCC_ARCH_WORKAROUND_2, state, NULL);
 338                 break;
 339
 340         case PSCI_CONDUIT_SMC:
 341                 arm_smccc_1_1_smc(ARM_SMCCC_ARCH_WORKAROUND_2, state, NULL);
 342                 break;
 343
 344         default:
 345                 WARN_ON_ONCE(1);
 346                 break;
 347         }
 348 }
 349
 350 static bool has_ssbd_mitigation(const struct arm64_cpu_capabilities *entry,
 351                                     int scope)
 352 {
 353         struct arm_smccc_res res;
 354         bool required = true;
 355         s32 val;
 356         bool this_cpu_safe = false;
 357
 358         WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible());
 359
 360         if (cpu_mitigations_off())
 361                 ssbd_state = ARM64_SSBD_FORCE_DISABLE;
 362
 363         /* delay setting __ssb_safe until we get a firmware response */
 364         if (is_midr_in_range_list(read_cpuid_id(), entry->midr_range_list))
 365                 this_cpu_safe = true;
 366
 367         if (this_cpu_has_cap(ARM64_SSBS)) {
 368                 if (!this_cpu_safe)
 369                         __ssb_safe = false;
 370                 required = false;
 371                 goto out_printmsg;
 372         }
 373
 374         if (psci_ops.smccc_version == SMCCC_VERSION_1_0) {
 375                 ssbd_state = ARM64_SSBD_UNKNOWN;
 376                 if (!this_cpu_safe)
 377                         __ssb_safe = false;
 378                 return false;
 379         }
 380
 381         switch (psci_ops.conduit) {
 382         case PSCI_CONDUIT_HVC:
 383                 arm_smccc_1_1_hvc(ARM_SMCCC_ARCH_FEATURES_FUNC_ID,
 384                                   ARM_SMCCC_ARCH_WORKAROUND_2, &res);
 385                 break;
 386
 387         case PSCI_CONDUIT_SMC:
 388                 arm_smccc_1_1_smc(ARM_SMCCC_ARCH_FEATURES_FUNC_ID,
 389                                   ARM_SMCCC_ARCH_WORKAROUND_2, &res);
 390                 break;
 391
 392         default:
 393                 ssbd_state = ARM64_SSBD_UNKNOWN;
 394                 if (!this_cpu_safe)
 395                         __ssb_safe = false;
 396                 return false;
 397         }
 398
 399         val = (s32)res.a0;
 400
 401         switch (val) {
 402         case SMCCC_RET_NOT_SUPPORTED:
 403                 ssbd_state = ARM64_SSBD_UNKNOWN;
 404                 if (!this_cpu_safe)
 405                         __ssb_safe = false;
 406                 return false;
 407
 408         /* machines with mixed mitigation requirements must not return this */
 409         case SMCCC_RET_NOT_REQUIRED:
 410                 pr_info_once("%s mitigation not required\n", entry->desc);
 411                 ssbd_state = ARM64_SSBD_MITIGATED;
 412                 return false;
 413
 414         case SMCCC_RET_SUCCESS:
 415                 __ssb_safe = false;
 416                 required = true;
 417                 break;
 418
 419         case 1: /* Mitigation not required on this CPU */
 420                 required = false;
 421                 break;
 422
 423         default:
 424                 WARN_ON(1);
 425                 if (!this_cpu_safe)
 426                         __ssb_safe = false;
 427                 return false;
 428         }
 429
 430         switch (ssbd_state) {
 431         case ARM64_SSBD_FORCE_DISABLE:
 432                 arm64_set_ssbd_mitigation(false);
 433                 required = false;
 434                 break;
 435
 436         case ARM64_SSBD_KERNEL:
 437                 if (required) {
 438                         __this_cpu_write(arm64_ssbd_callback_required, 1);
 439                         arm64_set_ssbd_mitigation(true);
 440                 }
 441                 break;
 442
 443         case ARM64_SSBD_FORCE_ENABLE:
 444                 arm64_set_ssbd_mitigation(true);
 445                 required = true;
 446                 break;
 447
 448         default:
 449                 WARN_ON(1);
 450                 break;
 451         }
 452
 453 out_printmsg:
 454         switch (ssbd_state) {
 455         case ARM64_SSBD_FORCE_DISABLE:
 456                 pr_info_once("%s disabled from command-line\n", entry->desc);
 457                 break;
 458
 459         case ARM64_SSBD_FORCE_ENABLE:
 460                 pr_info_once("%s forced from command-line\n", entry->desc);
 461                 break;
 462         }
 463
 464         return required;
 465 }
 466
 467 /* known invulnerable cores */
 468 static const struct midr_range arm64_ssb_cpus[] = {
 469         MIDR_ALL_VERSIONS(MIDR_CORTEX_A35),
 470         MIDR_ALL_VERSIONS(MIDR_CORTEX_A53),
 471         MIDR_ALL_VERSIONS(MIDR_CORTEX_A55),
 472         {},
 473 };
 474
 475 #ifdef CONFIG_ARM64_ERRATUM_1463225
 476 DEFINE_PER_CPU(int, __in_cortex_a76_erratum_1463225_wa);
 477
 478 static bool
 479 has_cortex_a76_erratum_1463225(const struct arm64_cpu_capabilities *entry,
 480                                int scope)
 481 {
 482         u32 midr = read_cpuid_id();
 483         /* Cortex-A76 r0p0 - r3p1 */
 484         struct midr_range range = MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 3, 1);
 485
 486         WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible());
 487         return is_midr_in_range(midr, &range) && is_kernel_in_hyp_mode();
 488 }
 489 #endif
 490
 491 #define CAP_MIDR_RANGE(model, v_min, r_min, v_max, r_max)       \
 492         .matches = is_affected_midr_range,                      \
 493         .midr_range = MIDR_RANGE(model, v_min, r_min, v_max, r_max)
 494
 495 #define CAP_MIDR_ALL_VERSIONS(model)                                    \
 496         .matches = is_affected_midr_range,                              \
 497         .midr_range = MIDR_ALL_VERSIONS(model)
 498
 499 #define MIDR_FIXED(rev, revidr_mask) \
 500         .fixed_revs = (struct arm64_midr_revidr[]){{ (rev), (revidr_mask) }, {}}
 501
 502 #define ERRATA_MIDR_RANGE(model, v_min, r_min, v_max, r_max)            \
 503         .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,                         \
 504         CAP_MIDR_RANGE(model, v_min, r_min, v_max, r_max)
 505
 506 #define CAP_MIDR_RANGE_LIST(list)                               \
 507         .matches = is_affected_midr_range_list,                 \
 508         .midr_range_list = list
 509
 510 /* Errata affecting a range of revisions of  given model variant */
 511 #define ERRATA_MIDR_REV_RANGE(m, var, r_min, r_max)      \
 512         ERRATA_MIDR_RANGE(m, var, r_min, var, r_max)
 513
 514 /* Errata affecting a single variant/revision of a model */
 515 #define ERRATA_MIDR_REV(model, var, rev)        \
 516         ERRATA_MIDR_RANGE(model, var, rev, var, rev)
 517
 518 /* Errata affecting all variants/revisions of a given a model */
 519 #define ERRATA_MIDR_ALL_VERSIONS(model)                         \
 520         .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,                 \
 521         CAP_MIDR_ALL_VERSIONS(model)
 522
 523 /* Errata affecting a list of midr ranges, with same work around */
 524 #define ERRATA_MIDR_RANGE_LIST(midr_list)                       \
 525         .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,                 \
 526         CAP_MIDR_RANGE_LIST(midr_list)
 527
 528 /* Track overall mitigation state. We are only mitigated if all cores are ok */
 529 static bool __hardenbp_enab = true;
 530 static bool __spectrev2_safe = true;
 531
 532 /*
 533  * Generic helper for handling capabilties with multiple (match,enable) pairs
 534  * of call backs, sharing the same capability bit.
 535  * Iterate over each entry to see if at least one matches.
 536  */
 537 static bool __maybe_unused
 538 multi_entry_cap_matches(const struct arm64_cpu_capabilities *entry, int scope)
 539 {
 540         const struct arm64_cpu_capabilities *caps;
 541
 542         for (caps = entry->match_list; caps->matches; caps++)
 543                 if (caps->matches(caps, scope))
 544                         return true;
 545
 546         return false;
 547 }
 548
 549 /*
 550  * Take appropriate action for all matching entries in the shared capability
 551  * entry.
 552  */
 553 static void __maybe_unused
 554 multi_entry_cap_cpu_enable(const struct arm64_cpu_capabilities *entry)
 555 {
 556         const struct arm64_cpu_capabilities *caps;
 557
 558         for (caps = entry->match_list; caps->matches; caps++)
 559                 if (caps->matches(caps, SCOPE_LOCAL_CPU) &&
 560                     caps->cpu_enable)
 561                         caps->cpu_enable(caps);
 562 }
 563
 564 /*
 565  * List of CPUs that do not need any Spectre-v2 mitigation at all.
 566  */
 567 static const struct midr_range spectre_v2_safe_list[] = {
 568         MIDR_ALL_VERSIONS(MIDR_CORTEX_A35),
 569         MIDR_ALL_VERSIONS(MIDR_CORTEX_A53),
 570         MIDR_ALL_VERSIONS(MIDR_CORTEX_A55),
 571         { /* sentinel */ }
 572 };
 573
 574 /*
 575  * Track overall bp hardening for all heterogeneous cores in the machine.
 576  * We are only considered "safe" if all booted cores are known safe.
 577  */
 578 static bool __maybe_unused
 579 check_branch_predictor(const struct arm64_cpu_capabilities *entry, int scope)
 580 {
 581         int need_wa;
 582
 583         WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible());
 584
 585         /* If the CPU has CSV2 set, we're safe */
 586         if (cpuid_feature_extract_unsigned_field(read_cpuid(ID_AA64PFR0_EL1),
 587                                                  ID_AA64PFR0_CSV2_SHIFT))
 588                 return false;
 589
 590         /* Alternatively, we have a list of unaffected CPUs */
 591         if (is_midr_in_range_list(read_cpuid_id(), spectre_v2_safe_list))
 592                 return false;
 593
 594         /* Fallback to firmware detection */
 595         need_wa = detect_harden_bp_fw();
 596         if (!need_wa)
 597                 return false;
 598
 599         __spectrev2_safe = false;
 600
 601         if (!IS_ENABLED(CONFIG_HARDEN_BRANCH_PREDICTOR)) {
 602                 pr_warn_once("spectrev2 mitigation disabled by kernel configuration\n");
 603                 __hardenbp_enab = false;
 604                 return false;
 605         }
 606
 607         /* forced off */
 608         if (__nospectre_v2 || cpu_mitigations_off()) {
 609                 pr_info_once("spectrev2 mitigation disabled by command line option\n");
 610                 __hardenbp_enab = false;
 611                 return false;
 612         }
 613
 614         if (need_wa < 0) {
 615                 pr_warn_once("ARM_SMCCC_ARCH_WORKAROUND_1 missing from firmware\n");
 616                 __hardenbp_enab = false;
 617         }
 618
 619         return (need_wa > 0);
 620 }
 621
 622 static void
 623 cpu_enable_branch_predictor_hardening(const struct arm64_cpu_capabilities *cap)
 624 {
 625         cap->matches(cap, SCOPE_LOCAL_CPU);
 626 }
 627
 628 static const __maybe_unused struct midr_range tx2_family_cpus[] = {
 629         MIDR_ALL_VERSIONS(MIDR_BRCM_VULCAN),
 630         MIDR_ALL_VERSIONS(MIDR_CAVIUM_THUNDERX2),
 631         {},
 632 };
 633
 634 static bool __maybe_unused
 635 needs_tx2_tvm_workaround(const struct arm64_cpu_capabilities *entry,
 636                          int scope)
 637 {
 638         int i;
 639
 640         if (!is_affected_midr_range_list(entry, scope) ||
 641             !is_hyp_mode_available())
 642                 return false;
 643
 644         for_each_possible_cpu(i) {
 645                 if (MPIDR_AFFINITY_LEVEL(cpu_logical_map(i), 0) != 0)
 646                         return true;
 647         }
 648
 649         return false;
 650 }
 651
 652 static bool __maybe_unused
 653 has_neoverse_n1_erratum_1542419(const struct arm64_cpu_capabilities *entry,
 654                                 int scope)
 655 {
 656         u32 midr = read_cpuid_id();
 657         bool has_dic = read_cpuid_cachetype() & BIT(CTR_DIC_SHIFT);
 658         const struct midr_range range = MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N1);
 659
 660         WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible());
 661         return is_midr_in_range(midr, &range) && has_dic;
 662 }
 663
 664 #ifdef CONFIG_HARDEN_EL2_VECTORS
 665
 666 static const struct midr_range arm64_harden_el2_vectors[] = {
 667         MIDR_ALL_VERSIONS(MIDR_CORTEX_A57),
 668         MIDR_ALL_VERSIONS(MIDR_CORTEX_A72),
 669         {},
 670 };
 671
 672 #endif
 673
 674 const struct arm64_cpu_capabilities arm64_errata[] = {
 675 #if     defined(CONFIG_ARM64_ERRATUM_826319) || \
 676         defined(CONFIG_ARM64_ERRATUM_827319) || \
 677         defined(CONFIG_ARM64_ERRATUM_824069)
 678         {
 679         /* Cortex-A53 r0p[012] */
 680                 .desc = "ARM errata 826319, 827319, 824069",
 681                 .capability = ARM64_WORKAROUND_CLEAN_CACHE,
 682                 ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 2),
 683                 .cpu_enable = cpu_enable_cache_maint_trap,
 684         },
 685 #endif
 686 #ifdef CONFIG_ARM64_ERRATUM_819472
 687         {
 688         /* Cortex-A53 r0p[01] */
 689                 .desc = "ARM errata 819472",
 690                 .capability = ARM64_WORKAROUND_CLEAN_CACHE,
 691                 ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 1),
 692                 .cpu_enable = cpu_enable_cache_maint_trap,
 693         },
 694 #endif
 695 #ifdef CONFIG_ARM64_ERRATUM_832075
 696         {
 697         /* Cortex-A57 r0p0 - r1p2 */
 698                 .desc = "ARM erratum 832075",
 699                 .capability = ARM64_WORKAROUND_DEVICE_LOAD_ACQUIRE,
 700                 ERRATA_MIDR_RANGE(MIDR_CORTEX_A57,
 701                                   0, 0,
 702                                   1, 2),
 703         },
 704 #endif
 705 #ifdef CONFIG_ARM64_ERRATUM_834220
 706         {
 707         /* Cortex-A57 r0p0 - r1p2 */
 708                 .desc = "ARM erratum 834220",
 709                 .capability = ARM64_WORKAROUND_834220,
 710                 ERRATA_MIDR_RANGE(MIDR_CORTEX_A57,
 711                                   0, 0,
 712                                   1, 2),
 713         },
 714 #endif
 715 #ifdef CONFIG_ARM64_ERRATUM_843419
 716         {
 717         /* Cortex-A53 r0p[01234] */
 718                 .desc = "ARM erratum 843419",
 719                 .capability = ARM64_WORKAROUND_843419,
 720                 ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 4),
 721                 MIDR_FIXED(0x4, BIT(8)),
 722         },
 723 #endif
 724 #ifdef CONFIG_ARM64_ERRATUM_845719
 725         {
 726         /* Cortex-A53 r0p[01234] */
 727                 .desc = "ARM erratum 845719",
 728                 .capability = ARM64_WORKAROUND_845719,
 729                 ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 4),
 730         },
 731 #endif
 732 #ifdef CONFIG_CAVIUM_ERRATUM_23154
 733         {
 734         /* Cavium ThunderX, pass 1.x */
 735                 .desc = "Cavium erratum 23154",
 736                 .capability = ARM64_WORKAROUND_CAVIUM_23154,
 737                 ERRATA_MIDR_REV_RANGE(MIDR_THUNDERX, 0, 0, 1),
 738         },
 739 #endif
 740 #ifdef CONFIG_CAVIUM_ERRATUM_27456
 741         {
 742         /* Cavium ThunderX, T88 pass 1.x - 2.1 */
 743                 .desc = "Cavium erratum 27456",
 744                 .capability = ARM64_WORKAROUND_CAVIUM_27456,
 745                 ERRATA_MIDR_RANGE(MIDR_THUNDERX,
 746                                   0, 0,
 747                                   1, 1),
 748         },
 749         {
 750         /* Cavium ThunderX, T81 pass 1.0 */
 751                 .desc = "Cavium erratum 27456",
 752                 .capability = ARM64_WORKAROUND_CAVIUM_27456,
 753                 ERRATA_MIDR_REV(MIDR_THUNDERX_81XX, 0, 0),
 754         },
 755 #endif
 756 #ifdef CONFIG_CAVIUM_ERRATUM_30115
 757         {
 758         /* Cavium ThunderX, T88 pass 1.x - 2.2 */
 759                 .desc = "Cavium erratum 30115",
 760                 .capability = ARM64_WORKAROUND_CAVIUM_30115,
 761                 ERRATA_MIDR_RANGE(MIDR_THUNDERX,
 762                                       0, 0,
 763                                       1, 2),
 764         },
 765         {
 766         /* Cavium ThunderX, T81 pass 1.0 - 1.2 */
 767                 .desc = "Cavium erratum 30115",
 768                 .capability = ARM64_WORKAROUND_CAVIUM_30115,
 769                 ERRATA_MIDR_REV_RANGE(MIDR_THUNDERX_81XX, 0, 0, 2),
 770         },
 771         {
 772         /* Cavium ThunderX, T83 pass 1.0 */
 773                 .desc = "Cavium erratum 30115",
 774                 .capability = ARM64_WORKAROUND_CAVIUM_30115,
 775                 ERRATA_MIDR_REV(MIDR_THUNDERX_83XX, 0, 0),
 776         },
 777 #endif
 778         {
 779                 .desc = "Mismatched cache line size",
 780                 .capability = ARM64_MISMATCHED_CACHE_LINE_SIZE,
 781                 .matches = has_mismatched_cache_type,
 782                 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
 783                 .cpu_enable = cpu_enable_trap_ctr_access,
 784         },
 785         {
 786                 .desc = "Mismatched cache type",
 787                 .capability = ARM64_MISMATCHED_CACHE_TYPE,
 788                 .matches = has_mismatched_cache_type,
 789                 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
 790                 .cpu_enable = cpu_enable_trap_ctr_access,
 791         },
 792 #ifdef CONFIG_QCOM_FALKOR_ERRATUM_1003
 793         {
 794                 .desc = "Qualcomm Technologies Falkor erratum 1003",
 795                 .capability = ARM64_WORKAROUND_QCOM_FALKOR_E1003,
 796                 ERRATA_MIDR_REV(MIDR_QCOM_FALKOR_V1, 0, 0),
 797         },
 798         {
 799                 .desc = "Qualcomm Technologies Kryo erratum 1003",
 800                 .capability = ARM64_WORKAROUND_QCOM_FALKOR_E1003,
 801                 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
 802                 .midr_range.model = MIDR_QCOM_KRYO,
 803                 .matches = is_kryo_midr,
 804         },
 805 #endif
 806 #ifdef CONFIG_QCOM_FALKOR_ERRATUM_1009
 807         {
 808                 .desc = "Qualcomm Technologies Falkor erratum 1009",
 809                 .capability = ARM64_WORKAROUND_REPEAT_TLBI,
 810                 ERRATA_MIDR_REV(MIDR_QCOM_FALKOR_V1, 0, 0),
 811         },
 812 #endif
 813 #ifdef CONFIG_ARM64_ERRATUM_858921
 814         {
 815         /* Cortex-A73 all versions */
 816                 .desc = "ARM erratum 858921",
 817                 .capability = ARM64_WORKAROUND_858921,
 818                 ERRATA_MIDR_ALL_VERSIONS(MIDR_CORTEX_A73),
 819         },
 820 #endif
 821         {
 822                 .desc = "Branch predictor hardening",
 823                 .capability = ARM64_HARDEN_BRANCH_PREDICTOR,
 824                 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
 825                 .matches = check_branch_predictor,
 826                 .cpu_enable = cpu_enable_branch_predictor_hardening,
 827         },
 828 #ifdef CONFIG_HARDEN_EL2_VECTORS
 829         {
 830                 .desc = "EL2 vector hardening",
 831                 .capability = ARM64_HARDEN_EL2_VECTORS,
 832                 ERRATA_MIDR_RANGE_LIST(arm64_harden_el2_vectors),
 833         },
 834 #endif
 835         {
 836                 .desc = "Speculative Store Bypass Disable",
 837                 .capability = ARM64_SSBD,
 838                 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
 839                 .matches = has_ssbd_mitigation,
 840                 .midr_range_list = arm64_ssb_cpus,
 841         },
 842 #ifdef CONFIG_ARM64_ERRATUM_1463225
 843         {
 844                 .desc = "ARM erratum 1463225",
 845                 .capability = ARM64_WORKAROUND_1463225,
 846                 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
 847                 .matches = has_cortex_a76_erratum_1463225,
 848         },
 849 #endif
 850 #ifdef CONFIG_CAVIUM_TX2_ERRATUM_219
 851         {
 852                 .desc = "Cavium ThunderX2 erratum 219 (KVM guest sysreg trapping)",
 853                 .capability = ARM64_WORKAROUND_CAVIUM_TX2_219_TVM,
 854                 ERRATA_MIDR_RANGE_LIST(tx2_family_cpus),
 855                 .matches = needs_tx2_tvm_workaround,
 856         },
 857 #endif
 858 #ifdef CONFIG_ARM64_ERRATUM_1542419
 859         {
 860                 /* we depend on the firmware portion for correctness */
 861                 .desc = "ARM erratum 1542419 (kernel portion)",
 862                 .capability = ARM64_WORKAROUND_1542419,
 863                 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
 864                 .matches = has_neoverse_n1_erratum_1542419,
 865                 .cpu_enable = cpu_enable_trap_ctr_access,
 866         },
 867 #endif
 868         {
 869         }
 870 };
 871
 872 ssize_t cpu_show_spectre_v1(struct device *dev, struct device_attribute *attr,
 873                             char *buf)
 874 {
 875         return sprintf(buf, "Mitigation: __user pointer sanitization\n");
 876 }
 877
 878 ssize_t cpu_show_spectre_v2(struct device *dev, struct device_attribute *attr,
 879                 char *buf)
 880 {
 881         if (__spectrev2_safe)
 882                 return sprintf(buf, "Not affected\n");
 883
 884         if (__hardenbp_enab)
 885                 return sprintf(buf, "Mitigation: Branch predictor hardening\n");
 886
 887         return sprintf(buf, "Vulnerable\n");
 888 }
 889
 890 ssize_t cpu_show_spec_store_bypass(struct device *dev,
 891                 struct device_attribute *attr, char *buf)
 892 {
 893         if (__ssb_safe)
 894                 return sprintf(buf, "Not affected\n");
 895
 896         switch (ssbd_state) {
 897         case ARM64_SSBD_KERNEL:
 898         case ARM64_SSBD_FORCE_ENABLE:
 899                 if (IS_ENABLED(CONFIG_ARM64_SSBD))
 900                         return sprintf(buf,
 901                             "Mitigation: Speculative Store Bypass disabled via prctl\n");
 902         }
 903
 904         return sprintf(buf, "Vulnerable\n");
 905 }